imsttfb.c 43 KB

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  1. /*
  2. * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
  3. *
  4. * This file is derived from the powermac console "imstt" driver:
  5. * Copyright (C) 1997 Sigurdur Asgeirsson
  6. * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
  7. * Modified by Danilo Beuche 1998
  8. * Some register values added by Damien Doligez, INRIA Rocquencourt
  9. * Various cleanups by Paul Mundt (lethal@chaoticdreams.org)
  10. *
  11. * This file was written by Ryan Nielsen (ran@krazynet.com)
  12. * Most of the frame buffer device stuff was copied from atyfb.c
  13. *
  14. * This file is subject to the terms and conditions of the GNU General Public
  15. * License. See the file COPYING in the main directory of this archive for
  16. * more details.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/kernel.h>
  20. #include <linux/errno.h>
  21. #include <linux/string.h>
  22. #include <linux/mm.h>
  23. #include <linux/slab.h>
  24. #include <linux/vmalloc.h>
  25. #include <linux/delay.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/fb.h>
  28. #include <linux/init.h>
  29. #include <linux/pci.h>
  30. #include <asm/io.h>
  31. #include <asm/uaccess.h>
  32. #if defined(CONFIG_PPC)
  33. #include <linux/nvram.h>
  34. #include <asm/prom.h>
  35. #include <asm/pci-bridge.h>
  36. #include "macmodes.h"
  37. #endif
  38. #ifndef __powerpc__
  39. #define eieio() /* Enforce In-order Execution of I/O */
  40. #endif
  41. /* TwinTurbo (Cosmo) registers */
  42. enum {
  43. S1SA = 0, /* 0x00 */
  44. S2SA = 1, /* 0x04 */
  45. SP = 2, /* 0x08 */
  46. DSA = 3, /* 0x0C */
  47. CNT = 4, /* 0x10 */
  48. DP_OCTL = 5, /* 0x14 */
  49. CLR = 6, /* 0x18 */
  50. BI = 8, /* 0x20 */
  51. MBC = 9, /* 0x24 */
  52. BLTCTL = 10, /* 0x28 */
  53. /* Scan Timing Generator Registers */
  54. HES = 12, /* 0x30 */
  55. HEB = 13, /* 0x34 */
  56. HSB = 14, /* 0x38 */
  57. HT = 15, /* 0x3C */
  58. VES = 16, /* 0x40 */
  59. VEB = 17, /* 0x44 */
  60. VSB = 18, /* 0x48 */
  61. VT = 19, /* 0x4C */
  62. HCIV = 20, /* 0x50 */
  63. VCIV = 21, /* 0x54 */
  64. TCDR = 22, /* 0x58 */
  65. VIL = 23, /* 0x5C */
  66. STGCTL = 24, /* 0x60 */
  67. /* Screen Refresh Generator Registers */
  68. SSR = 25, /* 0x64 */
  69. HRIR = 26, /* 0x68 */
  70. SPR = 27, /* 0x6C */
  71. CMR = 28, /* 0x70 */
  72. SRGCTL = 29, /* 0x74 */
  73. /* RAM Refresh Generator Registers */
  74. RRCIV = 30, /* 0x78 */
  75. RRSC = 31, /* 0x7C */
  76. RRCR = 34, /* 0x88 */
  77. /* System Registers */
  78. GIOE = 32, /* 0x80 */
  79. GIO = 33, /* 0x84 */
  80. SCR = 35, /* 0x8C */
  81. SSTATUS = 36, /* 0x90 */
  82. PRC = 37, /* 0x94 */
  83. #if 0
  84. /* PCI Registers */
  85. DVID = 0x00000000L,
  86. SC = 0x00000004L,
  87. CCR = 0x00000008L,
  88. OG = 0x0000000CL,
  89. BARM = 0x00000010L,
  90. BARER = 0x00000030L,
  91. #endif
  92. };
  93. /* IBM 624 RAMDAC Direct Registers */
  94. enum {
  95. PADDRW = 0x00,
  96. PDATA = 0x04,
  97. PPMASK = 0x08,
  98. PADDRR = 0x0c,
  99. PIDXLO = 0x10,
  100. PIDXHI = 0x14,
  101. PIDXDATA= 0x18,
  102. PIDXCTL = 0x1c
  103. };
  104. /* IBM 624 RAMDAC Indirect Registers */
  105. enum {
  106. CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */
  107. SYNCCTL = 0x03, /* (0x00) Sync Control */
  108. HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */
  109. PWRMNGMT = 0x05, /* (0x00) Power Management */
  110. DACOP = 0x06, /* (0x02) DAC Operation */
  111. PALETCTL = 0x07, /* (0x00) Palette Control */
  112. SYSCLKCTL = 0x08, /* (0x01) System Clock Control */
  113. PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
  114. BPP8 = 0x0b, /* () 8 Bits/Pixel Control */
  115. BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
  116. BPP24 = 0x0d, /* () 24 Bits/Pixel Control */
  117. BPP32 = 0x0e, /* () 32 Bits/Pixel Control */
  118. PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */
  119. PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */
  120. SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */
  121. SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */
  122. SYSCLKP = 0x17, /* () System Clock P */
  123. SYSCLKC = 0x18, /* () System Clock C */
  124. /*
  125. * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
  126. * c is charge pump bias which depends on the VCO frequency
  127. */
  128. PIXM0 = 0x20, /* () Pixel M 0 */
  129. PIXN0 = 0x21, /* () Pixel N 0 */
  130. PIXP0 = 0x22, /* () Pixel P 0 */
  131. PIXC0 = 0x23, /* () Pixel C 0 */
  132. CURSCTL = 0x30, /* (0x00) Cursor Control */
  133. CURSXLO = 0x31, /* () Cursor X position, low 8 bits */
  134. CURSXHI = 0x32, /* () Cursor X position, high 8 bits */
  135. CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */
  136. CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */
  137. CURSHOTX = 0x35, /* () Cursor Hot Spot X */
  138. CURSHOTY = 0x36, /* () Cursor Hot Spot Y */
  139. CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */
  140. CURSACATTR = 0x38, /* () Advanced Cursor Attribute */
  141. CURS1R = 0x40, /* () Cursor 1 Red */
  142. CURS1G = 0x41, /* () Cursor 1 Green */
  143. CURS1B = 0x42, /* () Cursor 1 Blue */
  144. CURS2R = 0x43, /* () Cursor 2 Red */
  145. CURS2G = 0x44, /* () Cursor 2 Green */
  146. CURS2B = 0x45, /* () Cursor 2 Blue */
  147. CURS3R = 0x46, /* () Cursor 3 Red */
  148. CURS3G = 0x47, /* () Cursor 3 Green */
  149. CURS3B = 0x48, /* () Cursor 3 Blue */
  150. BORDR = 0x60, /* () Border Color Red */
  151. BORDG = 0x61, /* () Border Color Green */
  152. BORDB = 0x62, /* () Border Color Blue */
  153. MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */
  154. MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */
  155. MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */
  156. KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */
  157. };
  158. /* TI TVP 3030 RAMDAC Direct Registers */
  159. enum {
  160. TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Address/Index */
  161. TVPPDATA = 0x04, /* 1 Palette Data RAM Data */
  162. TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
  163. TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Address */
  164. TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */
  165. TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */
  166. /* 6 reserved */
  167. TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */
  168. /* 8 reserved */
  169. TVPDCCTL = 0x24, /* 9 Direct Cursor Control */
  170. TVPIDATA = 0x28, /* 10 Index Data */
  171. TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */
  172. TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
  173. TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
  174. TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
  175. TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
  176. };
  177. /* TI TVP 3030 RAMDAC Indirect Registers */
  178. enum {
  179. TVPIRREV = 0x01, /* Silicon Revision [RO] */
  180. TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */
  181. TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */
  182. TVPIRLAC = 0x0f, /* Latch Control (0x06) */
  183. TVPIRTCC = 0x18, /* True Color Control (0x80) */
  184. TVPIRMXC = 0x19, /* Multiplex Control (0x98) */
  185. TVPIRCLS = 0x1a, /* Clock Selection (0x07) */
  186. TVPIRPPG = 0x1c, /* Palette Page (0x00) */
  187. TVPIRGEC = 0x1d, /* General Control (0x00) */
  188. TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */
  189. TVPIRPLA = 0x2c, /* PLL Address */
  190. TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */
  191. TVPIRMPD = 0x2e, /* Memory Clock PLL Data */
  192. TVPIRLPD = 0x2f, /* Loop Clock PLL Data */
  193. TVPIRCKL = 0x30, /* Color-Key Overlay Low */
  194. TVPIRCKH = 0x31, /* Color-Key Overlay High */
  195. TVPIRCRL = 0x32, /* Color-Key Red Low */
  196. TVPIRCRH = 0x33, /* Color-Key Red High */
  197. TVPIRCGL = 0x34, /* Color-Key Green Low */
  198. TVPIRCGH = 0x35, /* Color-Key Green High */
  199. TVPIRCBL = 0x36, /* Color-Key Blue Low */
  200. TVPIRCBH = 0x37, /* Color-Key Blue High */
  201. TVPIRCKC = 0x38, /* Color-Key Control (0x00) */
  202. TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
  203. TVPIRSEN = 0x3a, /* Sense Test (0x00) */
  204. TVPIRTMD = 0x3b, /* Test Mode Data */
  205. TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */
  206. TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */
  207. TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */
  208. TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */
  209. TVPIRRES = 0xff /* Software Reset [WO] */
  210. };
  211. struct initvalues {
  212. __u8 addr, value;
  213. };
  214. static struct initvalues ibm_initregs[] __devinitdata = {
  215. { CLKCTL, 0x21 },
  216. { SYNCCTL, 0x00 },
  217. { HSYNCPOS, 0x00 },
  218. { PWRMNGMT, 0x00 },
  219. { DACOP, 0x02 },
  220. { PALETCTL, 0x00 },
  221. { SYSCLKCTL, 0x01 },
  222. /*
  223. * Note that colors in X are correct only if all video data is
  224. * passed through the palette in the DAC. That is, "indirect
  225. * color" must be configured. This is the case for the IBM DAC
  226. * used in the 2MB and 4MB cards, at least.
  227. */
  228. { BPP8, 0x00 },
  229. { BPP16, 0x01 },
  230. { BPP24, 0x00 },
  231. { BPP32, 0x00 },
  232. { PIXCTL1, 0x05 },
  233. { PIXCTL2, 0x00 },
  234. { SYSCLKN, 0x08 },
  235. { SYSCLKM, 0x4f },
  236. { SYSCLKP, 0x00 },
  237. { SYSCLKC, 0x00 },
  238. { CURSCTL, 0x00 },
  239. { CURSACCTL, 0x01 },
  240. { CURSACATTR, 0xa8 },
  241. { CURS1R, 0xff },
  242. { CURS1G, 0xff },
  243. { CURS1B, 0xff },
  244. { CURS2R, 0xff },
  245. { CURS2G, 0xff },
  246. { CURS2B, 0xff },
  247. { CURS3R, 0xff },
  248. { CURS3G, 0xff },
  249. { CURS3B, 0xff },
  250. { BORDR, 0xff },
  251. { BORDG, 0xff },
  252. { BORDB, 0xff },
  253. { MISCTL1, 0x01 },
  254. { MISCTL2, 0x45 },
  255. { MISCTL3, 0x00 },
  256. { KEYCTL, 0x00 }
  257. };
  258. static struct initvalues tvp_initregs[] __devinitdata = {
  259. { TVPIRICC, 0x00 },
  260. { TVPIRBRC, 0xe4 },
  261. { TVPIRLAC, 0x06 },
  262. { TVPIRTCC, 0x80 },
  263. { TVPIRMXC, 0x4d },
  264. { TVPIRCLS, 0x05 },
  265. { TVPIRPPG, 0x00 },
  266. { TVPIRGEC, 0x00 },
  267. { TVPIRMIC, 0x08 },
  268. { TVPIRCKL, 0xff },
  269. { TVPIRCKH, 0xff },
  270. { TVPIRCRL, 0xff },
  271. { TVPIRCRH, 0xff },
  272. { TVPIRCGL, 0xff },
  273. { TVPIRCGH, 0xff },
  274. { TVPIRCBL, 0xff },
  275. { TVPIRCBH, 0xff },
  276. { TVPIRCKC, 0x00 },
  277. { TVPIRPLA, 0x00 },
  278. { TVPIRPPD, 0xc0 },
  279. { TVPIRPPD, 0xd5 },
  280. { TVPIRPPD, 0xea },
  281. { TVPIRPLA, 0x00 },
  282. { TVPIRMPD, 0xb9 },
  283. { TVPIRMPD, 0x3a },
  284. { TVPIRMPD, 0xb1 },
  285. { TVPIRPLA, 0x00 },
  286. { TVPIRLPD, 0xc1 },
  287. { TVPIRLPD, 0x3d },
  288. { TVPIRLPD, 0xf3 },
  289. };
  290. struct imstt_regvals {
  291. __u32 pitch;
  292. __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
  293. __u8 pclk_m, pclk_n, pclk_p;
  294. /* Values of the tvp which change depending on colormode x resolution */
  295. __u8 mlc[3]; /* Memory Loop Config 0x39 */
  296. __u8 lckl_p[3]; /* P value of LCKL PLL */
  297. };
  298. struct imstt_par {
  299. struct imstt_regvals init;
  300. __u32 __iomem *dc_regs;
  301. unsigned long cmap_regs_phys;
  302. __u8 *cmap_regs;
  303. __u32 ramdac;
  304. __u32 palette[16];
  305. };
  306. enum {
  307. IBM = 0,
  308. TVP = 1
  309. };
  310. #define USE_NV_MODES 1
  311. #define INIT_BPP 8
  312. #define INIT_XRES 640
  313. #define INIT_YRES 480
  314. static int inverse = 0;
  315. static char fontname[40] __initdata = { 0 };
  316. #if defined(CONFIG_PPC)
  317. static signed char init_vmode __devinitdata = -1, init_cmode __devinitdata = -1;
  318. #endif
  319. static struct imstt_regvals tvp_reg_init_2 = {
  320. 512,
  321. 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
  322. 0xec, 0x2a, 0xf3,
  323. { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
  324. };
  325. static struct imstt_regvals tvp_reg_init_6 = {
  326. 640,
  327. 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
  328. 0xef, 0x2e, 0xb2,
  329. { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
  330. };
  331. static struct imstt_regvals tvp_reg_init_12 = {
  332. 800,
  333. 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
  334. 0xf6, 0x2e, 0xf2,
  335. { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
  336. };
  337. static struct imstt_regvals tvp_reg_init_13 = {
  338. 832,
  339. 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
  340. 0xfe, 0x3e, 0xf1,
  341. { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
  342. };
  343. static struct imstt_regvals tvp_reg_init_17 = {
  344. 1024,
  345. 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
  346. 0xfc, 0x3a, 0xf1,
  347. { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
  348. };
  349. static struct imstt_regvals tvp_reg_init_18 = {
  350. 1152,
  351. 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
  352. 0xfd, 0x3a, 0xf1,
  353. { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
  354. };
  355. static struct imstt_regvals tvp_reg_init_19 = {
  356. 1280,
  357. 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
  358. 0xf7, 0x36, 0xf0,
  359. { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
  360. };
  361. static struct imstt_regvals tvp_reg_init_20 = {
  362. 1280,
  363. 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
  364. 0xf0, 0x2d, 0xf0,
  365. { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
  366. };
  367. /*
  368. * PCI driver prototypes
  369. */
  370. static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  371. static void imsttfb_remove(struct pci_dev *pdev);
  372. /*
  373. * Register access
  374. */
  375. static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex)
  376. {
  377. #ifdef __powerpc__
  378. return in_le32(base + regindex);
  379. #else
  380. return readl(base + regindex);
  381. #endif
  382. }
  383. static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val)
  384. {
  385. #ifdef __powerpc__
  386. out_le32(base + regindex, val);
  387. #else
  388. writel(val, base + regindex);
  389. #endif
  390. }
  391. static __u32
  392. getclkMHz(struct imstt_par *par)
  393. {
  394. __u32 clk_m, clk_n, clk_p;
  395. clk_m = par->init.pclk_m;
  396. clk_n = par->init.pclk_n;
  397. clk_p = par->init.pclk_p;
  398. return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
  399. }
  400. static void
  401. setclkMHz(struct imstt_par *par, __u32 MHz)
  402. {
  403. __u32 clk_m, clk_n, x, stage, spilled;
  404. clk_m = clk_n = 0;
  405. stage = spilled = 0;
  406. for (;;) {
  407. switch (stage) {
  408. case 0:
  409. clk_m++;
  410. break;
  411. case 1:
  412. clk_n++;
  413. break;
  414. }
  415. x = 20 * (clk_m + 1) / (clk_n + 1);
  416. if (x == MHz)
  417. break;
  418. if (x > MHz) {
  419. spilled = 1;
  420. stage = 1;
  421. } else if (spilled && x < MHz) {
  422. stage = 0;
  423. }
  424. }
  425. par->init.pclk_m = clk_m;
  426. par->init.pclk_n = clk_n;
  427. par->init.pclk_p = 0;
  428. }
  429. static struct imstt_regvals *
  430. compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres)
  431. {
  432. struct imstt_regvals *init = &par->init;
  433. __u32 MHz, hes, heb, veb, htp, vtp;
  434. switch (xres) {
  435. case 640:
  436. hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
  437. MHz = 30 /* .25 */ ;
  438. break;
  439. case 832:
  440. hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
  441. MHz = 57 /* .27_ */ ;
  442. break;
  443. case 1024:
  444. hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
  445. MHz = 80;
  446. break;
  447. case 1152:
  448. hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
  449. MHz = 101 /* .6_ */ ;
  450. break;
  451. case 1280:
  452. hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
  453. MHz = yres == 960 ? 126 : 135;
  454. break;
  455. case 1600:
  456. hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
  457. MHz = 200;
  458. break;
  459. default:
  460. return NULL;
  461. }
  462. setclkMHz(par, MHz);
  463. init->hes = hes;
  464. init->heb = heb;
  465. init->hsb = init->heb + (xres >> 3);
  466. init->ht = init->hsb + htp;
  467. init->ves = 0x0003;
  468. init->veb = veb;
  469. init->vsb = init->veb + yres;
  470. init->vt = init->vsb + vtp;
  471. init->vil = init->vsb;
  472. init->pitch = xres;
  473. return init;
  474. }
  475. static struct imstt_regvals *
  476. compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres)
  477. {
  478. struct imstt_regvals *init;
  479. switch (xres) {
  480. case 512:
  481. init = &tvp_reg_init_2;
  482. break;
  483. case 640:
  484. init = &tvp_reg_init_6;
  485. break;
  486. case 800:
  487. init = &tvp_reg_init_12;
  488. break;
  489. case 832:
  490. init = &tvp_reg_init_13;
  491. break;
  492. case 1024:
  493. init = &tvp_reg_init_17;
  494. break;
  495. case 1152:
  496. init = &tvp_reg_init_18;
  497. break;
  498. case 1280:
  499. init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
  500. break;
  501. default:
  502. return NULL;
  503. }
  504. par->init = *init;
  505. return init;
  506. }
  507. static struct imstt_regvals *
  508. compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres)
  509. {
  510. if (par->ramdac == IBM)
  511. return compute_imstt_regvals_ibm(par, xres, yres);
  512. else
  513. return compute_imstt_regvals_tvp(par, xres, yres);
  514. }
  515. static void
  516. set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp)
  517. {
  518. struct imstt_regvals *init = &par->init;
  519. __u8 pformat = (bpp >> 3) + 2;
  520. par->cmap_regs[PIDXHI] = 0; eieio();
  521. par->cmap_regs[PIDXLO] = PIXM0; eieio();
  522. par->cmap_regs[PIDXDATA] = init->pclk_m;eieio();
  523. par->cmap_regs[PIDXLO] = PIXN0; eieio();
  524. par->cmap_regs[PIDXDATA] = init->pclk_n;eieio();
  525. par->cmap_regs[PIDXLO] = PIXP0; eieio();
  526. par->cmap_regs[PIDXDATA] = init->pclk_p;eieio();
  527. par->cmap_regs[PIDXLO] = PIXC0; eieio();
  528. par->cmap_regs[PIDXDATA] = 0x02; eieio();
  529. par->cmap_regs[PIDXLO] = PIXFMT; eieio();
  530. par->cmap_regs[PIDXDATA] = pformat; eieio();
  531. }
  532. static void
  533. set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp)
  534. {
  535. struct imstt_regvals *init = &par->init;
  536. __u8 tcc, mxc, lckl_n, mic;
  537. __u8 mlc, lckl_p;
  538. switch (bpp) {
  539. default:
  540. case 8:
  541. tcc = 0x80;
  542. mxc = 0x4d;
  543. lckl_n = 0xc1;
  544. mlc = init->mlc[0];
  545. lckl_p = init->lckl_p[0];
  546. break;
  547. case 16:
  548. tcc = 0x44;
  549. mxc = 0x55;
  550. lckl_n = 0xe1;
  551. mlc = init->mlc[1];
  552. lckl_p = init->lckl_p[1];
  553. break;
  554. case 24:
  555. tcc = 0x5e;
  556. mxc = 0x5d;
  557. lckl_n = 0xf1;
  558. mlc = init->mlc[2];
  559. lckl_p = init->lckl_p[2];
  560. break;
  561. case 32:
  562. tcc = 0x46;
  563. mxc = 0x5d;
  564. lckl_n = 0xf1;
  565. mlc = init->mlc[2];
  566. lckl_p = init->lckl_p[2];
  567. break;
  568. }
  569. mic = 0x08;
  570. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  571. par->cmap_regs[TVPIDATA] = 0x00; eieio();
  572. par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
  573. par->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
  574. par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
  575. par->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
  576. par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
  577. par->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
  578. par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
  579. par->cmap_regs[TVPIDATA] = tcc; eieio();
  580. par->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
  581. par->cmap_regs[TVPIDATA] = mxc; eieio();
  582. par->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
  583. par->cmap_regs[TVPIDATA] = mic; eieio();
  584. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  585. par->cmap_regs[TVPIDATA] = 0x00; eieio();
  586. par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
  587. par->cmap_regs[TVPIDATA] = lckl_n; eieio();
  588. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  589. par->cmap_regs[TVPIDATA] = 0x15; eieio();
  590. par->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
  591. par->cmap_regs[TVPIDATA] = mlc; eieio();
  592. par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
  593. par->cmap_regs[TVPIDATA] = 0x2a; eieio();
  594. par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
  595. par->cmap_regs[TVPIDATA] = lckl_p; eieio();
  596. }
  597. static void
  598. set_imstt_regvals (struct fb_info *info, u_int bpp)
  599. {
  600. struct imstt_par *par = info->par;
  601. struct imstt_regvals *init = &par->init;
  602. __u32 ctl, pitch, byteswap, scr;
  603. if (par->ramdac == IBM)
  604. set_imstt_regvals_ibm(par, bpp);
  605. else
  606. set_imstt_regvals_tvp(par, bpp);
  607. /*
  608. * From what I (jsk) can gather poking around with MacsBug,
  609. * bits 8 and 9 in the SCR register control endianness
  610. * correction (byte swapping). These bits must be set according
  611. * to the color depth as follows:
  612. * Color depth Bit 9 Bit 8
  613. * ========== ===== =====
  614. * 8bpp 0 0
  615. * 16bpp 0 1
  616. * 32bpp 1 1
  617. */
  618. switch (bpp) {
  619. default:
  620. case 8:
  621. ctl = 0x17b1;
  622. pitch = init->pitch >> 2;
  623. byteswap = 0x000;
  624. break;
  625. case 16:
  626. ctl = 0x17b3;
  627. pitch = init->pitch >> 1;
  628. byteswap = 0x100;
  629. break;
  630. case 24:
  631. ctl = 0x17b9;
  632. pitch = init->pitch - (init->pitch >> 2);
  633. byteswap = 0x200;
  634. break;
  635. case 32:
  636. ctl = 0x17b5;
  637. pitch = init->pitch;
  638. byteswap = 0x300;
  639. break;
  640. }
  641. if (par->ramdac == TVP)
  642. ctl -= 0x30;
  643. write_reg_le32(par->dc_regs, HES, init->hes);
  644. write_reg_le32(par->dc_regs, HEB, init->heb);
  645. write_reg_le32(par->dc_regs, HSB, init->hsb);
  646. write_reg_le32(par->dc_regs, HT, init->ht);
  647. write_reg_le32(par->dc_regs, VES, init->ves);
  648. write_reg_le32(par->dc_regs, VEB, init->veb);
  649. write_reg_le32(par->dc_regs, VSB, init->vsb);
  650. write_reg_le32(par->dc_regs, VT, init->vt);
  651. write_reg_le32(par->dc_regs, VIL, init->vil);
  652. write_reg_le32(par->dc_regs, HCIV, 1);
  653. write_reg_le32(par->dc_regs, VCIV, 1);
  654. write_reg_le32(par->dc_regs, TCDR, 4);
  655. write_reg_le32(par->dc_regs, RRCIV, 1);
  656. write_reg_le32(par->dc_regs, RRSC, 0x980);
  657. write_reg_le32(par->dc_regs, RRCR, 0x11);
  658. if (par->ramdac == IBM) {
  659. write_reg_le32(par->dc_regs, HRIR, 0x0100);
  660. write_reg_le32(par->dc_regs, CMR, 0x00ff);
  661. write_reg_le32(par->dc_regs, SRGCTL, 0x0073);
  662. } else {
  663. write_reg_le32(par->dc_regs, HRIR, 0x0200);
  664. write_reg_le32(par->dc_regs, CMR, 0x01ff);
  665. write_reg_le32(par->dc_regs, SRGCTL, 0x0003);
  666. }
  667. switch (info->fix.smem_len) {
  668. case 0x200000:
  669. scr = 0x059d | byteswap;
  670. break;
  671. /* case 0x400000:
  672. case 0x800000: */
  673. default:
  674. pitch >>= 1;
  675. scr = 0x150dd | byteswap;
  676. break;
  677. }
  678. write_reg_le32(par->dc_regs, SCR, scr);
  679. write_reg_le32(par->dc_regs, SPR, pitch);
  680. write_reg_le32(par->dc_regs, STGCTL, ctl);
  681. }
  682. static inline void
  683. set_offset (struct fb_var_screeninfo *var, struct fb_info *info)
  684. {
  685. struct imstt_par *par = info->par;
  686. __u32 off = var->yoffset * (info->fix.line_length >> 3)
  687. + ((var->xoffset * (var->bits_per_pixel >> 3)) >> 3);
  688. write_reg_le32(par->dc_regs, SSR, off);
  689. }
  690. static inline void
  691. set_555 (struct imstt_par *par)
  692. {
  693. if (par->ramdac == IBM) {
  694. par->cmap_regs[PIDXHI] = 0; eieio();
  695. par->cmap_regs[PIDXLO] = BPP16; eieio();
  696. par->cmap_regs[PIDXDATA] = 0x01; eieio();
  697. } else {
  698. par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
  699. par->cmap_regs[TVPIDATA] = 0x44; eieio();
  700. }
  701. }
  702. static inline void
  703. set_565 (struct imstt_par *par)
  704. {
  705. if (par->ramdac == IBM) {
  706. par->cmap_regs[PIDXHI] = 0; eieio();
  707. par->cmap_regs[PIDXLO] = BPP16; eieio();
  708. par->cmap_regs[PIDXDATA] = 0x03; eieio();
  709. } else {
  710. par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
  711. par->cmap_regs[TVPIDATA] = 0x45; eieio();
  712. }
  713. }
  714. static int
  715. imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  716. {
  717. if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
  718. && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
  719. || var->xres_virtual < var->xres || var->yres_virtual < var->yres
  720. || var->nonstd
  721. || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
  722. return -EINVAL;
  723. if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len
  724. || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len)
  725. return -EINVAL;
  726. switch (var->bits_per_pixel) {
  727. case 8:
  728. var->red.offset = 0;
  729. var->red.length = 8;
  730. var->green.offset = 0;
  731. var->green.length = 8;
  732. var->blue.offset = 0;
  733. var->blue.length = 8;
  734. var->transp.offset = 0;
  735. var->transp.length = 0;
  736. break;
  737. case 16: /* RGB 555 or 565 */
  738. if (var->green.length != 6)
  739. var->red.offset = 10;
  740. var->red.length = 5;
  741. var->green.offset = 5;
  742. if (var->green.length != 6)
  743. var->green.length = 5;
  744. var->blue.offset = 0;
  745. var->blue.length = 5;
  746. var->transp.offset = 0;
  747. var->transp.length = 0;
  748. break;
  749. case 24: /* RGB 888 */
  750. var->red.offset = 16;
  751. var->red.length = 8;
  752. var->green.offset = 8;
  753. var->green.length = 8;
  754. var->blue.offset = 0;
  755. var->blue.length = 8;
  756. var->transp.offset = 0;
  757. var->transp.length = 0;
  758. break;
  759. case 32: /* RGBA 8888 */
  760. var->red.offset = 16;
  761. var->red.length = 8;
  762. var->green.offset = 8;
  763. var->green.length = 8;
  764. var->blue.offset = 0;
  765. var->blue.length = 8;
  766. var->transp.offset = 24;
  767. var->transp.length = 8;
  768. break;
  769. }
  770. if (var->yres == var->yres_virtual) {
  771. __u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2));
  772. var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual;
  773. if (var->yres_virtual < var->yres)
  774. var->yres_virtual = var->yres;
  775. }
  776. var->red.msb_right = 0;
  777. var->green.msb_right = 0;
  778. var->blue.msb_right = 0;
  779. var->transp.msb_right = 0;
  780. var->height = -1;
  781. var->width = -1;
  782. var->vmode = FB_VMODE_NONINTERLACED;
  783. var->left_margin = var->right_margin = 16;
  784. var->upper_margin = var->lower_margin = 16;
  785. var->hsync_len = var->vsync_len = 8;
  786. return 0;
  787. }
  788. static int
  789. imsttfb_set_par(struct fb_info *info)
  790. {
  791. struct imstt_par *par = info->par;
  792. if (!compute_imstt_regvals(par, info->var.xres, info->var.yres))
  793. return -EINVAL;
  794. if (info->var.green.length == 6)
  795. set_565(par);
  796. else
  797. set_555(par);
  798. set_imstt_regvals(info, info->var.bits_per_pixel);
  799. info->var.pixclock = 1000000 / getclkMHz(par);
  800. return 0;
  801. }
  802. static int
  803. imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
  804. u_int transp, struct fb_info *info)
  805. {
  806. struct imstt_par *par = info->par;
  807. u_int bpp = info->var.bits_per_pixel;
  808. if (regno > 255)
  809. return 1;
  810. red >>= 8;
  811. green >>= 8;
  812. blue >>= 8;
  813. /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
  814. if (0 && bpp == 16) /* screws up X */
  815. par->cmap_regs[PADDRW] = regno << 3;
  816. else
  817. par->cmap_regs[PADDRW] = regno;
  818. eieio();
  819. par->cmap_regs[PDATA] = red; eieio();
  820. par->cmap_regs[PDATA] = green; eieio();
  821. par->cmap_regs[PDATA] = blue; eieio();
  822. if (regno < 16)
  823. switch (bpp) {
  824. case 16:
  825. par->palette[regno] =
  826. (regno << (info->var.green.length ==
  827. 5 ? 10 : 11)) | (regno << 5) | regno;
  828. break;
  829. case 24:
  830. par->palette[regno] =
  831. (regno << 16) | (regno << 8) | regno;
  832. break;
  833. case 32: {
  834. int i = (regno << 8) | regno;
  835. par->palette[regno] = (i << 16) |i;
  836. break;
  837. }
  838. }
  839. return 0;
  840. }
  841. static int
  842. imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  843. {
  844. if (var->xoffset + info->var.xres > info->var.xres_virtual
  845. || var->yoffset + info->var.yres > info->var.yres_virtual)
  846. return -EINVAL;
  847. info->var.xoffset = var->xoffset;
  848. info->var.yoffset = var->yoffset;
  849. set_offset(var, info);
  850. return 0;
  851. }
  852. static int
  853. imsttfb_blank(int blank, struct fb_info *info)
  854. {
  855. struct imstt_par *par = info->par;
  856. __u32 ctrl;
  857. ctrl = read_reg_le32(par->dc_regs, STGCTL);
  858. if (blank > 0) {
  859. switch (blank) {
  860. case FB_BLANK_NORMAL:
  861. case FB_BLANK_POWERDOWN:
  862. ctrl &= ~0x00000380;
  863. if (par->ramdac == IBM) {
  864. par->cmap_regs[PIDXHI] = 0; eieio();
  865. par->cmap_regs[PIDXLO] = MISCTL2; eieio();
  866. par->cmap_regs[PIDXDATA] = 0x55; eieio();
  867. par->cmap_regs[PIDXLO] = MISCTL1; eieio();
  868. par->cmap_regs[PIDXDATA] = 0x11; eieio();
  869. par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
  870. par->cmap_regs[PIDXDATA] = 0x0f; eieio();
  871. par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
  872. par->cmap_regs[PIDXDATA] = 0x1f; eieio();
  873. par->cmap_regs[PIDXLO] = CLKCTL; eieio();
  874. par->cmap_regs[PIDXDATA] = 0xc0;
  875. }
  876. break;
  877. case FB_BLANK_VSYNC_SUSPEND:
  878. ctrl &= ~0x00000020;
  879. break;
  880. case FB_BLANK_HSYNC_SUSPEND:
  881. ctrl &= ~0x00000010;
  882. break;
  883. }
  884. } else {
  885. if (par->ramdac == IBM) {
  886. ctrl |= 0x000017b0;
  887. par->cmap_regs[PIDXHI] = 0; eieio();
  888. par->cmap_regs[PIDXLO] = CLKCTL; eieio();
  889. par->cmap_regs[PIDXDATA] = 0x01; eieio();
  890. par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
  891. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  892. par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
  893. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  894. par->cmap_regs[PIDXLO] = MISCTL1; eieio();
  895. par->cmap_regs[PIDXDATA] = 0x01; eieio();
  896. par->cmap_regs[PIDXLO] = MISCTL2; eieio();
  897. par->cmap_regs[PIDXDATA] = 0x45; eieio();
  898. } else
  899. ctrl |= 0x00001780;
  900. }
  901. write_reg_le32(par->dc_regs, STGCTL, ctrl);
  902. return 0;
  903. }
  904. static void
  905. imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  906. {
  907. struct imstt_par *par = info->par;
  908. __u32 Bpp, line_pitch, bgc, dx, dy, width, height;
  909. bgc = rect->color;
  910. bgc |= (bgc << 8);
  911. bgc |= (bgc << 16);
  912. Bpp = info->var.bits_per_pixel >> 3,
  913. line_pitch = info->fix.line_length;
  914. dy = rect->dy * line_pitch;
  915. dx = rect->dx * Bpp;
  916. height = rect->height;
  917. height--;
  918. width = rect->width * Bpp;
  919. width--;
  920. if (rect->rop == ROP_COPY) {
  921. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  922. write_reg_le32(par->dc_regs, DSA, dy + dx);
  923. write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
  924. write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
  925. write_reg_le32(par->dc_regs, BI, 0xffffffff);
  926. write_reg_le32(par->dc_regs, MBC, 0xffffffff);
  927. write_reg_le32(par->dc_regs, CLR, bgc);
  928. write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */
  929. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  930. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
  931. } else {
  932. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  933. write_reg_le32(par->dc_regs, DSA, dy + dx);
  934. write_reg_le32(par->dc_regs, S1SA, dy + dx);
  935. write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
  936. write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
  937. write_reg_le32(par->dc_regs, SP, line_pitch);
  938. write_reg_le32(par->dc_regs, BLTCTL, 0x40005);
  939. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  940. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
  941. }
  942. }
  943. static void
  944. imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  945. {
  946. struct imstt_par *par = info->par;
  947. __u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl;
  948. __u32 cnt, bltctl, sx, sy, dx, dy, height, width;
  949. Bpp = info->var.bits_per_pixel >> 3,
  950. sx = area->sx * Bpp;
  951. sy = area->sy;
  952. dx = area->dx * Bpp;
  953. dy = area->dy;
  954. height = area->height;
  955. height--;
  956. width = area->width * Bpp;
  957. width--;
  958. line_pitch = info->fix.line_length;
  959. bltctl = 0x05;
  960. sp = line_pitch << 16;
  961. cnt = height << 16;
  962. if (sy < dy) {
  963. sy += height;
  964. dy += height;
  965. sp |= -(line_pitch) & 0xffff;
  966. dp_octl = -(line_pitch) & 0xffff;
  967. } else {
  968. sp |= line_pitch;
  969. dp_octl = line_pitch;
  970. }
  971. if (sx < dx) {
  972. sx += width;
  973. dx += width;
  974. bltctl |= 0x80;
  975. cnt |= -(width) & 0xffff;
  976. } else {
  977. cnt |= width;
  978. }
  979. fb_offset_old = sy * line_pitch + sx;
  980. fb_offset_new = dy * line_pitch + dx;
  981. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  982. write_reg_le32(par->dc_regs, S1SA, fb_offset_old);
  983. write_reg_le32(par->dc_regs, SP, sp);
  984. write_reg_le32(par->dc_regs, DSA, fb_offset_new);
  985. write_reg_le32(par->dc_regs, CNT, cnt);
  986. write_reg_le32(par->dc_regs, DP_OCTL, dp_octl);
  987. write_reg_le32(par->dc_regs, BLTCTL, bltctl);
  988. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
  989. while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
  990. }
  991. #if 0
  992. static int
  993. imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc)
  994. {
  995. u_int x, y;
  996. if (width > 32 || height > 32)
  997. return -EINVAL;
  998. if (par->ramdac == IBM) {
  999. par->cmap_regs[PIDXHI] = 1; eieio();
  1000. for (x = 0; x < 0x100; x++) {
  1001. par->cmap_regs[PIDXLO] = x; eieio();
  1002. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  1003. }
  1004. par->cmap_regs[PIDXHI] = 1; eieio();
  1005. for (y = 0; y < height; y++)
  1006. for (x = 0; x < width >> 2; x++) {
  1007. par->cmap_regs[PIDXLO] = x + y * 8; eieio();
  1008. par->cmap_regs[PIDXDATA] = 0xff; eieio();
  1009. }
  1010. par->cmap_regs[PIDXHI] = 0; eieio();
  1011. par->cmap_regs[PIDXLO] = CURS1R; eieio();
  1012. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1013. par->cmap_regs[PIDXLO] = CURS1G; eieio();
  1014. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1015. par->cmap_regs[PIDXLO] = CURS1B; eieio();
  1016. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1017. par->cmap_regs[PIDXLO] = CURS2R; eieio();
  1018. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1019. par->cmap_regs[PIDXLO] = CURS2G; eieio();
  1020. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1021. par->cmap_regs[PIDXLO] = CURS2B; eieio();
  1022. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1023. par->cmap_regs[PIDXLO] = CURS3R; eieio();
  1024. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1025. par->cmap_regs[PIDXLO] = CURS3G; eieio();
  1026. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1027. par->cmap_regs[PIDXLO] = CURS3B; eieio();
  1028. par->cmap_regs[PIDXDATA] = fgc; eieio();
  1029. } else {
  1030. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1031. par->cmap_regs[TVPIDATA] &= 0x03; eieio();
  1032. par->cmap_regs[TVPADDRW] = 0; eieio();
  1033. for (x = 0; x < 0x200; x++) {
  1034. par->cmap_regs[TVPCRDAT] = 0x00; eieio();
  1035. }
  1036. for (x = 0; x < 0x200; x++) {
  1037. par->cmap_regs[TVPCRDAT] = 0xff; eieio();
  1038. }
  1039. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1040. par->cmap_regs[TVPIDATA] &= 0x03; eieio();
  1041. for (y = 0; y < height; y++)
  1042. for (x = 0; x < width >> 3; x++) {
  1043. par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
  1044. par->cmap_regs[TVPCRDAT] = 0xff; eieio();
  1045. }
  1046. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1047. par->cmap_regs[TVPIDATA] |= 0x08; eieio();
  1048. for (y = 0; y < height; y++)
  1049. for (x = 0; x < width >> 3; x++) {
  1050. par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
  1051. par->cmap_regs[TVPCRDAT] = 0xff; eieio();
  1052. }
  1053. par->cmap_regs[TVPCADRW] = 0x00; eieio();
  1054. for (x = 0; x < 12; x++)
  1055. par->cmap_regs[TVPCDATA] = fgc; eieio();
  1056. }
  1057. return 1;
  1058. }
  1059. static void
  1060. imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on)
  1061. {
  1062. if (par->ramdac == IBM) {
  1063. par->cmap_regs[PIDXHI] = 0; eieio();
  1064. if (!on) {
  1065. par->cmap_regs[PIDXLO] = CURSCTL; eieio();
  1066. par->cmap_regs[PIDXDATA] = 0x00; eieio();
  1067. } else {
  1068. par->cmap_regs[PIDXLO] = CURSXHI; eieio();
  1069. par->cmap_regs[PIDXDATA] = d->dx >> 8; eieio();
  1070. par->cmap_regs[PIDXLO] = CURSXLO; eieio();
  1071. par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio();
  1072. par->cmap_regs[PIDXLO] = CURSYHI; eieio();
  1073. par->cmap_regs[PIDXDATA] = d->dy >> 8; eieio();
  1074. par->cmap_regs[PIDXLO] = CURSYLO; eieio();
  1075. par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio();
  1076. par->cmap_regs[PIDXLO] = CURSCTL; eieio();
  1077. par->cmap_regs[PIDXDATA] = 0x02; eieio();
  1078. }
  1079. } else {
  1080. if (!on) {
  1081. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1082. par->cmap_regs[TVPIDATA] = 0x00; eieio();
  1083. } else {
  1084. __u16 x = d->dx + 0x40, y = d->dy + 0x40;
  1085. par->cmap_regs[TVPCXPOH] = x >> 8; eieio();
  1086. par->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
  1087. par->cmap_regs[TVPCYPOH] = y >> 8; eieio();
  1088. par->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
  1089. par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
  1090. par->cmap_regs[TVPIDATA] = 0x02; eieio();
  1091. }
  1092. }
  1093. }
  1094. static int
  1095. imsttfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  1096. {
  1097. struct imstt_par *par = info->par;
  1098. u32 flags = cursor->set, fg, bg, xx, yy;
  1099. if (cursor->dest == NULL && cursor->rop == ROP_XOR)
  1100. return 1;
  1101. imstt_set_cursor(info, cursor, 0);
  1102. if (flags & FB_CUR_SETPOS) {
  1103. xx = cursor->image.dx - info->var.xoffset;
  1104. yy = cursor->image.dy - info->var.yoffset;
  1105. }
  1106. if (flags & FB_CUR_SETSIZE) {
  1107. }
  1108. if (flags & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
  1109. int fg_idx = cursor->image.fg_color;
  1110. int width = (cursor->image.width+7)/8;
  1111. u8 *dat = (u8 *) cursor->image.data;
  1112. u8 *dst = (u8 *) cursor->dest;
  1113. u8 *msk = (u8 *) cursor->mask;
  1114. switch (cursor->rop) {
  1115. case ROP_XOR:
  1116. for (i = 0; i < cursor->image.height; i++) {
  1117. for (j = 0; j < width; j++) {
  1118. d_idx = i * MAX_CURS/8 + j;
  1119. data[d_idx] = byte_rev[dat[s_idx] ^
  1120. dst[s_idx]];
  1121. mask[d_idx] = byte_rev[msk[s_idx]];
  1122. s_idx++;
  1123. }
  1124. }
  1125. break;
  1126. case ROP_COPY:
  1127. default:
  1128. for (i = 0; i < cursor->image.height; i++) {
  1129. for (j = 0; j < width; j++) {
  1130. d_idx = i * MAX_CURS/8 + j;
  1131. data[d_idx] = byte_rev[dat[s_idx]];
  1132. mask[d_idx] = byte_rev[msk[s_idx]];
  1133. s_idx++;
  1134. }
  1135. }
  1136. break;
  1137. }
  1138. fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
  1139. ((info->cmap.green[fg_idx] & 0xf8) << 2) |
  1140. ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
  1141. imsttfb_load_cursor_image(par, xx, yy, fgc);
  1142. }
  1143. if (cursor->enable)
  1144. imstt_set_cursor(info, cursor, 1);
  1145. return 0;
  1146. }
  1147. #endif
  1148. #define FBIMSTT_SETREG 0x545401
  1149. #define FBIMSTT_GETREG 0x545402
  1150. #define FBIMSTT_SETCMAPREG 0x545403
  1151. #define FBIMSTT_GETCMAPREG 0x545404
  1152. #define FBIMSTT_SETIDXREG 0x545405
  1153. #define FBIMSTT_GETIDXREG 0x545406
  1154. static int
  1155. imsttfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
  1156. {
  1157. struct imstt_par *par = info->par;
  1158. void __user *argp = (void __user *)arg;
  1159. __u32 reg[2];
  1160. __u8 idx[2];
  1161. switch (cmd) {
  1162. case FBIMSTT_SETREG:
  1163. if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1164. return -EFAULT;
  1165. write_reg_le32(par->dc_regs, reg[0], reg[1]);
  1166. return 0;
  1167. case FBIMSTT_GETREG:
  1168. if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1169. return -EFAULT;
  1170. reg[1] = read_reg_le32(par->dc_regs, reg[0]);
  1171. if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
  1172. return -EFAULT;
  1173. return 0;
  1174. case FBIMSTT_SETCMAPREG:
  1175. if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1176. return -EFAULT;
  1177. write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]);
  1178. return 0;
  1179. case FBIMSTT_GETCMAPREG:
  1180. if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
  1181. return -EFAULT;
  1182. reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]);
  1183. if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
  1184. return -EFAULT;
  1185. return 0;
  1186. case FBIMSTT_SETIDXREG:
  1187. if (copy_from_user(idx, argp, 2))
  1188. return -EFAULT;
  1189. par->cmap_regs[PIDXHI] = 0; eieio();
  1190. par->cmap_regs[PIDXLO] = idx[0]; eieio();
  1191. par->cmap_regs[PIDXDATA] = idx[1]; eieio();
  1192. return 0;
  1193. case FBIMSTT_GETIDXREG:
  1194. if (copy_from_user(idx, argp, 1))
  1195. return -EFAULT;
  1196. par->cmap_regs[PIDXHI] = 0; eieio();
  1197. par->cmap_regs[PIDXLO] = idx[0]; eieio();
  1198. idx[1] = par->cmap_regs[PIDXDATA];
  1199. if (copy_to_user((void __user *)(arg + 1), &idx[1], 1))
  1200. return -EFAULT;
  1201. return 0;
  1202. default:
  1203. return -ENOIOCTLCMD;
  1204. }
  1205. }
  1206. static struct pci_device_id imsttfb_pci_tbl[] = {
  1207. { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128,
  1208. PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM },
  1209. { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D,
  1210. PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP },
  1211. { 0, }
  1212. };
  1213. MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl);
  1214. static struct pci_driver imsttfb_pci_driver = {
  1215. .name = "imsttfb",
  1216. .id_table = imsttfb_pci_tbl,
  1217. .probe = imsttfb_probe,
  1218. .remove = __devexit_p(imsttfb_remove),
  1219. };
  1220. static struct fb_ops imsttfb_ops = {
  1221. .owner = THIS_MODULE,
  1222. .fb_check_var = imsttfb_check_var,
  1223. .fb_set_par = imsttfb_set_par,
  1224. .fb_setcolreg = imsttfb_setcolreg,
  1225. .fb_pan_display = imsttfb_pan_display,
  1226. .fb_blank = imsttfb_blank,
  1227. .fb_fillrect = imsttfb_fillrect,
  1228. .fb_copyarea = imsttfb_copyarea,
  1229. .fb_imageblit = cfb_imageblit,
  1230. .fb_ioctl = imsttfb_ioctl,
  1231. };
  1232. static void __devinit
  1233. init_imstt(struct fb_info *info)
  1234. {
  1235. struct imstt_par *par = info->par;
  1236. __u32 i, tmp, *ip, *end;
  1237. tmp = read_reg_le32(par->dc_regs, PRC);
  1238. if (par->ramdac == IBM)
  1239. info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000;
  1240. else
  1241. info->fix.smem_len = 0x800000;
  1242. ip = (__u32 *)info->screen_base;
  1243. end = (__u32 *)(info->screen_base + info->fix.smem_len);
  1244. while (ip < end)
  1245. *ip++ = 0;
  1246. /* initialize the card */
  1247. tmp = read_reg_le32(par->dc_regs, STGCTL);
  1248. write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
  1249. write_reg_le32(par->dc_regs, SSR, 0);
  1250. /* set default values for DAC registers */
  1251. if (par->ramdac == IBM) {
  1252. par->cmap_regs[PPMASK] = 0xff;
  1253. eieio();
  1254. par->cmap_regs[PIDXHI] = 0;
  1255. eieio();
  1256. for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) {
  1257. par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;
  1258. eieio();
  1259. par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;
  1260. eieio();
  1261. }
  1262. } else {
  1263. for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) {
  1264. par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;
  1265. eieio();
  1266. par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;
  1267. eieio();
  1268. }
  1269. }
  1270. #if USE_NV_MODES && defined(CONFIG_PPC)
  1271. {
  1272. int vmode = init_vmode, cmode = init_cmode;
  1273. if (vmode == -1) {
  1274. vmode = nvram_read_byte(NV_VMODE);
  1275. if (vmode <= 0 || vmode > VMODE_MAX)
  1276. vmode = VMODE_640_480_67;
  1277. }
  1278. if (cmode == -1) {
  1279. cmode = nvram_read_byte(NV_CMODE);
  1280. if (cmode < CMODE_8 || cmode > CMODE_32)
  1281. cmode = CMODE_8;
  1282. }
  1283. if (mac_vmode_to_var(vmode, cmode, &info->var)) {
  1284. info->var.xres = info->var.xres_virtual = INIT_XRES;
  1285. info->var.yres = info->var.yres_virtual = INIT_YRES;
  1286. info->var.bits_per_pixel = INIT_BPP;
  1287. }
  1288. }
  1289. #else
  1290. info->var.xres = info->var.xres_virtual = INIT_XRES;
  1291. info->var.yres = info->var.yres_virtual = INIT_YRES;
  1292. info->var.bits_per_pixel = INIT_BPP;
  1293. #endif
  1294. if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len
  1295. || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) {
  1296. printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
  1297. framebuffer_release(info);
  1298. return;
  1299. }
  1300. sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP");
  1301. info->fix.mmio_len = 0x1000;
  1302. info->fix.accel = FB_ACCEL_IMS_TWINTURBO;
  1303. info->fix.type = FB_TYPE_PACKED_PIXELS;
  1304. info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
  1305. : FB_VISUAL_DIRECTCOLOR;
  1306. info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3);
  1307. info->fix.xpanstep = 8;
  1308. info->fix.ypanstep = 1;
  1309. info->fix.ywrapstep = 0;
  1310. info->var.accel_flags = FB_ACCELF_TEXT;
  1311. // if (par->ramdac == IBM)
  1312. // imstt_cursor_init(info);
  1313. if (info->var.green.length == 6)
  1314. set_565(par);
  1315. else
  1316. set_555(par);
  1317. set_imstt_regvals(info, info->var.bits_per_pixel);
  1318. info->var.pixclock = 1000000 / getclkMHz(par);
  1319. info->fbops = &imsttfb_ops;
  1320. info->flags = FBINFO_DEFAULT |
  1321. FBINFO_HWACCEL_COPYAREA |
  1322. FBINFO_HWACCEL_FILLRECT |
  1323. FBINFO_HWACCEL_YPAN;
  1324. fb_alloc_cmap(&info->cmap, 0, 0);
  1325. if (register_framebuffer(info) < 0) {
  1326. framebuffer_release(info);
  1327. return;
  1328. }
  1329. tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
  1330. printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
  1331. info->node, info->fix.id, info->fix.smem_len >> 20, tmp);
  1332. }
  1333. static int __devinit
  1334. imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1335. {
  1336. unsigned long addr, size;
  1337. struct imstt_par *par;
  1338. struct fb_info *info;
  1339. #ifdef CONFIG_PPC_OF
  1340. struct device_node *dp;
  1341. dp = pci_device_to_OF_node(pdev);
  1342. if(dp)
  1343. printk(KERN_INFO "%s: OF name %s\n",__FUNCTION__, dp->name);
  1344. else
  1345. printk(KERN_ERR "imsttfb: no OF node for pci device\n");
  1346. #endif /* CONFIG_PPC_OF */
  1347. info = framebuffer_alloc(sizeof(struct imstt_par), &pdev->dev);
  1348. if (!info) {
  1349. printk(KERN_ERR "imsttfb: Can't allocate memory\n");
  1350. return -ENOMEM;
  1351. }
  1352. par = info->par;
  1353. addr = pci_resource_start (pdev, 0);
  1354. size = pci_resource_len (pdev, 0);
  1355. if (!request_mem_region(addr, size, "imsttfb")) {
  1356. printk(KERN_ERR "imsttfb: Can't reserve memory region\n");
  1357. framebuffer_release(info);
  1358. return -ENODEV;
  1359. }
  1360. switch (pdev->device) {
  1361. case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */
  1362. par->ramdac = IBM;
  1363. #ifdef CONFIG_PPC_OF
  1364. if (dp && ((strcmp(dp->name, "IMS,tt128mb8") == 0) ||
  1365. (strcmp(dp->name, "IMS,tt128mb8A") == 0)))
  1366. par->ramdac = TVP;
  1367. #endif /* CONFIG_PPC_OF */
  1368. break;
  1369. case PCI_DEVICE_ID_IMS_TT3D: /* IMS,tt3d */
  1370. par->ramdac = TVP;
  1371. break;
  1372. default:
  1373. printk(KERN_INFO "imsttfb: Device 0x%x unknown, "
  1374. "contact maintainer.\n", pdev->device);
  1375. release_mem_region(addr, size);
  1376. framebuffer_release(info);
  1377. return -ENODEV;
  1378. }
  1379. info->fix.smem_start = addr;
  1380. info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ?
  1381. 0x400000 : 0x800000);
  1382. info->fix.mmio_start = addr + 0x800000;
  1383. par->dc_regs = ioremap(addr + 0x800000, 0x1000);
  1384. par->cmap_regs_phys = addr + 0x840000;
  1385. par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
  1386. info->pseudo_palette = par->palette;
  1387. init_imstt(info);
  1388. pci_set_drvdata(pdev, info);
  1389. return 0;
  1390. }
  1391. static void __devexit
  1392. imsttfb_remove(struct pci_dev *pdev)
  1393. {
  1394. struct fb_info *info = pci_get_drvdata(pdev);
  1395. struct imstt_par *par = info->par;
  1396. int size = pci_resource_len(pdev, 0);
  1397. unregister_framebuffer(info);
  1398. iounmap(par->cmap_regs);
  1399. iounmap(par->dc_regs);
  1400. iounmap(info->screen_base);
  1401. release_mem_region(info->fix.smem_start, size);
  1402. framebuffer_release(info);
  1403. }
  1404. #ifndef MODULE
  1405. static int __init
  1406. imsttfb_setup(char *options)
  1407. {
  1408. char *this_opt;
  1409. if (!options || !*options)
  1410. return 0;
  1411. while ((this_opt = strsep(&options, ",")) != NULL) {
  1412. if (!strncmp(this_opt, "font:", 5)) {
  1413. char *p;
  1414. int i;
  1415. p = this_opt + 5;
  1416. for (i = 0; i < sizeof(fontname) - 1; i++)
  1417. if (!*p || *p == ' ' || *p == ',')
  1418. break;
  1419. memcpy(fontname, this_opt + 5, i);
  1420. fontname[i] = 0;
  1421. } else if (!strncmp(this_opt, "inverse", 7)) {
  1422. inverse = 1;
  1423. fb_invert_cmaps();
  1424. }
  1425. #if defined(CONFIG_PPC)
  1426. else if (!strncmp(this_opt, "vmode:", 6)) {
  1427. int vmode = simple_strtoul(this_opt+6, NULL, 0);
  1428. if (vmode > 0 && vmode <= VMODE_MAX)
  1429. init_vmode = vmode;
  1430. } else if (!strncmp(this_opt, "cmode:", 6)) {
  1431. int cmode = simple_strtoul(this_opt+6, NULL, 0);
  1432. switch (cmode) {
  1433. case CMODE_8:
  1434. case 8:
  1435. init_cmode = CMODE_8;
  1436. break;
  1437. case CMODE_16:
  1438. case 15:
  1439. case 16:
  1440. init_cmode = CMODE_16;
  1441. break;
  1442. case CMODE_32:
  1443. case 24:
  1444. case 32:
  1445. init_cmode = CMODE_32;
  1446. break;
  1447. }
  1448. }
  1449. #endif
  1450. }
  1451. return 0;
  1452. }
  1453. #endif /* MODULE */
  1454. static int __init imsttfb_init(void)
  1455. {
  1456. #ifndef MODULE
  1457. char *option = NULL;
  1458. if (fb_get_options("imsttfb", &option))
  1459. return -ENODEV;
  1460. imsttfb_setup(option);
  1461. #endif
  1462. return pci_register_driver(&imsttfb_pci_driver);
  1463. }
  1464. static void __exit imsttfb_exit(void)
  1465. {
  1466. pci_unregister_driver(&imsttfb_pci_driver);
  1467. }
  1468. MODULE_LICENSE("GPL");
  1469. module_init(imsttfb_init);
  1470. module_exit(imsttfb_exit);