gxt4500.c 21 KB

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  1. /*
  2. * Frame buffer device for IBM GXT4500P and GXT6000P display adaptors
  3. *
  4. * Copyright (C) 2006 Paul Mackerras, IBM Corp. <paulus@samba.org>
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/fb.h>
  9. #include <linux/console.h>
  10. #include <linux/pci.h>
  11. #include <linux/pci_ids.h>
  12. #include <linux/delay.h>
  13. #include <linux/string.h>
  14. #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
  15. #define PCI_DEVICE_ID_IBM_GXT6000P 0x170
  16. /* GXT4500P registers */
  17. /* Registers in PCI config space */
  18. #define CFG_ENDIAN0 0x40
  19. /* Misc control/status registers */
  20. #define STATUS 0x1000
  21. #define CTRL_REG0 0x1004
  22. #define CR0_HALT_DMA 0x4
  23. #define CR0_RASTER_RESET 0x8
  24. #define CR0_GEOM_RESET 0x10
  25. #define CR0_MEM_CTRLER_RESET 0x20
  26. /* Framebuffer control registers */
  27. #define FB_AB_CTRL 0x1100
  28. #define FB_CD_CTRL 0x1104
  29. #define FB_WID_CTRL 0x1108
  30. #define FB_Z_CTRL 0x110c
  31. #define FB_VGA_CTRL 0x1110
  32. #define REFRESH_AB_CTRL 0x1114
  33. #define REFRESH_CD_CTRL 0x1118
  34. #define FB_OVL_CTRL 0x111c
  35. #define FB_CTRL_TYPE 0x80000000
  36. #define FB_CTRL_WIDTH_MASK 0x007f0000
  37. #define FB_CTRL_WIDTH_SHIFT 16
  38. #define FB_CTRL_START_SEG_MASK 0x00003fff
  39. #define REFRESH_START 0x1098
  40. #define REFRESH_SIZE 0x109c
  41. /* "Direct" framebuffer access registers */
  42. #define DFA_FB_A 0x11e0
  43. #define DFA_FB_B 0x11e4
  44. #define DFA_FB_C 0x11e8
  45. #define DFA_FB_D 0x11ec
  46. #define DFA_FB_ENABLE 0x80000000
  47. #define DFA_FB_BASE_MASK 0x03f00000
  48. #define DFA_FB_STRIDE_1k 0x00000000
  49. #define DFA_FB_STRIDE_2k 0x00000010
  50. #define DFA_FB_STRIDE_4k 0x00000020
  51. #define DFA_PIX_8BIT 0x00000000
  52. #define DFA_PIX_16BIT_565 0x00000001
  53. #define DFA_PIX_16BIT_1555 0x00000002
  54. #define DFA_PIX_24BIT 0x00000004
  55. #define DFA_PIX_32BIT 0x00000005
  56. /* maps DFA_PIX_* to pixel size in bytes */
  57. static const unsigned char pixsize[] = {
  58. 1, 2, 2, 2, 4, 4
  59. };
  60. /* Display timing generator registers */
  61. #define DTG_CONTROL 0x1900
  62. #define DTG_CTL_SCREEN_REFRESH 2
  63. #define DTG_CTL_ENABLE 1
  64. #define DTG_HORIZ_EXTENT 0x1904
  65. #define DTG_HORIZ_DISPLAY 0x1908
  66. #define DTG_HSYNC_START 0x190c
  67. #define DTG_HSYNC_END 0x1910
  68. #define DTG_HSYNC_END_COMP 0x1914
  69. #define DTG_VERT_EXTENT 0x1918
  70. #define DTG_VERT_DISPLAY 0x191c
  71. #define DTG_VSYNC_START 0x1920
  72. #define DTG_VSYNC_END 0x1924
  73. #define DTG_VERT_SHORT 0x1928
  74. /* PLL/RAMDAC registers */
  75. #define DISP_CTL 0x402c
  76. #define DISP_CTL_OFF 2
  77. #define SYNC_CTL 0x4034
  78. #define SYNC_CTL_SYNC_ON_RGB 1
  79. #define SYNC_CTL_SYNC_OFF 2
  80. #define SYNC_CTL_HSYNC_INV 8
  81. #define SYNC_CTL_VSYNC_INV 0x10
  82. #define SYNC_CTL_HSYNC_OFF 0x20
  83. #define SYNC_CTL_VSYNC_OFF 0x40
  84. #define PLL_M 0x4040
  85. #define PLL_N 0x4044
  86. #define PLL_POSTDIV 0x4048
  87. #define PLL_C 0x404c
  88. /* Hardware cursor */
  89. #define CURSOR_X 0x4078
  90. #define CURSOR_Y 0x407c
  91. #define CURSOR_HOTSPOT 0x4080
  92. #define CURSOR_MODE 0x4084
  93. #define CURSOR_MODE_OFF 0
  94. #define CURSOR_MODE_4BPP 1
  95. #define CURSOR_PIXMAP 0x5000
  96. #define CURSOR_CMAP 0x7400
  97. /* Window attribute table */
  98. #define WAT_FMT 0x4100
  99. #define WAT_FMT_24BIT 0
  100. #define WAT_FMT_16BIT_565 1
  101. #define WAT_FMT_16BIT_1555 2
  102. #define WAT_FMT_32BIT 3 /* 0 vs. 3 is a guess */
  103. #define WAT_FMT_8BIT_332 9
  104. #define WAT_FMT_8BIT 0xa
  105. #define WAT_FMT_NO_CMAP 4 /* ORd in to other values */
  106. #define WAT_CMAP_OFFSET 0x4104 /* 4-bit value gets << 6 */
  107. #define WAT_CTRL 0x4108
  108. #define WAT_CTRL_SEL_B 1 /* select B buffer if 1 */
  109. #define WAT_CTRL_NO_INC 2
  110. #define WAT_GAMMA_CTRL 0x410c
  111. #define WAT_GAMMA_DISABLE 1 /* disables gamma cmap */
  112. #define WAT_OVL_CTRL 0x430c /* controls overlay */
  113. /* Indexed by DFA_PIX_* values */
  114. static const unsigned char watfmt[] = {
  115. WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0,
  116. WAT_FMT_24BIT, WAT_FMT_32BIT
  117. };
  118. /* Colormap array; 1k entries of 4 bytes each */
  119. #define CMAP 0x6000
  120. #define readreg(par, reg) readl((par)->regs + (reg))
  121. #define writereg(par, reg, val) writel((val), (par)->regs + (reg))
  122. struct gxt4500_par {
  123. void __iomem *regs;
  124. int pixfmt; /* pixel format, see DFA_PIX_* values */
  125. /* PLL parameters */
  126. int refclk_ps; /* ref clock period in picoseconds */
  127. int pll_m; /* ref clock divisor */
  128. int pll_n; /* VCO divisor */
  129. int pll_pd1; /* first post-divisor */
  130. int pll_pd2; /* second post-divisor */
  131. u32 pseudo_palette[16]; /* used in color blits */
  132. };
  133. /* mode requested by user */
  134. static char *mode_option;
  135. /* default mode: 1280x1024 @ 60 Hz, 8 bpp */
  136. static const struct fb_videomode defaultmode __devinitdata = {
  137. .refresh = 60,
  138. .xres = 1280,
  139. .yres = 1024,
  140. .pixclock = 9295,
  141. .left_margin = 248,
  142. .right_margin = 48,
  143. .upper_margin = 38,
  144. .lower_margin = 1,
  145. .hsync_len = 112,
  146. .vsync_len = 3,
  147. .vmode = FB_VMODE_NONINTERLACED
  148. };
  149. /* List of supported cards */
  150. enum gxt_cards {
  151. GXT4500P,
  152. GXT6000P
  153. };
  154. /* Card-specific information */
  155. static const struct cardinfo {
  156. int refclk_ps; /* period of PLL reference clock in ps */
  157. const char *cardname;
  158. } cardinfo[] = {
  159. [GXT4500P] = { .refclk_ps = 9259, .cardname = "IBM GXT4500P" },
  160. [GXT6000P] = { .refclk_ps = 40000, .cardname = "IBM GXT6000P" },
  161. };
  162. /*
  163. * The refclk and VCO dividers appear to use a linear feedback shift
  164. * register, which gets reloaded when it reaches a terminal value, at
  165. * which point the divider output is toggled. Thus one can obtain
  166. * whatever divisor is required by putting the appropriate value into
  167. * the reload register. For a divisor of N, one puts the value from
  168. * the LFSR sequence that comes N-1 places before the terminal value
  169. * into the reload register.
  170. */
  171. static const unsigned char mdivtab[] = {
  172. /* 1 */ 0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a,
  173. /* 10 */ 0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11,
  174. /* 20 */ 0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d,
  175. /* 30 */ 0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02,
  176. /* 40 */ 0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e,
  177. /* 50 */ 0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e,
  178. /* 60 */ 0x1f, 0x0f, 0x07, 0x03, 0x01,
  179. };
  180. static const unsigned char ndivtab[] = {
  181. /* 2 */ 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e,
  182. /* 10 */ 0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e,
  183. /* 20 */ 0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf,
  184. /* 30 */ 0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc,
  185. /* 40 */ 0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8,
  186. /* 50 */ 0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6,
  187. /* 60 */ 0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62,
  188. /* 70 */ 0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57,
  189. /* 80 */ 0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94,
  190. /* 90 */ 0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79,
  191. /* 100 */ 0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24,
  192. /* 110 */ 0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45,
  193. /* 120 */ 0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d,
  194. /* 130 */ 0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e,
  195. /* 140 */ 0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98,
  196. /* 150 */ 0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2,
  197. /* 160 */ 0x69,
  198. };
  199. static int calc_pll(int period_ps, struct gxt4500_par *par)
  200. {
  201. int m, n, pdiv1, pdiv2, postdiv;
  202. int pll_period, best_error, t, intf;
  203. /* only deal with range 5MHz - 300MHz */
  204. if (period_ps < 3333 || period_ps > 200000)
  205. return -1;
  206. best_error = 1000000;
  207. for (pdiv1 = 1; pdiv1 <= 8; ++pdiv1) {
  208. for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) {
  209. postdiv = pdiv1 * pdiv2;
  210. pll_period = (period_ps + postdiv - 1) / postdiv;
  211. /* keep pll in range 350..600 MHz */
  212. if (pll_period < 1666 || pll_period > 2857)
  213. continue;
  214. for (m = 1; m <= 64; ++m) {
  215. intf = m * par->refclk_ps;
  216. if (intf > 500000)
  217. break;
  218. n = intf * postdiv / period_ps;
  219. if (n < 3 || n > 160)
  220. continue;
  221. t = par->refclk_ps * m * postdiv / n;
  222. t -= period_ps;
  223. if (t >= 0 && t < best_error) {
  224. par->pll_m = m;
  225. par->pll_n = n;
  226. par->pll_pd1 = pdiv1;
  227. par->pll_pd2 = pdiv2;
  228. best_error = t;
  229. }
  230. }
  231. }
  232. }
  233. if (best_error == 1000000)
  234. return -1;
  235. return 0;
  236. }
  237. static int calc_pixclock(struct gxt4500_par *par)
  238. {
  239. return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2
  240. / par->pll_n;
  241. }
  242. static int gxt4500_var_to_par(struct fb_var_screeninfo *var,
  243. struct gxt4500_par *par)
  244. {
  245. if (var->xres + var->xoffset > var->xres_virtual ||
  246. var->yres + var->yoffset > var->yres_virtual ||
  247. var->xres_virtual > 4096)
  248. return -EINVAL;
  249. if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
  250. return -EINVAL;
  251. if (calc_pll(var->pixclock, par) < 0)
  252. return -EINVAL;
  253. switch (var->bits_per_pixel) {
  254. case 32:
  255. if (var->transp.length)
  256. par->pixfmt = DFA_PIX_32BIT;
  257. else
  258. par->pixfmt = DFA_PIX_24BIT;
  259. break;
  260. case 24:
  261. par->pixfmt = DFA_PIX_24BIT;
  262. break;
  263. case 16:
  264. if (var->green.length == 5)
  265. par->pixfmt = DFA_PIX_16BIT_1555;
  266. else
  267. par->pixfmt = DFA_PIX_16BIT_565;
  268. break;
  269. case 8:
  270. par->pixfmt = DFA_PIX_8BIT;
  271. break;
  272. default:
  273. return -EINVAL;
  274. }
  275. return 0;
  276. }
  277. static const struct fb_bitfield eightbits = {0, 8};
  278. static const struct fb_bitfield nobits = {0, 0};
  279. static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var,
  280. int pixfmt)
  281. {
  282. var->bits_per_pixel = pixsize[pixfmt] * 8;
  283. var->red = eightbits;
  284. var->green = eightbits;
  285. var->blue = eightbits;
  286. var->transp = nobits;
  287. switch (pixfmt) {
  288. case DFA_PIX_16BIT_565:
  289. var->red.length = 5;
  290. var->green.length = 6;
  291. var->blue.length = 5;
  292. break;
  293. case DFA_PIX_16BIT_1555:
  294. var->red.length = 5;
  295. var->green.length = 5;
  296. var->blue.length = 5;
  297. var->transp.length = 1;
  298. break;
  299. case DFA_PIX_32BIT:
  300. var->transp.length = 8;
  301. break;
  302. }
  303. if (pixfmt != DFA_PIX_8BIT) {
  304. var->green.offset = var->red.length;
  305. var->blue.offset = var->green.offset + var->green.length;
  306. if (var->transp.length)
  307. var->transp.offset =
  308. var->blue.offset + var->blue.length;
  309. }
  310. }
  311. static int gxt4500_check_var(struct fb_var_screeninfo *var,
  312. struct fb_info *info)
  313. {
  314. struct gxt4500_par par;
  315. int err;
  316. par = *(struct gxt4500_par *)info->par;
  317. err = gxt4500_var_to_par(var, &par);
  318. if (!err) {
  319. var->pixclock = calc_pixclock(&par);
  320. gxt4500_unpack_pixfmt(var, par.pixfmt);
  321. }
  322. return err;
  323. }
  324. static int gxt4500_set_par(struct fb_info *info)
  325. {
  326. struct gxt4500_par *par = info->par;
  327. struct fb_var_screeninfo *var = &info->var;
  328. int err;
  329. u32 ctrlreg, tmp;
  330. unsigned int dfa_ctl, pixfmt, stride;
  331. unsigned int wid_tiles, i;
  332. unsigned int prefetch_pix, htot;
  333. struct gxt4500_par save_par;
  334. save_par = *par;
  335. err = gxt4500_var_to_par(var, par);
  336. if (err) {
  337. *par = save_par;
  338. return err;
  339. }
  340. /* turn off DTG for now */
  341. ctrlreg = readreg(par, DTG_CONTROL);
  342. ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH);
  343. writereg(par, DTG_CONTROL, ctrlreg);
  344. /* set PLL registers */
  345. tmp = readreg(par, PLL_C) & ~0x7f;
  346. if (par->pll_n < 38)
  347. tmp |= 0x29;
  348. if (par->pll_n < 69)
  349. tmp |= 0x35;
  350. else if (par->pll_n < 100)
  351. tmp |= 0x76;
  352. else
  353. tmp |= 0x7e;
  354. writereg(par, PLL_C, tmp);
  355. writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
  356. writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
  357. tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1);
  358. if (par->pll_pd1 == 8 || par->pll_pd2 == 8) {
  359. /* work around erratum */
  360. writereg(par, PLL_POSTDIV, tmp | 0x9);
  361. udelay(1);
  362. }
  363. writereg(par, PLL_POSTDIV, tmp);
  364. msleep(20);
  365. /* turn off hardware cursor */
  366. writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
  367. /* reset raster engine */
  368. writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
  369. udelay(10);
  370. writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16);
  371. /* set display timing generator registers */
  372. htot = var->xres + var->left_margin + var->right_margin +
  373. var->hsync_len;
  374. writereg(par, DTG_HORIZ_EXTENT, htot - 1);
  375. writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1);
  376. writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1);
  377. writereg(par, DTG_HSYNC_END,
  378. var->xres + var->right_margin + var->hsync_len - 1);
  379. writereg(par, DTG_HSYNC_END_COMP,
  380. var->xres + var->right_margin + var->hsync_len - 1);
  381. writereg(par, DTG_VERT_EXTENT,
  382. var->yres + var->upper_margin + var->lower_margin +
  383. var->vsync_len - 1);
  384. writereg(par, DTG_VERT_DISPLAY, var->yres - 1);
  385. writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1);
  386. writereg(par, DTG_VSYNC_END,
  387. var->yres + var->lower_margin + var->vsync_len - 1);
  388. prefetch_pix = 3300000 / var->pixclock;
  389. if (prefetch_pix >= htot)
  390. prefetch_pix = htot - 1;
  391. writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1);
  392. ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH;
  393. writereg(par, DTG_CONTROL, ctrlreg);
  394. /* calculate stride in DFA aperture */
  395. if (var->xres_virtual > 2048) {
  396. stride = 4096;
  397. dfa_ctl = DFA_FB_STRIDE_4k;
  398. } else if (var->xres_virtual > 1024) {
  399. stride = 2048;
  400. dfa_ctl = DFA_FB_STRIDE_2k;
  401. } else {
  402. stride = 1024;
  403. dfa_ctl = DFA_FB_STRIDE_1k;
  404. }
  405. /* Set up framebuffer definition */
  406. wid_tiles = (var->xres_virtual + 63) >> 6;
  407. /* XXX add proper FB allocation here someday */
  408. writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  409. writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  410. writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  411. writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  412. writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
  413. writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres);
  414. /* Set up framebuffer access by CPU */
  415. pixfmt = par->pixfmt;
  416. dfa_ctl |= DFA_FB_ENABLE | pixfmt;
  417. writereg(par, DFA_FB_A, dfa_ctl);
  418. /*
  419. * Set up window attribute table.
  420. * We set all WAT entries the same so it doesn't matter what the
  421. * window ID (WID) plane contains.
  422. */
  423. for (i = 0; i < 32; ++i) {
  424. writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]);
  425. writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);
  426. writereg(par, WAT_CTRL + (i << 4), 0);
  427. writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE);
  428. }
  429. /* Set sync polarity etc. */
  430. ctrlreg = readreg(par, SYNC_CTL) &
  431. ~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV |
  432. SYNC_CTL_VSYNC_INV);
  433. if (var->sync & FB_SYNC_ON_GREEN)
  434. ctrlreg |= SYNC_CTL_SYNC_ON_RGB;
  435. if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
  436. ctrlreg |= SYNC_CTL_HSYNC_INV;
  437. if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
  438. ctrlreg |= SYNC_CTL_VSYNC_INV;
  439. writereg(par, SYNC_CTL, ctrlreg);
  440. info->fix.line_length = stride * pixsize[pixfmt];
  441. info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR:
  442. FB_VISUAL_DIRECTCOLOR;
  443. return 0;
  444. }
  445. static int gxt4500_setcolreg(unsigned int reg, unsigned int red,
  446. unsigned int green, unsigned int blue,
  447. unsigned int transp, struct fb_info *info)
  448. {
  449. u32 cmap_entry;
  450. struct gxt4500_par *par = info->par;
  451. if (reg > 1023)
  452. return 1;
  453. cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
  454. (green & 0xff00) | (blue >> 8);
  455. writereg(par, CMAP + reg * 4, cmap_entry);
  456. if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) {
  457. u32 *pal = info->pseudo_palette;
  458. u32 val = reg;
  459. switch (par->pixfmt) {
  460. case DFA_PIX_16BIT_565:
  461. val |= (reg << 11) | (reg << 6);
  462. break;
  463. case DFA_PIX_16BIT_1555:
  464. val |= (reg << 10) | (reg << 5);
  465. break;
  466. case DFA_PIX_32BIT:
  467. val |= (reg << 24);
  468. /* fall through */
  469. case DFA_PIX_24BIT:
  470. val |= (reg << 16) | (reg << 8);
  471. break;
  472. }
  473. pal[reg] = val;
  474. }
  475. return 0;
  476. }
  477. static int gxt4500_pan_display(struct fb_var_screeninfo *var,
  478. struct fb_info *info)
  479. {
  480. struct gxt4500_par *par = info->par;
  481. if (var->xoffset & 7)
  482. return -EINVAL;
  483. if (var->xoffset + var->xres > var->xres_virtual ||
  484. var->yoffset + var->yres > var->yres_virtual)
  485. return -EINVAL;
  486. writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
  487. return 0;
  488. }
  489. static int gxt4500_blank(int blank, struct fb_info *info)
  490. {
  491. struct gxt4500_par *par = info->par;
  492. int ctrl, dctl;
  493. ctrl = readreg(par, SYNC_CTL);
  494. ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF);
  495. dctl = readreg(par, DISP_CTL);
  496. dctl |= DISP_CTL_OFF;
  497. switch (blank) {
  498. case FB_BLANK_UNBLANK:
  499. dctl &= ~DISP_CTL_OFF;
  500. break;
  501. case FB_BLANK_POWERDOWN:
  502. ctrl |= SYNC_CTL_SYNC_OFF;
  503. break;
  504. case FB_BLANK_HSYNC_SUSPEND:
  505. ctrl |= SYNC_CTL_HSYNC_OFF;
  506. break;
  507. case FB_BLANK_VSYNC_SUSPEND:
  508. ctrl |= SYNC_CTL_VSYNC_OFF;
  509. break;
  510. default: ;
  511. }
  512. writereg(par, SYNC_CTL, ctrl);
  513. writereg(par, DISP_CTL, dctl);
  514. return 0;
  515. }
  516. static const struct fb_fix_screeninfo gxt4500_fix __devinitdata = {
  517. .id = "IBM GXT4500P",
  518. .type = FB_TYPE_PACKED_PIXELS,
  519. .visual = FB_VISUAL_PSEUDOCOLOR,
  520. .xpanstep = 8,
  521. .ypanstep = 1,
  522. .mmio_len = 0x20000,
  523. };
  524. static struct fb_ops gxt4500_ops = {
  525. .owner = THIS_MODULE,
  526. .fb_check_var = gxt4500_check_var,
  527. .fb_set_par = gxt4500_set_par,
  528. .fb_setcolreg = gxt4500_setcolreg,
  529. .fb_pan_display = gxt4500_pan_display,
  530. .fb_blank = gxt4500_blank,
  531. .fb_fillrect = cfb_fillrect,
  532. .fb_copyarea = cfb_copyarea,
  533. .fb_imageblit = cfb_imageblit,
  534. };
  535. /* PCI functions */
  536. static int __devinit gxt4500_probe(struct pci_dev *pdev,
  537. const struct pci_device_id *ent)
  538. {
  539. int err;
  540. unsigned long reg_phys, fb_phys;
  541. struct gxt4500_par *par;
  542. struct fb_info *info;
  543. struct fb_var_screeninfo var;
  544. enum gxt_cards cardtype;
  545. err = pci_enable_device(pdev);
  546. if (err) {
  547. dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n",
  548. err);
  549. return err;
  550. }
  551. reg_phys = pci_resource_start(pdev, 0);
  552. if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0),
  553. "gxt4500 regs")) {
  554. dev_err(&pdev->dev, "gxt4500: cannot get registers\n");
  555. goto err_nodev;
  556. }
  557. fb_phys = pci_resource_start(pdev, 1);
  558. if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1),
  559. "gxt4500 FB")) {
  560. dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n");
  561. goto err_free_regs;
  562. }
  563. info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev);
  564. if (!info) {
  565. dev_err(&pdev->dev, "gxt4500: cannot alloc FB info record");
  566. goto err_free_fb;
  567. }
  568. par = info->par;
  569. cardtype = ent->driver_data;
  570. par->refclk_ps = cardinfo[cardtype].refclk_ps;
  571. info->fix = gxt4500_fix;
  572. strlcpy(info->fix.id, cardinfo[cardtype].cardname,
  573. sizeof(info->fix.id));
  574. info->pseudo_palette = par->pseudo_palette;
  575. info->fix.mmio_start = reg_phys;
  576. par->regs = ioremap(reg_phys, pci_resource_len(pdev, 0));
  577. if (!par->regs) {
  578. dev_err(&pdev->dev, "gxt4500: cannot map registers\n");
  579. goto err_free_all;
  580. }
  581. info->fix.smem_start = fb_phys;
  582. info->fix.smem_len = pci_resource_len(pdev, 1);
  583. info->screen_base = ioremap(fb_phys, pci_resource_len(pdev, 1));
  584. if (!info->screen_base) {
  585. dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n");
  586. goto err_unmap_regs;
  587. }
  588. pci_set_drvdata(pdev, info);
  589. /* Set byte-swapping for DFA aperture for all pixel sizes */
  590. pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300);
  591. info->fbops = &gxt4500_ops;
  592. info->flags = FBINFO_FLAG_DEFAULT;
  593. err = fb_alloc_cmap(&info->cmap, 256, 0);
  594. if (err) {
  595. dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n");
  596. goto err_unmap_all;
  597. }
  598. gxt4500_blank(FB_BLANK_UNBLANK, info);
  599. if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) {
  600. dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n");
  601. goto err_free_cmap;
  602. }
  603. info->var = var;
  604. if (gxt4500_set_par(info)) {
  605. printk(KERN_ERR "gxt4500: cannot set video mode\n");
  606. goto err_free_cmap;
  607. }
  608. if (register_framebuffer(info) < 0) {
  609. dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n");
  610. goto err_free_cmap;
  611. }
  612. printk(KERN_INFO "fb%d: %s frame buffer device\n",
  613. info->node, info->fix.id);
  614. return 0;
  615. err_free_cmap:
  616. fb_dealloc_cmap(&info->cmap);
  617. err_unmap_all:
  618. iounmap(info->screen_base);
  619. err_unmap_regs:
  620. iounmap(par->regs);
  621. err_free_all:
  622. framebuffer_release(info);
  623. err_free_fb:
  624. release_mem_region(fb_phys, pci_resource_len(pdev, 1));
  625. err_free_regs:
  626. release_mem_region(reg_phys, pci_resource_len(pdev, 0));
  627. err_nodev:
  628. return -ENODEV;
  629. }
  630. static void __devexit gxt4500_remove(struct pci_dev *pdev)
  631. {
  632. struct fb_info *info = pci_get_drvdata(pdev);
  633. struct gxt4500_par *par;
  634. if (!info)
  635. return;
  636. par = info->par;
  637. unregister_framebuffer(info);
  638. fb_dealloc_cmap(&info->cmap);
  639. iounmap(par->regs);
  640. iounmap(info->screen_base);
  641. release_mem_region(pci_resource_start(pdev, 0),
  642. pci_resource_len(pdev, 0));
  643. release_mem_region(pci_resource_start(pdev, 1),
  644. pci_resource_len(pdev, 1));
  645. framebuffer_release(info);
  646. }
  647. /* supported chipsets */
  648. static const struct pci_device_id gxt4500_pci_tbl[] = {
  649. { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P),
  650. .driver_data = GXT4500P },
  651. { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6000P),
  652. .driver_data = GXT6000P },
  653. { 0 }
  654. };
  655. MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl);
  656. static struct pci_driver gxt4500_driver = {
  657. .name = "gxt4500",
  658. .id_table = gxt4500_pci_tbl,
  659. .probe = gxt4500_probe,
  660. .remove = __devexit_p(gxt4500_remove),
  661. };
  662. static int __devinit gxt4500_init(void)
  663. {
  664. #ifndef MODULE
  665. if (fb_get_options("gxt4500", &mode_option))
  666. return -ENODEV;
  667. #endif
  668. return pci_register_driver(&gxt4500_driver);
  669. }
  670. module_init(gxt4500_init);
  671. static void __exit gxt4500_exit(void)
  672. {
  673. pci_unregister_driver(&gxt4500_driver);
  674. }
  675. module_exit(gxt4500_exit);
  676. MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>");
  677. MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P/6000P");
  678. MODULE_LICENSE("GPL");
  679. module_param(mode_option, charp, 0);
  680. MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\"");