ffb.c 25 KB

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  1. /* ffb.c: Creator/Elite3D frame buffer driver
  2. *
  3. * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
  4. * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
  5. *
  6. * Driver layout based loosely on tgafb.c, see that file for credits.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/errno.h>
  11. #include <linux/string.h>
  12. #include <linux/slab.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/fb.h>
  16. #include <linux/mm.h>
  17. #include <linux/timer.h>
  18. #include <asm/io.h>
  19. #include <asm/upa.h>
  20. #include <asm/prom.h>
  21. #include <asm/of_device.h>
  22. #include <asm/fbio.h>
  23. #include "sbuslib.h"
  24. /*
  25. * Local functions.
  26. */
  27. static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
  28. unsigned, struct fb_info *);
  29. static int ffb_blank(int, struct fb_info *);
  30. static void ffb_init_fix(struct fb_info *);
  31. static void ffb_imageblit(struct fb_info *, const struct fb_image *);
  32. static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
  33. static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
  34. static int ffb_sync(struct fb_info *);
  35. static int ffb_mmap(struct fb_info *, struct vm_area_struct *);
  36. static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long);
  37. static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
  38. /*
  39. * Frame buffer operations
  40. */
  41. static struct fb_ops ffb_ops = {
  42. .owner = THIS_MODULE,
  43. .fb_setcolreg = ffb_setcolreg,
  44. .fb_blank = ffb_blank,
  45. .fb_pan_display = ffb_pan_display,
  46. .fb_fillrect = ffb_fillrect,
  47. .fb_copyarea = ffb_copyarea,
  48. .fb_imageblit = ffb_imageblit,
  49. .fb_sync = ffb_sync,
  50. .fb_mmap = ffb_mmap,
  51. .fb_ioctl = ffb_ioctl,
  52. #ifdef CONFIG_COMPAT
  53. .fb_compat_ioctl = sbusfb_compat_ioctl,
  54. #endif
  55. };
  56. /* Register layout and definitions */
  57. #define FFB_SFB8R_VOFF 0x00000000
  58. #define FFB_SFB8G_VOFF 0x00400000
  59. #define FFB_SFB8B_VOFF 0x00800000
  60. #define FFB_SFB8X_VOFF 0x00c00000
  61. #define FFB_SFB32_VOFF 0x01000000
  62. #define FFB_SFB64_VOFF 0x02000000
  63. #define FFB_FBC_REGS_VOFF 0x04000000
  64. #define FFB_BM_FBC_REGS_VOFF 0x04002000
  65. #define FFB_DFB8R_VOFF 0x04004000
  66. #define FFB_DFB8G_VOFF 0x04404000
  67. #define FFB_DFB8B_VOFF 0x04804000
  68. #define FFB_DFB8X_VOFF 0x04c04000
  69. #define FFB_DFB24_VOFF 0x05004000
  70. #define FFB_DFB32_VOFF 0x06004000
  71. #define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */
  72. #define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */
  73. #define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */
  74. #define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */
  75. #define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */
  76. #define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */
  77. #define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */
  78. #define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */
  79. #define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */
  80. #define FFB_FBC_KREGS_VOFF 0x0bc04000
  81. #define FFB_DAC_VOFF 0x0bc06000
  82. #define FFB_PROM_VOFF 0x0bc08000
  83. #define FFB_EXP_VOFF 0x0bc18000
  84. #define FFB_SFB8R_POFF 0x04000000UL
  85. #define FFB_SFB8G_POFF 0x04400000UL
  86. #define FFB_SFB8B_POFF 0x04800000UL
  87. #define FFB_SFB8X_POFF 0x04c00000UL
  88. #define FFB_SFB32_POFF 0x05000000UL
  89. #define FFB_SFB64_POFF 0x06000000UL
  90. #define FFB_FBC_REGS_POFF 0x00600000UL
  91. #define FFB_BM_FBC_REGS_POFF 0x00600000UL
  92. #define FFB_DFB8R_POFF 0x01000000UL
  93. #define FFB_DFB8G_POFF 0x01400000UL
  94. #define FFB_DFB8B_POFF 0x01800000UL
  95. #define FFB_DFB8X_POFF 0x01c00000UL
  96. #define FFB_DFB24_POFF 0x02000000UL
  97. #define FFB_DFB32_POFF 0x03000000UL
  98. #define FFB_FBC_KREGS_POFF 0x00610000UL
  99. #define FFB_DAC_POFF 0x00400000UL
  100. #define FFB_PROM_POFF 0x00000000UL
  101. #define FFB_EXP_POFF 0x00200000UL
  102. #define FFB_DFB422A_POFF 0x09000000UL
  103. #define FFB_DFB422AD_POFF 0x09800000UL
  104. #define FFB_DFB24B_POFF 0x0a000000UL
  105. #define FFB_DFB422B_POFF 0x0b000000UL
  106. #define FFB_DFB422BD_POFF 0x0b800000UL
  107. #define FFB_SFB16Z_POFF 0x0c800000UL
  108. #define FFB_SFB8Z_POFF 0x0c000000UL
  109. #define FFB_SFB422_POFF 0x0d000000UL
  110. #define FFB_SFB422D_POFF 0x0d800000UL
  111. /* Draw operations */
  112. #define FFB_DRAWOP_DOT 0x00
  113. #define FFB_DRAWOP_AADOT 0x01
  114. #define FFB_DRAWOP_BRLINECAP 0x02
  115. #define FFB_DRAWOP_BRLINEOPEN 0x03
  116. #define FFB_DRAWOP_DDLINE 0x04
  117. #define FFB_DRAWOP_AALINE 0x05
  118. #define FFB_DRAWOP_TRIANGLE 0x06
  119. #define FFB_DRAWOP_POLYGON 0x07
  120. #define FFB_DRAWOP_RECTANGLE 0x08
  121. #define FFB_DRAWOP_FASTFILL 0x09
  122. #define FFB_DRAWOP_BCOPY 0x0a
  123. #define FFB_DRAWOP_VSCROLL 0x0b
  124. /* Pixel processor control */
  125. /* Force WID */
  126. #define FFB_PPC_FW_DISABLE 0x800000
  127. #define FFB_PPC_FW_ENABLE 0xc00000
  128. /* Auxiliary clip */
  129. #define FFB_PPC_ACE_DISABLE 0x040000
  130. #define FFB_PPC_ACE_AUX_SUB 0x080000
  131. #define FFB_PPC_ACE_AUX_ADD 0x0c0000
  132. /* Depth cue */
  133. #define FFB_PPC_DCE_DISABLE 0x020000
  134. #define FFB_PPC_DCE_ENABLE 0x030000
  135. /* Alpha blend */
  136. #define FFB_PPC_ABE_DISABLE 0x008000
  137. #define FFB_PPC_ABE_ENABLE 0x00c000
  138. /* View clip */
  139. #define FFB_PPC_VCE_DISABLE 0x001000
  140. #define FFB_PPC_VCE_2D 0x002000
  141. #define FFB_PPC_VCE_3D 0x003000
  142. /* Area pattern */
  143. #define FFB_PPC_APE_DISABLE 0x000800
  144. #define FFB_PPC_APE_ENABLE 0x000c00
  145. /* Transparent background */
  146. #define FFB_PPC_TBE_OPAQUE 0x000200
  147. #define FFB_PPC_TBE_TRANSPARENT 0x000300
  148. /* Z source */
  149. #define FFB_PPC_ZS_VAR 0x000080
  150. #define FFB_PPC_ZS_CONST 0x0000c0
  151. /* Y source */
  152. #define FFB_PPC_YS_VAR 0x000020
  153. #define FFB_PPC_YS_CONST 0x000030
  154. /* X source */
  155. #define FFB_PPC_XS_WID 0x000004
  156. #define FFB_PPC_XS_VAR 0x000008
  157. #define FFB_PPC_XS_CONST 0x00000c
  158. /* Color (BGR) source */
  159. #define FFB_PPC_CS_VAR 0x000002
  160. #define FFB_PPC_CS_CONST 0x000003
  161. #define FFB_ROP_NEW 0x83
  162. #define FFB_ROP_OLD 0x85
  163. #define FFB_ROP_NEW_XOR_OLD 0x86
  164. #define FFB_UCSR_FIFO_MASK 0x00000fff
  165. #define FFB_UCSR_FB_BUSY 0x01000000
  166. #define FFB_UCSR_RP_BUSY 0x02000000
  167. #define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
  168. #define FFB_UCSR_READ_ERR 0x40000000
  169. #define FFB_UCSR_FIFO_OVFL 0x80000000
  170. #define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
  171. struct ffb_fbc {
  172. /* Next vertex registers */
  173. u32 xxx1[3];
  174. u32 alpha;
  175. u32 red;
  176. u32 green;
  177. u32 blue;
  178. u32 depth;
  179. u32 y;
  180. u32 x;
  181. u32 xxx2[2];
  182. u32 ryf;
  183. u32 rxf;
  184. u32 xxx3[2];
  185. u32 dmyf;
  186. u32 dmxf;
  187. u32 xxx4[2];
  188. u32 ebyi;
  189. u32 ebxi;
  190. u32 xxx5[2];
  191. u32 by;
  192. u32 bx;
  193. u32 dy;
  194. u32 dx;
  195. u32 bh;
  196. u32 bw;
  197. u32 xxx6[2];
  198. u32 xxx7[32];
  199. /* Setup unit vertex state register */
  200. u32 suvtx;
  201. u32 xxx8[63];
  202. /* Control registers */
  203. u32 ppc;
  204. u32 wid;
  205. u32 fg;
  206. u32 bg;
  207. u32 consty;
  208. u32 constz;
  209. u32 xclip;
  210. u32 dcss;
  211. u32 vclipmin;
  212. u32 vclipmax;
  213. u32 vclipzmin;
  214. u32 vclipzmax;
  215. u32 dcsf;
  216. u32 dcsb;
  217. u32 dczf;
  218. u32 dczb;
  219. u32 xxx9;
  220. u32 blendc;
  221. u32 blendc1;
  222. u32 blendc2;
  223. u32 fbramitc;
  224. u32 fbc;
  225. u32 rop;
  226. u32 cmp;
  227. u32 matchab;
  228. u32 matchc;
  229. u32 magnab;
  230. u32 magnc;
  231. u32 fbcfg0;
  232. u32 fbcfg1;
  233. u32 fbcfg2;
  234. u32 fbcfg3;
  235. u32 ppcfg;
  236. u32 pick;
  237. u32 fillmode;
  238. u32 fbramwac;
  239. u32 pmask;
  240. u32 xpmask;
  241. u32 ypmask;
  242. u32 zpmask;
  243. u32 clip0min;
  244. u32 clip0max;
  245. u32 clip1min;
  246. u32 clip1max;
  247. u32 clip2min;
  248. u32 clip2max;
  249. u32 clip3min;
  250. u32 clip3max;
  251. /* New 3dRAM III support regs */
  252. u32 rawblend2;
  253. u32 rawpreblend;
  254. u32 rawstencil;
  255. u32 rawstencilctl;
  256. u32 threedram1;
  257. u32 threedram2;
  258. u32 passin;
  259. u32 rawclrdepth;
  260. u32 rawpmask;
  261. u32 rawcsrc;
  262. u32 rawmatch;
  263. u32 rawmagn;
  264. u32 rawropblend;
  265. u32 rawcmp;
  266. u32 rawwac;
  267. u32 fbramid;
  268. u32 drawop;
  269. u32 xxx10[2];
  270. u32 fontlpat;
  271. u32 xxx11;
  272. u32 fontxy;
  273. u32 fontw;
  274. u32 fontinc;
  275. u32 font;
  276. u32 xxx12[3];
  277. u32 blend2;
  278. u32 preblend;
  279. u32 stencil;
  280. u32 stencilctl;
  281. u32 xxx13[4];
  282. u32 dcss1;
  283. u32 dcss2;
  284. u32 dcss3;
  285. u32 widpmask;
  286. u32 dcs2;
  287. u32 dcs3;
  288. u32 dcs4;
  289. u32 xxx14;
  290. u32 dcd2;
  291. u32 dcd3;
  292. u32 dcd4;
  293. u32 xxx15;
  294. u32 pattern[32];
  295. u32 xxx16[256];
  296. u32 devid;
  297. u32 xxx17[63];
  298. u32 ucsr;
  299. u32 xxx18[31];
  300. u32 mer;
  301. };
  302. struct ffb_dac {
  303. u32 type;
  304. u32 value;
  305. u32 type2;
  306. u32 value2;
  307. };
  308. #define FFB_DAC_UCTRL 0x1001 /* User Control */
  309. #define FFB_DAC_UCTRL_MANREV 0x00000f00 /* 4-bit Manufacturing Revision */
  310. #define FFB_DAC_UCTRL_MANREV_SHIFT 8
  311. #define FFB_DAC_TGEN 0x6000 /* Timing Generator */
  312. #define FFB_DAC_TGEN_VIDE 0x00000001 /* Video Enable */
  313. #define FFB_DAC_DID 0x8000 /* Device Identification */
  314. #define FFB_DAC_DID_PNUM 0x0ffff000 /* Device Part Number */
  315. #define FFB_DAC_DID_PNUM_SHIFT 12
  316. #define FFB_DAC_DID_REV 0xf0000000 /* Device Revision */
  317. #define FFB_DAC_DID_REV_SHIFT 28
  318. #define FFB_DAC_CUR_CTRL 0x100
  319. #define FFB_DAC_CUR_CTRL_P0 0x00000001
  320. #define FFB_DAC_CUR_CTRL_P1 0x00000002
  321. struct ffb_par {
  322. spinlock_t lock;
  323. struct ffb_fbc __iomem *fbc;
  324. struct ffb_dac __iomem *dac;
  325. u32 flags;
  326. #define FFB_FLAG_AFB 0x00000001 /* AFB m3 or m6 */
  327. #define FFB_FLAG_BLANKED 0x00000002 /* screen is blanked */
  328. #define FFB_FLAG_INVCURSOR 0x00000004 /* DAC has inverted cursor logic */
  329. u32 fg_cache __attribute__((aligned (8)));
  330. u32 bg_cache;
  331. u32 rop_cache;
  332. int fifo_cache;
  333. unsigned long physbase;
  334. unsigned long fbsize;
  335. int board_type;
  336. };
  337. static void FFBFifo(struct ffb_par *par, int n)
  338. {
  339. struct ffb_fbc __iomem *fbc;
  340. int cache = par->fifo_cache;
  341. if (cache - n < 0) {
  342. fbc = par->fbc;
  343. do { cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK) - 8;
  344. } while (cache - n < 0);
  345. }
  346. par->fifo_cache = cache - n;
  347. }
  348. static void FFBWait(struct ffb_par *par)
  349. {
  350. struct ffb_fbc __iomem *fbc;
  351. int limit = 10000;
  352. fbc = par->fbc;
  353. do {
  354. if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
  355. break;
  356. if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
  357. upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
  358. }
  359. udelay(10);
  360. } while(--limit > 0);
  361. }
  362. static int ffb_sync(struct fb_info *p)
  363. {
  364. struct ffb_par *par = (struct ffb_par *) p->par;
  365. FFBWait(par);
  366. return 0;
  367. }
  368. static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
  369. {
  370. if (par->rop_cache != rop) {
  371. FFBFifo(par, 1);
  372. upa_writel(rop, &par->fbc->rop);
  373. par->rop_cache = rop;
  374. }
  375. }
  376. static void ffb_switch_from_graph(struct ffb_par *par)
  377. {
  378. struct ffb_fbc __iomem *fbc = par->fbc;
  379. struct ffb_dac __iomem *dac = par->dac;
  380. unsigned long flags;
  381. spin_lock_irqsave(&par->lock, flags);
  382. FFBWait(par);
  383. par->fifo_cache = 0;
  384. FFBFifo(par, 7);
  385. upa_writel(FFB_PPC_VCE_DISABLE|FFB_PPC_TBE_OPAQUE|
  386. FFB_PPC_APE_DISABLE|FFB_PPC_CS_CONST,
  387. &fbc->ppc);
  388. upa_writel(0x2000707f, &fbc->fbc);
  389. upa_writel(par->rop_cache, &fbc->rop);
  390. upa_writel(0xffffffff, &fbc->pmask);
  391. upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
  392. upa_writel(par->fg_cache, &fbc->fg);
  393. upa_writel(par->bg_cache, &fbc->bg);
  394. FFBWait(par);
  395. /* Disable cursor. */
  396. upa_writel(FFB_DAC_CUR_CTRL, &dac->type2);
  397. if (par->flags & FFB_FLAG_INVCURSOR)
  398. upa_writel(0, &dac->value2);
  399. else
  400. upa_writel((FFB_DAC_CUR_CTRL_P0 |
  401. FFB_DAC_CUR_CTRL_P1), &dac->value2);
  402. spin_unlock_irqrestore(&par->lock, flags);
  403. }
  404. static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  405. {
  406. struct ffb_par *par = (struct ffb_par *) info->par;
  407. /* We just use this to catch switches out of
  408. * graphics mode.
  409. */
  410. ffb_switch_from_graph(par);
  411. if (var->xoffset || var->yoffset || var->vmode)
  412. return -EINVAL;
  413. return 0;
  414. }
  415. /**
  416. * ffb_fillrect - REQUIRED function. Can use generic routines if
  417. * non acclerated hardware and packed pixel based.
  418. * Draws a rectangle on the screen.
  419. *
  420. * @info: frame buffer structure that represents a single frame buffer
  421. * @rect: structure defining the rectagle and operation.
  422. */
  423. static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  424. {
  425. struct ffb_par *par = (struct ffb_par *) info->par;
  426. struct ffb_fbc __iomem *fbc = par->fbc;
  427. unsigned long flags;
  428. u32 fg;
  429. BUG_ON(rect->rop != ROP_COPY && rect->rop != ROP_XOR);
  430. fg = ((u32 *)info->pseudo_palette)[rect->color];
  431. spin_lock_irqsave(&par->lock, flags);
  432. if (fg != par->fg_cache) {
  433. FFBFifo(par, 1);
  434. upa_writel(fg, &fbc->fg);
  435. par->fg_cache = fg;
  436. }
  437. ffb_rop(par, (rect->rop == ROP_COPY ?
  438. FFB_ROP_NEW :
  439. FFB_ROP_NEW_XOR_OLD));
  440. FFBFifo(par, 5);
  441. upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
  442. upa_writel(rect->dy, &fbc->by);
  443. upa_writel(rect->dx, &fbc->bx);
  444. upa_writel(rect->height, &fbc->bh);
  445. upa_writel(rect->width, &fbc->bw);
  446. spin_unlock_irqrestore(&par->lock, flags);
  447. }
  448. /**
  449. * ffb_copyarea - REQUIRED function. Can use generic routines if
  450. * non acclerated hardware and packed pixel based.
  451. * Copies on area of the screen to another area.
  452. *
  453. * @info: frame buffer structure that represents a single frame buffer
  454. * @area: structure defining the source and destination.
  455. */
  456. static void
  457. ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  458. {
  459. struct ffb_par *par = (struct ffb_par *) info->par;
  460. struct ffb_fbc __iomem *fbc = par->fbc;
  461. unsigned long flags;
  462. if (area->dx != area->sx ||
  463. area->dy == area->sy) {
  464. cfb_copyarea(info, area);
  465. return;
  466. }
  467. spin_lock_irqsave(&par->lock, flags);
  468. ffb_rop(par, FFB_ROP_OLD);
  469. FFBFifo(par, 7);
  470. upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
  471. upa_writel(area->sy, &fbc->by);
  472. upa_writel(area->sx, &fbc->bx);
  473. upa_writel(area->dy, &fbc->dy);
  474. upa_writel(area->dx, &fbc->dx);
  475. upa_writel(area->height, &fbc->bh);
  476. upa_writel(area->width, &fbc->bw);
  477. spin_unlock_irqrestore(&par->lock, flags);
  478. }
  479. /**
  480. * ffb_imageblit - REQUIRED function. Can use generic routines if
  481. * non acclerated hardware and packed pixel based.
  482. * Copies a image from system memory to the screen.
  483. *
  484. * @info: frame buffer structure that represents a single frame buffer
  485. * @image: structure defining the image.
  486. */
  487. static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
  488. {
  489. struct ffb_par *par = (struct ffb_par *) info->par;
  490. struct ffb_fbc __iomem *fbc = par->fbc;
  491. const u8 *data = image->data;
  492. unsigned long flags;
  493. u32 fg, bg, xy;
  494. u64 fgbg;
  495. int i, width, stride;
  496. if (image->depth > 1) {
  497. cfb_imageblit(info, image);
  498. return;
  499. }
  500. fg = ((u32 *)info->pseudo_palette)[image->fg_color];
  501. bg = ((u32 *)info->pseudo_palette)[image->bg_color];
  502. fgbg = ((u64) fg << 32) | (u64) bg;
  503. xy = (image->dy << 16) | image->dx;
  504. width = image->width;
  505. stride = ((width + 7) >> 3);
  506. spin_lock_irqsave(&par->lock, flags);
  507. if (fgbg != *(u64 *)&par->fg_cache) {
  508. FFBFifo(par, 2);
  509. upa_writeq(fgbg, &fbc->fg);
  510. *(u64 *)&par->fg_cache = fgbg;
  511. }
  512. if (width >= 32) {
  513. FFBFifo(par, 1);
  514. upa_writel(32, &fbc->fontw);
  515. }
  516. while (width >= 32) {
  517. const u8 *next_data = data + 4;
  518. FFBFifo(par, 1);
  519. upa_writel(xy, &fbc->fontxy);
  520. xy += (32 << 0);
  521. for (i = 0; i < image->height; i++) {
  522. u32 val = (((u32)data[0] << 24) |
  523. ((u32)data[1] << 16) |
  524. ((u32)data[2] << 8) |
  525. ((u32)data[3] << 0));
  526. FFBFifo(par, 1);
  527. upa_writel(val, &fbc->font);
  528. data += stride;
  529. }
  530. data = next_data;
  531. width -= 32;
  532. }
  533. if (width) {
  534. FFBFifo(par, 2);
  535. upa_writel(width, &fbc->fontw);
  536. upa_writel(xy, &fbc->fontxy);
  537. for (i = 0; i < image->height; i++) {
  538. u32 val = (((u32)data[0] << 24) |
  539. ((u32)data[1] << 16) |
  540. ((u32)data[2] << 8) |
  541. ((u32)data[3] << 0));
  542. FFBFifo(par, 1);
  543. upa_writel(val, &fbc->font);
  544. data += stride;
  545. }
  546. }
  547. spin_unlock_irqrestore(&par->lock, flags);
  548. }
  549. static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
  550. {
  551. var->red.offset = 0;
  552. var->red.length = 8;
  553. var->green.offset = 8;
  554. var->green.length = 8;
  555. var->blue.offset = 16;
  556. var->blue.length = 8;
  557. var->transp.offset = 0;
  558. var->transp.length = 0;
  559. }
  560. /**
  561. * ffb_setcolreg - Optional function. Sets a color register.
  562. * @regno: boolean, 0 copy local, 1 get_user() function
  563. * @red: frame buffer colormap structure
  564. * @green: The green value which can be up to 16 bits wide
  565. * @blue: The blue value which can be up to 16 bits wide.
  566. * @transp: If supported the alpha value which can be up to 16 bits wide.
  567. * @info: frame buffer info structure
  568. */
  569. static int ffb_setcolreg(unsigned regno,
  570. unsigned red, unsigned green, unsigned blue,
  571. unsigned transp, struct fb_info *info)
  572. {
  573. u32 value;
  574. if (regno >= 256)
  575. return 1;
  576. red >>= 8;
  577. green >>= 8;
  578. blue >>= 8;
  579. value = (blue << 16) | (green << 8) | red;
  580. ((u32 *)info->pseudo_palette)[regno] = value;
  581. return 0;
  582. }
  583. /**
  584. * ffb_blank - Optional function. Blanks the display.
  585. * @blank_mode: the blank mode we want.
  586. * @info: frame buffer structure that represents a single frame buffer
  587. */
  588. static int
  589. ffb_blank(int blank, struct fb_info *info)
  590. {
  591. struct ffb_par *par = (struct ffb_par *) info->par;
  592. struct ffb_dac __iomem *dac = par->dac;
  593. unsigned long flags;
  594. u32 val;
  595. int i;
  596. spin_lock_irqsave(&par->lock, flags);
  597. FFBWait(par);
  598. upa_writel(FFB_DAC_TGEN, &dac->type);
  599. val = upa_readl(&dac->value);
  600. switch (blank) {
  601. case FB_BLANK_UNBLANK: /* Unblanking */
  602. val |= FFB_DAC_TGEN_VIDE;
  603. par->flags &= ~FFB_FLAG_BLANKED;
  604. break;
  605. case FB_BLANK_NORMAL: /* Normal blanking */
  606. case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
  607. case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
  608. case FB_BLANK_POWERDOWN: /* Poweroff */
  609. val &= ~FFB_DAC_TGEN_VIDE;
  610. par->flags |= FFB_FLAG_BLANKED;
  611. break;
  612. }
  613. upa_writel(FFB_DAC_TGEN, &dac->type);
  614. upa_writel(val, &dac->value);
  615. for (i = 0; i < 10; i++) {
  616. upa_writel(FFB_DAC_TGEN, &dac->type);
  617. upa_readl(&dac->value);
  618. }
  619. spin_unlock_irqrestore(&par->lock, flags);
  620. return 0;
  621. }
  622. static struct sbus_mmap_map ffb_mmap_map[] = {
  623. {
  624. .voff = FFB_SFB8R_VOFF,
  625. .poff = FFB_SFB8R_POFF,
  626. .size = 0x0400000
  627. },
  628. {
  629. .voff = FFB_SFB8G_VOFF,
  630. .poff = FFB_SFB8G_POFF,
  631. .size = 0x0400000
  632. },
  633. {
  634. .voff = FFB_SFB8B_VOFF,
  635. .poff = FFB_SFB8B_POFF,
  636. .size = 0x0400000
  637. },
  638. {
  639. .voff = FFB_SFB8X_VOFF,
  640. .poff = FFB_SFB8X_POFF,
  641. .size = 0x0400000
  642. },
  643. {
  644. .voff = FFB_SFB32_VOFF,
  645. .poff = FFB_SFB32_POFF,
  646. .size = 0x1000000
  647. },
  648. {
  649. .voff = FFB_SFB64_VOFF,
  650. .poff = FFB_SFB64_POFF,
  651. .size = 0x2000000
  652. },
  653. {
  654. .voff = FFB_FBC_REGS_VOFF,
  655. .poff = FFB_FBC_REGS_POFF,
  656. .size = 0x0002000
  657. },
  658. {
  659. .voff = FFB_BM_FBC_REGS_VOFF,
  660. .poff = FFB_BM_FBC_REGS_POFF,
  661. .size = 0x0002000
  662. },
  663. {
  664. .voff = FFB_DFB8R_VOFF,
  665. .poff = FFB_DFB8R_POFF,
  666. .size = 0x0400000
  667. },
  668. {
  669. .voff = FFB_DFB8G_VOFF,
  670. .poff = FFB_DFB8G_POFF,
  671. .size = 0x0400000
  672. },
  673. {
  674. .voff = FFB_DFB8B_VOFF,
  675. .poff = FFB_DFB8B_POFF,
  676. .size = 0x0400000
  677. },
  678. {
  679. .voff = FFB_DFB8X_VOFF,
  680. .poff = FFB_DFB8X_POFF,
  681. .size = 0x0400000
  682. },
  683. {
  684. .voff = FFB_DFB24_VOFF,
  685. .poff = FFB_DFB24_POFF,
  686. .size = 0x1000000
  687. },
  688. {
  689. .voff = FFB_DFB32_VOFF,
  690. .poff = FFB_DFB32_POFF,
  691. .size = 0x1000000
  692. },
  693. {
  694. .voff = FFB_FBC_KREGS_VOFF,
  695. .poff = FFB_FBC_KREGS_POFF,
  696. .size = 0x0002000
  697. },
  698. {
  699. .voff = FFB_DAC_VOFF,
  700. .poff = FFB_DAC_POFF,
  701. .size = 0x0002000
  702. },
  703. {
  704. .voff = FFB_PROM_VOFF,
  705. .poff = FFB_PROM_POFF,
  706. .size = 0x0010000
  707. },
  708. {
  709. .voff = FFB_EXP_VOFF,
  710. .poff = FFB_EXP_POFF,
  711. .size = 0x0002000
  712. },
  713. {
  714. .voff = FFB_DFB422A_VOFF,
  715. .poff = FFB_DFB422A_POFF,
  716. .size = 0x0800000
  717. },
  718. {
  719. .voff = FFB_DFB422AD_VOFF,
  720. .poff = FFB_DFB422AD_POFF,
  721. .size = 0x0800000
  722. },
  723. {
  724. .voff = FFB_DFB24B_VOFF,
  725. .poff = FFB_DFB24B_POFF,
  726. .size = 0x1000000
  727. },
  728. {
  729. .voff = FFB_DFB422B_VOFF,
  730. .poff = FFB_DFB422B_POFF,
  731. .size = 0x0800000
  732. },
  733. {
  734. .voff = FFB_DFB422BD_VOFF,
  735. .poff = FFB_DFB422BD_POFF,
  736. .size = 0x0800000
  737. },
  738. {
  739. .voff = FFB_SFB16Z_VOFF,
  740. .poff = FFB_SFB16Z_POFF,
  741. .size = 0x0800000
  742. },
  743. {
  744. .voff = FFB_SFB8Z_VOFF,
  745. .poff = FFB_SFB8Z_POFF,
  746. .size = 0x0800000
  747. },
  748. {
  749. .voff = FFB_SFB422_VOFF,
  750. .poff = FFB_SFB422_POFF,
  751. .size = 0x0800000
  752. },
  753. {
  754. .voff = FFB_SFB422D_VOFF,
  755. .poff = FFB_SFB422D_POFF,
  756. .size = 0x0800000
  757. },
  758. { .size = 0 }
  759. };
  760. static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma)
  761. {
  762. struct ffb_par *par = (struct ffb_par *)info->par;
  763. return sbusfb_mmap_helper(ffb_mmap_map,
  764. par->physbase, par->fbsize,
  765. 0, vma);
  766. }
  767. static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  768. {
  769. struct ffb_par *par = (struct ffb_par *) info->par;
  770. return sbusfb_ioctl_helper(cmd, arg, info,
  771. FBTYPE_CREATOR, 24, par->fbsize);
  772. }
  773. /*
  774. * Initialisation
  775. */
  776. static void
  777. ffb_init_fix(struct fb_info *info)
  778. {
  779. struct ffb_par *par = (struct ffb_par *)info->par;
  780. const char *ffb_type_name;
  781. if (!(par->flags & FFB_FLAG_AFB)) {
  782. if ((par->board_type & 0x7) == 0x3)
  783. ffb_type_name = "Creator 3D";
  784. else
  785. ffb_type_name = "Creator";
  786. } else
  787. ffb_type_name = "Elite 3D";
  788. strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
  789. info->fix.type = FB_TYPE_PACKED_PIXELS;
  790. info->fix.visual = FB_VISUAL_TRUECOLOR;
  791. /* Framebuffer length is the same regardless of resolution. */
  792. info->fix.line_length = 8192;
  793. info->fix.accel = FB_ACCEL_SUN_CREATOR;
  794. }
  795. struct all_info {
  796. struct fb_info info;
  797. struct ffb_par par;
  798. u32 pseudo_palette[256];
  799. };
  800. static int ffb_init_one(struct of_device *op)
  801. {
  802. struct device_node *dp = op->node;
  803. struct ffb_fbc __iomem *fbc;
  804. struct ffb_dac __iomem *dac;
  805. struct all_info *all;
  806. int err;
  807. u32 dac_pnum, dac_rev, dac_mrev;
  808. all = kzalloc(sizeof(*all), GFP_KERNEL);
  809. if (!all)
  810. return -ENOMEM;
  811. spin_lock_init(&all->par.lock);
  812. all->par.fbc = of_ioremap(&op->resource[2], 0,
  813. sizeof(struct ffb_fbc), "ffb fbc");
  814. if (!all->par.fbc) {
  815. kfree(all);
  816. return -ENOMEM;
  817. }
  818. all->par.dac = of_ioremap(&op->resource[1], 0,
  819. sizeof(struct ffb_dac), "ffb dac");
  820. if (!all->par.dac) {
  821. of_iounmap(&op->resource[2],
  822. all->par.fbc, sizeof(struct ffb_fbc));
  823. kfree(all);
  824. return -ENOMEM;
  825. }
  826. all->par.rop_cache = FFB_ROP_NEW;
  827. all->par.physbase = op->resource[0].start;
  828. /* Don't mention copyarea, so SCROLL_REDRAW is always
  829. * used. It is the fastest on this chip.
  830. */
  831. all->info.flags = (FBINFO_DEFAULT |
  832. /* FBINFO_HWACCEL_COPYAREA | */
  833. FBINFO_HWACCEL_FILLRECT |
  834. FBINFO_HWACCEL_IMAGEBLIT);
  835. all->info.fbops = &ffb_ops;
  836. all->info.screen_base = (char *) all->par.physbase + FFB_DFB24_POFF;
  837. all->info.par = &all->par;
  838. all->info.pseudo_palette = all->pseudo_palette;
  839. sbusfb_fill_var(&all->info.var, dp->node, 32);
  840. all->par.fbsize = PAGE_ALIGN(all->info.var.xres *
  841. all->info.var.yres *
  842. 4);
  843. ffb_fixup_var_rgb(&all->info.var);
  844. all->info.var.accel_flags = FB_ACCELF_TEXT;
  845. if (!strcmp(dp->name, "SUNW,afb"))
  846. all->par.flags |= FFB_FLAG_AFB;
  847. all->par.board_type = of_getintprop_default(dp, "board_type", 0);
  848. fbc = all->par.fbc;
  849. if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
  850. upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
  851. dac = all->par.dac;
  852. upa_writel(FFB_DAC_DID, &dac->type);
  853. dac_pnum = upa_readl(&dac->value);
  854. dac_rev = (dac_pnum & FFB_DAC_DID_REV) >> FFB_DAC_DID_REV_SHIFT;
  855. dac_pnum = (dac_pnum & FFB_DAC_DID_PNUM) >> FFB_DAC_DID_PNUM_SHIFT;
  856. upa_writel(FFB_DAC_UCTRL, &dac->type);
  857. dac_mrev = upa_readl(&dac->value);
  858. dac_mrev = (dac_mrev & FFB_DAC_UCTRL_MANREV) >>
  859. FFB_DAC_UCTRL_MANREV_SHIFT;
  860. /* Elite3D has different DAC revision numbering, and no DAC revisions
  861. * have the reversed meaning of cursor enable. Otherwise, Pacifica 1
  862. * ramdacs with manufacturing revision less than 3 have inverted
  863. * cursor logic. We identify Pacifica 1 as not Pacifica 2, the
  864. * latter having a part number value of 0x236e.
  865. */
  866. if ((all->par.flags & FFB_FLAG_AFB) || dac_pnum == 0x236e) {
  867. all->par.flags &= ~FFB_FLAG_INVCURSOR;
  868. } else {
  869. if (dac_mrev < 3)
  870. all->par.flags |= FFB_FLAG_INVCURSOR;
  871. }
  872. ffb_switch_from_graph(&all->par);
  873. /* Unblank it just to be sure. When there are multiple
  874. * FFB/AFB cards in the system, or it is not the OBP
  875. * chosen console, it will have video outputs off in
  876. * the DAC.
  877. */
  878. ffb_blank(0, &all->info);
  879. if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
  880. printk(KERN_ERR "ffb: Could not allocate color map.\n");
  881. of_iounmap(&op->resource[2],
  882. all->par.fbc, sizeof(struct ffb_fbc));
  883. of_iounmap(&op->resource[1],
  884. all->par.dac, sizeof(struct ffb_dac));
  885. kfree(all);
  886. return -ENOMEM;
  887. }
  888. ffb_init_fix(&all->info);
  889. err = register_framebuffer(&all->info);
  890. if (err < 0) {
  891. printk(KERN_ERR "ffb: Could not register framebuffer.\n");
  892. fb_dealloc_cmap(&all->info.cmap);
  893. of_iounmap(&op->resource[2],
  894. all->par.fbc, sizeof(struct ffb_fbc));
  895. of_iounmap(&op->resource[1],
  896. all->par.dac, sizeof(struct ffb_dac));
  897. kfree(all);
  898. return err;
  899. }
  900. dev_set_drvdata(&op->dev, all);
  901. printk("%s: %s at %016lx, type %d, "
  902. "DAC pnum[%x] rev[%d] manuf_rev[%d]\n",
  903. dp->full_name,
  904. ((all->par.flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
  905. all->par.physbase, all->par.board_type,
  906. dac_pnum, dac_rev, dac_mrev);
  907. return 0;
  908. }
  909. static int __devinit ffb_probe(struct of_device *dev, const struct of_device_id *match)
  910. {
  911. struct of_device *op = to_of_device(&dev->dev);
  912. return ffb_init_one(op);
  913. }
  914. static int __devexit ffb_remove(struct of_device *op)
  915. {
  916. struct all_info *all = dev_get_drvdata(&op->dev);
  917. unregister_framebuffer(&all->info);
  918. fb_dealloc_cmap(&all->info.cmap);
  919. of_iounmap(&op->resource[2], all->par.fbc, sizeof(struct ffb_fbc));
  920. of_iounmap(&op->resource[1], all->par.dac, sizeof(struct ffb_dac));
  921. kfree(all);
  922. dev_set_drvdata(&op->dev, NULL);
  923. return 0;
  924. }
  925. static struct of_device_id ffb_match[] = {
  926. {
  927. .name = "SUNW,ffb",
  928. },
  929. {
  930. .name = "SUNW,afb",
  931. },
  932. {},
  933. };
  934. MODULE_DEVICE_TABLE(of, ffb_match);
  935. static struct of_platform_driver ffb_driver = {
  936. .name = "ffb",
  937. .match_table = ffb_match,
  938. .probe = ffb_probe,
  939. .remove = __devexit_p(ffb_remove),
  940. };
  941. int __init ffb_init(void)
  942. {
  943. if (fb_get_options("ffb", NULL))
  944. return -ENODEV;
  945. return of_register_driver(&ffb_driver, &of_bus_type);
  946. }
  947. void __exit ffb_exit(void)
  948. {
  949. of_unregister_driver(&ffb_driver);
  950. }
  951. module_init(ffb_init);
  952. module_exit(ffb_exit);
  953. MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
  954. MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
  955. MODULE_VERSION("2.0");
  956. MODULE_LICENSE("GPL");