dnfb.c 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302
  1. #include <linux/kernel.h>
  2. #include <linux/errno.h>
  3. #include <linux/string.h>
  4. #include <linux/mm.h>
  5. #include <linux/slab.h>
  6. #include <linux/delay.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/platform_device.h>
  9. #include <asm/setup.h>
  10. #include <asm/system.h>
  11. #include <asm/irq.h>
  12. #include <asm/amigahw.h>
  13. #include <asm/amigaints.h>
  14. #include <asm/apollohw.h>
  15. #include <linux/fb.h>
  16. #include <linux/module.h>
  17. /* apollo video HW definitions */
  18. /*
  19. * Control Registers. IOBASE + $x
  20. *
  21. * Note: these are the Memory/IO BASE definitions for a mono card set to the
  22. * alternate address
  23. *
  24. * Control 3A and 3B serve identical functions except that 3A
  25. * deals with control 1 and 3b deals with Color LUT reg.
  26. */
  27. #define AP_IOBASE 0x3b0 /* Base address of 1 plane board. */
  28. #define AP_STATUS isaIO2mem(AP_IOBASE+0) /* Status register. Read */
  29. #define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0) /* Write Enable Register Write */
  30. #define AP_DEVICE_ID isaIO2mem(AP_IOBASE+1) /* Device ID Register. Read */
  31. #define AP_ROP_1 isaIO2mem(AP_IOBASE+2) /* Raster Operation reg. Write Word */
  32. #define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4) /* Diagnostic Memory Request. Write Word */
  33. #define AP_CONTROL_0 isaIO2mem(AP_IOBASE+8) /* Control Register 0. Read/Write */
  34. #define AP_CONTROL_1 isaIO2mem(AP_IOBASE+0xa) /* Control Register 1. Read/Write */
  35. #define AP_CONTROL_3A isaIO2mem(AP_IOBASE+0xe) /* Control Register 3a. Read/Write */
  36. #define AP_CONTROL_2 isaIO2mem(AP_IOBASE+0xc) /* Control Register 2. Read/Write */
  37. #define FRAME_BUFFER_START 0x0FA0000
  38. #define FRAME_BUFFER_LEN 0x40000
  39. /* CREG 0 */
  40. #define VECTOR_MODE 0x40 /* 010x.xxxx */
  41. #define DBLT_MODE 0x80 /* 100x.xxxx */
  42. #define NORMAL_MODE 0xE0 /* 111x.xxxx */
  43. #define SHIFT_BITS 0x1F /* xxx1.1111 */
  44. /* other bits are Shift value */
  45. /* CREG 1 */
  46. #define AD_BLT 0x80 /* 1xxx.xxxx */
  47. #define NORMAL 0x80 /* 1xxx.xxxx */ /* What is happening here ?? */
  48. #define INVERSE 0x00 /* 0xxx.xxxx */ /* Clearing this reverses the screen */
  49. #define PIX_BLT 0x00 /* 0xxx.xxxx */
  50. #define AD_HIBIT 0x40 /* xIxx.xxxx */
  51. #define ROP_EN 0x10 /* xxx1.xxxx */
  52. #define DST_EQ_SRC 0x00 /* xxx0.xxxx */
  53. #define nRESET_SYNC 0x08 /* xxxx.1xxx */
  54. #define SYNC_ENAB 0x02 /* xxxx.xx1x */
  55. #define BLANK_DISP 0x00 /* xxxx.xxx0 */
  56. #define ENAB_DISP 0x01 /* xxxx.xxx1 */
  57. #define NORM_CREG1 (nRESET_SYNC | SYNC_ENAB | ENAB_DISP) /* no reset sync */
  58. /* CREG 2 */
  59. /*
  60. * Following 3 defines are common to 1, 4 and 8 plane.
  61. */
  62. #define S_DATA_1s 0x00 /* 00xx.xxxx */ /* set source to all 1's -- vector drawing */
  63. #define S_DATA_PIX 0x40 /* 01xx.xxxx */ /* takes source from ls-bits and replicates over 16 bits */
  64. #define S_DATA_PLN 0xC0 /* 11xx.xxxx */ /* normal, each data access =16-bits in
  65. one plane of image mem */
  66. /* CREG 3A/CREG 3B */
  67. # define RESET_CREG 0x80 /* 1000.0000 */
  68. /* ROP REG - all one nibble */
  69. /* ********* NOTE : this is used r0,r1,r2,r3 *********** */
  70. #define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) )
  71. #define DEST_ZERO 0x0
  72. #define SRC_AND_DEST 0x1
  73. #define SRC_AND_nDEST 0x2
  74. #define SRC 0x3
  75. #define nSRC_AND_DEST 0x4
  76. #define DEST 0x5
  77. #define SRC_XOR_DEST 0x6
  78. #define SRC_OR_DEST 0x7
  79. #define SRC_NOR_DEST 0x8
  80. #define SRC_XNOR_DEST 0x9
  81. #define nDEST 0xA
  82. #define SRC_OR_nDEST 0xB
  83. #define nSRC 0xC
  84. #define nSRC_OR_DEST 0xD
  85. #define SRC_NAND_DEST 0xE
  86. #define DEST_ONE 0xF
  87. #define SWAP(A) ((A>>8) | ((A&0xff) <<8))
  88. /* frame buffer operations */
  89. static int dnfb_blank(int blank, struct fb_info *info);
  90. static void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
  91. static struct fb_ops dn_fb_ops = {
  92. .owner = THIS_MODULE,
  93. .fb_blank = dnfb_blank,
  94. .fb_fillrect = cfb_fillrect,
  95. .fb_copyarea = dnfb_copyarea,
  96. .fb_imageblit = cfb_imageblit,
  97. };
  98. struct fb_var_screeninfo dnfb_var __devinitdata = {
  99. .xres = 1280,
  100. .yres = 1024,
  101. .xres_virtual = 2048,
  102. .yres_virtual = 1024,
  103. .bits_per_pixel = 1,
  104. .height = -1,
  105. .width = -1,
  106. .vmode = FB_VMODE_NONINTERLACED,
  107. };
  108. static struct fb_fix_screeninfo dnfb_fix __devinitdata = {
  109. .id = "Apollo Mono",
  110. .smem_start = (FRAME_BUFFER_START + IO_BASE),
  111. .smem_len = FRAME_BUFFER_LEN,
  112. .type = FB_TYPE_PACKED_PIXELS,
  113. .visual = FB_VISUAL_MONO10,
  114. .line_length = 256,
  115. };
  116. static int dnfb_blank(int blank, struct fb_info *info)
  117. {
  118. if (blank)
  119. out_8(AP_CONTROL_3A, 0x0);
  120. else
  121. out_8(AP_CONTROL_3A, 0x1);
  122. return 0;
  123. }
  124. static
  125. void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  126. {
  127. int incr, y_delta, pre_read = 0, x_end, x_word_count;
  128. uint start_mask, end_mask, dest;
  129. ushort *src, dummy;
  130. short i, j;
  131. incr = (area->dy <= area->sy) ? 1 : -1;
  132. src = (ushort *)(info->screen_base + area->sy * info->fix.line_length +
  133. (area->sx >> 4));
  134. dest = area->dy * (info->fix.line_length >> 1) + (area->dx >> 4);
  135. if (incr > 0) {
  136. y_delta = (info->fix.line_length * 8) - area->sx - area->width;
  137. x_end = area->dx + area->width - 1;
  138. x_word_count = (x_end >> 4) - (area->dx >> 4) + 1;
  139. start_mask = 0xffff0000 >> (area->dx & 0xf);
  140. end_mask = 0x7ffff >> (x_end & 0xf);
  141. out_8(AP_CONTROL_0,
  142. (((area->dx & 0xf) - (area->sx & 0xf)) % 16) | (0x4 << 5));
  143. if ((area->dx & 0xf) < (area->sx & 0xf))
  144. pre_read = 1;
  145. } else {
  146. y_delta = -((info->fix.line_length * 8) - area->sx - area->width);
  147. x_end = area->dx - area->width + 1;
  148. x_word_count = (area->dx >> 4) - (x_end >> 4) + 1;
  149. start_mask = 0x7ffff >> (area->dx & 0xf);
  150. end_mask = 0xffff0000 >> (x_end & 0xf);
  151. out_8(AP_CONTROL_0,
  152. ((-((area->sx & 0xf) - (area->dx & 0xf))) % 16) |
  153. (0x4 << 5));
  154. if ((area->dx & 0xf) > (area->sx & 0xf))
  155. pre_read = 1;
  156. }
  157. for (i = 0; i < area->height; i++) {
  158. out_8(AP_CONTROL_3A, 0xc | (dest >> 16));
  159. if (pre_read) {
  160. dummy = *src;
  161. src += incr;
  162. }
  163. if (x_word_count) {
  164. out_8(AP_WRITE_ENABLE, start_mask);
  165. *src = dest;
  166. src += incr;
  167. dest += incr;
  168. out_8(AP_WRITE_ENABLE, 0);
  169. for (j = 1; j < (x_word_count - 1); j++) {
  170. *src = dest;
  171. src += incr;
  172. dest += incr;
  173. }
  174. out_8(AP_WRITE_ENABLE, start_mask);
  175. *src = dest;
  176. dest += incr;
  177. src += incr;
  178. } else {
  179. out_8(AP_WRITE_ENABLE, start_mask | end_mask);
  180. *src = dest;
  181. dest += incr;
  182. src += incr;
  183. }
  184. src += (y_delta / 16);
  185. dest += (y_delta / 16);
  186. }
  187. out_8(AP_CONTROL_0, NORMAL_MODE);
  188. }
  189. /*
  190. * Initialization
  191. */
  192. static int __devinit dnfb_probe(struct platform_device *dev)
  193. {
  194. struct fb_info *info;
  195. int err = 0;
  196. info = framebuffer_alloc(0, &dev->dev);
  197. if (!info)
  198. return -ENOMEM;
  199. info->fbops = &dn_fb_ops;
  200. info->fix = dnfb_fix;
  201. info->var = dnfb_var;
  202. info->var.red.length = 1;
  203. info->var.red.offset = 0;
  204. info->var.green = info->var.blue = info->var.red;
  205. info->screen_base = (u_char *) info->fix.smem_start;
  206. err = fb_alloc_cmap(&info->cmap, 2, 0);
  207. if (err < 0) {
  208. framebuffer_release(info);
  209. return err;
  210. }
  211. err = register_framebuffer(info);
  212. if (err < 0) {
  213. fb_dealloc_cmap(&info->cmap);
  214. framebuffer_release(info);
  215. return err;
  216. }
  217. platform_set_drvdata(dev, info);
  218. /* now we have registered we can safely setup the hardware */
  219. out_8(AP_CONTROL_3A, RESET_CREG);
  220. out_be16(AP_WRITE_ENABLE, 0x0);
  221. out_8(AP_CONTROL_0, NORMAL_MODE);
  222. out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1));
  223. out_8(AP_CONTROL_2, S_DATA_PLN);
  224. out_be16(AP_ROP_1, SWAP(0x3));
  225. printk("apollo frame buffer alive and kicking !\n");
  226. return err;
  227. }
  228. static struct platform_driver dnfb_driver = {
  229. .probe = dnfb_probe,
  230. .driver = {
  231. .name = "dnfb",
  232. },
  233. };
  234. static struct platform_device dnfb_device = {
  235. .name = "dnfb",
  236. };
  237. int __init dnfb_init(void)
  238. {
  239. int ret;
  240. if (fb_get_options("dnfb", NULL))
  241. return -ENODEV;
  242. ret = platform_driver_register(&dnfb_driver);
  243. if (!ret) {
  244. ret = platform_device_register(&dnfb_device);
  245. if (ret)
  246. platform_driver_unregister(&dnfb_driver);
  247. }
  248. return ret;
  249. }
  250. module_init(dnfb_init);
  251. MODULE_LICENSE("GPL");