cyblafb.c 44 KB

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  1. /*
  2. * Frame buffer driver for Trident Cyberblade/i1 graphics core
  3. *
  4. * Copyright 2005 Knut Petersen <Knut_Petersen@t-online.de>
  5. *
  6. * CREDITS:
  7. * tridentfb.c by Jani Monoses
  8. * see files above for further credits
  9. *
  10. */
  11. #define CYBLAFB_DEBUG 0
  12. #define CYBLAFB_KD_GRAPHICS_QUIRK 1
  13. #define CYBLAFB_PIXMAPSIZE 8192
  14. #include <linux/module.h>
  15. #include <linux/string.h>
  16. #include <linux/fb.h>
  17. #include <linux/init.h>
  18. #include <linux/pci.h>
  19. #include <asm/types.h>
  20. #include <video/cyblafb.h>
  21. #define VERSION "0.62"
  22. struct cyblafb_par {
  23. u32 pseudo_pal[16];
  24. struct fb_ops ops;
  25. };
  26. static struct fb_fix_screeninfo cyblafb_fix __devinitdata = {
  27. .id = "CyBla",
  28. .type = FB_TYPE_PACKED_PIXELS,
  29. .xpanstep = 1,
  30. .ypanstep = 1,
  31. .ywrapstep = 1,
  32. .visual = FB_VISUAL_PSEUDOCOLOR,
  33. .accel = FB_ACCEL_NONE,
  34. };
  35. static char *mode __devinitdata = NULL;
  36. static int bpp __devinitdata = 8;
  37. static int ref __devinitdata = 75;
  38. static int fp __devinitdata;
  39. static int crt __devinitdata;
  40. static int memsize __devinitdata;
  41. static int basestride;
  42. static int vesafb;
  43. static int nativex;
  44. static int center;
  45. static int stretch;
  46. static int pciwb = 1;
  47. static int pcirb = 1;
  48. static int pciwr = 1;
  49. static int pcirr = 1;
  50. static int disabled;
  51. static int verbosity;
  52. static int displaytype;
  53. static void __iomem *io_virt; // iospace virtual memory address
  54. module_param(mode, charp, 0);
  55. module_param(bpp, int, 0);
  56. module_param(ref, int, 0);
  57. module_param(fp, int, 0);
  58. module_param(crt, int, 0);
  59. module_param(nativex, int, 0);
  60. module_param(center, int, 0);
  61. module_param(stretch, int, 0);
  62. module_param(pciwb, int, 0);
  63. module_param(pcirb, int, 0);
  64. module_param(pciwr, int, 0);
  65. module_param(pcirr, int, 0);
  66. module_param(memsize, int, 0);
  67. module_param(verbosity, int, 0);
  68. //=========================================
  69. //
  70. // Well, we have to fix the upper layers.
  71. // Until this has been done, we work around
  72. // the bugs.
  73. //
  74. //=========================================
  75. #if (CYBLAFB_KD_GRAPHICS_QUIRK && CYBLAFB_DEBUG)
  76. if (disabled) { \
  77. printk("********\n");\
  78. dump_stack();\
  79. return val;\
  80. }
  81. #elif CYBLAFB_KD_GRAPHICS_QUIRK
  82. #define KD_GRAPHICS_RETURN(val)\
  83. if (disabled) {\
  84. return val;\
  85. }
  86. #else
  87. #define KD_GRAPHICS_RETURN(val)
  88. #endif
  89. //=========================================
  90. //
  91. // Port access macros for memory mapped io
  92. //
  93. //=========================================
  94. #define out8(r, v) writeb(v, io_virt + r)
  95. #define out32(r, v) writel(v, io_virt + r)
  96. #define in8(r) readb(io_virt + r)
  97. #define in32(r) readl(io_virt + r)
  98. //======================================
  99. //
  100. // Hardware access inline functions
  101. //
  102. //======================================
  103. static inline u8 read3X4(u32 reg)
  104. {
  105. out8(0x3D4, reg);
  106. return in8(0x3D5);
  107. }
  108. static inline u8 read3C4(u32 reg)
  109. {
  110. out8(0x3C4, reg);
  111. return in8(0x3C5);
  112. }
  113. static inline u8 read3CE(u32 reg)
  114. {
  115. out8(0x3CE, reg);
  116. return in8(0x3CF);
  117. }
  118. static inline void write3X4(u32 reg, u8 val)
  119. {
  120. out8(0x3D4, reg);
  121. out8(0x3D5, val);
  122. }
  123. static inline void write3C4(u32 reg, u8 val)
  124. {
  125. out8(0x3C4, reg);
  126. out8(0x3C5, val);
  127. }
  128. static inline void write3CE(u32 reg, u8 val)
  129. {
  130. out8(0x3CE, reg);
  131. out8(0x3CF, val);
  132. }
  133. static inline void write3C0(u32 reg, u8 val)
  134. {
  135. in8(0x3DA); // read to reset index
  136. out8(0x3C0, reg);
  137. out8(0x3C0, val);
  138. }
  139. //=================================================
  140. //
  141. // Enable memory mapped io and unprotect registers
  142. //
  143. //=================================================
  144. static void enable_mmio(void)
  145. {
  146. u8 tmp;
  147. outb(0x0B, 0x3C4);
  148. inb(0x3C5); // Set NEW mode
  149. outb(SR0E, 0x3C4); // write enable a lot of extended ports
  150. outb(0x80, 0x3C5);
  151. outb(SR11, 0x3C4); // write enable those extended ports that
  152. outb(0x87, 0x3C5); // are not affected by SR0E_New
  153. outb(CR1E, 0x3d4); // clear write protect bit for port 0x3c2
  154. tmp = inb(0x3d5) & 0xBF;
  155. outb(CR1E, 0x3d4);
  156. outb(tmp, 0x3d5);
  157. outb(CR39, 0x3D4);
  158. outb(inb(0x3D5) | 0x01, 0x3D5); // Enable mmio
  159. }
  160. //=================================================
  161. //
  162. // Set pixel clock VCLK1
  163. // - multipliers set elswhere
  164. // - freq in units of 0.01 MHz
  165. //
  166. // Hardware bug: SR18 >= 250 is broken for the
  167. // cyberblade/i1
  168. //
  169. //=================================================
  170. static void set_vclk(struct cyblafb_par *par, int freq)
  171. {
  172. u32 m, n, k;
  173. int f, fi, d, di;
  174. u8 lo = 0, hi = 0;
  175. d = 2000;
  176. k = freq >= 10000 ? 0 : freq >= 5000 ? 1 : freq >= 2500 ? 2 : 3;
  177. for (m = 0; m < 64; m++)
  178. for (n = 0; n < 250; n++) {
  179. fi = (int)(((5864727 * (n + 8)) /
  180. ((m + 2) * (1 << k))) >> 12);
  181. if ((di = abs(fi - freq)) < d) {
  182. d = di;
  183. f = fi;
  184. lo = (u8) n;
  185. hi = (u8) ((k << 6) | m);
  186. }
  187. }
  188. write3C4(SR19, hi);
  189. write3C4(SR18, lo);
  190. if (verbosity > 0)
  191. output("pixclock = %d.%02d MHz, k/m/n %x %x %x\n",
  192. freq / 100, freq % 100, (hi & 0xc0) >> 6, hi & 0x3f, lo);
  193. }
  194. //================================================
  195. //
  196. // Cyberblade specific Graphics Engine (GE) setup
  197. //
  198. //================================================
  199. static void cyblafb_setup_GE(int pitch, int bpp)
  200. {
  201. KD_GRAPHICS_RETURN();
  202. switch (bpp) {
  203. case 8:
  204. basestride = ((pitch >> 3) << 20) | (0 << 29);
  205. break;
  206. case 15:
  207. basestride = ((pitch >> 3) << 20) | (5 << 29);
  208. break;
  209. case 16:
  210. basestride = ((pitch >> 3) << 20) | (1 << 29);
  211. break;
  212. case 24:
  213. case 32:
  214. basestride = ((pitch >> 3) << 20) | (2 << 29);
  215. break;
  216. }
  217. write3X4(CR36, 0x90); // reset GE
  218. write3X4(CR36, 0x80); // enable GE
  219. out32(GE24, 1 << 7); // reset all GE pointers by toggling
  220. out32(GE24, 0); // d7 of GE24
  221. write3X4(CR2D, 0x00); // GE Timinigs, no delays
  222. out32(GE6C, 0); // Pattern and Style, p 129, ok
  223. }
  224. //=====================================================================
  225. //
  226. // Cyberblade specific syncing
  227. //
  228. // A timeout might be caused by disabled mmio.
  229. // Cause:
  230. // - bit CR39 & 1 == 0 upon return, X trident driver bug
  231. // - kdm bug (KD_GRAPHICS not set on first switch)
  232. // - kernel design flaw (it believes in the correctness
  233. // of kdm/X
  234. // First we try to sync ignoring that problem, as most of the
  235. // time that will succeed immediately and the enable_mmio()
  236. // would only degrade performance.
  237. //
  238. //=====================================================================
  239. static int cyblafb_sync(struct fb_info *info)
  240. {
  241. u32 status, i = 100000;
  242. KD_GRAPHICS_RETURN(0);
  243. while (((status = in32(GE20)) & 0xFe800000) && i != 0)
  244. i--;
  245. if (i == 0) {
  246. enable_mmio();
  247. i = 1000000;
  248. while (((status = in32(GE20)) & 0xFA800000) && i != 0)
  249. i--;
  250. if (i == 0) {
  251. output("GE Timeout, status: %x\n", status);
  252. if (status & 0x80000000)
  253. output("Bresenham Engine : Busy\n");
  254. if (status & 0x40000000)
  255. output("Setup Engine : Busy\n");
  256. if (status & 0x20000000)
  257. output("SP / DPE : Busy\n");
  258. if (status & 0x10000000)
  259. output("Memory Interface : Busy\n");
  260. if (status & 0x08000000)
  261. output("Com Lst Proc : Busy\n");
  262. if (status & 0x04000000)
  263. output("Block Write : Busy\n");
  264. if (status & 0x02000000)
  265. output("Command Buffer : Full\n");
  266. if (status & 0x01000000)
  267. output("RESERVED : Busy\n");
  268. if (status & 0x00800000)
  269. output("PCI Write Buffer : Busy\n");
  270. cyblafb_setup_GE(info->var.xres,
  271. info->var.bits_per_pixel);
  272. }
  273. }
  274. return 0;
  275. }
  276. //==============================
  277. //
  278. // Cyberblade specific fillrect
  279. //
  280. //==============================
  281. static void cyblafb_fillrect(struct fb_info *info, const struct fb_fillrect *fr)
  282. {
  283. u32 bpp = info->var.bits_per_pixel, col, desty, height;
  284. KD_GRAPHICS_RETURN();
  285. switch (bpp) {
  286. default:
  287. case 8:
  288. col = fr->color;
  289. col |= col << 8;
  290. col |= col << 16;
  291. break;
  292. case 16:
  293. col = ((u32 *) (info->pseudo_palette))[fr->color];
  294. col |= col << 16;
  295. break;
  296. case 32:
  297. col = ((u32 *) (info->pseudo_palette))[fr->color];
  298. break;
  299. }
  300. desty = fr->dy;
  301. height = fr->height;
  302. while (height) {
  303. out32(GEB8, basestride | ((desty * info->var.xres_virtual *
  304. bpp) >> 6));
  305. out32(GE60, col);
  306. out32(GE48, fr->rop ? 0x66 : ROP_S);
  307. out32(GE44, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
  308. out32(GE08, point(fr->dx, 0));
  309. out32(GE0C, point(fr->dx + fr->width - 1,
  310. height > 4096 ? 4095 : height - 1));
  311. if (likely(height <= 4096))
  312. return;
  313. desty += 4096;
  314. height -= 4096;
  315. }
  316. }
  317. //================================================
  318. //
  319. // Cyberblade specific copyarea
  320. //
  321. // This function silently assumes that it never
  322. // will be called with width or height exceeding
  323. // 4096.
  324. //
  325. //================================================
  326. static void cyblafb_copyarea(struct fb_info *info, const struct fb_copyarea *ca)
  327. {
  328. u32 s1, s2, d1, d2, direction;
  329. KD_GRAPHICS_RETURN();
  330. s1 = point(ca->sx, 0);
  331. s2 = point(ca->sx + ca->width - 1, ca->height - 1);
  332. d1 = point(ca->dx, 0);
  333. d2 = point(ca->dx + ca->width - 1, ca->height - 1);
  334. if ((ca->sy > ca->dy) || ((ca->sy == ca->dy) && (ca->sx > ca->dx)))
  335. direction = 0;
  336. else
  337. direction = 2;
  338. out32(GEB8, basestride | ((ca->dy * info->var.xres_virtual *
  339. info->var.bits_per_pixel) >> 6));
  340. out32(GEC8, basestride | ((ca->sy * info->var.xres_virtual *
  341. info->var.bits_per_pixel) >> 6));
  342. out32(GE44, 0xa0000000 | 1 << 19 | 1 << 2 | direction);
  343. out32(GE00, direction ? s2 : s1);
  344. out32(GE04, direction ? s1 : s2);
  345. out32(GE08, direction ? d2 : d1);
  346. out32(GE0C, direction ? d1 : d2);
  347. }
  348. //=======================================================================
  349. //
  350. // Cyberblade specific imageblit
  351. //
  352. // Accelerated for the most usual case, blitting 1 - bit deep
  353. // character images. Everything else is passed to the generic imageblit
  354. // unless it is so insane that it is better to printk an alert.
  355. //
  356. // Hardware bug: _Never_ blit across pixel column 2048, that will lock
  357. // the system. We split those blit requests into three blitting
  358. // operations.
  359. //
  360. //=======================================================================
  361. static void cyblafb_imageblit(struct fb_info *info,
  362. const struct fb_image *image)
  363. {
  364. u32 fgcol, bgcol;
  365. u32 *pd = (u32 *) image->data;
  366. u32 bpp = info->var.bits_per_pixel;
  367. KD_GRAPHICS_RETURN();
  368. // Used only for drawing the penguine (image->depth > 1)
  369. if (image->depth != 1) {
  370. cfb_imageblit(info, image);
  371. return;
  372. }
  373. // That should never happen, but it would be fatal
  374. if (image->width == 0 || image->height == 0) {
  375. output("imageblit: width/height 0 detected\n");
  376. return;
  377. }
  378. if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
  379. info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
  380. fgcol = ((u32 *) (info->pseudo_palette))[image->fg_color];
  381. bgcol = ((u32 *) (info->pseudo_palette))[image->bg_color];
  382. } else {
  383. fgcol = image->fg_color;
  384. bgcol = image->bg_color;
  385. }
  386. switch (bpp) {
  387. case 8:
  388. fgcol |= fgcol << 8;
  389. bgcol |= bgcol << 8;
  390. case 16:
  391. fgcol |= fgcol << 16;
  392. bgcol |= bgcol << 16;
  393. default:
  394. break;
  395. }
  396. out32(GEB8, basestride | ((image->dy * info->var.xres_virtual *
  397. bpp) >> 6));
  398. out32(GE60, fgcol);
  399. out32(GE64, bgcol);
  400. if (!(image->dx < 2048 && (image->dx + image->width - 1) >= 2048)) {
  401. u32 dds = ((image->width + 31) >> 5) * image->height;
  402. out32(GE44, 0xa0000000 | 1 << 20 | 1 << 19);
  403. out32(GE08, point(image->dx, 0));
  404. out32(GE0C, point(image->dx + image->width - 1,
  405. image->height - 1));
  406. while (dds--)
  407. out32(GE9C, *pd++);
  408. } else {
  409. int i, j;
  410. u32 ddstotal = (image->width + 31) >> 5;
  411. u32 ddsleft = (2048 - image->dx + 31) >> 5;
  412. u32 skipleft = ddstotal - ddsleft;
  413. out32(GE44, 0xa0000000 | 1 << 20 | 1 << 19);
  414. out32(GE08, point(image->dx, 0));
  415. out32(GE0C, point(2048 - 1, image->height - 1));
  416. for (i = 0; i < image->height; i++) {
  417. for (j = 0; j < ddsleft; j++)
  418. out32(GE9C, *pd++);
  419. pd += skipleft;
  420. }
  421. if (image->dx % 32) {
  422. out32(GE44, 0xa0000000 | 1 << 20 | 1 << 19);
  423. out32(GE08, point(2048, 0));
  424. if (image->width > ddsleft << 5)
  425. out32(GE0C, point(image->dx + (ddsleft << 5) -
  426. 1, image->height - 1));
  427. else
  428. out32(GE0C, point(image->dx + image->width - 1,
  429. image->height - 1));
  430. pd = ((u32 *) image->data) + ddstotal - skipleft - 1;
  431. for (i = 0; i < image->height; i++) {
  432. out32(GE9C, swab32(swab32(*pd) << ((32 -
  433. (image->dx & 31)) & 31)));
  434. pd += ddstotal;
  435. }
  436. }
  437. if (skipleft) {
  438. out32(GE44, 0xa0000000 | 1 << 20 | 1 << 19);
  439. out32(GE08, point(image->dx + (ddsleft << 5), 0));
  440. out32(GE0C, point(image->dx + image->width - 1,
  441. image->height - 1));
  442. pd = (u32 *) image->data;
  443. for (i = 0; i < image->height; i++) {
  444. pd += ddsleft;
  445. for (j = 0; j < skipleft; j++)
  446. out32(GE9C, *pd++);
  447. }
  448. }
  449. }
  450. }
  451. //==========================================================
  452. //
  453. // Check if video mode is acceptable. We change var->??? if
  454. // video mode is slightly off or return error otherwise.
  455. // info->??? must not be changed!
  456. //
  457. //==========================================================
  458. static int cyblafb_check_var(struct fb_var_screeninfo *var,
  459. struct fb_info *info)
  460. {
  461. int bpp = var->bits_per_pixel;
  462. //
  463. // we try to support 8, 16, 24 and 32 bpp modes,
  464. // default to 8
  465. //
  466. // there is a 24 bpp mode, but for now we change requests to 32 bpp
  467. // (This is what tridentfb does ... will be changed in the future)
  468. //
  469. //
  470. if (bpp % 8 != 0 || bpp < 8 || bpp > 32)
  471. bpp = 8;
  472. if (bpp == 24)
  473. bpp = var->bits_per_pixel = 32;
  474. //
  475. // interlaced modes are broken, fail if one is requested
  476. //
  477. if (var->vmode & FB_VMODE_INTERLACED)
  478. return -EINVAL;
  479. //
  480. // fail if requested resolution is higher than physical
  481. // flatpanel resolution
  482. //
  483. if ((displaytype == DISPLAY_FP) && nativex && var->xres > nativex)
  484. return -EINVAL;
  485. //
  486. // we do not allow vclk to exceed 230 MHz. If the requested
  487. // vclk is too high, we default to 200 MHz
  488. //
  489. if ((bpp == 32 ? 200000000 : 100000000) / var->pixclock > 23000)
  490. var->pixclock = (bpp == 32 ? 200000000 : 100000000) / 20000;
  491. //
  492. // enforce (h|v)sync_len limits
  493. //
  494. var->hsync_len &= ~7;
  495. if(var->hsync_len > 248)
  496. var->hsync_len = 248;
  497. var->vsync_len &= 15;
  498. //
  499. // Enforce horizontal and vertical hardware limits.
  500. // 1600x1200 is mentioned as a maximum, but higher resolutions could
  501. // work with slow refresh, small margins and short sync.
  502. //
  503. var->xres &= ~7;
  504. if (((var->xres + var->left_margin + var->right_margin +
  505. var->hsync_len) > (bpp == 32 ? 2040 : 4088)) ||
  506. ((var->yres + var->upper_margin + var->lower_margin +
  507. var->vsync_len) > 2047))
  508. return -EINVAL;
  509. if ((var->xres > 1600) || (var->yres > 1200))
  510. output("Mode %dx%d exceeds documented limits.\n",
  511. var->xres, var->yres);
  512. //
  513. // try to be smart about (x|y)res_virtual problems.
  514. //
  515. if (var->xres > var->xres_virtual)
  516. var->xres_virtual = var->xres;
  517. if (var->yres > var->yres_virtual)
  518. var->yres_virtual = var->yres;
  519. if (bpp == 8 || bpp == 16) {
  520. if (var->xres_virtual > 4088)
  521. var->xres_virtual = 4088;
  522. } else {
  523. if (var->xres_virtual > 2040)
  524. var->xres_virtual = 2040;
  525. }
  526. var->xres_virtual &= ~7;
  527. while (var->xres_virtual * var->yres_virtual * bpp / 8 >
  528. info->fix.smem_len) {
  529. if (var->yres_virtual > var->yres)
  530. var->yres_virtual--;
  531. else if (var->xres_virtual > var->xres)
  532. var->xres_virtual -= 8;
  533. else
  534. return -EINVAL;
  535. }
  536. switch (bpp) {
  537. case 8:
  538. var->red.offset = 0;
  539. var->green.offset = 0;
  540. var->blue.offset = 0;
  541. var->red.length = 6;
  542. var->green.length = 6;
  543. var->blue.length = 6;
  544. break;
  545. case 16:
  546. var->red.offset = 11;
  547. var->green.offset = 5;
  548. var->blue.offset = 0;
  549. var->red.length = 5;
  550. var->green.length = 6;
  551. var->blue.length = 5;
  552. break;
  553. case 32:
  554. var->red.offset = 16;
  555. var->green.offset = 8;
  556. var->blue.offset = 0;
  557. var->red.length = 8;
  558. var->green.length = 8;
  559. var->blue.length = 8;
  560. break;
  561. default:
  562. return -EINVAL;
  563. }
  564. return 0;
  565. }
  566. //=====================================================================
  567. //
  568. // Pan the display
  569. //
  570. // The datasheets defines crt start address to be 20 bits wide and
  571. // to be programmed to CR0C, CR0D, CR1E and CR27. Actually there is
  572. // CR2B[5] as an undocumented extension bit. Epia BIOS 2.07 does use
  573. // it, so it is also safe to be used here. BTW: datasheet CR0E on page
  574. // 90 really is CR1E, the real CRE is documented on page 72.
  575. //
  576. // BUT:
  577. //
  578. // As of internal version 0.60 we do not use vga panning any longer.
  579. // Vga panning did not allow us the use of all available video memory
  580. // and thus prevented ywrap scrolling. We do use the "right view"
  581. // register now.
  582. //
  583. //
  584. //=====================================================================
  585. static int cyblafb_pan_display(struct fb_var_screeninfo *var,
  586. struct fb_info *info)
  587. {
  588. KD_GRAPHICS_RETURN(0);
  589. info->var.xoffset = var->xoffset;
  590. info->var.yoffset = var->yoffset;
  591. out32(GE10, 0x80000000 | ((var->xoffset + (var->yoffset *
  592. var->xres_virtual)) * var->bits_per_pixel / 32));
  593. return 0;
  594. }
  595. //============================================
  596. //
  597. // This will really help in case of a bug ...
  598. // dump most gaphics core registers.
  599. //
  600. //============================================
  601. static void regdump(struct cyblafb_par *par)
  602. {
  603. int i;
  604. if (verbosity < 2)
  605. return;
  606. printk("\n");
  607. for (i = 0; i <= 0xff; i++) {
  608. outb(i, 0x3d4);
  609. printk("CR%02x=%02x ", i, inb(0x3d5));
  610. if (i % 16 == 15)
  611. printk("\n");
  612. }
  613. outb(0x30, 0x3ce);
  614. outb(inb(0x3cf) | 0x40, 0x3cf);
  615. for (i = 0; i <= 0x1f; i++) {
  616. if (i == 0 || (i > 2 && i < 8) || i == 0x10 || i == 0x11
  617. || i == 0x16) {
  618. outb(i, 0x3d4);
  619. printk("CR%02x=%02x ", i, inb(0x3d5));
  620. } else
  621. printk("------- ");
  622. if (i % 16 == 15)
  623. printk("\n");
  624. }
  625. outb(0x30, 0x3ce);
  626. outb(inb(0x3cf) & 0xbf, 0x3cf);
  627. printk("\n");
  628. for (i = 0; i <= 0x7f; i++) {
  629. outb(i, 0x3ce);
  630. printk("GR%02x=%02x ", i, inb(0x3cf));
  631. if (i % 16 == 15)
  632. printk("\n");
  633. }
  634. printk("\n");
  635. for (i = 0; i <= 0xff; i++) {
  636. outb(i, 0x3c4);
  637. printk("SR%02x=%02x ", i, inb(0x3c5));
  638. if (i % 16 == 15)
  639. printk("\n");
  640. }
  641. printk("\n");
  642. for (i = 0; i <= 0x1F; i++) {
  643. inb(0x3da); // next access is index!
  644. outb(i, 0x3c0);
  645. printk("AR%02x=%02x ", i, inb(0x3c1));
  646. if (i % 16 == 15)
  647. printk("\n");
  648. }
  649. printk("\n");
  650. inb(0x3DA); // reset internal flag to 3c0 index
  651. outb(0x20, 0x3C0); // enable attr
  652. return;
  653. }
  654. //=======================================================================
  655. //
  656. // Save State
  657. //
  658. // This function is called while a switch to KD_TEXT is in progress,
  659. // before any of the other functions are called.
  660. //
  661. //=======================================================================
  662. static void cyblafb_save_state(struct fb_info *info)
  663. {
  664. struct cyblafb_par *par = info->par;
  665. if (verbosity > 0)
  666. output("Switching to KD_TEXT\n");
  667. disabled = 0;
  668. regdump(par);
  669. enable_mmio();
  670. return;
  671. }
  672. //=======================================================================
  673. //
  674. // Restore State
  675. //
  676. // This function is called while a switch to KD_GRAPHICS is in progress,
  677. // We have to turn on vga style panning registers again because the
  678. // trident driver of X does not know about GE10.
  679. //
  680. //=======================================================================
  681. static void cyblafb_restore_state(struct fb_info *info)
  682. {
  683. if (verbosity > 0)
  684. output("Switching to KD_GRAPHICS\n");
  685. out32(GE10, 0);
  686. disabled = 1;
  687. return;
  688. }
  689. //======================================
  690. //
  691. // Set hardware to requested video mode
  692. //
  693. //======================================
  694. static int cyblafb_set_par(struct fb_info *info)
  695. {
  696. struct cyblafb_par *par = info->par;
  697. u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart,
  698. hblankend, preendfetch, vtotal, vdispend, vsyncstart,
  699. vsyncend, vblankstart, vblankend;
  700. struct fb_var_screeninfo *var = &info->var;
  701. int bpp = var->bits_per_pixel;
  702. int i;
  703. KD_GRAPHICS_RETURN(0);
  704. if (verbosity > 0)
  705. output("Switching to new mode: "
  706. "fbset -g %d %d %d %d %d -t %d %d %d %d %d %d %d\n",
  707. var->xres, var->yres, var->xres_virtual,
  708. var->yres_virtual, var->bits_per_pixel, var->pixclock,
  709. var->left_margin, var->right_margin, var->upper_margin,
  710. var->lower_margin, var->hsync_len, var->vsync_len);
  711. htotal = (var->xres + var->left_margin + var->right_margin +
  712. var->hsync_len) / 8 - 5;
  713. hdispend = var->xres / 8 - 1;
  714. hsyncstart = (var->xres + var->right_margin) / 8;
  715. hsyncend = var->hsync_len / 8;
  716. hblankstart = hdispend + 1;
  717. hblankend = htotal + 3; // should be htotal + 5, bios does it this way
  718. preendfetch = ((var->xres >> 3) + 1) * ((bpp + 1) >> 3);
  719. vtotal = var->yres + var->upper_margin + var->lower_margin +
  720. var->vsync_len - 2;
  721. vdispend = var->yres - 1;
  722. vsyncstart = var->yres + var->lower_margin;
  723. vblankstart = var->yres;
  724. vblankend = vtotal; // should be vtotal + 2, but bios does it this way
  725. vsyncend = var->vsync_len;
  726. enable_mmio(); // necessary! ... check X ...
  727. write3X4(CR11, read3X4(CR11) & 0x7F); // unlock cr00 .. cr07
  728. write3CE(GR30, 8);
  729. if ((displaytype == DISPLAY_FP) && var->xres < nativex) {
  730. // stretch or center ?
  731. out8(0x3C2, 0xEB);
  732. write3CE(GR30, read3CE(GR30) | 0x81); // shadow mode on
  733. if (center) {
  734. write3CE(GR52, (read3CE(GR52) & 0x7C) | 0x80);
  735. write3CE(GR53, (read3CE(GR53) & 0x7C) | 0x80);
  736. } else if (stretch) {
  737. write3CE(GR5D, 0);
  738. write3CE(GR52, (read3CE(GR52) & 0x7C) | 1);
  739. write3CE(GR53, (read3CE(GR53) & 0x7C) | 1);
  740. }
  741. } else {
  742. out8(0x3C2, 0x2B);
  743. write3CE(GR30, 8);
  744. }
  745. //
  746. // Setup CRxx regs
  747. //
  748. write3X4(CR00, htotal & 0xFF);
  749. write3X4(CR01, hdispend & 0xFF);
  750. write3X4(CR02, hblankstart & 0xFF);
  751. write3X4(CR03, hblankend & 0x1F);
  752. write3X4(CR04, hsyncstart & 0xFF);
  753. write3X4(CR05, (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
  754. write3X4(CR06, vtotal & 0xFF);
  755. write3X4(CR07, (vtotal & 0x100) >> 8 |
  756. (vdispend & 0x100) >> 7 |
  757. (vsyncstart & 0x100) >> 6 |
  758. (vblankstart & 0x100) >> 5 |
  759. 0x10 |
  760. (vtotal & 0x200) >> 4 |
  761. (vdispend & 0x200) >> 3 | (vsyncstart & 0x200) >> 2);
  762. write3X4(CR08, 0);
  763. write3X4(CR09, (vblankstart & 0x200) >> 4 | 0x40 | // FIX !!!
  764. ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0));
  765. write3X4(CR0A, 0); // Init to some reasonable default
  766. write3X4(CR0B, 0); // Init to some reasonable default
  767. write3X4(CR0C, 0); // Offset 0
  768. write3X4(CR0D, 0); // Offset 0
  769. write3X4(CR0E, 0); // Init to some reasonable default
  770. write3X4(CR0F, 0); // Init to some reasonable default
  771. write3X4(CR10, vsyncstart & 0xFF);
  772. write3X4(CR11, (vsyncend & 0x0F));
  773. write3X4(CR12, vdispend & 0xFF);
  774. write3X4(CR13, ((info->var.xres_virtual * bpp) / (4 * 16)) & 0xFF);
  775. write3X4(CR14, 0x40); // double word mode
  776. write3X4(CR15, vblankstart & 0xFF);
  777. write3X4(CR16, vblankend & 0xFF);
  778. write3X4(CR17, 0xE3);
  779. write3X4(CR18, 0xFF);
  780. // CR19: needed for interlaced modes ... ignore it for now
  781. write3X4(CR1A, 0x07); // Arbitration Control Counter 1
  782. write3X4(CR1B, 0x07); // Arbitration Control Counter 2
  783. write3X4(CR1C, 0x07); // Arbitration Control Counter 3
  784. write3X4(CR1D, 0x00); // Don't know, doesn't hurt ; -)
  785. write3X4(CR1E, (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80);
  786. // CR1F: do not set, contains BIOS info about memsize
  787. write3X4(CR20, 0x20); // enabe wr buf, disable 16bit planar mode
  788. write3X4(CR21, 0x20); // enable linear memory access
  789. // CR22: RO cpu latch readback
  790. // CR23: ???
  791. // CR24: RO AR flag state
  792. // CR25: RAMDAC rw timing, pclk buffer tristate control ????
  793. // CR26: ???
  794. write3X4(CR27, (vdispend & 0x400) >> 6 |
  795. (vsyncstart & 0x400) >> 5 |
  796. (vblankstart & 0x400) >> 4 |
  797. (vtotal & 0x400) >> 3 |
  798. 0x8);
  799. // CR28: ???
  800. write3X4(CR29, (read3X4(CR29) & 0xCF) | ((((info->var.xres_virtual *
  801. bpp) / (4 * 16)) & 0x300) >> 4));
  802. write3X4(CR2A, read3X4(CR2A) | 0x40);
  803. write3X4(CR2B, (htotal & 0x100) >> 8 |
  804. (hdispend & 0x100) >> 7 |
  805. // (0x00 & 0x100) >> 6 | hinterlace para bit 8 ???
  806. (hsyncstart & 0x100) >> 5 |
  807. (hblankstart & 0x100) >> 4);
  808. // CR2C: ???
  809. // CR2D: initialized in cyblafb_setup_GE()
  810. write3X4(CR2F, 0x92); // conservative, better signal quality
  811. // CR30: reserved
  812. // CR31: reserved
  813. // CR32: reserved
  814. // CR33: reserved
  815. // CR34: disabled in CR36
  816. // CR35: disabled in CR36
  817. // CR36: initialized in cyblafb_setup_GE
  818. // CR37: i2c, ignore for now
  819. write3X4(CR38, (bpp == 8) ? 0x00 : //
  820. (bpp == 16) ? 0x05 : // highcolor
  821. (bpp == 24) ? 0x29 : // packed 24bit truecolor
  822. (bpp == 32) ? 0x09 : 0); // truecolor, 16 bit pixelbus
  823. write3X4(CR39, 0x01 | // MMIO enable
  824. (pcirb ? 0x02 : 0) | // pci read burst enable
  825. (pciwb ? 0x04 : 0)); // pci write burst enable
  826. write3X4(CR55, 0x1F | // pci clocks * 2 for STOP# during 1st data phase
  827. (pcirr ? 0x40 : 0) | // pci read retry enable
  828. (pciwr ? 0x80 : 0)); // pci write retry enable
  829. write3X4(CR56, preendfetch >> 8 < 2 ? (preendfetch >> 8 & 0x01) | 2
  830. : 0);
  831. write3X4(CR57, preendfetch >> 8 < 2 ? preendfetch & 0xff : 0);
  832. write3X4(CR58, 0x82); // Bios does this .... don't know more
  833. //
  834. // Setup SRxx regs
  835. //
  836. write3C4(SR00, 3);
  837. write3C4(SR01, 1); //set char clock 8 dots wide
  838. write3C4(SR02, 0x0F); //enable 4 maps needed in chain4 mode
  839. write3C4(SR03, 0); //no character map select
  840. write3C4(SR04, 0x0E); //memory mode: ext mem, even, chain4
  841. out8(0x3C4, 0x0b);
  842. in8(0x3C5); // Set NEW mode
  843. write3C4(SR0D, 0x00); // test ... check
  844. set_vclk(par, (bpp == 32 ? 200000000 : 100000000)
  845. / info->var.pixclock); //SR18, SR19
  846. //
  847. // Setup GRxx regs
  848. //
  849. write3CE(GR00, 0x00); // test ... check
  850. write3CE(GR01, 0x00); // test ... check
  851. write3CE(GR02, 0x00); // test ... check
  852. write3CE(GR03, 0x00); // test ... check
  853. write3CE(GR04, 0x00); // test ... check
  854. write3CE(GR05, 0x40); // no CGA compat, allow 256 col
  855. write3CE(GR06, 0x05); // graphics mode
  856. write3CE(GR07, 0x0F); // planes?
  857. write3CE(GR08, 0xFF); // test ... check
  858. write3CE(GR0F, (bpp == 32) ? 0x1A : 0x12); // vclk / 2 if 32bpp, chain4
  859. write3CE(GR20, 0xC0); // test ... check
  860. write3CE(GR2F, 0xA0); // PCLK = VCLK, no skew,
  861. //
  862. // Setup ARxx regs
  863. //
  864. for (i = 0; i < 0x10; i++) // set AR00 .. AR0f
  865. write3C0(i, i);
  866. write3C0(AR10, 0x41); // graphics mode and support 256 color modes
  867. write3C0(AR12, 0x0F); // planes
  868. write3C0(AR13, 0); // horizontal pel panning
  869. in8(0x3DA); // reset internal flag to 3c0 index
  870. out8(0x3C0, 0x20); // enable attr
  871. //
  872. // Setup hidden RAMDAC command register
  873. //
  874. in8(0x3C8); // these reads are
  875. in8(0x3C6); // necessary to
  876. in8(0x3C6); // unmask the RAMDAC
  877. in8(0x3C6); // command reg, otherwise
  878. in8(0x3C6); // we would write the pixelmask reg!
  879. out8(0x3C6, (bpp == 8) ? 0x00 : // 256 colors
  880. (bpp == 15) ? 0x10 : //
  881. (bpp == 16) ? 0x30 : // hicolor
  882. (bpp == 24) ? 0xD0 : // truecolor
  883. (bpp == 32) ? 0xD0 : 0); // truecolor
  884. in8(0x3C8);
  885. //
  886. // GR31 is not mentioned in the datasheet
  887. //
  888. if (displaytype == DISPLAY_FP)
  889. write3CE(GR31, (read3CE(GR31) & 0x8F) |
  890. ((info->var.yres > 1024) ? 0x50 :
  891. (info->var.yres > 768) ? 0x30 :
  892. (info->var.yres > 600) ? 0x20 :
  893. (info->var.yres > 480) ? 0x10 : 0));
  894. info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR
  895. : FB_VISUAL_TRUECOLOR;
  896. info->fix.line_length = info->var.xres_virtual * (bpp >> 3);
  897. info->cmap.len = (bpp == 8) ? 256 : 16;
  898. //
  899. // init acceleration engine
  900. //
  901. cyblafb_setup_GE(info->var.xres_virtual, info->var.bits_per_pixel);
  902. //
  903. // Set/clear flags to allow proper scroll mode selection.
  904. //
  905. if (var->xres == var->xres_virtual)
  906. info->flags &= ~FBINFO_HWACCEL_XPAN;
  907. else
  908. info->flags |= FBINFO_HWACCEL_XPAN;
  909. if (var->yres == var->yres_virtual)
  910. info->flags &= ~FBINFO_HWACCEL_YPAN;
  911. else
  912. info->flags |= FBINFO_HWACCEL_YPAN;
  913. if (info->fix.smem_len !=
  914. var->xres_virtual * var->yres_virtual * bpp / 8)
  915. info->flags &= ~FBINFO_HWACCEL_YWRAP;
  916. else
  917. info->flags |= FBINFO_HWACCEL_YWRAP;
  918. regdump(par);
  919. return 0;
  920. }
  921. //========================
  922. //
  923. // Set one color register
  924. //
  925. //========================
  926. static int cyblafb_setcolreg(unsigned regno, unsigned red, unsigned green,
  927. unsigned blue, unsigned transp,
  928. struct fb_info *info)
  929. {
  930. int bpp = info->var.bits_per_pixel;
  931. KD_GRAPHICS_RETURN(0);
  932. if (regno >= info->cmap.len)
  933. return 1;
  934. if (bpp == 8) {
  935. out8(0x3C6, 0xFF);
  936. out8(0x3C8, regno);
  937. out8(0x3C9, red >> 10);
  938. out8(0x3C9, green >> 10);
  939. out8(0x3C9, blue >> 10);
  940. } else if (bpp == 16) // RGB 565
  941. ((u32 *) info->pseudo_palette)[regno] =
  942. (red & 0xF800) |
  943. ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
  944. else if (bpp == 32) // ARGB 8888
  945. ((u32 *) info->pseudo_palette)[regno] =
  946. ((transp & 0xFF00) << 16) |
  947. ((red & 0xFF00) << 8) |
  948. ((green & 0xFF00)) | ((blue & 0xFF00) >> 8);
  949. return 0;
  950. }
  951. //==========================================================
  952. //
  953. // Try blanking the screen. For flat panels it does nothing
  954. //
  955. //==========================================================
  956. static int cyblafb_blank(int blank_mode, struct fb_info *info)
  957. {
  958. unsigned char PMCont, DPMSCont;
  959. KD_GRAPHICS_RETURN(0);
  960. if (displaytype == DISPLAY_FP)
  961. return 0;
  962. out8(0x83C8, 0x04); // DPMS Control
  963. PMCont = in8(0x83C6) & 0xFC;
  964. DPMSCont = read3CE(GR23) & 0xFC;
  965. switch (blank_mode) {
  966. case FB_BLANK_UNBLANK: // Screen: On, HSync: On, VSync: On
  967. case FB_BLANK_NORMAL: // Screen: Off, HSync: On, VSync: On
  968. PMCont |= 0x03;
  969. DPMSCont |= 0x00;
  970. break;
  971. case FB_BLANK_HSYNC_SUSPEND: // Screen: Off, HSync: Off, VSync: On
  972. PMCont |= 0x02;
  973. DPMSCont |= 0x01;
  974. break;
  975. case FB_BLANK_VSYNC_SUSPEND: // Screen: Off, HSync: On, VSync: Off
  976. PMCont |= 0x02;
  977. DPMSCont |= 0x02;
  978. break;
  979. case FB_BLANK_POWERDOWN: // Screen: Off, HSync: Off, VSync: Off
  980. PMCont |= 0x00;
  981. DPMSCont |= 0x03;
  982. break;
  983. }
  984. write3CE(GR23, DPMSCont);
  985. out8(0x83C8, 4);
  986. out8(0x83C6, PMCont);
  987. //
  988. // let fbcon do a softblank for us
  989. //
  990. return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
  991. }
  992. static struct fb_ops cyblafb_ops __devinitdata = {
  993. .owner = THIS_MODULE,
  994. .fb_setcolreg = cyblafb_setcolreg,
  995. .fb_pan_display = cyblafb_pan_display,
  996. .fb_blank = cyblafb_blank,
  997. .fb_check_var = cyblafb_check_var,
  998. .fb_set_par = cyblafb_set_par,
  999. .fb_fillrect = cyblafb_fillrect,
  1000. .fb_copyarea = cyblafb_copyarea,
  1001. .fb_imageblit = cyblafb_imageblit,
  1002. .fb_sync = cyblafb_sync,
  1003. .fb_restore_state = cyblafb_restore_state,
  1004. .fb_save_state = cyblafb_save_state,
  1005. };
  1006. //==========================================================================
  1007. //
  1008. // getstartupmode() decides about the inital video mode
  1009. //
  1010. // There is no reason to use modedb, a lot of video modes there would
  1011. // need altered timings to display correctly. So I decided that it is much
  1012. // better to provide a limited optimized set of modes plus the option of
  1013. // using the mode in effect at startup time (might be selected using the
  1014. // vga=??? paramter). After that the user might use fbset to select any
  1015. // mode he likes, check_var will not try to alter geometry parameters as
  1016. // it would be necessary otherwise.
  1017. //
  1018. //==========================================================================
  1019. static int __devinit getstartupmode(struct fb_info *info)
  1020. {
  1021. u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend,
  1022. vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend,
  1023. cr00, cr01, cr02, cr03, cr04, cr05, cr2b,
  1024. cr06, cr07, cr09, cr10, cr11, cr12, cr15, cr16, cr27,
  1025. cr38, sr0d, sr18, sr19, gr0f, fi, pxclkdiv, vclkdiv, tmp, i;
  1026. struct modus {
  1027. int xres; int vxres; int yres; int vyres;
  1028. int bpp; int pxclk;
  1029. int left_margin; int right_margin;
  1030. int upper_margin; int lower_margin;
  1031. int hsync_len; int vsync_len;
  1032. } modedb[5] = {
  1033. {
  1034. 0, 2048, 0, 4096, 0, 0, 0, 0, 0, 0, 0, 0}, {
  1035. 640, 2048, 480, 4096, 0, 0, -40, 24, 17, 0, 216, 3}, {
  1036. 800, 2048, 600, 4096, 0, 0, 96, 24, 14, 0, 136, 11}, {
  1037. 1024, 2048, 768, 4096, 0, 0, 144, 24, 29, 0, 120, 3}, {
  1038. 1280, 2048, 1024, 4096, 0, 0, 232, 16, 39, 0, 160, 3}
  1039. };
  1040. outb(0x00, 0x3d4); cr00 = inb(0x3d5);
  1041. outb(0x01, 0x3d4); cr01 = inb(0x3d5);
  1042. outb(0x02, 0x3d4); cr02 = inb(0x3d5);
  1043. outb(0x03, 0x3d4); cr03 = inb(0x3d5);
  1044. outb(0x04, 0x3d4); cr04 = inb(0x3d5);
  1045. outb(0x05, 0x3d4); cr05 = inb(0x3d5);
  1046. outb(0x06, 0x3d4); cr06 = inb(0x3d5);
  1047. outb(0x07, 0x3d4); cr07 = inb(0x3d5);
  1048. outb(0x09, 0x3d4); cr09 = inb(0x3d5);
  1049. outb(0x10, 0x3d4); cr10 = inb(0x3d5);
  1050. outb(0x11, 0x3d4); cr11 = inb(0x3d5);
  1051. outb(0x12, 0x3d4); cr12 = inb(0x3d5);
  1052. outb(0x15, 0x3d4); cr15 = inb(0x3d5);
  1053. outb(0x16, 0x3d4); cr16 = inb(0x3d5);
  1054. outb(0x27, 0x3d4); cr27 = inb(0x3d5);
  1055. outb(0x2b, 0x3d4); cr2b = inb(0x3d5);
  1056. outb(0x38, 0x3d4); cr38 = inb(0x3d5);
  1057. outb(0x0b, 0x3c4);
  1058. inb(0x3c5);
  1059. outb(0x0d, 0x3c4); sr0d = inb(0x3c5);
  1060. outb(0x18, 0x3c4); sr18 = inb(0x3c5);
  1061. outb(0x19, 0x3c4); sr19 = inb(0x3c5);
  1062. outb(0x0f, 0x3ce); gr0f = inb(0x3cf);
  1063. htotal = cr00 | (cr2b & 0x01) << 8;
  1064. hdispend = cr01 | (cr2b & 0x02) << 7;
  1065. hblankstart = cr02 | (cr2b & 0x10) << 4;
  1066. hblankend = (cr03 & 0x1f) | (cr05 & 0x80) >> 2;
  1067. hsyncstart = cr04 | (cr2b & 0x08) << 5;
  1068. hsyncend = cr05 & 0x1f;
  1069. modedb[0].xres = hblankstart * 8;
  1070. modedb[0].hsync_len = hsyncend * 8;
  1071. modedb[0].right_margin = hsyncstart * 8 - modedb[0].xres;
  1072. modedb[0].left_margin = (htotal + 5) * 8 - modedb[0].xres -
  1073. modedb[0].right_margin - modedb[0].hsync_len;
  1074. vtotal = cr06 | (cr07 & 0x01) << 8 | (cr07 & 0x20) << 4
  1075. | (cr27 & 0x80) << 3;
  1076. vdispend = cr12 | (cr07 & 0x02) << 7 | (cr07 & 0x40) << 3
  1077. | (cr27 & 0x10) << 6;
  1078. vsyncstart = cr10 | (cr07 & 0x04) << 6 | (cr07 & 0x80) << 2
  1079. | (cr27 & 0x20) << 5;
  1080. vsyncend = cr11 & 0x0f;
  1081. vblankstart = cr15 | (cr07 & 0x08) << 5 | (cr09 & 0x20) << 4
  1082. | (cr27 & 0x40) << 4;
  1083. vblankend = cr16;
  1084. modedb[0].yres = vdispend + 1;
  1085. modedb[0].vsync_len = vsyncend;
  1086. modedb[0].lower_margin = vsyncstart - modedb[0].yres;
  1087. modedb[0].upper_margin = vtotal - modedb[0].yres -
  1088. modedb[0].lower_margin - modedb[0].vsync_len + 2;
  1089. tmp = cr38 & 0x3c;
  1090. modedb[0].bpp = tmp == 0 ? 8 : tmp == 4 ? 16 : tmp == 28 ? 24 :
  1091. tmp == 8 ? 32 : 8;
  1092. fi = ((5864727 * (sr18 + 8)) /
  1093. (((sr19 & 0x3f) + 2) * (1 << ((sr19 & 0xc0) >> 6)))) >> 12;
  1094. pxclkdiv = ((gr0f & 0x08) >> 3 | (gr0f & 0x40) >> 5) + 1;
  1095. tmp = sr0d & 0x06;
  1096. vclkdiv = tmp == 0 ? 2 : tmp == 2 ? 4 : tmp == 4 ? 8 : 3; // * 2 !
  1097. modedb[0].pxclk = ((100000000 * pxclkdiv * vclkdiv) >> 1) / fi;
  1098. if (verbosity > 0)
  1099. output("detected startup mode: "
  1100. "fbset -g %d %d %d ??? %d -t %d %d %d %d %d %d %d\n",
  1101. modedb[0].xres, modedb[0].yres, modedb[0].xres,
  1102. modedb[0].bpp, modedb[0].pxclk, modedb[0].left_margin,
  1103. modedb[0].right_margin, modedb[0].upper_margin,
  1104. modedb[0].lower_margin, modedb[0].hsync_len,
  1105. modedb[0].vsync_len);
  1106. //
  1107. // We use this goto target in case of a failed check_var. No, I really
  1108. // do not want to do it in another way!
  1109. //
  1110. tryagain:
  1111. i = (mode == NULL) ? 0 :
  1112. !strncmp(mode, "640x480", 7) ? 1 :
  1113. !strncmp(mode, "800x600", 7) ? 2 :
  1114. !strncmp(mode, "1024x768", 8) ? 3 :
  1115. !strncmp(mode, "1280x1024", 9) ? 4 : 0;
  1116. ref = (ref < 50) ? 50 : (ref > 85) ? 85 : ref;
  1117. if (i == 0) {
  1118. info->var.pixclock = modedb[i].pxclk;
  1119. info->var.bits_per_pixel = modedb[i].bpp;
  1120. } else {
  1121. info->var.pixclock = (100000000 /
  1122. ((modedb[i].left_margin +
  1123. modedb[i].xres +
  1124. modedb[i].right_margin +
  1125. modedb[i].hsync_len) *
  1126. (modedb[i].upper_margin +
  1127. modedb[i].yres +
  1128. modedb[i].lower_margin +
  1129. modedb[i].vsync_len) * ref / 10000));
  1130. info->var.bits_per_pixel = bpp;
  1131. }
  1132. info->var.left_margin = modedb[i].left_margin;
  1133. info->var.right_margin = modedb[i].right_margin;
  1134. info->var.xres = modedb[i].xres;
  1135. if (!(modedb[i].yres == 1280 && modedb[i].bpp == 32))
  1136. info->var.xres_virtual = modedb[i].vxres;
  1137. else
  1138. info->var.xres_virtual = modedb[i].xres;
  1139. info->var.xoffset = 0;
  1140. info->var.hsync_len = modedb[i].hsync_len;
  1141. info->var.upper_margin = modedb[i].upper_margin;
  1142. info->var.yres = modedb[i].yres;
  1143. info->var.yres_virtual = modedb[i].vyres;
  1144. info->var.yoffset = 0;
  1145. info->var.lower_margin = modedb[i].lower_margin;
  1146. info->var.vsync_len = modedb[i].vsync_len;
  1147. info->var.sync = 0;
  1148. info->var.vmode = FB_VMODE_NONINTERLACED;
  1149. if (cyblafb_check_var(&info->var, info)) {
  1150. // 640x480 - 8@75 should really never fail. One case would
  1151. // be fp == 1 and nativex < 640 ... give up then
  1152. if (i == 1 && bpp == 8 && ref == 75) {
  1153. output("Can't find a valid mode :-(\n");
  1154. return -EINVAL;
  1155. }
  1156. // Our detected mode is unlikely to fail. If it does,
  1157. // try 640x480 - 8@75 ...
  1158. if (i == 0) {
  1159. mode = "640x480";
  1160. bpp = 8;
  1161. ref = 75;
  1162. output("Detected mode failed check_var! "
  1163. "Trying 640x480 - 8@75\n");
  1164. goto tryagain;
  1165. }
  1166. // A specified video mode failed for some reason.
  1167. // Try the startup mode first
  1168. output("Specified mode '%s' failed check! "
  1169. "Falling back to startup mode.\n", mode);
  1170. mode = NULL;
  1171. goto tryagain;
  1172. }
  1173. return 0;
  1174. }
  1175. //========================================================
  1176. //
  1177. // Detect activated memory size. Undefined values require
  1178. // memsize parameter.
  1179. //
  1180. //========================================================
  1181. static unsigned int __devinit get_memsize(void)
  1182. {
  1183. unsigned char tmp;
  1184. unsigned int k;
  1185. if (memsize)
  1186. k = memsize * Kb;
  1187. else {
  1188. tmp = read3X4(CR1F) & 0x0F;
  1189. switch (tmp) {
  1190. case 0x03:
  1191. k = 1 * 1024 * 1024;
  1192. break;
  1193. case 0x07:
  1194. k = 2 * 1024 * 1024;
  1195. break;
  1196. case 0x0F:
  1197. k = 4 * 1024 * 1024;
  1198. break;
  1199. case 0x04:
  1200. k = 8 * 1024 * 1024;
  1201. break;
  1202. default:
  1203. k = 1 * 1024 * 1024;
  1204. output("Unknown memory size code %x in CR1F."
  1205. " We default to 1 Mb for now, please"
  1206. " do provide a memsize parameter!\n", tmp);
  1207. }
  1208. }
  1209. if (verbosity > 0)
  1210. output("framebuffer size = %d Kb\n", k / Kb);
  1211. return k;
  1212. }
  1213. //=========================================================
  1214. //
  1215. // Detect if a flat panel monitor connected to the special
  1216. // interface is active. Override is possible by fp and crt
  1217. // parameters.
  1218. //
  1219. //=========================================================
  1220. static unsigned int __devinit get_displaytype(void)
  1221. {
  1222. if (fp)
  1223. return DISPLAY_FP;
  1224. if (crt)
  1225. return DISPLAY_CRT;
  1226. return (read3CE(GR33) & 0x10) ? DISPLAY_FP : DISPLAY_CRT;
  1227. }
  1228. //=====================================
  1229. //
  1230. // Get native resolution of flat panel
  1231. //
  1232. //=====================================
  1233. static int __devinit get_nativex(void)
  1234. {
  1235. int x, y, tmp;
  1236. if (nativex)
  1237. return nativex;
  1238. tmp = (read3CE(GR52) >> 4) & 3;
  1239. switch (tmp) {
  1240. case 0: x = 1280; y = 1024;
  1241. break;
  1242. case 2: x = 1024; y = 768;
  1243. break;
  1244. case 3: x = 800; y = 600;
  1245. break;
  1246. case 4: x = 1400; y = 1050;
  1247. break;
  1248. case 1:
  1249. default:
  1250. x = 640; y = 480;
  1251. break;
  1252. }
  1253. if (verbosity > 0)
  1254. output("%dx%d flat panel found\n", x, y);
  1255. return x;
  1256. }
  1257. static int __devinit cybla_pci_probe(struct pci_dev *dev,
  1258. const struct pci_device_id *id)
  1259. {
  1260. struct fb_info *info;
  1261. struct cyblafb_par *par;
  1262. info = framebuffer_alloc(sizeof(struct cyblafb_par), &dev->dev);
  1263. if (!info)
  1264. goto errout_alloc_info;
  1265. info->pixmap.addr = kzalloc(CYBLAFB_PIXMAPSIZE, GFP_KERNEL);
  1266. if (!info->pixmap.addr) {
  1267. output("allocation of pixmap buffer failed!\n");
  1268. goto errout_alloc_pixmap;
  1269. }
  1270. info->pixmap.size = CYBLAFB_PIXMAPSIZE - 4;
  1271. info->pixmap.buf_align = 4;
  1272. info->pixmap.access_align = 32;
  1273. info->pixmap.flags = FB_PIXMAP_SYSTEM;
  1274. info->pixmap.scan_align = 4;
  1275. par = info->par;
  1276. par->ops = cyblafb_ops;
  1277. info->fix = cyblafb_fix;
  1278. info->fbops = &par->ops;
  1279. info->fix = cyblafb_fix;
  1280. if (pci_enable_device(dev)) {
  1281. output("could not enable device!\n");
  1282. goto errout_enable;
  1283. }
  1284. // might already be requested by vga console or vesafb,
  1285. // so we do care about success
  1286. if (!request_region(0x3c0, 0x20, "cyblafb")) {
  1287. output("region 0x3c0/0x20 already reserved\n");
  1288. vesafb |= 1;
  1289. }
  1290. //
  1291. // Graphics Engine Registers
  1292. //
  1293. if (!request_region(GEBase, 0x100, "cyblafb")) {
  1294. output("region %#x/0x100 already reserved\n", GEBase);
  1295. vesafb |= 2;
  1296. }
  1297. regdump(par);
  1298. enable_mmio();
  1299. // setup MMIO region
  1300. info->fix.mmio_start = pci_resource_start(dev, 1);
  1301. info->fix.mmio_len = 0x20000;
  1302. if (!request_mem_region(info->fix.mmio_start,
  1303. info->fix.mmio_len, "cyblafb")) {
  1304. output("request_mem_region failed for mmio region!\n");
  1305. goto errout_mmio_reqmem;
  1306. }
  1307. io_virt = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
  1308. if (!io_virt) {
  1309. output("ioremap failed for mmio region\n");
  1310. goto errout_mmio_remap;
  1311. }
  1312. // setup framebuffer memory ... might already be requested
  1313. // by vesafb. Not to fail in case of an unsuccessful request
  1314. // is useful if both are loaded.
  1315. info->fix.smem_start = pci_resource_start(dev, 0);
  1316. info->fix.smem_len = get_memsize();
  1317. if (!request_mem_region(info->fix.smem_start,
  1318. info->fix.smem_len, "cyblafb")) {
  1319. output("region %#lx/%#x already reserved\n",
  1320. info->fix.smem_start, info->fix.smem_len);
  1321. vesafb |= 4;
  1322. }
  1323. info->screen_base = ioremap_nocache(info->fix.smem_start,
  1324. info->fix.smem_len);
  1325. if (!info->screen_base) {
  1326. output("ioremap failed for smem region\n");
  1327. goto errout_smem_remap;
  1328. }
  1329. displaytype = get_displaytype();
  1330. if (displaytype == DISPLAY_FP)
  1331. nativex = get_nativex();
  1332. info->flags = FBINFO_DEFAULT
  1333. | FBINFO_HWACCEL_COPYAREA
  1334. | FBINFO_HWACCEL_FILLRECT
  1335. | FBINFO_HWACCEL_IMAGEBLIT
  1336. | FBINFO_READS_FAST
  1337. // | FBINFO_PARTIAL_PAN_OK
  1338. | FBINFO_MISC_ALWAYS_SETPAR;
  1339. info->pseudo_palette = par->pseudo_pal;
  1340. if (getstartupmode(info))
  1341. goto errout_findmode;
  1342. fb_alloc_cmap(&info->cmap, 256, 0);
  1343. if (register_framebuffer(info)) {
  1344. output("Could not register CyBla framebuffer\n");
  1345. goto errout_register;
  1346. }
  1347. pci_set_drvdata(dev, info);
  1348. //
  1349. // normal exit and error paths
  1350. //
  1351. return 0;
  1352. errout_register:
  1353. errout_findmode:
  1354. iounmap(info->screen_base);
  1355. errout_smem_remap:
  1356. if (!(vesafb & 4))
  1357. release_mem_region(info->fix.smem_start, info->fix.smem_len);
  1358. iounmap(io_virt);
  1359. errout_mmio_remap:
  1360. release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
  1361. errout_mmio_reqmem:
  1362. if (!(vesafb & 1))
  1363. release_region(0x3c0, 32);
  1364. errout_enable:
  1365. kfree(info->pixmap.addr);
  1366. errout_alloc_pixmap:
  1367. framebuffer_release(info);
  1368. errout_alloc_info:
  1369. output("CyblaFB version %s aborting init.\n", VERSION);
  1370. return -ENODEV;
  1371. }
  1372. static void __devexit cybla_pci_remove(struct pci_dev *dev)
  1373. {
  1374. struct fb_info *info = pci_get_drvdata(dev);
  1375. unregister_framebuffer(info);
  1376. iounmap(io_virt);
  1377. iounmap(info->screen_base);
  1378. if (!(vesafb & 4))
  1379. release_mem_region(info->fix.smem_start, info->fix.smem_len);
  1380. release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
  1381. fb_dealloc_cmap(&info->cmap);
  1382. if (!(vesafb & 2))
  1383. release_region(GEBase, 0x100);
  1384. if (!(vesafb & 1))
  1385. release_region(0x3c0, 32);
  1386. kfree(info->pixmap.addr);
  1387. framebuffer_release(info);
  1388. output("CyblaFB version %s normal exit.\n", VERSION);
  1389. }
  1390. //
  1391. // List of boards that we are trying to support
  1392. //
  1393. static struct pci_device_id cybla_devices[] = {
  1394. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  1395. {0,}
  1396. };
  1397. MODULE_DEVICE_TABLE(pci, cybla_devices);
  1398. static struct pci_driver cyblafb_pci_driver = {
  1399. .name = "cyblafb",
  1400. .id_table = cybla_devices,
  1401. .probe = cybla_pci_probe,
  1402. .remove = __devexit_p(cybla_pci_remove)
  1403. };
  1404. //=============================================================
  1405. //
  1406. // kernel command line example:
  1407. //
  1408. // video=cyblafb:1280x1024, bpp=16, ref=50 ...
  1409. //
  1410. // modprobe command line example:
  1411. //
  1412. // modprobe cyblafb mode=1280x1024 bpp=16 ref=50 ...
  1413. //
  1414. //=============================================================
  1415. static int __devinit cyblafb_init(void)
  1416. {
  1417. #ifndef MODULE
  1418. char *options = NULL;
  1419. char *opt;
  1420. if (fb_get_options("cyblafb", &options))
  1421. return -ENODEV;
  1422. if (options && *options)
  1423. while ((opt = strsep(&options, ",")) != NULL) {
  1424. if (!*opt)
  1425. continue;
  1426. else if (!strncmp(opt, "bpp=", 4))
  1427. bpp = simple_strtoul(opt + 4, NULL, 0);
  1428. else if (!strncmp(opt, "ref=", 4))
  1429. ref = simple_strtoul(opt + 4, NULL, 0);
  1430. else if (!strncmp(opt, "fp", 2))
  1431. displaytype = DISPLAY_FP;
  1432. else if (!strncmp(opt, "crt", 3))
  1433. displaytype = DISPLAY_CRT;
  1434. else if (!strncmp(opt, "nativex=", 8))
  1435. nativex = simple_strtoul(opt + 8, NULL, 0);
  1436. else if (!strncmp(opt, "center", 6))
  1437. center = 1;
  1438. else if (!strncmp(opt, "stretch", 7))
  1439. stretch = 1;
  1440. else if (!strncmp(opt, "pciwb=", 6))
  1441. pciwb = simple_strtoul(opt + 6, NULL, 0);
  1442. else if (!strncmp(opt, "pcirb=", 6))
  1443. pcirb = simple_strtoul(opt + 6, NULL, 0);
  1444. else if (!strncmp(opt, "pciwr=", 6))
  1445. pciwr = simple_strtoul(opt + 6, NULL, 0);
  1446. else if (!strncmp(opt, "pcirr=", 6))
  1447. pcirr = simple_strtoul(opt + 6, NULL, 0);
  1448. else if (!strncmp(opt, "memsize=", 8))
  1449. memsize = simple_strtoul(opt + 8, NULL, 0);
  1450. else if (!strncmp(opt, "verbosity=", 10))
  1451. verbosity = simple_strtoul(opt + 10, NULL, 0);
  1452. else
  1453. mode = opt;
  1454. }
  1455. #endif
  1456. output("CyblaFB version %s initializing\n", VERSION);
  1457. return pci_register_driver(&cyblafb_pci_driver);
  1458. }
  1459. static void __exit cyblafb_exit(void)
  1460. {
  1461. pci_unregister_driver(&cyblafb_pci_driver);
  1462. }
  1463. module_init(cyblafb_init);
  1464. module_exit(cyblafb_exit);
  1465. MODULE_AUTHOR("Knut Petersen <knut_petersen@t-online.de>");
  1466. MODULE_DESCRIPTION("Framebuffer driver for Cyberblade/i1 graphics core");
  1467. MODULE_LICENSE("GPL");