cyber2000fb.h 16 KB

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  1. /*
  2. * linux/drivers/video/cyber2000fb.h
  3. *
  4. * Copyright (C) 1998-2000 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Integraphics Cyber2000 frame buffer device
  11. */
  12. /*
  13. * Internal CyberPro sizes and offsets.
  14. */
  15. #define MMIO_OFFSET 0x00800000
  16. #define MMIO_SIZE 0x000c0000
  17. #define NR_PALETTE 256
  18. #if defined(DEBUG) && defined(CONFIG_DEBUG_LL)
  19. static void debug_printf(char *fmt, ...)
  20. {
  21. extern void printascii(const char *);
  22. char buffer[128];
  23. va_list ap;
  24. va_start(ap, fmt);
  25. vsprintf(buffer, fmt, ap);
  26. va_end(ap);
  27. printascii(buffer);
  28. }
  29. #else
  30. #define debug_printf(x...) do { } while (0)
  31. #endif
  32. #define RAMDAC_RAMPWRDN 0x01
  33. #define RAMDAC_DAC8BIT 0x02
  34. #define RAMDAC_VREFEN 0x04
  35. #define RAMDAC_BYPASS 0x10
  36. #define RAMDAC_DACPWRDN 0x40
  37. #define EXT_CRT_VRTOFL 0x11
  38. #define EXT_CRT_VRTOFL_LINECOMP10 0x10
  39. #define EXT_CRT_VRTOFL_INTERLACE 0x20
  40. #define EXT_CRT_IRQ 0x12
  41. #define EXT_CRT_IRQ_ENABLE 0x01
  42. #define EXT_CRT_IRQ_ACT_HIGH 0x04
  43. #define EXT_CRT_TEST 0x13
  44. #define EXT_SYNC_CTL 0x16
  45. #define EXT_SYNC_CTL_HS_NORMAL 0x00
  46. #define EXT_SYNC_CTL_HS_0 0x01
  47. #define EXT_SYNC_CTL_HS_1 0x02
  48. #define EXT_SYNC_CTL_HS_HSVS 0x03
  49. #define EXT_SYNC_CTL_VS_NORMAL 0x00
  50. #define EXT_SYNC_CTL_VS_0 0x04
  51. #define EXT_SYNC_CTL_VS_1 0x08
  52. #define EXT_SYNC_CTL_VS_COMP 0x0c
  53. #define EXT_BUS_CTL 0x30
  54. #define EXT_BUS_CTL_LIN_1MB 0x00
  55. #define EXT_BUS_CTL_LIN_2MB 0x01
  56. #define EXT_BUS_CTL_LIN_4MB 0x02
  57. #define EXT_BUS_CTL_ZEROWAIT 0x04
  58. #define EXT_BUS_CTL_PCIBURST_WRITE 0x20
  59. #define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */
  60. #define EXT_SEG_WRITE_PTR 0x31
  61. #define EXT_SEG_READ_PTR 0x32
  62. #define EXT_BIU_MISC 0x33
  63. #define EXT_BIU_MISC_LIN_ENABLE 0x01
  64. #define EXT_BIU_MISC_COP_ENABLE 0x04
  65. #define EXT_BIU_MISC_COP_BFC 0x08
  66. #define EXT_FUNC_CTL 0x3c
  67. #define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */
  68. #define PCI_BM_CTL 0x3e
  69. #define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */
  70. #define PCI_BM_CTL_BURST 0x02 /* enable burst */
  71. #define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */
  72. #define PCI_BM_CTL_DUMMY 0x08 /* insert dummy cycle */
  73. #define X_V2_VID_MEM_START 0x40
  74. #define X_V2_VID_SRC_WIDTH 0x43
  75. #define X_V2_X_START 0x45
  76. #define X_V2_X_END 0x47
  77. #define X_V2_Y_START 0x49
  78. #define X_V2_Y_END 0x4b
  79. #define X_V2_VID_SRC_WIN_WIDTH 0x4d
  80. #define Y_V2_DDA_X_INC 0x43
  81. #define Y_V2_DDA_Y_INC 0x47
  82. #define Y_V2_VID_FIFO_CTL 0x49
  83. #define Y_V2_VID_FMT 0x4b
  84. #define Y_V2_VID_DISP_CTL1 0x4c
  85. #define Y_V2_VID_FIFO_CTL1 0x4d
  86. #define J_X2_VID_MEM_START 0x40
  87. #define J_X2_VID_SRC_WIDTH 0x43
  88. #define J_X2_X_START 0x47
  89. #define J_X2_X_END 0x49
  90. #define J_X2_Y_START 0x4b
  91. #define J_X2_Y_END 0x4d
  92. #define J_X2_VID_SRC_WIN_WIDTH 0x4f
  93. #define K_X2_DDA_X_INIT 0x40
  94. #define K_X2_DDA_X_INC 0x42
  95. #define K_X2_DDA_Y_INIT 0x44
  96. #define K_X2_DDA_Y_INC 0x46
  97. #define K_X2_VID_FMT 0x48
  98. #define K_X2_VID_DISP_CTL1 0x49
  99. #define K_CAP_X2_CTL1 0x49
  100. #define CURS_H_START 0x50
  101. #define CURS_H_PRESET 0x52
  102. #define CURS_V_START 0x53
  103. #define CURS_V_PRESET 0x55
  104. #define CURS_CTL 0x56
  105. #define EXT_ATTRIB_CTL 0x57
  106. #define EXT_ATTRIB_CTL_EXT 0x01
  107. #define EXT_OVERSCAN_RED 0x58
  108. #define EXT_OVERSCAN_GREEN 0x59
  109. #define EXT_OVERSCAN_BLUE 0x5a
  110. #define CAP_X_START 0x60
  111. #define CAP_X_END 0x62
  112. #define CAP_Y_START 0x64
  113. #define CAP_Y_END 0x66
  114. #define CAP_DDA_X_INIT 0x68
  115. #define CAP_DDA_X_INC 0x6a
  116. #define CAP_DDA_Y_INIT 0x6c
  117. #define CAP_DDA_Y_INC 0x6e
  118. #define EXT_MEM_CTL0 0x70
  119. #define EXT_MEM_CTL0_7CLK 0x01
  120. #define EXT_MEM_CTL0_RAS_1 0x02
  121. #define EXT_MEM_CTL0_RAS2CAS_1 0x04
  122. #define EXT_MEM_CTL0_MULTCAS 0x08
  123. #define EXT_MEM_CTL0_ASYM 0x10
  124. #define EXT_MEM_CTL0_CAS1ON 0x20
  125. #define EXT_MEM_CTL0_FIFOFLUSH 0x40
  126. #define EXT_MEM_CTL0_SEQRESET 0x80
  127. #define EXT_MEM_CTL1 0x71
  128. #define EXT_MEM_CTL1_PAR 0x00
  129. #define EXT_MEM_CTL1_SERPAR 0x01
  130. #define EXT_MEM_CTL1_SER 0x03
  131. #define EXT_MEM_CTL1_SYNC 0x04
  132. #define EXT_MEM_CTL1_VRAM 0x08
  133. #define EXT_MEM_CTL1_4K_REFRESH 0x10
  134. #define EXT_MEM_CTL1_256Kx4 0x00
  135. #define EXT_MEM_CTL1_512Kx8 0x40
  136. #define EXT_MEM_CTL1_1Mx16 0x60
  137. #define EXT_MEM_CTL2 0x72
  138. #define MEM_CTL2_SIZE_1MB 0x00
  139. #define MEM_CTL2_SIZE_2MB 0x01
  140. #define MEM_CTL2_SIZE_4MB 0x02
  141. #define MEM_CTL2_SIZE_MASK 0x03
  142. #define MEM_CTL2_64BIT 0x04
  143. #define EXT_HIDDEN_CTL1 0x73
  144. #define EXT_FIFO_CTL 0x74
  145. #define EXT_SEQ_MISC 0x77
  146. #define EXT_SEQ_MISC_8 0x01
  147. #define EXT_SEQ_MISC_16_RGB565 0x02
  148. #define EXT_SEQ_MISC_32 0x03
  149. #define EXT_SEQ_MISC_24_RGB888 0x04
  150. #define EXT_SEQ_MISC_16_RGB555 0x06
  151. #define EXT_SEQ_MISC_8_RGB332 0x09
  152. #define EXT_SEQ_MISC_16_RGB444 0x0a
  153. #define EXT_HIDDEN_CTL4 0x7a
  154. #define CURS_MEM_START 0x7e /* bits 23..12 */
  155. #define CAP_PIP_X_START 0x80
  156. #define CAP_PIP_X_END 0x82
  157. #define CAP_PIP_Y_START 0x84
  158. #define CAP_PIP_Y_END 0x86
  159. #define EXT_CAP_CTL1 0x88
  160. #define EXT_CAP_CTL2 0x89
  161. #define EXT_CAP_CTL2_ODDFRAMEIRQ 0x01
  162. #define EXT_CAP_CTL2_ANYFRAMEIRQ 0x02
  163. #define BM_CTRL0 0x9c
  164. #define BM_CTRL1 0x9d
  165. #define EXT_CAP_MODE1 0xa4
  166. #define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */
  167. #define EXT_CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */
  168. #define EXT_CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */
  169. #define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */
  170. #define EXT_CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */
  171. #define EXT_CAP_MODE1_MIRRORY 0x40 /* mirror vertically */
  172. #define EXT_CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */
  173. #define EXT_CAP_MODE2 0xa5
  174. #define EXT_CAP_MODE2_CCIRINVOE 0x01
  175. #define EXT_CAP_MODE2_CCIRINVVGT 0x02
  176. #define EXT_CAP_MODE2_CCIRINVHGT 0x04
  177. #define EXT_CAP_MODE2_CCIRINVDG 0x08
  178. #define EXT_CAP_MODE2_DATEND 0x10
  179. #define EXT_CAP_MODE2_CCIRDGH 0x20
  180. #define EXT_CAP_MODE2_FIXSONY 0x40
  181. #define EXT_CAP_MODE2_SYNCFREEZE 0x80
  182. #define EXT_TV_CTL 0xae
  183. #define EXT_DCLK_MULT 0xb0
  184. #define EXT_DCLK_DIV 0xb1
  185. #define EXT_DCLK_DIV_VFSEL 0x20
  186. #define EXT_MCLK_MULT 0xb2
  187. #define EXT_MCLK_DIV 0xb3
  188. #define EXT_LATCH1 0xb5
  189. #define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */
  190. #define EXT_FEATURE 0xb7
  191. #define EXT_FEATURE_BUS_MASK 0x07 /* host bus mask */
  192. #define EXT_FEATURE_BUS_PCI 0x00
  193. #define EXT_FEATURE_BUS_VL_STD 0x04
  194. #define EXT_FEATURE_BUS_VL_LINEAR 0x05
  195. #define EXT_FEATURE_1682 0x20 /* IGS 1682 compatibility */
  196. #define EXT_LATCH2 0xb6
  197. #define EXT_LATCH2_I2C_CLKEN 0x10
  198. #define EXT_LATCH2_I2C_CLK 0x20
  199. #define EXT_LATCH2_I2C_DATEN 0x40
  200. #define EXT_LATCH2_I2C_DAT 0x80
  201. #define EXT_XT_CTL 0xbe
  202. #define EXT_XT_CAP16 0x04
  203. #define EXT_XT_LINEARFB 0x08
  204. #define EXT_XT_PAL 0x10
  205. #define EXT_MEM_START 0xc0 /* ext start address 21 bits */
  206. #define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */
  207. #define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */
  208. #define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */
  209. #define EXT_X_START 0xc5 /* ext->screen, 16 bits */
  210. #define EXT_X_END 0xc7 /* ext->screen, 16 bits */
  211. #define EXT_Y_START 0xc9 /* ext->screen, 16 bits */
  212. #define EXT_Y_END 0xcb /* ext->screen, 16 bits */
  213. #define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */
  214. #define EXT_COLOUR_COMPARE 0xce /* 24 bits */
  215. #define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */
  216. #define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */
  217. #define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */
  218. #define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */
  219. #define EXT_VID_FIFO_CTL 0xd9
  220. #define EXT_VID_FMT 0xdb
  221. #define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */
  222. #define EXT_VID_FMT_RGB555 0x01
  223. #define EXT_VID_FMT_RGB565 0x02
  224. #define EXT_VID_FMT_RGB888_24 0x03
  225. #define EXT_VID_FMT_RGB888_32 0x04
  226. #define EXT_VID_FMT_RGB8 0x05
  227. #define EXT_VID_FMT_RGB4444 0x06
  228. #define EXT_VID_FMT_RGB8T 0x07
  229. #define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */
  230. #define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */
  231. #define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */
  232. #define EXT_VID_FMT_YUV128 0x80 /* YUV data offset by 128 */
  233. #define EXT_VID_DISP_CTL1 0xdc
  234. #define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */
  235. #define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */
  236. #define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */
  237. #define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */
  238. #define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 (if YUV128 set) */
  239. #define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* disable vertical interpolation */
  240. #define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */
  241. #define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */
  242. #define EXT_VID_FIFO_CTL1 0xdd
  243. #define EXT_VID_FIFO_CTL1_OE_HIGH 0x02
  244. #define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */
  245. #define EXT_ROM_UCB4GH 0xe5
  246. #define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */
  247. #define EXT_ROM_UCB4GH_ODDFRAME 0x04 /* 1 = odd frame captured */
  248. #define EXT_ROM_UCB4GH_1HL 0x08 /* first horizonal line after VGT falling edge */
  249. #define EXT_ROM_UCB4GH_ODD 0x10 /* odd frame indicator */
  250. #define EXT_ROM_UCB4GH_INTSTAT 0x20 /* video interrupt */
  251. #define VFAC_CTL1 0xe8
  252. #define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/
  253. #define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */
  254. #define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */
  255. #define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */
  256. #define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */
  257. #define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */
  258. #define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */
  259. #define VFAC_CTL2 0xe9
  260. #define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */
  261. #define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */
  262. #define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */
  263. #define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */
  264. #define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */
  265. #define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */
  266. #define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */
  267. #define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */
  268. #define VFAC_CTL3 0xea
  269. #define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */
  270. #define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */
  271. #define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */
  272. #define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */
  273. #define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */
  274. #define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */
  275. #define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */
  276. #define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */
  277. #define CAP_MEM_START 0xeb /* 18 bits */
  278. #define CAP_MAP_WIDTH 0xed /* high 6 bits */
  279. #define CAP_PITCH 0xee /* 8 bits */
  280. #define CAP_CTL_MISC 0xef
  281. #define CAP_CTL_MISC_HDIV 0x01
  282. #define CAP_CTL_MISC_HDIV4 0x02
  283. #define CAP_CTL_MISC_ODDEVEN 0x04
  284. #define CAP_CTL_MISC_HSYNCDIV2 0x08
  285. #define CAP_CTL_MISC_SYNCTZHIGH 0x10
  286. #define CAP_CTL_MISC_SYNCTZOR 0x20
  287. #define CAP_CTL_MISC_DISPUSED 0x80
  288. #define REG_BANK 0xfa
  289. #define REG_BANK_X 0x00
  290. #define REG_BANK_Y 0x01
  291. #define REG_BANK_W 0x02
  292. #define REG_BANK_T 0x03
  293. #define REG_BANK_J 0x04
  294. #define REG_BANK_K 0x05
  295. /*
  296. * Bus-master
  297. */
  298. #define BM_VID_ADDR_LOW 0xbc040
  299. #define BM_VID_ADDR_HIGH 0xbc044
  300. #define BM_ADDRESS_LOW 0xbc080
  301. #define BM_ADDRESS_HIGH 0xbc084
  302. #define BM_LENGTH 0xbc088
  303. #define BM_CONTROL 0xbc08c
  304. #define BM_CONTROL_ENABLE 0x01 /* enable transfer */
  305. #define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */
  306. #define BM_CONTROL_INIT 0x04 /* initialise status & count */
  307. #define BM_COUNT 0xbc090 /* read-only */
  308. /*
  309. * TV registers
  310. */
  311. #define TV_VBLANK_EVEN_START 0xbe43c
  312. #define TV_VBLANK_EVEN_END 0xbe440
  313. #define TV_VBLANK_ODD_START 0xbe444
  314. #define TV_VBLANK_ODD_END 0xbe448
  315. #define TV_SYNC_YGAIN 0xbe44c
  316. #define TV_UV_GAIN 0xbe450
  317. #define TV_PED_UVDET 0xbe454
  318. #define TV_UV_BURST_AMP 0xbe458
  319. #define TV_HSYNC_START 0xbe45c
  320. #define TV_HSYNC_END 0xbe460
  321. #define TV_Y_DELAY1 0xbe464
  322. #define TV_Y_DELAY2 0xbe468
  323. #define TV_UV_DELAY1 0xbe46c
  324. #define TV_BURST_START 0xbe470
  325. #define TV_BURST_END 0xbe474
  326. #define TV_HBLANK_START 0xbe478
  327. #define TV_HBLANK_END 0xbe47c
  328. #define TV_PED_EVEN_START 0xbe480
  329. #define TV_PED_EVEN_END 0xbe484
  330. #define TV_PED_ODD_START 0xbe488
  331. #define TV_PED_ODD_END 0xbe48c
  332. #define TV_VSYNC_EVEN_START 0xbe490
  333. #define TV_VSYNC_EVEN_END 0xbe494
  334. #define TV_VSYNC_ODD_START 0xbe498
  335. #define TV_VSYNC_ODD_END 0xbe49c
  336. #define TV_SCFL 0xbe4a0
  337. #define TV_SCFH 0xbe4a4
  338. #define TV_SCP 0xbe4a8
  339. #define TV_DELAYBYPASS 0xbe4b4
  340. #define TV_EQL_END 0xbe4bc
  341. #define TV_SERR_START 0xbe4c0
  342. #define TV_SERR_END 0xbe4c4
  343. #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/
  344. #define TV_VSYNC_VGA_HS 0xbe4e8
  345. #define TV_FLICK_XMIN 0xbe514
  346. #define TV_FLICK_XMAX 0xbe518
  347. #define TV_FLICK_YMIN 0xbe51c
  348. #define TV_FLICK_YMAX 0xbe520
  349. /*
  350. * Graphics Co-processor
  351. */
  352. #define CO_REG_CONTROL 0xbf011
  353. #define CO_CTRL_BUSY 0x80
  354. #define CO_CTRL_CMDFULL 0x04
  355. #define CO_CTRL_FIFOEMPTY 0x02
  356. #define CO_CTRL_READY 0x01
  357. #define CO_REG_SRC_WIDTH 0xbf018
  358. #define CO_REG_PIXFMT 0xbf01c
  359. #define CO_PIXFMT_32BPP 0x03
  360. #define CO_PIXFMT_24BPP 0x02
  361. #define CO_PIXFMT_16BPP 0x01
  362. #define CO_PIXFMT_8BPP 0x00
  363. #define CO_REG_FGMIX 0xbf048
  364. #define CO_FG_MIX_ZERO 0x00
  365. #define CO_FG_MIX_SRC_AND_DST 0x01
  366. #define CO_FG_MIX_SRC_AND_NDST 0x02
  367. #define CO_FG_MIX_SRC 0x03
  368. #define CO_FG_MIX_NSRC_AND_DST 0x04
  369. #define CO_FG_MIX_DST 0x05
  370. #define CO_FG_MIX_SRC_XOR_DST 0x06
  371. #define CO_FG_MIX_SRC_OR_DST 0x07
  372. #define CO_FG_MIX_NSRC_AND_NDST 0x08
  373. #define CO_FG_MIX_SRC_XOR_NDST 0x09
  374. #define CO_FG_MIX_NDST 0x0a
  375. #define CO_FG_MIX_SRC_OR_NDST 0x0b
  376. #define CO_FG_MIX_NSRC 0x0c
  377. #define CO_FG_MIX_NSRC_OR_DST 0x0d
  378. #define CO_FG_MIX_NSRC_OR_NDST 0x0e
  379. #define CO_FG_MIX_ONES 0x0f
  380. #define CO_REG_FGCOLOUR 0xbf058
  381. #define CO_REG_BGCOLOUR 0xbf05c
  382. #define CO_REG_PIXWIDTH 0xbf060
  383. #define CO_REG_PIXHEIGHT 0xbf062
  384. #define CO_REG_X_PHASE 0xbf078
  385. #define CO_REG_CMD_L 0xbf07c
  386. #define CO_CMD_L_PATTERN_FGCOL 0x8000
  387. #define CO_CMD_L_INC_LEFT 0x0004
  388. #define CO_CMD_L_INC_UP 0x0002
  389. #define CO_REG_CMD_H 0xbf07e
  390. #define CO_CMD_H_BGSRCMAP 0x8000 /* otherwise bg colour */
  391. #define CO_CMD_H_FGSRCMAP 0x2000 /* otherwise fg colour */
  392. #define CO_CMD_H_BLITTER 0x0800
  393. #define CO_REG_SRC1_PTR 0xbf170
  394. #define CO_REG_SRC2_PTR 0xbf174
  395. #define CO_REG_DEST_PTR 0xbf178
  396. #define CO_REG_DEST_WIDTH 0xbf218
  397. /*
  398. * Private structure
  399. */
  400. struct cfb_info;
  401. struct cyberpro_info {
  402. struct pci_dev *dev;
  403. unsigned char __iomem *regs;
  404. char __iomem *fb;
  405. char dev_name[32];
  406. unsigned int fb_size;
  407. unsigned int chip_id;
  408. /*
  409. * The following is a pointer to be passed into the
  410. * functions below. The modules outside the main
  411. * cyber2000fb.c driver have no knowledge as to what
  412. * is within this structure.
  413. */
  414. struct cfb_info *info;
  415. /*
  416. * Use these to enable the BM or TV registers. In an SMP
  417. * environment, these two function pointers should only be
  418. * called from the module_init() or module_exit()
  419. * functions.
  420. */
  421. void (*enable_extregs)(struct cfb_info *);
  422. void (*disable_extregs)(struct cfb_info *);
  423. };
  424. #define ID_IGA_1682 0
  425. #define ID_CYBERPRO_2000 1
  426. #define ID_CYBERPRO_2010 2
  427. #define ID_CYBERPRO_5000 3
  428. struct fb_var_screeninfo;
  429. /*
  430. * Note! Writing to the Cyber20x0 registers from an interrupt
  431. * routine is definitely a bad idea atm.
  432. */
  433. int cyber2000fb_attach(struct cyberpro_info *info, int idx);
  434. void cyber2000fb_detach(int idx);
  435. void cyber2000fb_enable_extregs(struct cfb_info *cfb);
  436. void cyber2000fb_disable_extregs(struct cfb_info *cfb);
  437. void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var);