cyber2000fb.c 43 KB

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  1. /*
  2. * linux/drivers/video/cyber2000fb.c
  3. *
  4. * Copyright (C) 1998-2002 Russell King
  5. *
  6. * MIPS and 50xx clock support
  7. * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com>
  8. *
  9. * 32 bit support, text color and panning fixes for modes != 8 bit
  10. * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
  17. *
  18. * Based on cyberfb.c.
  19. *
  20. * Note that we now use the new fbcon fix, var and cmap scheme. We do
  21. * still have to check which console is the currently displayed one
  22. * however, especially for the colourmap stuff.
  23. *
  24. * We also use the new hotplug PCI subsystem. I'm not sure if there
  25. * are any such cards, but I'm erring on the side of caution. We don't
  26. * want to go pop just because someone does have one.
  27. *
  28. * Note that this doesn't work fully in the case of multiple CyberPro
  29. * cards with grabbers. We currently can only attach to the first
  30. * CyberPro card found.
  31. *
  32. * When we're in truecolour mode, we power down the LUT RAM as a power
  33. * saving feature. Also, when we enter any of the powersaving modes
  34. * (except soft blanking) we power down the RAMDACs. This saves about
  35. * 1W, which is roughly 8% of the power consumption of a NetWinder
  36. * (which, incidentally, is about the same saving as a 2.5in hard disk
  37. * entering standby mode.)
  38. */
  39. #include <linux/module.h>
  40. #include <linux/kernel.h>
  41. #include <linux/errno.h>
  42. #include <linux/string.h>
  43. #include <linux/mm.h>
  44. #include <linux/slab.h>
  45. #include <linux/delay.h>
  46. #include <linux/fb.h>
  47. #include <linux/pci.h>
  48. #include <linux/init.h>
  49. #include <asm/io.h>
  50. #include <asm/pgtable.h>
  51. #include <asm/system.h>
  52. #include <asm/uaccess.h>
  53. #ifdef __arm__
  54. #include <asm/mach-types.h>
  55. #endif
  56. #include "cyber2000fb.h"
  57. struct cfb_info {
  58. struct fb_info fb;
  59. struct display_switch *dispsw;
  60. struct display *display;
  61. struct pci_dev *dev;
  62. unsigned char __iomem *region;
  63. unsigned char __iomem *regs;
  64. u_int id;
  65. int func_use_count;
  66. u_long ref_ps;
  67. /*
  68. * Clock divisors
  69. */
  70. u_int divisors[4];
  71. struct {
  72. u8 red, green, blue;
  73. } palette[NR_PALETTE];
  74. u_char mem_ctl1;
  75. u_char mem_ctl2;
  76. u_char mclk_mult;
  77. u_char mclk_div;
  78. /*
  79. * RAMDAC control register is both of these or'ed together
  80. */
  81. u_char ramdac_ctrl;
  82. u_char ramdac_powerdown;
  83. u32 pseudo_palette[16];
  84. };
  85. static char *default_font = "Acorn8x8";
  86. module_param(default_font, charp, 0);
  87. MODULE_PARM_DESC(default_font, "Default font name");
  88. /*
  89. * Our access methods.
  90. */
  91. #define cyber2000fb_writel(val,reg,cfb) writel(val, (cfb)->regs + (reg))
  92. #define cyber2000fb_writew(val,reg,cfb) writew(val, (cfb)->regs + (reg))
  93. #define cyber2000fb_writeb(val,reg,cfb) writeb(val, (cfb)->regs + (reg))
  94. #define cyber2000fb_readb(reg,cfb) readb((cfb)->regs + (reg))
  95. static inline void
  96. cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
  97. {
  98. cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb);
  99. }
  100. static inline void
  101. cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
  102. {
  103. cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb);
  104. }
  105. static inline unsigned int
  106. cyber2000_grphr(unsigned int reg, struct cfb_info *cfb)
  107. {
  108. cyber2000fb_writeb(reg, 0x3ce, cfb);
  109. return cyber2000fb_readb(0x3cf, cfb);
  110. }
  111. static inline void
  112. cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
  113. {
  114. cyber2000fb_readb(0x3da, cfb);
  115. cyber2000fb_writeb(reg, 0x3c0, cfb);
  116. cyber2000fb_readb(0x3c1, cfb);
  117. cyber2000fb_writeb(val, 0x3c0, cfb);
  118. }
  119. static inline void
  120. cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
  121. {
  122. cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb);
  123. }
  124. /* -------------------- Hardware specific routines ------------------------- */
  125. /*
  126. * Hardware Cyber2000 Acceleration
  127. */
  128. static void
  129. cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  130. {
  131. struct cfb_info *cfb = (struct cfb_info *)info;
  132. unsigned long dst, col;
  133. if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
  134. cfb_fillrect(info, rect);
  135. return;
  136. }
  137. cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
  138. cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb);
  139. cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb);
  140. col = rect->color;
  141. if (cfb->fb.var.bits_per_pixel > 8)
  142. col = ((u32 *)cfb->fb.pseudo_palette)[col];
  143. cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb);
  144. dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual;
  145. if (cfb->fb.var.bits_per_pixel == 24) {
  146. cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
  147. dst *= 3;
  148. }
  149. cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
  150. cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
  151. cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb);
  152. cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb);
  153. }
  154. static void
  155. cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
  156. {
  157. struct cfb_info *cfb = (struct cfb_info *)info;
  158. unsigned int cmd = CO_CMD_L_PATTERN_FGCOL;
  159. unsigned long src, dst;
  160. if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
  161. cfb_copyarea(info, region);
  162. return;
  163. }
  164. cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
  165. cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb);
  166. cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb);
  167. src = region->sx + region->sy * cfb->fb.var.xres_virtual;
  168. dst = region->dx + region->dy * cfb->fb.var.xres_virtual;
  169. if (region->sx < region->dx) {
  170. src += region->width - 1;
  171. dst += region->width - 1;
  172. cmd |= CO_CMD_L_INC_LEFT;
  173. }
  174. if (region->sy < region->dy) {
  175. src += (region->height - 1) * cfb->fb.var.xres_virtual;
  176. dst += (region->height - 1) * cfb->fb.var.xres_virtual;
  177. cmd |= CO_CMD_L_INC_UP;
  178. }
  179. if (cfb->fb.var.bits_per_pixel == 24) {
  180. cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
  181. src *= 3;
  182. dst *= 3;
  183. }
  184. cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb);
  185. cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
  186. cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
  187. cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb);
  188. cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER,
  189. CO_REG_CMD_H, cfb);
  190. }
  191. static void
  192. cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image)
  193. {
  194. // struct cfb_info *cfb = (struct cfb_info *)info;
  195. // if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
  196. cfb_imageblit(info, image);
  197. return;
  198. // }
  199. }
  200. static int cyber2000fb_sync(struct fb_info *info)
  201. {
  202. struct cfb_info *cfb = (struct cfb_info *)info;
  203. int count = 100000;
  204. if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT))
  205. return 0;
  206. while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) {
  207. if (!count--) {
  208. debug_printf("accel_wait timed out\n");
  209. cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
  210. break;
  211. }
  212. udelay(1);
  213. }
  214. return 0;
  215. }
  216. /*
  217. * ===========================================================================
  218. */
  219. static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf)
  220. {
  221. u_int mask = (1 << bf->length) - 1;
  222. return (val >> (16 - bf->length) & mask) << bf->offset;
  223. }
  224. /*
  225. * Set a single color register. Return != 0 for invalid regno.
  226. */
  227. static int
  228. cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  229. u_int transp, struct fb_info *info)
  230. {
  231. struct cfb_info *cfb = (struct cfb_info *)info;
  232. struct fb_var_screeninfo *var = &cfb->fb.var;
  233. u32 pseudo_val;
  234. int ret = 1;
  235. switch (cfb->fb.fix.visual) {
  236. default:
  237. return 1;
  238. /*
  239. * Pseudocolour:
  240. * 8 8
  241. * pixel --/--+--/--> red lut --> red dac
  242. * | 8
  243. * +--/--> green lut --> green dac
  244. * | 8
  245. * +--/--> blue lut --> blue dac
  246. */
  247. case FB_VISUAL_PSEUDOCOLOR:
  248. if (regno >= NR_PALETTE)
  249. return 1;
  250. red >>= 8;
  251. green >>= 8;
  252. blue >>= 8;
  253. cfb->palette[regno].red = red;
  254. cfb->palette[regno].green = green;
  255. cfb->palette[regno].blue = blue;
  256. cyber2000fb_writeb(regno, 0x3c8, cfb);
  257. cyber2000fb_writeb(red, 0x3c9, cfb);
  258. cyber2000fb_writeb(green, 0x3c9, cfb);
  259. cyber2000fb_writeb(blue, 0x3c9, cfb);
  260. return 0;
  261. /*
  262. * Direct colour:
  263. * n rl
  264. * pixel --/--+--/--> red lut --> red dac
  265. * | gl
  266. * +--/--> green lut --> green dac
  267. * | bl
  268. * +--/--> blue lut --> blue dac
  269. * n = bpp, rl = red length, gl = green length, bl = blue length
  270. */
  271. case FB_VISUAL_DIRECTCOLOR:
  272. red >>= 8;
  273. green >>= 8;
  274. blue >>= 8;
  275. if (var->green.length == 6 && regno < 64) {
  276. cfb->palette[regno << 2].green = green;
  277. /*
  278. * The 6 bits of the green component are applied
  279. * to the high 6 bits of the LUT.
  280. */
  281. cyber2000fb_writeb(regno << 2, 0x3c8, cfb);
  282. cyber2000fb_writeb(cfb->palette[regno >> 1].red, 0x3c9, cfb);
  283. cyber2000fb_writeb(green, 0x3c9, cfb);
  284. cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 0x3c9, cfb);
  285. green = cfb->palette[regno << 3].green;
  286. ret = 0;
  287. }
  288. if (var->green.length >= 5 && regno < 32) {
  289. cfb->palette[regno << 3].red = red;
  290. cfb->palette[regno << 3].green = green;
  291. cfb->palette[regno << 3].blue = blue;
  292. /*
  293. * The 5 bits of each colour component are
  294. * applied to the high 5 bits of the LUT.
  295. */
  296. cyber2000fb_writeb(regno << 3, 0x3c8, cfb);
  297. cyber2000fb_writeb(red, 0x3c9, cfb);
  298. cyber2000fb_writeb(green, 0x3c9, cfb);
  299. cyber2000fb_writeb(blue, 0x3c9, cfb);
  300. ret = 0;
  301. }
  302. if (var->green.length == 4 && regno < 16) {
  303. cfb->palette[regno << 4].red = red;
  304. cfb->palette[regno << 4].green = green;
  305. cfb->palette[regno << 4].blue = blue;
  306. /*
  307. * The 5 bits of each colour component are
  308. * applied to the high 5 bits of the LUT.
  309. */
  310. cyber2000fb_writeb(regno << 4, 0x3c8, cfb);
  311. cyber2000fb_writeb(red, 0x3c9, cfb);
  312. cyber2000fb_writeb(green, 0x3c9, cfb);
  313. cyber2000fb_writeb(blue, 0x3c9, cfb);
  314. ret = 0;
  315. }
  316. /*
  317. * Since this is only used for the first 16 colours, we
  318. * don't have to care about overflowing for regno >= 32
  319. */
  320. pseudo_val = regno << var->red.offset |
  321. regno << var->green.offset |
  322. regno << var->blue.offset;
  323. break;
  324. /*
  325. * True colour:
  326. * n rl
  327. * pixel --/--+--/--> red dac
  328. * | gl
  329. * +--/--> green dac
  330. * | bl
  331. * +--/--> blue dac
  332. * n = bpp, rl = red length, gl = green length, bl = blue length
  333. */
  334. case FB_VISUAL_TRUECOLOR:
  335. pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp);
  336. pseudo_val |= convert_bitfield(red, &var->red);
  337. pseudo_val |= convert_bitfield(green, &var->green);
  338. pseudo_val |= convert_bitfield(blue, &var->blue);
  339. break;
  340. }
  341. /*
  342. * Now set our pseudo palette for the CFB16/24/32 drivers.
  343. */
  344. if (regno < 16)
  345. ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val;
  346. return ret;
  347. }
  348. struct par_info {
  349. /*
  350. * Hardware
  351. */
  352. u_char clock_mult;
  353. u_char clock_div;
  354. u_char extseqmisc;
  355. u_char co_pixfmt;
  356. u_char crtc_ofl;
  357. u_char crtc[19];
  358. u_int width;
  359. u_int pitch;
  360. u_int fetch;
  361. /*
  362. * Other
  363. */
  364. u_char ramdac;
  365. };
  366. static const u_char crtc_idx[] = {
  367. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  368. 0x08, 0x09,
  369. 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
  370. };
  371. static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
  372. {
  373. unsigned int i;
  374. unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown;
  375. cyber2000fb_writeb(0x56, 0x3ce, cfb);
  376. i = cyber2000fb_readb(0x3cf, cfb);
  377. cyber2000fb_writeb(i | 4, 0x3cf, cfb);
  378. cyber2000fb_writeb(val, 0x3c6, cfb);
  379. cyber2000fb_writeb(i, 0x3cf, cfb);
  380. }
  381. static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
  382. {
  383. u_int i;
  384. /*
  385. * Blank palette
  386. */
  387. for (i = 0; i < NR_PALETTE; i++) {
  388. cyber2000fb_writeb(i, 0x3c8, cfb);
  389. cyber2000fb_writeb(0, 0x3c9, cfb);
  390. cyber2000fb_writeb(0, 0x3c9, cfb);
  391. cyber2000fb_writeb(0, 0x3c9, cfb);
  392. }
  393. cyber2000fb_writeb(0xef, 0x3c2, cfb);
  394. cyber2000_crtcw(0x11, 0x0b, cfb);
  395. cyber2000_attrw(0x11, 0x00, cfb);
  396. cyber2000_seqw(0x00, 0x01, cfb);
  397. cyber2000_seqw(0x01, 0x01, cfb);
  398. cyber2000_seqw(0x02, 0x0f, cfb);
  399. cyber2000_seqw(0x03, 0x00, cfb);
  400. cyber2000_seqw(0x04, 0x0e, cfb);
  401. cyber2000_seqw(0x00, 0x03, cfb);
  402. for (i = 0; i < sizeof(crtc_idx); i++)
  403. cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb);
  404. for (i = 0x0a; i < 0x10; i++)
  405. cyber2000_crtcw(i, 0, cfb);
  406. cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb);
  407. cyber2000_grphw(0x00, 0x00, cfb);
  408. cyber2000_grphw(0x01, 0x00, cfb);
  409. cyber2000_grphw(0x02, 0x00, cfb);
  410. cyber2000_grphw(0x03, 0x00, cfb);
  411. cyber2000_grphw(0x04, 0x00, cfb);
  412. cyber2000_grphw(0x05, 0x60, cfb);
  413. cyber2000_grphw(0x06, 0x05, cfb);
  414. cyber2000_grphw(0x07, 0x0f, cfb);
  415. cyber2000_grphw(0x08, 0xff, cfb);
  416. /* Attribute controller registers */
  417. for (i = 0; i < 16; i++)
  418. cyber2000_attrw(i, i, cfb);
  419. cyber2000_attrw(0x10, 0x01, cfb);
  420. cyber2000_attrw(0x11, 0x00, cfb);
  421. cyber2000_attrw(0x12, 0x0f, cfb);
  422. cyber2000_attrw(0x13, 0x00, cfb);
  423. cyber2000_attrw(0x14, 0x00, cfb);
  424. /* PLL registers */
  425. cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
  426. cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb);
  427. cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
  428. cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb);
  429. cyber2000_grphw(0x90, 0x01, cfb);
  430. cyber2000_grphw(0xb9, 0x80, cfb);
  431. cyber2000_grphw(0xb9, 0x00, cfb);
  432. cfb->ramdac_ctrl = hw->ramdac;
  433. cyber2000fb_write_ramdac_ctrl(cfb);
  434. cyber2000fb_writeb(0x20, 0x3c0, cfb);
  435. cyber2000fb_writeb(0xff, 0x3c6, cfb);
  436. cyber2000_grphw(0x14, hw->fetch, cfb);
  437. cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) |
  438. ((hw->pitch >> 4) & 0x30), cfb);
  439. cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb);
  440. /*
  441. * Set up accelerator registers
  442. */
  443. cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb);
  444. cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb);
  445. cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb);
  446. }
  447. static inline int
  448. cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var)
  449. {
  450. u_int base = var->yoffset * var->xres_virtual + var->xoffset;
  451. base *= var->bits_per_pixel;
  452. /*
  453. * Convert to bytes and shift two extra bits because DAC
  454. * can only start on 4 byte aligned data.
  455. */
  456. base >>= 5;
  457. if (base >= 1 << 20)
  458. return -EINVAL;
  459. cyber2000_grphw(0x10, base >> 16 | 0x10, cfb);
  460. cyber2000_crtcw(0x0c, base >> 8, cfb);
  461. cyber2000_crtcw(0x0d, base, cfb);
  462. return 0;
  463. }
  464. static int
  465. cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb,
  466. struct fb_var_screeninfo *var)
  467. {
  468. u_int Htotal, Hblankend, Hsyncend;
  469. u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend;
  470. #define BIT(v,b1,m,b2) (((v >> b1) & m) << b2)
  471. hw->crtc[13] = hw->pitch;
  472. hw->crtc[17] = 0xe3;
  473. hw->crtc[14] = 0;
  474. hw->crtc[8] = 0;
  475. Htotal = var->xres + var->right_margin +
  476. var->hsync_len + var->left_margin;
  477. if (Htotal > 2080)
  478. return -EINVAL;
  479. hw->crtc[0] = (Htotal >> 3) - 5;
  480. hw->crtc[1] = (var->xres >> 3) - 1;
  481. hw->crtc[2] = var->xres >> 3;
  482. hw->crtc[4] = (var->xres + var->right_margin) >> 3;
  483. Hblankend = (Htotal - 4*8) >> 3;
  484. hw->crtc[3] = BIT(Hblankend, 0, 0x1f, 0) |
  485. BIT(1, 0, 0x01, 7);
  486. Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3;
  487. hw->crtc[5] = BIT(Hsyncend, 0, 0x1f, 0) |
  488. BIT(Hblankend, 5, 0x01, 7);
  489. Vdispend = var->yres - 1;
  490. Vsyncstart = var->yres + var->lower_margin;
  491. Vsyncend = var->yres + var->lower_margin + var->vsync_len;
  492. Vtotal = var->yres + var->lower_margin + var->vsync_len +
  493. var->upper_margin - 2;
  494. if (Vtotal > 2047)
  495. return -EINVAL;
  496. Vblankstart = var->yres + 6;
  497. Vblankend = Vtotal - 10;
  498. hw->crtc[6] = Vtotal;
  499. hw->crtc[7] = BIT(Vtotal, 8, 0x01, 0) |
  500. BIT(Vdispend, 8, 0x01, 1) |
  501. BIT(Vsyncstart, 8, 0x01, 2) |
  502. BIT(Vblankstart,8, 0x01, 3) |
  503. BIT(1, 0, 0x01, 4) |
  504. BIT(Vtotal, 9, 0x01, 5) |
  505. BIT(Vdispend, 9, 0x01, 6) |
  506. BIT(Vsyncstart, 9, 0x01, 7);
  507. hw->crtc[9] = BIT(0, 0, 0x1f, 0) |
  508. BIT(Vblankstart,9, 0x01, 5) |
  509. BIT(1, 0, 0x01, 6);
  510. hw->crtc[10] = Vsyncstart;
  511. hw->crtc[11] = BIT(Vsyncend, 0, 0x0f, 0) |
  512. BIT(1, 0, 0x01, 7);
  513. hw->crtc[12] = Vdispend;
  514. hw->crtc[15] = Vblankstart;
  515. hw->crtc[16] = Vblankend;
  516. hw->crtc[18] = 0xff;
  517. /*
  518. * overflow - graphics reg 0x11
  519. * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
  520. * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
  521. */
  522. hw->crtc_ofl =
  523. BIT(Vtotal, 10, 0x01, 0) |
  524. BIT(Vdispend, 10, 0x01, 1) |
  525. BIT(Vsyncstart, 10, 0x01, 2) |
  526. BIT(Vblankstart,10, 0x01, 3) |
  527. EXT_CRT_VRTOFL_LINECOMP10;
  528. /* woody: set the interlaced bit... */
  529. /* FIXME: what about doublescan? */
  530. if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
  531. hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE;
  532. return 0;
  533. }
  534. /*
  535. * The following was discovered by a good monitor, bit twiddling, theorising
  536. * and but mostly luck. Strangely, it looks like everyone elses' PLL!
  537. *
  538. * Clock registers:
  539. * fclock = fpll / div2
  540. * fpll = fref * mult / div1
  541. * where:
  542. * fref = 14.318MHz (69842ps)
  543. * mult = reg0xb0.7:0
  544. * div1 = (reg0xb1.5:0 + 1)
  545. * div2 = 2^(reg0xb1.7:6)
  546. * fpll should be between 115 and 260 MHz
  547. * (8696ps and 3846ps)
  548. */
  549. static int
  550. cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
  551. struct fb_var_screeninfo *var)
  552. {
  553. u_long pll_ps = var->pixclock;
  554. const u_long ref_ps = cfb->ref_ps;
  555. u_int div2, t_div1, best_div1, best_mult;
  556. int best_diff;
  557. int vco;
  558. /*
  559. * Step 1:
  560. * find div2 such that 115MHz < fpll < 260MHz
  561. * and 0 <= div2 < 4
  562. */
  563. for (div2 = 0; div2 < 4; div2++) {
  564. u_long new_pll;
  565. new_pll = pll_ps / cfb->divisors[div2];
  566. if (8696 > new_pll && new_pll > 3846) {
  567. pll_ps = new_pll;
  568. break;
  569. }
  570. }
  571. if (div2 == 4)
  572. return -EINVAL;
  573. /*
  574. * Step 2:
  575. * Given pll_ps and ref_ps, find:
  576. * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
  577. * where { 1 < best_div1 < 32, 1 < best_mult < 256 }
  578. * pll_ps_calc = best_div1 / (ref_ps * best_mult)
  579. */
  580. best_diff = 0x7fffffff;
  581. best_mult = 32;
  582. best_div1 = 255;
  583. for (t_div1 = 32; t_div1 > 1; t_div1 -= 1) {
  584. u_int rr, t_mult, t_pll_ps;
  585. int diff;
  586. /*
  587. * Find the multiplier for this divisor
  588. */
  589. rr = ref_ps * t_div1;
  590. t_mult = (rr + pll_ps / 2) / pll_ps;
  591. /*
  592. * Is the multiplier within the correct range?
  593. */
  594. if (t_mult > 256 || t_mult < 2)
  595. continue;
  596. /*
  597. * Calculate the actual clock period from this multiplier
  598. * and divisor, and estimate the error.
  599. */
  600. t_pll_ps = (rr + t_mult / 2) / t_mult;
  601. diff = pll_ps - t_pll_ps;
  602. if (diff < 0)
  603. diff = -diff;
  604. if (diff < best_diff) {
  605. best_diff = diff;
  606. best_mult = t_mult;
  607. best_div1 = t_div1;
  608. }
  609. /*
  610. * If we hit an exact value, there is no point in continuing.
  611. */
  612. if (diff == 0)
  613. break;
  614. }
  615. /*
  616. * Step 3:
  617. * combine values
  618. */
  619. hw->clock_mult = best_mult - 1;
  620. hw->clock_div = div2 << 6 | (best_div1 - 1);
  621. vco = ref_ps * best_div1 / best_mult;
  622. if ((ref_ps == 40690) && (vco < 5556))
  623. /* Set VFSEL when VCO > 180MHz (5.556 ps). */
  624. hw->clock_div |= EXT_DCLK_DIV_VFSEL;
  625. return 0;
  626. }
  627. /*
  628. * Set the User Defined Part of the Display
  629. */
  630. static int
  631. cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  632. {
  633. struct cfb_info *cfb = (struct cfb_info *)info;
  634. struct par_info hw;
  635. unsigned int mem;
  636. int err;
  637. var->transp.msb_right = 0;
  638. var->red.msb_right = 0;
  639. var->green.msb_right = 0;
  640. var->blue.msb_right = 0;
  641. switch (var->bits_per_pixel) {
  642. case 8: /* PSEUDOCOLOUR, 256 */
  643. var->transp.offset = 0;
  644. var->transp.length = 0;
  645. var->red.offset = 0;
  646. var->red.length = 8;
  647. var->green.offset = 0;
  648. var->green.length = 8;
  649. var->blue.offset = 0;
  650. var->blue.length = 8;
  651. break;
  652. case 16:/* DIRECTCOLOUR, 64k or 32k */
  653. switch (var->green.length) {
  654. case 6: /* RGB565, 64k */
  655. var->transp.offset = 0;
  656. var->transp.length = 0;
  657. var->red.offset = 11;
  658. var->red.length = 5;
  659. var->green.offset = 5;
  660. var->green.length = 6;
  661. var->blue.offset = 0;
  662. var->blue.length = 5;
  663. break;
  664. default:
  665. case 5: /* RGB555, 32k */
  666. var->transp.offset = 0;
  667. var->transp.length = 0;
  668. var->red.offset = 10;
  669. var->red.length = 5;
  670. var->green.offset = 5;
  671. var->green.length = 5;
  672. var->blue.offset = 0;
  673. var->blue.length = 5;
  674. break;
  675. case 4: /* RGB444, 4k + transparency? */
  676. var->transp.offset = 12;
  677. var->transp.length = 4;
  678. var->red.offset = 8;
  679. var->red.length = 4;
  680. var->green.offset = 4;
  681. var->green.length = 4;
  682. var->blue.offset = 0;
  683. var->blue.length = 4;
  684. break;
  685. }
  686. break;
  687. case 24:/* TRUECOLOUR, 16m */
  688. var->transp.offset = 0;
  689. var->transp.length = 0;
  690. var->red.offset = 16;
  691. var->red.length = 8;
  692. var->green.offset = 8;
  693. var->green.length = 8;
  694. var->blue.offset = 0;
  695. var->blue.length = 8;
  696. break;
  697. case 32:/* TRUECOLOUR, 16m */
  698. var->transp.offset = 24;
  699. var->transp.length = 8;
  700. var->red.offset = 16;
  701. var->red.length = 8;
  702. var->green.offset = 8;
  703. var->green.length = 8;
  704. var->blue.offset = 0;
  705. var->blue.length = 8;
  706. break;
  707. default:
  708. return -EINVAL;
  709. }
  710. mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
  711. if (mem > cfb->fb.fix.smem_len)
  712. var->yres_virtual = cfb->fb.fix.smem_len * 8 /
  713. (var->bits_per_pixel * var->xres_virtual);
  714. if (var->yres > var->yres_virtual)
  715. var->yres = var->yres_virtual;
  716. if (var->xres > var->xres_virtual)
  717. var->xres = var->xres_virtual;
  718. err = cyber2000fb_decode_clock(&hw, cfb, var);
  719. if (err)
  720. return err;
  721. err = cyber2000fb_decode_crtc(&hw, cfb, var);
  722. if (err)
  723. return err;
  724. return 0;
  725. }
  726. static int cyber2000fb_set_par(struct fb_info *info)
  727. {
  728. struct cfb_info *cfb = (struct cfb_info *)info;
  729. struct fb_var_screeninfo *var = &cfb->fb.var;
  730. struct par_info hw;
  731. unsigned int mem;
  732. hw.width = var->xres_virtual;
  733. hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT;
  734. switch (var->bits_per_pixel) {
  735. case 8:
  736. hw.co_pixfmt = CO_PIXFMT_8BPP;
  737. hw.pitch = hw.width >> 3;
  738. hw.extseqmisc = EXT_SEQ_MISC_8;
  739. break;
  740. case 16:
  741. hw.co_pixfmt = CO_PIXFMT_16BPP;
  742. hw.pitch = hw.width >> 2;
  743. switch (var->green.length) {
  744. case 6: /* RGB565, 64k */
  745. hw.extseqmisc = EXT_SEQ_MISC_16_RGB565;
  746. break;
  747. case 5: /* RGB555, 32k */
  748. hw.extseqmisc = EXT_SEQ_MISC_16_RGB555;
  749. break;
  750. case 4: /* RGB444, 4k + transparency? */
  751. hw.extseqmisc = EXT_SEQ_MISC_16_RGB444;
  752. break;
  753. default:
  754. BUG();
  755. }
  756. case 24:/* TRUECOLOUR, 16m */
  757. hw.co_pixfmt = CO_PIXFMT_24BPP;
  758. hw.width *= 3;
  759. hw.pitch = hw.width >> 3;
  760. hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
  761. hw.extseqmisc = EXT_SEQ_MISC_24_RGB888;
  762. break;
  763. case 32:/* TRUECOLOUR, 16m */
  764. hw.co_pixfmt = CO_PIXFMT_32BPP;
  765. hw.pitch = hw.width >> 1;
  766. hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
  767. hw.extseqmisc = EXT_SEQ_MISC_32;
  768. break;
  769. default:
  770. BUG();
  771. }
  772. /*
  773. * Sigh, this is absolutely disgusting, but caused by
  774. * the way the fbcon developers want to separate out
  775. * the "checking" and the "setting" of the video mode.
  776. *
  777. * If the mode is not suitable for the hardware here,
  778. * we can't prevent it being set by returning an error.
  779. *
  780. * In theory, since NetWinders contain just one VGA card,
  781. * we should never end up hitting this problem.
  782. */
  783. BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0);
  784. BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0);
  785. hw.width -= 1;
  786. hw.fetch = hw.pitch;
  787. if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT))
  788. hw.fetch <<= 1;
  789. hw.fetch += 1;
  790. cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
  791. /*
  792. * Same here - if the size of the video mode exceeds the
  793. * available RAM, we can't prevent this mode being set.
  794. *
  795. * In theory, since NetWinders contain just one VGA card,
  796. * we should never end up hitting this problem.
  797. */
  798. mem = cfb->fb.fix.line_length * var->yres_virtual;
  799. BUG_ON(mem > cfb->fb.fix.smem_len);
  800. /*
  801. * 8bpp displays are always pseudo colour. 16bpp and above
  802. * are direct colour or true colour, depending on whether
  803. * the RAMDAC palettes are bypassed. (Direct colour has
  804. * palettes, true colour does not.)
  805. */
  806. if (var->bits_per_pixel == 8)
  807. cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
  808. else if (hw.ramdac & RAMDAC_BYPASS)
  809. cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
  810. else
  811. cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR;
  812. cyber2000fb_set_timing(cfb, &hw);
  813. cyber2000fb_update_start(cfb, var);
  814. return 0;
  815. }
  816. /*
  817. * Pan or Wrap the Display
  818. */
  819. static int
  820. cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  821. {
  822. struct cfb_info *cfb = (struct cfb_info *)info;
  823. if (cyber2000fb_update_start(cfb, var))
  824. return -EINVAL;
  825. cfb->fb.var.xoffset = var->xoffset;
  826. cfb->fb.var.yoffset = var->yoffset;
  827. if (var->vmode & FB_VMODE_YWRAP) {
  828. cfb->fb.var.vmode |= FB_VMODE_YWRAP;
  829. } else {
  830. cfb->fb.var.vmode &= ~FB_VMODE_YWRAP;
  831. }
  832. return 0;
  833. }
  834. /*
  835. * (Un)Blank the display.
  836. *
  837. * Blank the screen if blank_mode != 0, else unblank. If
  838. * blank == NULL then the caller blanks by setting the CLUT
  839. * (Color Look Up Table) to all black. Return 0 if blanking
  840. * succeeded, != 0 if un-/blanking failed due to e.g. a
  841. * video mode which doesn't support it. Implements VESA
  842. * suspend and powerdown modes on hardware that supports
  843. * disabling hsync/vsync:
  844. * blank_mode == 2: suspend vsync
  845. * blank_mode == 3: suspend hsync
  846. * blank_mode == 4: powerdown
  847. *
  848. * wms...Enable VESA DMPS compatible powerdown mode
  849. * run "setterm -powersave powerdown" to take advantage
  850. */
  851. static int cyber2000fb_blank(int blank, struct fb_info *info)
  852. {
  853. struct cfb_info *cfb = (struct cfb_info *)info;
  854. unsigned int sync = 0;
  855. int i;
  856. switch (blank) {
  857. case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
  858. sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0;
  859. break;
  860. case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
  861. sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0;
  862. break;
  863. case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
  864. sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL;
  865. break;
  866. case FB_BLANK_NORMAL: /* soft blank */
  867. default: /* unblank */
  868. break;
  869. }
  870. cyber2000_grphw(EXT_SYNC_CTL, sync, cfb);
  871. if (blank <= 1) {
  872. /* turn on ramdacs */
  873. cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
  874. cyber2000fb_write_ramdac_ctrl(cfb);
  875. }
  876. /*
  877. * Soft blank/unblank the display.
  878. */
  879. if (blank) { /* soft blank */
  880. for (i = 0; i < NR_PALETTE; i++) {
  881. cyber2000fb_writeb(i, 0x3c8, cfb);
  882. cyber2000fb_writeb(0, 0x3c9, cfb);
  883. cyber2000fb_writeb(0, 0x3c9, cfb);
  884. cyber2000fb_writeb(0, 0x3c9, cfb);
  885. }
  886. } else { /* unblank */
  887. for (i = 0; i < NR_PALETTE; i++) {
  888. cyber2000fb_writeb(i, 0x3c8, cfb);
  889. cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb);
  890. cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb);
  891. cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb);
  892. }
  893. }
  894. if (blank >= 2) {
  895. /* turn off ramdacs */
  896. cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN;
  897. cyber2000fb_write_ramdac_ctrl(cfb);
  898. }
  899. return 0;
  900. }
  901. static struct fb_ops cyber2000fb_ops = {
  902. .owner = THIS_MODULE,
  903. .fb_check_var = cyber2000fb_check_var,
  904. .fb_set_par = cyber2000fb_set_par,
  905. .fb_setcolreg = cyber2000fb_setcolreg,
  906. .fb_blank = cyber2000fb_blank,
  907. .fb_pan_display = cyber2000fb_pan_display,
  908. .fb_fillrect = cyber2000fb_fillrect,
  909. .fb_copyarea = cyber2000fb_copyarea,
  910. .fb_imageblit = cyber2000fb_imageblit,
  911. .fb_sync = cyber2000fb_sync,
  912. };
  913. /*
  914. * This is the only "static" reference to the internal data structures
  915. * of this driver. It is here solely at the moment to support the other
  916. * CyberPro modules external to this driver.
  917. */
  918. static struct cfb_info *int_cfb_info;
  919. /*
  920. * Enable access to the extended registers
  921. */
  922. void cyber2000fb_enable_extregs(struct cfb_info *cfb)
  923. {
  924. cfb->func_use_count += 1;
  925. if (cfb->func_use_count == 1) {
  926. int old;
  927. old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
  928. old |= EXT_FUNC_CTL_EXTREGENBL;
  929. cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
  930. }
  931. }
  932. /*
  933. * Disable access to the extended registers
  934. */
  935. void cyber2000fb_disable_extregs(struct cfb_info *cfb)
  936. {
  937. if (cfb->func_use_count == 1) {
  938. int old;
  939. old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
  940. old &= ~EXT_FUNC_CTL_EXTREGENBL;
  941. cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
  942. }
  943. if (cfb->func_use_count == 0)
  944. printk(KERN_ERR "disable_extregs: count = 0\n");
  945. else
  946. cfb->func_use_count -= 1;
  947. }
  948. void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var)
  949. {
  950. memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo));
  951. }
  952. /*
  953. * Attach a capture/tv driver to the core CyberX0X0 driver.
  954. */
  955. int cyber2000fb_attach(struct cyberpro_info *info, int idx)
  956. {
  957. if (int_cfb_info != NULL) {
  958. info->dev = int_cfb_info->dev;
  959. info->regs = int_cfb_info->regs;
  960. info->fb = int_cfb_info->fb.screen_base;
  961. info->fb_size = int_cfb_info->fb.fix.smem_len;
  962. info->enable_extregs = cyber2000fb_enable_extregs;
  963. info->disable_extregs = cyber2000fb_disable_extregs;
  964. info->info = int_cfb_info;
  965. strlcpy(info->dev_name, int_cfb_info->fb.fix.id, sizeof(info->dev_name));
  966. }
  967. return int_cfb_info != NULL;
  968. }
  969. /*
  970. * Detach a capture/tv driver from the core CyberX0X0 driver.
  971. */
  972. void cyber2000fb_detach(int idx)
  973. {
  974. }
  975. EXPORT_SYMBOL(cyber2000fb_attach);
  976. EXPORT_SYMBOL(cyber2000fb_detach);
  977. EXPORT_SYMBOL(cyber2000fb_enable_extregs);
  978. EXPORT_SYMBOL(cyber2000fb_disable_extregs);
  979. EXPORT_SYMBOL(cyber2000fb_get_fb_var);
  980. /*
  981. * These parameters give
  982. * 640x480, hsync 31.5kHz, vsync 60Hz
  983. */
  984. static struct fb_videomode __devinitdata cyber2000fb_default_mode = {
  985. .refresh = 60,
  986. .xres = 640,
  987. .yres = 480,
  988. .pixclock = 39722,
  989. .left_margin = 56,
  990. .right_margin = 16,
  991. .upper_margin = 34,
  992. .lower_margin = 9,
  993. .hsync_len = 88,
  994. .vsync_len = 2,
  995. .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  996. .vmode = FB_VMODE_NONINTERLACED
  997. };
  998. static char igs_regs[] = {
  999. EXT_CRT_IRQ, 0,
  1000. EXT_CRT_TEST, 0,
  1001. EXT_SYNC_CTL, 0,
  1002. EXT_SEG_WRITE_PTR, 0,
  1003. EXT_SEG_READ_PTR, 0,
  1004. EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE |
  1005. EXT_BIU_MISC_COP_ENABLE |
  1006. EXT_BIU_MISC_COP_BFC,
  1007. EXT_FUNC_CTL, 0,
  1008. CURS_H_START, 0,
  1009. CURS_H_START + 1, 0,
  1010. CURS_H_PRESET, 0,
  1011. CURS_V_START, 0,
  1012. CURS_V_START + 1, 0,
  1013. CURS_V_PRESET, 0,
  1014. CURS_CTL, 0,
  1015. EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT,
  1016. EXT_OVERSCAN_RED, 0,
  1017. EXT_OVERSCAN_GREEN, 0,
  1018. EXT_OVERSCAN_BLUE, 0,
  1019. /* some of these are questionable when we have a BIOS */
  1020. EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK |
  1021. EXT_MEM_CTL0_RAS_1 |
  1022. EXT_MEM_CTL0_MULTCAS,
  1023. EXT_HIDDEN_CTL1, 0x30,
  1024. EXT_FIFO_CTL, 0x0b,
  1025. EXT_FIFO_CTL + 1, 0x17,
  1026. 0x76, 0x00,
  1027. EXT_HIDDEN_CTL4, 0xc8
  1028. };
  1029. /*
  1030. * Initialise the CyberPro hardware. On the CyberPro5XXXX,
  1031. * ensure that we're using the correct PLL (5XXX's may be
  1032. * programmed to use an additional set of PLLs.)
  1033. */
  1034. static void cyberpro_init_hw(struct cfb_info *cfb)
  1035. {
  1036. int i;
  1037. for (i = 0; i < sizeof(igs_regs); i += 2)
  1038. cyber2000_grphw(igs_regs[i], igs_regs[i+1], cfb);
  1039. if (cfb->id == ID_CYBERPRO_5000) {
  1040. unsigned char val;
  1041. cyber2000fb_writeb(0xba, 0x3ce, cfb);
  1042. val = cyber2000fb_readb(0x3cf, cfb) & 0x80;
  1043. cyber2000fb_writeb(val, 0x3cf, cfb);
  1044. }
  1045. }
  1046. static struct cfb_info * __devinit
  1047. cyberpro_alloc_fb_info(unsigned int id, char *name)
  1048. {
  1049. struct cfb_info *cfb;
  1050. cfb = kmalloc(sizeof(struct cfb_info), GFP_KERNEL);
  1051. if (!cfb)
  1052. return NULL;
  1053. memset(cfb, 0, sizeof(struct cfb_info));
  1054. cfb->id = id;
  1055. if (id == ID_CYBERPRO_5000)
  1056. cfb->ref_ps = 40690; // 24.576 MHz
  1057. else
  1058. cfb->ref_ps = 69842; // 14.31818 MHz (69841?)
  1059. cfb->divisors[0] = 1;
  1060. cfb->divisors[1] = 2;
  1061. cfb->divisors[2] = 4;
  1062. if (id == ID_CYBERPRO_2000)
  1063. cfb->divisors[3] = 8;
  1064. else
  1065. cfb->divisors[3] = 6;
  1066. strcpy(cfb->fb.fix.id, name);
  1067. cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
  1068. cfb->fb.fix.type_aux = 0;
  1069. cfb->fb.fix.xpanstep = 0;
  1070. cfb->fb.fix.ypanstep = 1;
  1071. cfb->fb.fix.ywrapstep = 0;
  1072. switch (id) {
  1073. case ID_IGA_1682:
  1074. cfb->fb.fix.accel = 0;
  1075. break;
  1076. case ID_CYBERPRO_2000:
  1077. cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000;
  1078. break;
  1079. case ID_CYBERPRO_2010:
  1080. cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010;
  1081. break;
  1082. case ID_CYBERPRO_5000:
  1083. cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000;
  1084. break;
  1085. }
  1086. cfb->fb.var.nonstd = 0;
  1087. cfb->fb.var.activate = FB_ACTIVATE_NOW;
  1088. cfb->fb.var.height = -1;
  1089. cfb->fb.var.width = -1;
  1090. cfb->fb.var.accel_flags = FB_ACCELF_TEXT;
  1091. cfb->fb.fbops = &cyber2000fb_ops;
  1092. cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  1093. cfb->fb.pseudo_palette = cfb->pseudo_palette;
  1094. fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
  1095. return cfb;
  1096. }
  1097. static void
  1098. cyberpro_free_fb_info(struct cfb_info *cfb)
  1099. {
  1100. if (cfb) {
  1101. /*
  1102. * Free the colourmap
  1103. */
  1104. fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
  1105. kfree(cfb);
  1106. }
  1107. }
  1108. /*
  1109. * Parse Cyber2000fb options. Usage:
  1110. * video=cyber2000:font:fontname
  1111. */
  1112. #ifndef MODULE
  1113. static int
  1114. cyber2000fb_setup(char *options)
  1115. {
  1116. char *opt;
  1117. if (!options || !*options)
  1118. return 0;
  1119. while ((opt = strsep(&options, ",")) != NULL) {
  1120. if (!*opt)
  1121. continue;
  1122. if (strncmp(opt, "font:", 5) == 0) {
  1123. static char default_font_storage[40];
  1124. strlcpy(default_font_storage, opt + 5, sizeof(default_font_storage));
  1125. default_font = default_font_storage;
  1126. continue;
  1127. }
  1128. printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt);
  1129. }
  1130. return 0;
  1131. }
  1132. #endif /* MODULE */
  1133. /*
  1134. * The CyberPro chips can be placed on many different bus types.
  1135. * This probe function is common to all bus types. The bus-specific
  1136. * probe function is expected to have:
  1137. * - enabled access to the linear memory region
  1138. * - memory mapped access to the registers
  1139. * - initialised mem_ctl1 and mem_ctl2 appropriately.
  1140. */
  1141. static int __devinit cyberpro_common_probe(struct cfb_info *cfb)
  1142. {
  1143. u_long smem_size;
  1144. u_int h_sync, v_sync;
  1145. int err;
  1146. cyberpro_init_hw(cfb);
  1147. /*
  1148. * Get the video RAM size and width from the VGA register.
  1149. * This should have been already initialised by the BIOS,
  1150. * but if it's garbage, claim default 1MB VRAM (woody)
  1151. */
  1152. cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb);
  1153. cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb);
  1154. /*
  1155. * Determine the size of the memory.
  1156. */
  1157. switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) {
  1158. case MEM_CTL2_SIZE_4MB: smem_size = 0x00400000; break;
  1159. case MEM_CTL2_SIZE_2MB: smem_size = 0x00200000; break;
  1160. case MEM_CTL2_SIZE_1MB: smem_size = 0x00100000; break;
  1161. default: smem_size = 0x00100000; break;
  1162. }
  1163. cfb->fb.fix.smem_len = smem_size;
  1164. cfb->fb.fix.mmio_len = MMIO_SIZE;
  1165. cfb->fb.screen_base = cfb->region;
  1166. err = -EINVAL;
  1167. if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
  1168. &cyber2000fb_default_mode, 8)) {
  1169. printk("%s: no valid mode found\n", cfb->fb.fix.id);
  1170. goto failed;
  1171. }
  1172. cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 /
  1173. (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual);
  1174. if (cfb->fb.var.yres_virtual < cfb->fb.var.yres)
  1175. cfb->fb.var.yres_virtual = cfb->fb.var.yres;
  1176. // fb_set_var(&cfb->fb.var, -1, &cfb->fb);
  1177. /*
  1178. * Calculate the hsync and vsync frequencies. Note that
  1179. * we split the 1e12 constant up so that we can preserve
  1180. * the precision and fit the results into 32-bit registers.
  1181. * (1953125000 * 512 = 1e12)
  1182. */
  1183. h_sync = 1953125000 / cfb->fb.var.pixclock;
  1184. h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin +
  1185. cfb->fb.var.right_margin + cfb->fb.var.hsync_len);
  1186. v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin +
  1187. cfb->fb.var.lower_margin + cfb->fb.var.vsync_len);
  1188. printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
  1189. cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10,
  1190. cfb->fb.var.xres, cfb->fb.var.yres,
  1191. h_sync / 1000, h_sync % 1000, v_sync);
  1192. if (cfb->dev)
  1193. cfb->fb.device = &cfb->dev->dev;
  1194. err = register_framebuffer(&cfb->fb);
  1195. failed:
  1196. return err;
  1197. }
  1198. static void cyberpro_common_resume(struct cfb_info *cfb)
  1199. {
  1200. cyberpro_init_hw(cfb);
  1201. /*
  1202. * Reprogram the MEM_CTL1 and MEM_CTL2 registers
  1203. */
  1204. cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb);
  1205. cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb);
  1206. /*
  1207. * Restore the old video mode and the palette.
  1208. * We also need to tell fbcon to redraw the console.
  1209. */
  1210. cyber2000fb_set_par(&cfb->fb);
  1211. }
  1212. #ifdef CONFIG_ARCH_SHARK
  1213. #include <asm/arch/hardware.h>
  1214. static int __devinit
  1215. cyberpro_vl_probe(void)
  1216. {
  1217. struct cfb_info *cfb;
  1218. int err = -ENOMEM;
  1219. if (!request_mem_region(FB_START,FB_SIZE,"CyberPro2010")) return err;
  1220. cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010");
  1221. if (!cfb)
  1222. goto failed_release;
  1223. cfb->dev = NULL;
  1224. cfb->region = ioremap(FB_START,FB_SIZE);
  1225. if (!cfb->region)
  1226. goto failed_ioremap;
  1227. cfb->regs = cfb->region + MMIO_OFFSET;
  1228. cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET;
  1229. cfb->fb.fix.smem_start = FB_START;
  1230. /*
  1231. * Bring up the hardware. This is expected to enable access
  1232. * to the linear memory region, and allow access to the memory
  1233. * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
  1234. * initialised.
  1235. */
  1236. cyber2000fb_writeb(0x18, 0x46e8, cfb);
  1237. cyber2000fb_writeb(0x01, 0x102, cfb);
  1238. cyber2000fb_writeb(0x08, 0x46e8, cfb);
  1239. cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb);
  1240. cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb);
  1241. cfb->mclk_mult = 0xdb;
  1242. cfb->mclk_div = 0x54;
  1243. err = cyberpro_common_probe(cfb);
  1244. if (err)
  1245. goto failed;
  1246. if (int_cfb_info == NULL)
  1247. int_cfb_info = cfb;
  1248. return 0;
  1249. failed:
  1250. iounmap(cfb->region);
  1251. failed_ioremap:
  1252. cyberpro_free_fb_info(cfb);
  1253. failed_release:
  1254. release_mem_region(FB_START,FB_SIZE);
  1255. return err;
  1256. }
  1257. #endif /* CONFIG_ARCH_SHARK */
  1258. /*
  1259. * PCI specific support.
  1260. */
  1261. #ifdef CONFIG_PCI
  1262. /*
  1263. * We need to wake up the CyberPro, and make sure its in linear memory
  1264. * mode. Unfortunately, this is specific to the platform and card that
  1265. * we are running on.
  1266. *
  1267. * On x86 and ARM, should we be initialising the CyberPro first via the
  1268. * IO registers, and then the MMIO registers to catch all cases? Can we
  1269. * end up in the situation where the chip is in MMIO mode, but not awake
  1270. * on an x86 system?
  1271. */
  1272. static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
  1273. {
  1274. unsigned char val;
  1275. #if defined(__sparc_v9__)
  1276. #error "You lose, consult DaveM."
  1277. #elif defined(__sparc__)
  1278. /*
  1279. * SPARC does not have an "outb" instruction, so we generate
  1280. * I/O cycles storing into a reserved memory space at
  1281. * physical address 0x3000000
  1282. */
  1283. unsigned char __iomem *iop;
  1284. iop = ioremap(0x3000000, 0x5000);
  1285. if (iop == NULL) {
  1286. prom_printf("iga5000: cannot map I/O\n");
  1287. return -ENOMEM;
  1288. }
  1289. writeb(0x18, iop + 0x46e8);
  1290. writeb(0x01, iop + 0x102);
  1291. writeb(0x08, iop + 0x46e8);
  1292. writeb(EXT_BIU_MISC, iop + 0x3ce);
  1293. writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
  1294. iounmap(iop);
  1295. #else
  1296. /*
  1297. * Most other machine types are "normal", so
  1298. * we use the standard IO-based wakeup.
  1299. */
  1300. outb(0x18, 0x46e8);
  1301. outb(0x01, 0x102);
  1302. outb(0x08, 0x46e8);
  1303. outb(EXT_BIU_MISC, 0x3ce);
  1304. outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf);
  1305. #endif
  1306. /*
  1307. * Allow the CyberPro to accept PCI burst accesses
  1308. */
  1309. if (cfb->id == ID_CYBERPRO_2010) {
  1310. printk(KERN_INFO "%s: NOT enabling PCI bursts\n", cfb->fb.fix.id);
  1311. } else {
  1312. val = cyber2000_grphr(EXT_BUS_CTL, cfb);
  1313. if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) {
  1314. printk(KERN_INFO "%s: enabling PCI bursts\n",
  1315. cfb->fb.fix.id);
  1316. val |= EXT_BUS_CTL_PCIBURST_WRITE;
  1317. if (cfb->id == ID_CYBERPRO_5000)
  1318. val |= EXT_BUS_CTL_PCIBURST_READ;
  1319. cyber2000_grphw(EXT_BUS_CTL, val, cfb);
  1320. }
  1321. }
  1322. return 0;
  1323. }
  1324. static int __devinit
  1325. cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  1326. {
  1327. struct cfb_info *cfb;
  1328. char name[16];
  1329. int err;
  1330. sprintf(name, "CyberPro%4X", id->device);
  1331. err = pci_enable_device(dev);
  1332. if (err)
  1333. return err;
  1334. err = pci_request_regions(dev, name);
  1335. if (err)
  1336. return err;
  1337. err = -ENOMEM;
  1338. cfb = cyberpro_alloc_fb_info(id->driver_data, name);
  1339. if (!cfb)
  1340. goto failed_release;
  1341. cfb->dev = dev;
  1342. cfb->region = ioremap(pci_resource_start(dev, 0),
  1343. pci_resource_len(dev, 0));
  1344. if (!cfb->region)
  1345. goto failed_ioremap;
  1346. cfb->regs = cfb->region + MMIO_OFFSET;
  1347. cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
  1348. cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
  1349. /*
  1350. * Bring up the hardware. This is expected to enable access
  1351. * to the linear memory region, and allow access to the memory
  1352. * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
  1353. * initialised.
  1354. */
  1355. err = cyberpro_pci_enable_mmio(cfb);
  1356. if (err)
  1357. goto failed;
  1358. /*
  1359. * Use MCLK from BIOS. FIXME: what about hotplug?
  1360. */
  1361. cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
  1362. cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb);
  1363. #ifdef __arm__
  1364. /*
  1365. * MCLK on the NetWinder and the Shark is fixed at 75MHz
  1366. */
  1367. if (machine_is_netwinder()) {
  1368. cfb->mclk_mult = 0xdb;
  1369. cfb->mclk_div = 0x54;
  1370. }
  1371. #endif
  1372. err = cyberpro_common_probe(cfb);
  1373. if (err)
  1374. goto failed;
  1375. /*
  1376. * Our driver data
  1377. */
  1378. pci_set_drvdata(dev, cfb);
  1379. if (int_cfb_info == NULL)
  1380. int_cfb_info = cfb;
  1381. return 0;
  1382. failed:
  1383. iounmap(cfb->region);
  1384. failed_ioremap:
  1385. cyberpro_free_fb_info(cfb);
  1386. failed_release:
  1387. pci_release_regions(dev);
  1388. return err;
  1389. }
  1390. static void __devexit cyberpro_pci_remove(struct pci_dev *dev)
  1391. {
  1392. struct cfb_info *cfb = pci_get_drvdata(dev);
  1393. if (cfb) {
  1394. /*
  1395. * If unregister_framebuffer fails, then
  1396. * we will be leaving hooks that could cause
  1397. * oopsen laying around.
  1398. */
  1399. if (unregister_framebuffer(&cfb->fb))
  1400. printk(KERN_WARNING "%s: danger Will Robinson, "
  1401. "danger danger! Oopsen imminent!\n",
  1402. cfb->fb.fix.id);
  1403. iounmap(cfb->region);
  1404. cyberpro_free_fb_info(cfb);
  1405. /*
  1406. * Ensure that the driver data is no longer
  1407. * valid.
  1408. */
  1409. pci_set_drvdata(dev, NULL);
  1410. if (cfb == int_cfb_info)
  1411. int_cfb_info = NULL;
  1412. pci_release_regions(dev);
  1413. }
  1414. }
  1415. static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state)
  1416. {
  1417. return 0;
  1418. }
  1419. /*
  1420. * Re-initialise the CyberPro hardware
  1421. */
  1422. static int cyberpro_pci_resume(struct pci_dev *dev)
  1423. {
  1424. struct cfb_info *cfb = pci_get_drvdata(dev);
  1425. if (cfb) {
  1426. cyberpro_pci_enable_mmio(cfb);
  1427. cyberpro_common_resume(cfb);
  1428. }
  1429. return 0;
  1430. }
  1431. static struct pci_device_id cyberpro_pci_table[] = {
  1432. // Not yet
  1433. // { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
  1434. // PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
  1435. { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000,
  1436. PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 },
  1437. { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010,
  1438. PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 },
  1439. { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000,
  1440. PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 },
  1441. { 0, }
  1442. };
  1443. MODULE_DEVICE_TABLE(pci,cyberpro_pci_table);
  1444. static struct pci_driver cyberpro_driver = {
  1445. .name = "CyberPro",
  1446. .probe = cyberpro_pci_probe,
  1447. .remove = __devexit_p(cyberpro_pci_remove),
  1448. .suspend = cyberpro_pci_suspend,
  1449. .resume = cyberpro_pci_resume,
  1450. .id_table = cyberpro_pci_table
  1451. };
  1452. #endif
  1453. /*
  1454. * I don't think we can use the "module_init" stuff here because
  1455. * the fbcon stuff may not be initialised yet. Hence the #ifdef
  1456. * around module_init.
  1457. *
  1458. * Tony: "module_init" is now required
  1459. */
  1460. static int __init cyber2000fb_init(void)
  1461. {
  1462. int ret = -1, err;
  1463. #ifndef MODULE
  1464. char *option = NULL;
  1465. if (fb_get_options("cyber2000fb", &option))
  1466. return -ENODEV;
  1467. cyber2000fb_setup(option);
  1468. #endif
  1469. #ifdef CONFIG_ARCH_SHARK
  1470. err = cyberpro_vl_probe();
  1471. if (!err) {
  1472. ret = 0;
  1473. __module_get(THIS_MODULE);
  1474. }
  1475. #endif
  1476. #ifdef CONFIG_PCI
  1477. err = pci_register_driver(&cyberpro_driver);
  1478. if (!err)
  1479. ret = 0;
  1480. #endif
  1481. return ret ? err : 0;
  1482. }
  1483. static void __exit cyberpro_exit(void)
  1484. {
  1485. pci_unregister_driver(&cyberpro_driver);
  1486. }
  1487. module_init(cyber2000fb_init);
  1488. module_exit(cyberpro_exit);
  1489. MODULE_AUTHOR("Russell King");
  1490. MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
  1491. MODULE_LICENSE("GPL");