chipsfb.c 12 KB

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  1. /*
  2. * drivers/video/chipsfb.c -- frame buffer device for
  3. * Chips & Technologies 65550 chip.
  4. *
  5. * Copyright (C) 1998-2002 Paul Mackerras
  6. *
  7. * This file is derived from the Powermac "chips" driver:
  8. * Copyright (C) 1997 Fabio Riccardi.
  9. * And from the frame buffer device for Open Firmware-initialized devices:
  10. * Copyright (C) 1997 Geert Uytterhoeven.
  11. *
  12. * This file is subject to the terms and conditions of the GNU General Public
  13. * License. See the file COPYING in the main directory of this archive for
  14. * more details.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/string.h>
  20. #include <linux/mm.h>
  21. #include <linux/slab.h>
  22. #include <linux/vmalloc.h>
  23. #include <linux/delay.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/fb.h>
  26. #include <linux/init.h>
  27. #include <linux/pci.h>
  28. #include <linux/console.h>
  29. #include <asm/io.h>
  30. #ifdef CONFIG_PMAC_BACKLIGHT
  31. #include <asm/backlight.h>
  32. #endif
  33. /*
  34. * Since we access the display with inb/outb to fixed port numbers,
  35. * we can only handle one 6555x chip. -- paulus
  36. */
  37. #define write_ind(num, val, ap, dp) do { \
  38. outb((num), (ap)); outb((val), (dp)); \
  39. } while (0)
  40. #define read_ind(num, var, ap, dp) do { \
  41. outb((num), (ap)); var = inb((dp)); \
  42. } while (0)
  43. /* extension registers */
  44. #define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7)
  45. #define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7)
  46. /* flat panel registers */
  47. #define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1)
  48. #define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1)
  49. /* CRTC registers */
  50. #define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5)
  51. #define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5)
  52. /* graphics registers */
  53. #define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf)
  54. #define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf)
  55. /* sequencer registers */
  56. #define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5)
  57. #define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5)
  58. /* attribute registers - slightly strange */
  59. #define write_ar(num, val) do { \
  60. inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
  61. } while (0)
  62. #define read_ar(num, var) do { \
  63. inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
  64. } while (0)
  65. /*
  66. * Exported functions
  67. */
  68. int chips_init(void);
  69. static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
  70. static int chipsfb_check_var(struct fb_var_screeninfo *var,
  71. struct fb_info *info);
  72. static int chipsfb_set_par(struct fb_info *info);
  73. static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  74. u_int transp, struct fb_info *info);
  75. static int chipsfb_blank(int blank, struct fb_info *info);
  76. static struct fb_ops chipsfb_ops = {
  77. .owner = THIS_MODULE,
  78. .fb_check_var = chipsfb_check_var,
  79. .fb_set_par = chipsfb_set_par,
  80. .fb_setcolreg = chipsfb_setcolreg,
  81. .fb_blank = chipsfb_blank,
  82. .fb_fillrect = cfb_fillrect,
  83. .fb_copyarea = cfb_copyarea,
  84. .fb_imageblit = cfb_imageblit,
  85. };
  86. static int chipsfb_check_var(struct fb_var_screeninfo *var,
  87. struct fb_info *info)
  88. {
  89. if (var->xres > 800 || var->yres > 600
  90. || var->xres_virtual > 800 || var->yres_virtual > 600
  91. || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
  92. || var->nonstd
  93. || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
  94. return -EINVAL;
  95. var->xres = var->xres_virtual = 800;
  96. var->yres = var->yres_virtual = 600;
  97. return 0;
  98. }
  99. static int chipsfb_set_par(struct fb_info *info)
  100. {
  101. if (info->var.bits_per_pixel == 16) {
  102. write_cr(0x13, 200); // Set line length (doublewords)
  103. write_xr(0x81, 0x14); // 15 bit (555) color mode
  104. write_xr(0x82, 0x00); // Disable palettes
  105. write_xr(0x20, 0x10); // 16 bit blitter mode
  106. info->fix.line_length = 800*2;
  107. info->fix.visual = FB_VISUAL_TRUECOLOR;
  108. info->var.red.offset = 10;
  109. info->var.green.offset = 5;
  110. info->var.blue.offset = 0;
  111. info->var.red.length = info->var.green.length =
  112. info->var.blue.length = 5;
  113. } else {
  114. /* p->var.bits_per_pixel == 8 */
  115. write_cr(0x13, 100); // Set line length (doublewords)
  116. write_xr(0x81, 0x12); // 8 bit color mode
  117. write_xr(0x82, 0x08); // Graphics gamma enable
  118. write_xr(0x20, 0x00); // 8 bit blitter mode
  119. info->fix.line_length = 800;
  120. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  121. info->var.red.offset = info->var.green.offset =
  122. info->var.blue.offset = 0;
  123. info->var.red.length = info->var.green.length =
  124. info->var.blue.length = 8;
  125. }
  126. return 0;
  127. }
  128. static int chipsfb_blank(int blank, struct fb_info *info)
  129. {
  130. return 1; /* get fb_blank to set the colormap to all black */
  131. }
  132. static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  133. u_int transp, struct fb_info *info)
  134. {
  135. if (regno > 255)
  136. return 1;
  137. red >>= 8;
  138. green >>= 8;
  139. blue >>= 8;
  140. outb(regno, 0x3c8);
  141. udelay(1);
  142. outb(red, 0x3c9);
  143. outb(green, 0x3c9);
  144. outb(blue, 0x3c9);
  145. return 0;
  146. }
  147. struct chips_init_reg {
  148. unsigned char addr;
  149. unsigned char data;
  150. };
  151. static struct chips_init_reg chips_init_sr[] = {
  152. { 0x00, 0x03 },
  153. { 0x01, 0x01 },
  154. { 0x02, 0x0f },
  155. { 0x04, 0x0e }
  156. };
  157. static struct chips_init_reg chips_init_gr[] = {
  158. { 0x05, 0x00 },
  159. { 0x06, 0x0d },
  160. { 0x08, 0xff }
  161. };
  162. static struct chips_init_reg chips_init_ar[] = {
  163. { 0x10, 0x01 },
  164. { 0x12, 0x0f },
  165. { 0x13, 0x00 }
  166. };
  167. static struct chips_init_reg chips_init_cr[] = {
  168. { 0x00, 0x7f },
  169. { 0x01, 0x63 },
  170. { 0x02, 0x63 },
  171. { 0x03, 0x83 },
  172. { 0x04, 0x66 },
  173. { 0x05, 0x10 },
  174. { 0x06, 0x72 },
  175. { 0x07, 0x3e },
  176. { 0x08, 0x00 },
  177. { 0x09, 0x40 },
  178. { 0x0c, 0x00 },
  179. { 0x0d, 0x00 },
  180. { 0x10, 0x59 },
  181. { 0x11, 0x0d },
  182. { 0x12, 0x57 },
  183. { 0x13, 0x64 },
  184. { 0x14, 0x00 },
  185. { 0x15, 0x57 },
  186. { 0x16, 0x73 },
  187. { 0x17, 0xe3 },
  188. { 0x18, 0xff },
  189. { 0x30, 0x02 },
  190. { 0x31, 0x02 },
  191. { 0x32, 0x02 },
  192. { 0x33, 0x02 },
  193. { 0x40, 0x00 },
  194. { 0x41, 0x00 },
  195. { 0x40, 0x80 }
  196. };
  197. static struct chips_init_reg chips_init_fr[] = {
  198. { 0x01, 0x02 },
  199. { 0x03, 0x08 },
  200. { 0x04, 0x81 },
  201. { 0x05, 0x21 },
  202. { 0x08, 0x0c },
  203. { 0x0a, 0x74 },
  204. { 0x0b, 0x11 },
  205. { 0x10, 0x0c },
  206. { 0x11, 0xe0 },
  207. /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
  208. { 0x20, 0x63 },
  209. { 0x21, 0x68 },
  210. { 0x22, 0x19 },
  211. { 0x23, 0x7f },
  212. { 0x24, 0x68 },
  213. { 0x26, 0x00 },
  214. { 0x27, 0x0f },
  215. { 0x30, 0x57 },
  216. { 0x31, 0x58 },
  217. { 0x32, 0x0d },
  218. { 0x33, 0x72 },
  219. { 0x34, 0x02 },
  220. { 0x35, 0x22 },
  221. { 0x36, 0x02 },
  222. { 0x37, 0x00 }
  223. };
  224. static struct chips_init_reg chips_init_xr[] = {
  225. { 0xce, 0x00 }, /* set default memory clock */
  226. { 0xcc, 0x43 }, /* memory clock ratio */
  227. { 0xcd, 0x18 },
  228. { 0xce, 0xa1 },
  229. { 0xc8, 0x84 },
  230. { 0xc9, 0x0a },
  231. { 0xca, 0x00 },
  232. { 0xcb, 0x20 },
  233. { 0xcf, 0x06 },
  234. { 0xd0, 0x0e },
  235. { 0x09, 0x01 },
  236. { 0x0a, 0x02 },
  237. { 0x0b, 0x01 },
  238. { 0x20, 0x00 },
  239. { 0x40, 0x03 },
  240. { 0x41, 0x01 },
  241. { 0x42, 0x00 },
  242. { 0x80, 0x82 },
  243. { 0x81, 0x12 },
  244. { 0x82, 0x08 },
  245. { 0xa0, 0x00 },
  246. { 0xa8, 0x00 }
  247. };
  248. static void __init chips_hw_init(void)
  249. {
  250. int i;
  251. for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
  252. write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
  253. outb(0x29, 0x3c2); /* set misc output reg */
  254. for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
  255. write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
  256. for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
  257. write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
  258. for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
  259. write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
  260. for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
  261. write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
  262. for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
  263. write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
  264. }
  265. static struct fb_fix_screeninfo chipsfb_fix __initdata = {
  266. .id = "C&T 65550",
  267. .type = FB_TYPE_PACKED_PIXELS,
  268. .visual = FB_VISUAL_PSEUDOCOLOR,
  269. .accel = FB_ACCEL_NONE,
  270. .line_length = 800,
  271. // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
  272. // * "3500" PowerBook G3 (the original PB G3) has 2MB.
  273. // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
  274. // Motherboard actually supports 2MB -- there are two blank locations
  275. // for a second pair of DRAMs. (Thanks, Apple!)
  276. // * 3400 has 1MB (I think). Don't know if it's expandable.
  277. // -- Tim Seufert
  278. .smem_len = 0x100000, /* 1MB */
  279. };
  280. static struct fb_var_screeninfo chipsfb_var __initdata = {
  281. .xres = 800,
  282. .yres = 600,
  283. .xres_virtual = 800,
  284. .yres_virtual = 600,
  285. .bits_per_pixel = 8,
  286. .red = { .length = 8 },
  287. .green = { .length = 8 },
  288. .blue = { .length = 8 },
  289. .height = -1,
  290. .width = -1,
  291. .vmode = FB_VMODE_NONINTERLACED,
  292. .pixclock = 10000,
  293. .left_margin = 16,
  294. .right_margin = 16,
  295. .upper_margin = 16,
  296. .lower_margin = 16,
  297. .hsync_len = 8,
  298. .vsync_len = 8,
  299. };
  300. static void __init init_chips(struct fb_info *p, unsigned long addr)
  301. {
  302. memset(p->screen_base, 0, 0x100000);
  303. p->fix = chipsfb_fix;
  304. p->fix.smem_start = addr;
  305. p->var = chipsfb_var;
  306. p->fbops = &chipsfb_ops;
  307. p->flags = FBINFO_DEFAULT;
  308. fb_alloc_cmap(&p->cmap, 256, 0);
  309. chips_hw_init();
  310. }
  311. static int __devinit
  312. chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
  313. {
  314. struct fb_info *p;
  315. unsigned long addr, size;
  316. unsigned short cmd;
  317. int rc = -ENODEV;
  318. if (pci_enable_device(dp) < 0) {
  319. dev_err(&dp->dev, "Cannot enable PCI device\n");
  320. goto err_out;
  321. }
  322. if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
  323. goto err_disable;
  324. addr = pci_resource_start(dp, 0);
  325. size = pci_resource_len(dp, 0);
  326. if (addr == 0)
  327. goto err_disable;
  328. p = framebuffer_alloc(0, &dp->dev);
  329. if (p == NULL) {
  330. dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
  331. rc = -ENOMEM;
  332. goto err_disable;
  333. }
  334. if (pci_request_region(dp, 0, "chipsfb") != 0) {
  335. dev_err(&dp->dev, "Cannot request framebuffer\n");
  336. rc = -EBUSY;
  337. goto err_release_fb;
  338. }
  339. #ifdef __BIG_ENDIAN
  340. addr += 0x800000; // Use big-endian aperture
  341. #endif
  342. /* we should use pci_enable_device here, but,
  343. the device doesn't declare its I/O ports in its BARs
  344. so pci_enable_device won't turn on I/O responses */
  345. pci_read_config_word(dp, PCI_COMMAND, &cmd);
  346. cmd |= 3; /* enable memory and IO space */
  347. pci_write_config_word(dp, PCI_COMMAND, cmd);
  348. #ifdef CONFIG_PMAC_BACKLIGHT
  349. /* turn on the backlight */
  350. mutex_lock(&pmac_backlight_mutex);
  351. if (pmac_backlight) {
  352. pmac_backlight->props.power = FB_BLANK_UNBLANK;
  353. backlight_update_status(pmac_backlight);
  354. }
  355. mutex_unlock(&pmac_backlight_mutex);
  356. #endif /* CONFIG_PMAC_BACKLIGHT */
  357. #ifdef CONFIG_PPC
  358. p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
  359. #else
  360. p->screen_base = ioremap(addr, 0x200000);
  361. #endif
  362. if (p->screen_base == NULL) {
  363. dev_err(&dp->dev, "Cannot map framebuffer\n");
  364. rc = -ENOMEM;
  365. goto err_release_pci;
  366. }
  367. pci_set_drvdata(dp, p);
  368. p->device = &dp->dev;
  369. init_chips(p, addr);
  370. if (register_framebuffer(p) < 0) {
  371. dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
  372. goto err_unmap;
  373. }
  374. dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
  375. " (%dK RAM detected)\n",
  376. p->node, p->fix.smem_len / 1024);
  377. return 0;
  378. err_unmap:
  379. iounmap(p->screen_base);
  380. err_release_pci:
  381. pci_release_region(dp, 0);
  382. err_release_fb:
  383. framebuffer_release(p);
  384. err_disable:
  385. err_out:
  386. return rc;
  387. }
  388. static void __devexit chipsfb_remove(struct pci_dev *dp)
  389. {
  390. struct fb_info *p = pci_get_drvdata(dp);
  391. if (p->screen_base == NULL)
  392. return;
  393. unregister_framebuffer(p);
  394. iounmap(p->screen_base);
  395. p->screen_base = NULL;
  396. pci_release_region(dp, 0);
  397. }
  398. #ifdef CONFIG_PM
  399. static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  400. {
  401. struct fb_info *p = pci_get_drvdata(pdev);
  402. if (state.event == pdev->dev.power.power_state.event)
  403. return 0;
  404. if (state.event != PM_SUSPEND_MEM)
  405. goto done;
  406. acquire_console_sem();
  407. chipsfb_blank(1, p);
  408. fb_set_suspend(p, 1);
  409. release_console_sem();
  410. done:
  411. pdev->dev.power.power_state = state;
  412. return 0;
  413. }
  414. static int chipsfb_pci_resume(struct pci_dev *pdev)
  415. {
  416. struct fb_info *p = pci_get_drvdata(pdev);
  417. acquire_console_sem();
  418. fb_set_suspend(p, 0);
  419. chipsfb_blank(0, p);
  420. release_console_sem();
  421. pdev->dev.power.power_state = PMSG_ON;
  422. return 0;
  423. }
  424. #endif /* CONFIG_PM */
  425. static struct pci_device_id chipsfb_pci_tbl[] = {
  426. { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
  427. { 0 }
  428. };
  429. MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
  430. static struct pci_driver chipsfb_driver = {
  431. .name = "chipsfb",
  432. .id_table = chipsfb_pci_tbl,
  433. .probe = chipsfb_pci_init,
  434. .remove = __devexit_p(chipsfb_remove),
  435. #ifdef CONFIG_PM
  436. .suspend = chipsfb_pci_suspend,
  437. .resume = chipsfb_pci_resume,
  438. #endif
  439. };
  440. int __init chips_init(void)
  441. {
  442. if (fb_get_options("chipsfb", NULL))
  443. return -ENODEV;
  444. return pci_register_driver(&chipsfb_driver);
  445. }
  446. module_init(chips_init);
  447. static void __exit chipsfb_exit(void)
  448. {
  449. pci_unregister_driver(&chipsfb_driver);
  450. }
  451. MODULE_LICENSE("GPL");