cg3.c 12 KB

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  1. /* cg3.c: CGTHREE frame buffer driver
  2. *
  3. * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
  4. * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
  5. * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
  6. * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
  7. *
  8. * Driver layout based loosely on tgafb.c, see that file for credits.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/errno.h>
  13. #include <linux/string.h>
  14. #include <linux/slab.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <linux/fb.h>
  18. #include <linux/mm.h>
  19. #include <asm/io.h>
  20. #include <asm/oplib.h>
  21. #include <asm/prom.h>
  22. #include <asm/of_device.h>
  23. #include <asm/fbio.h>
  24. #include "sbuslib.h"
  25. /*
  26. * Local functions.
  27. */
  28. static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
  29. unsigned, struct fb_info *);
  30. static int cg3_blank(int, struct fb_info *);
  31. static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
  32. static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
  33. /*
  34. * Frame buffer operations
  35. */
  36. static struct fb_ops cg3_ops = {
  37. .owner = THIS_MODULE,
  38. .fb_setcolreg = cg3_setcolreg,
  39. .fb_blank = cg3_blank,
  40. .fb_fillrect = cfb_fillrect,
  41. .fb_copyarea = cfb_copyarea,
  42. .fb_imageblit = cfb_imageblit,
  43. .fb_mmap = cg3_mmap,
  44. .fb_ioctl = cg3_ioctl,
  45. #ifdef CONFIG_COMPAT
  46. .fb_compat_ioctl = sbusfb_compat_ioctl,
  47. #endif
  48. };
  49. /* Control Register Constants */
  50. #define CG3_CR_ENABLE_INTS 0x80
  51. #define CG3_CR_ENABLE_VIDEO 0x40
  52. #define CG3_CR_ENABLE_TIMING 0x20
  53. #define CG3_CR_ENABLE_CURCMP 0x10
  54. #define CG3_CR_XTAL_MASK 0x0c
  55. #define CG3_CR_DIVISOR_MASK 0x03
  56. /* Status Register Constants */
  57. #define CG3_SR_PENDING_INT 0x80
  58. #define CG3_SR_RES_MASK 0x70
  59. #define CG3_SR_1152_900_76_A 0x40
  60. #define CG3_SR_1152_900_76_B 0x60
  61. #define CG3_SR_ID_MASK 0x0f
  62. #define CG3_SR_ID_COLOR 0x01
  63. #define CG3_SR_ID_MONO 0x02
  64. #define CG3_SR_ID_MONO_ECL 0x03
  65. enum cg3_type {
  66. CG3_AT_66HZ = 0,
  67. CG3_AT_76HZ,
  68. CG3_RDI
  69. };
  70. struct bt_regs {
  71. u32 addr;
  72. u32 color_map;
  73. u32 control;
  74. u32 cursor;
  75. };
  76. struct cg3_regs {
  77. struct bt_regs cmap;
  78. u8 control;
  79. u8 status;
  80. u8 cursor_start;
  81. u8 cursor_end;
  82. u8 h_blank_start;
  83. u8 h_blank_end;
  84. u8 h_sync_start;
  85. u8 h_sync_end;
  86. u8 comp_sync_end;
  87. u8 v_blank_start_high;
  88. u8 v_blank_start_low;
  89. u8 v_blank_end;
  90. u8 v_sync_start;
  91. u8 v_sync_end;
  92. u8 xfer_holdoff_start;
  93. u8 xfer_holdoff_end;
  94. };
  95. /* Offset of interesting structures in the OBIO space */
  96. #define CG3_REGS_OFFSET 0x400000UL
  97. #define CG3_RAM_OFFSET 0x800000UL
  98. struct cg3_par {
  99. spinlock_t lock;
  100. struct cg3_regs __iomem *regs;
  101. u32 sw_cmap[((256 * 3) + 3) / 4];
  102. u32 flags;
  103. #define CG3_FLAG_BLANKED 0x00000001
  104. #define CG3_FLAG_RDI 0x00000002
  105. unsigned long physbase;
  106. unsigned long which_io;
  107. unsigned long fbsize;
  108. };
  109. /**
  110. * cg3_setcolreg - Optional function. Sets a color register.
  111. * @regno: boolean, 0 copy local, 1 get_user() function
  112. * @red: frame buffer colormap structure
  113. * @green: The green value which can be up to 16 bits wide
  114. * @blue: The blue value which can be up to 16 bits wide.
  115. * @transp: If supported the alpha value which can be up to 16 bits wide.
  116. * @info: frame buffer info structure
  117. *
  118. * The cg3 palette is loaded with 4 color values at each time
  119. * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
  120. * We keep a sw copy of the hw cmap to assist us in this esoteric
  121. * loading procedure.
  122. */
  123. static int cg3_setcolreg(unsigned regno,
  124. unsigned red, unsigned green, unsigned blue,
  125. unsigned transp, struct fb_info *info)
  126. {
  127. struct cg3_par *par = (struct cg3_par *) info->par;
  128. struct bt_regs __iomem *bt = &par->regs->cmap;
  129. unsigned long flags;
  130. u32 *p32;
  131. u8 *p8;
  132. int count;
  133. if (regno >= 256)
  134. return 1;
  135. red >>= 8;
  136. green >>= 8;
  137. blue >>= 8;
  138. spin_lock_irqsave(&par->lock, flags);
  139. p8 = (u8 *)par->sw_cmap + (regno * 3);
  140. p8[0] = red;
  141. p8[1] = green;
  142. p8[2] = blue;
  143. #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)*3 */
  144. #define D4M4(x) ((x)&~0x3) /* (x/4)*4 */
  145. count = 3;
  146. p32 = &par->sw_cmap[D4M3(regno)];
  147. sbus_writel(D4M4(regno), &bt->addr);
  148. while (count--)
  149. sbus_writel(*p32++, &bt->color_map);
  150. #undef D4M3
  151. #undef D4M4
  152. spin_unlock_irqrestore(&par->lock, flags);
  153. return 0;
  154. }
  155. /**
  156. * cg3_blank - Optional function. Blanks the display.
  157. * @blank_mode: the blank mode we want.
  158. * @info: frame buffer structure that represents a single frame buffer
  159. */
  160. static int cg3_blank(int blank, struct fb_info *info)
  161. {
  162. struct cg3_par *par = (struct cg3_par *) info->par;
  163. struct cg3_regs __iomem *regs = par->regs;
  164. unsigned long flags;
  165. u8 val;
  166. spin_lock_irqsave(&par->lock, flags);
  167. switch (blank) {
  168. case FB_BLANK_UNBLANK: /* Unblanking */
  169. val = sbus_readb(&regs->control);
  170. val |= CG3_CR_ENABLE_VIDEO;
  171. sbus_writeb(val, &regs->control);
  172. par->flags &= ~CG3_FLAG_BLANKED;
  173. break;
  174. case FB_BLANK_NORMAL: /* Normal blanking */
  175. case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
  176. case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
  177. case FB_BLANK_POWERDOWN: /* Poweroff */
  178. val = sbus_readb(&regs->control);
  179. val &= ~CG3_CR_ENABLE_VIDEO;
  180. sbus_writeb(val, &regs->control);
  181. par->flags |= CG3_FLAG_BLANKED;
  182. break;
  183. }
  184. spin_unlock_irqrestore(&par->lock, flags);
  185. return 0;
  186. }
  187. static struct sbus_mmap_map cg3_mmap_map[] = {
  188. {
  189. .voff = CG3_MMAP_OFFSET,
  190. .poff = CG3_RAM_OFFSET,
  191. .size = SBUS_MMAP_FBSIZE(1)
  192. },
  193. { .size = 0 }
  194. };
  195. static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
  196. {
  197. struct cg3_par *par = (struct cg3_par *)info->par;
  198. return sbusfb_mmap_helper(cg3_mmap_map,
  199. par->physbase, par->fbsize,
  200. par->which_io,
  201. vma);
  202. }
  203. static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  204. {
  205. struct cg3_par *par = (struct cg3_par *) info->par;
  206. return sbusfb_ioctl_helper(cmd, arg, info,
  207. FBTYPE_SUN3COLOR, 8, par->fbsize);
  208. }
  209. /*
  210. * Initialisation
  211. */
  212. static void __devinit cg3_init_fix(struct fb_info *info, int linebytes,
  213. struct device_node *dp)
  214. {
  215. strlcpy(info->fix.id, dp->name, sizeof(info->fix.id));
  216. info->fix.type = FB_TYPE_PACKED_PIXELS;
  217. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  218. info->fix.line_length = linebytes;
  219. info->fix.accel = FB_ACCEL_SUN_CGTHREE;
  220. }
  221. static void __devinit cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
  222. struct device_node *dp)
  223. {
  224. char *params;
  225. char *p;
  226. int ww, hh;
  227. params = of_get_property(dp, "params", NULL);
  228. if (params) {
  229. ww = simple_strtoul(params, &p, 10);
  230. if (ww && *p == 'x') {
  231. hh = simple_strtoul(p + 1, &p, 10);
  232. if (hh && *p == '-') {
  233. if (var->xres != ww ||
  234. var->yres != hh) {
  235. var->xres = var->xres_virtual = ww;
  236. var->yres = var->yres_virtual = hh;
  237. }
  238. }
  239. }
  240. }
  241. }
  242. static u8 cg3regvals_66hz[] __devinitdata = { /* 1152 x 900, 66 Hz */
  243. 0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
  244. 0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
  245. 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
  246. 0x10, 0x20, 0
  247. };
  248. static u8 cg3regvals_76hz[] __devinitdata = { /* 1152 x 900, 76 Hz */
  249. 0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
  250. 0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
  251. 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
  252. 0x10, 0x24, 0
  253. };
  254. static u8 cg3regvals_rdi[] __devinitdata = { /* 640 x 480, cgRDI */
  255. 0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
  256. 0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
  257. 0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
  258. 0x10, 0x22, 0
  259. };
  260. static u8 *cg3_regvals[] __devinitdata = {
  261. cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
  262. };
  263. static u_char cg3_dacvals[] __devinitdata = {
  264. 4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0
  265. };
  266. static void __devinit cg3_do_default_mode(struct cg3_par *par)
  267. {
  268. enum cg3_type type;
  269. u8 *p;
  270. if (par->flags & CG3_FLAG_RDI)
  271. type = CG3_RDI;
  272. else {
  273. u8 status = sbus_readb(&par->regs->status), mon;
  274. if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
  275. mon = status & CG3_SR_RES_MASK;
  276. if (mon == CG3_SR_1152_900_76_A ||
  277. mon == CG3_SR_1152_900_76_B)
  278. type = CG3_AT_76HZ;
  279. else
  280. type = CG3_AT_66HZ;
  281. } else {
  282. prom_printf("cgthree: can't handle SR %02x\n",
  283. status);
  284. prom_halt();
  285. return;
  286. }
  287. }
  288. for (p = cg3_regvals[type]; *p; p += 2) {
  289. u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
  290. sbus_writeb(p[1], regp);
  291. }
  292. for (p = cg3_dacvals; *p; p += 2) {
  293. u8 __iomem *regp;
  294. regp = (u8 __iomem *)&par->regs->cmap.addr;
  295. sbus_writeb(p[0], regp);
  296. regp = (u8 __iomem *)&par->regs->cmap.control;
  297. sbus_writeb(p[1], regp);
  298. }
  299. }
  300. struct all_info {
  301. struct fb_info info;
  302. struct cg3_par par;
  303. };
  304. static int __devinit cg3_init_one(struct of_device *op)
  305. {
  306. struct device_node *dp = op->node;
  307. struct all_info *all;
  308. int linebytes, err;
  309. all = kzalloc(sizeof(*all), GFP_KERNEL);
  310. if (!all)
  311. return -ENOMEM;
  312. spin_lock_init(&all->par.lock);
  313. all->par.physbase = op->resource[0].start;
  314. all->par.which_io = op->resource[0].flags & IORESOURCE_BITS;
  315. sbusfb_fill_var(&all->info.var, dp->node, 8);
  316. all->info.var.red.length = 8;
  317. all->info.var.green.length = 8;
  318. all->info.var.blue.length = 8;
  319. if (!strcmp(dp->name, "cgRDI"))
  320. all->par.flags |= CG3_FLAG_RDI;
  321. if (all->par.flags & CG3_FLAG_RDI)
  322. cg3_rdi_maybe_fixup_var(&all->info.var, dp);
  323. linebytes = of_getintprop_default(dp, "linebytes",
  324. all->info.var.xres);
  325. all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
  326. all->par.regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
  327. sizeof(struct cg3_regs), "cg3 regs");
  328. all->info.flags = FBINFO_DEFAULT;
  329. all->info.fbops = &cg3_ops;
  330. all->info.screen_base =
  331. of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
  332. all->par.fbsize, "cg3 ram");
  333. all->info.par = &all->par;
  334. cg3_blank(0, &all->info);
  335. if (!of_find_property(dp, "width", NULL))
  336. cg3_do_default_mode(&all->par);
  337. if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
  338. of_iounmap(&op->resource[0],
  339. all->par.regs, sizeof(struct cg3_regs));
  340. of_iounmap(&op->resource[0],
  341. all->info.screen_base, all->par.fbsize);
  342. kfree(all);
  343. return -ENOMEM;
  344. }
  345. fb_set_cmap(&all->info.cmap, &all->info);
  346. cg3_init_fix(&all->info, linebytes, dp);
  347. err = register_framebuffer(&all->info);
  348. if (err < 0) {
  349. fb_dealloc_cmap(&all->info.cmap);
  350. of_iounmap(&op->resource[0],
  351. all->par.regs, sizeof(struct cg3_regs));
  352. of_iounmap(&op->resource[0],
  353. all->info.screen_base, all->par.fbsize);
  354. kfree(all);
  355. return err;
  356. }
  357. dev_set_drvdata(&op->dev, all);
  358. printk("%s: cg3 at %lx:%lx\n",
  359. dp->full_name, all->par.which_io, all->par.physbase);
  360. return 0;
  361. }
  362. static int __devinit cg3_probe(struct of_device *dev,
  363. const struct of_device_id *match)
  364. {
  365. struct of_device *op = to_of_device(&dev->dev);
  366. return cg3_init_one(op);
  367. }
  368. static int __devexit cg3_remove(struct of_device *op)
  369. {
  370. struct all_info *all = dev_get_drvdata(&op->dev);
  371. unregister_framebuffer(&all->info);
  372. fb_dealloc_cmap(&all->info.cmap);
  373. of_iounmap(&op->resource[0], all->par.regs, sizeof(struct cg3_regs));
  374. of_iounmap(&op->resource[0], all->info.screen_base, all->par.fbsize);
  375. kfree(all);
  376. dev_set_drvdata(&op->dev, NULL);
  377. return 0;
  378. }
  379. static struct of_device_id cg3_match[] = {
  380. {
  381. .name = "cgthree",
  382. },
  383. {
  384. .name = "cgRDI",
  385. },
  386. {},
  387. };
  388. MODULE_DEVICE_TABLE(of, cg3_match);
  389. static struct of_platform_driver cg3_driver = {
  390. .name = "cg3",
  391. .match_table = cg3_match,
  392. .probe = cg3_probe,
  393. .remove = __devexit_p(cg3_remove),
  394. };
  395. static int __init cg3_init(void)
  396. {
  397. if (fb_get_options("cg3fb", NULL))
  398. return -ENODEV;
  399. return of_register_driver(&cg3_driver, &of_bus_type);
  400. }
  401. static void __exit cg3_exit(void)
  402. {
  403. of_unregister_driver(&cg3_driver);
  404. }
  405. module_init(cg3_init);
  406. module_exit(cg3_exit);
  407. MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
  408. MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
  409. MODULE_VERSION("2.0");
  410. MODULE_LICENSE("GPL");