asiliantfb.c 16 KB

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  1. /*
  2. * drivers/video/asiliantfb.c
  3. * frame buffer driver for Asiliant 69000 chip
  4. * Copyright (C) 2001-2003 Saito.K & Jeanne
  5. *
  6. * from driver/video/chipsfb.c and,
  7. *
  8. * drivers/video/asiliantfb.c -- frame buffer device for
  9. * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies)
  10. * Author: apc@agelectronics.co.uk
  11. * Copyright (C) 2000 AG Electronics
  12. * Note: the data sheets don't seem to be available from Asiliant.
  13. * They are available by searching developer.intel.com, but are not otherwise
  14. * linked to.
  15. *
  16. * This driver should be portable with minimal effort to the 69000 display
  17. * chip, and to the twin-display mode of the 69030.
  18. * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks)
  19. *
  20. * Derived from the CT65550 driver chipsfb.c:
  21. * Copyright (C) 1998 Paul Mackerras
  22. * ...which was derived from the Powermac "chips" driver:
  23. * Copyright (C) 1997 Fabio Riccardi.
  24. * And from the frame buffer device for Open Firmware-initialized devices:
  25. * Copyright (C) 1997 Geert Uytterhoeven.
  26. *
  27. * This file is subject to the terms and conditions of the GNU General Public
  28. * License. See the file COPYING in the main directory of this archive for
  29. * more details.
  30. */
  31. #include <linux/module.h>
  32. #include <linux/kernel.h>
  33. #include <linux/errno.h>
  34. #include <linux/string.h>
  35. #include <linux/mm.h>
  36. #include <linux/slab.h>
  37. #include <linux/vmalloc.h>
  38. #include <linux/delay.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/fb.h>
  41. #include <linux/init.h>
  42. #include <linux/pci.h>
  43. #include <asm/io.h>
  44. /* Built in clock of the 69030 */
  45. static const unsigned Fref = 14318180;
  46. #define mmio_base (p->screen_base + 0x400000)
  47. #define mm_write_ind(num, val, ap, dp) do { \
  48. writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
  49. } while (0)
  50. static void mm_write_xr(struct fb_info *p, u8 reg, u8 data)
  51. {
  52. mm_write_ind(reg, data, 0x7ac, 0x7ad);
  53. }
  54. #define write_xr(num, val) mm_write_xr(p, num, val)
  55. static void mm_write_fr(struct fb_info *p, u8 reg, u8 data)
  56. {
  57. mm_write_ind(reg, data, 0x7a0, 0x7a1);
  58. }
  59. #define write_fr(num, val) mm_write_fr(p, num, val)
  60. static void mm_write_cr(struct fb_info *p, u8 reg, u8 data)
  61. {
  62. mm_write_ind(reg, data, 0x7a8, 0x7a9);
  63. }
  64. #define write_cr(num, val) mm_write_cr(p, num, val)
  65. static void mm_write_gr(struct fb_info *p, u8 reg, u8 data)
  66. {
  67. mm_write_ind(reg, data, 0x79c, 0x79d);
  68. }
  69. #define write_gr(num, val) mm_write_gr(p, num, val)
  70. static void mm_write_sr(struct fb_info *p, u8 reg, u8 data)
  71. {
  72. mm_write_ind(reg, data, 0x788, 0x789);
  73. }
  74. #define write_sr(num, val) mm_write_sr(p, num, val)
  75. static void mm_write_ar(struct fb_info *p, u8 reg, u8 data)
  76. {
  77. readb(mmio_base + 0x7b4);
  78. mm_write_ind(reg, data, 0x780, 0x780);
  79. }
  80. #define write_ar(num, val) mm_write_ar(p, num, val)
  81. static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
  82. static int asiliantfb_check_var(struct fb_var_screeninfo *var,
  83. struct fb_info *info);
  84. static int asiliantfb_set_par(struct fb_info *info);
  85. static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  86. u_int transp, struct fb_info *info);
  87. static struct fb_ops asiliantfb_ops = {
  88. .owner = THIS_MODULE,
  89. .fb_check_var = asiliantfb_check_var,
  90. .fb_set_par = asiliantfb_set_par,
  91. .fb_setcolreg = asiliantfb_setcolreg,
  92. .fb_fillrect = cfb_fillrect,
  93. .fb_copyarea = cfb_copyarea,
  94. .fb_imageblit = cfb_imageblit,
  95. };
  96. /* Calculate the ratios for the dot clocks without using a single long long
  97. * value */
  98. static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div)
  99. {
  100. unsigned pixclock = *ppixclock;
  101. unsigned Ftarget = 1000000 * (1000000 / pixclock);
  102. unsigned n;
  103. unsigned best_error = 0xffffffff;
  104. unsigned best_m = 0xffffffff,
  105. best_n = 0xffffffff;
  106. unsigned ratio;
  107. unsigned remainder;
  108. unsigned char divisor = 0;
  109. /* Calculate the frequency required. This is hard enough. */
  110. ratio = 1000000 / pixclock;
  111. remainder = 1000000 % pixclock;
  112. Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock;
  113. while (Ftarget < 100000000) {
  114. divisor += 0x10;
  115. Ftarget <<= 1;
  116. }
  117. ratio = Ftarget / Fref;
  118. remainder = Ftarget % Fref;
  119. /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz,
  120. * together with 3 <= n <= 257. */
  121. for (n = 3; n <= 257; n++) {
  122. unsigned m = n * ratio + (n * remainder) / Fref;
  123. /* 3 <= m <= 257 */
  124. if (m >= 3 && m <= 257) {
  125. unsigned new_error = ((Ftarget * n) - (Fref * m)) >= 0 ?
  126. ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n));
  127. if (new_error < best_error) {
  128. best_n = n;
  129. best_m = m;
  130. best_error = new_error;
  131. }
  132. }
  133. /* But if VLD = 4, then 4m <= 1028 */
  134. else if (m <= 1028) {
  135. /* remember there are still only 8-bits of precision in m, so
  136. * avoid over-optimistic error calculations */
  137. unsigned new_error = ((Ftarget * n) - (Fref * (m & ~3))) >= 0 ?
  138. ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n));
  139. if (new_error < best_error) {
  140. best_n = n;
  141. best_m = m;
  142. best_error = new_error;
  143. }
  144. }
  145. }
  146. if (best_m > 257)
  147. best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */
  148. else
  149. divisor |= 4; /* or set VCO loop divide to 1 */
  150. *dclk2_m = best_m - 2;
  151. *dclk2_n = best_n - 2;
  152. *dclk2_div = divisor;
  153. *ppixclock = pixclock;
  154. return;
  155. }
  156. static void asiliant_set_timing(struct fb_info *p)
  157. {
  158. unsigned hd = p->var.xres / 8;
  159. unsigned hs = (p->var.xres + p->var.right_margin) / 8;
  160. unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
  161. unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
  162. unsigned vd = p->var.yres;
  163. unsigned vs = p->var.yres + p->var.lower_margin;
  164. unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len;
  165. unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len;
  166. unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8;
  167. if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) {
  168. write_fr(0x01, 0x02); /* LCD */
  169. } else {
  170. write_fr(0x01, 0x01); /* CRT */
  171. }
  172. write_cr(0x11, (ve - 1) & 0x0f);
  173. write_cr(0x00, (ht - 5) & 0xff);
  174. write_cr(0x01, hd - 1);
  175. write_cr(0x02, hd);
  176. write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);
  177. write_cr(0x04, hs);
  178. write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));
  179. write_cr(0x3c, (ht - 1) & 0xc0);
  180. write_cr(0x06, (vt - 2) & 0xff);
  181. write_cr(0x30, (vt - 2) >> 8);
  182. write_cr(0x07, 0x00);
  183. write_cr(0x08, 0x00);
  184. write_cr(0x09, 0x00);
  185. write_cr(0x10, (vs - 1) & 0xff);
  186. write_cr(0x32, ((vs - 1) >> 8) & 0xf);
  187. write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);
  188. write_cr(0x12, (vd - 1) & 0xff);
  189. write_cr(0x31, ((vd - 1) & 0xf00) >> 8);
  190. write_cr(0x13, wd & 0xff);
  191. write_cr(0x41, (wd & 0xf00) >> 8);
  192. write_cr(0x15, (vs - 1) & 0xff);
  193. write_cr(0x33, ((vs - 1) >> 8) & 0xf);
  194. write_cr(0x38, ((ht - 5) & 0x100) >> 8);
  195. write_cr(0x16, (vt - 1) & 0xff);
  196. write_cr(0x18, 0x00);
  197. if (p->var.xres == 640) {
  198. writeb(0xc7, mmio_base + 0x784); /* set misc output reg */
  199. } else {
  200. writeb(0x07, mmio_base + 0x784); /* set misc output reg */
  201. }
  202. }
  203. static int asiliantfb_check_var(struct fb_var_screeninfo *var,
  204. struct fb_info *p)
  205. {
  206. unsigned long Ftarget, ratio, remainder;
  207. ratio = 1000000 / var->pixclock;
  208. remainder = 1000000 % var->pixclock;
  209. Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock;
  210. /* First check the constraint that the maximum post-VCO divisor is 32,
  211. * and the maximum Fvco is 220MHz */
  212. if (Ftarget > 220000000 || Ftarget < 3125000) {
  213. printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n");
  214. return -ENXIO;
  215. }
  216. var->xres_virtual = var->xres;
  217. var->yres_virtual = var->yres;
  218. if (var->bits_per_pixel == 24) {
  219. var->red.offset = 16;
  220. var->green.offset = 8;
  221. var->blue.offset = 0;
  222. var->red.length = var->blue.length = var->green.length = 8;
  223. } else if (var->bits_per_pixel == 16) {
  224. switch (var->red.offset) {
  225. case 11:
  226. var->green.length = 6;
  227. break;
  228. case 10:
  229. var->green.length = 5;
  230. break;
  231. default:
  232. return -EINVAL;
  233. }
  234. var->green.offset = 5;
  235. var->blue.offset = 0;
  236. var->red.length = var->blue.length = 5;
  237. } else if (var->bits_per_pixel == 8) {
  238. var->red.offset = var->green.offset = var->blue.offset = 0;
  239. var->red.length = var->green.length = var->blue.length = 8;
  240. }
  241. return 0;
  242. }
  243. static int asiliantfb_set_par(struct fb_info *p)
  244. {
  245. u8 dclk2_m; /* Holds m-2 value for register */
  246. u8 dclk2_n; /* Holds n-2 value for register */
  247. u8 dclk2_div; /* Holds divisor bitmask */
  248. /* Set pixclock */
  249. asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div);
  250. /* Set color depth */
  251. if (p->var.bits_per_pixel == 24) {
  252. write_xr(0x81, 0x16); /* 24 bit packed color mode */
  253. write_xr(0x82, 0x00); /* Disable palettes */
  254. write_xr(0x20, 0x20); /* 24 bit blitter mode */
  255. } else if (p->var.bits_per_pixel == 16) {
  256. if (p->var.red.offset == 11)
  257. write_xr(0x81, 0x15); /* 16 bit color mode */
  258. else
  259. write_xr(0x81, 0x14); /* 15 bit color mode */
  260. write_xr(0x82, 0x00); /* Disable palettes */
  261. write_xr(0x20, 0x10); /* 16 bit blitter mode */
  262. } else if (p->var.bits_per_pixel == 8) {
  263. write_xr(0x0a, 0x02); /* Linear */
  264. write_xr(0x81, 0x12); /* 8 bit color mode */
  265. write_xr(0x82, 0x00); /* Graphics gamma enable */
  266. write_xr(0x20, 0x00); /* 8 bit blitter mode */
  267. }
  268. p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3);
  269. p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  270. write_xr(0xc4, dclk2_m);
  271. write_xr(0xc5, dclk2_n);
  272. write_xr(0xc7, dclk2_div);
  273. /* Set up the CR registers */
  274. asiliant_set_timing(p);
  275. return 0;
  276. }
  277. static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  278. u_int transp, struct fb_info *p)
  279. {
  280. if (regno > 255)
  281. return 1;
  282. red >>= 8;
  283. green >>= 8;
  284. blue >>= 8;
  285. /* Set hardware palete */
  286. writeb(regno, mmio_base + 0x790);
  287. udelay(1);
  288. writeb(red, mmio_base + 0x791);
  289. writeb(green, mmio_base + 0x791);
  290. writeb(blue, mmio_base + 0x791);
  291. if (regno < 16) {
  292. switch(p->var.red.offset) {
  293. case 10: /* RGB 555 */
  294. ((u32 *)(p->pseudo_palette))[regno] =
  295. ((red & 0xf8) << 7) |
  296. ((green & 0xf8) << 2) |
  297. ((blue & 0xf8) >> 3);
  298. break;
  299. case 11: /* RGB 565 */
  300. ((u32 *)(p->pseudo_palette))[regno] =
  301. ((red & 0xf8) << 8) |
  302. ((green & 0xfc) << 3) |
  303. ((blue & 0xf8) >> 3);
  304. break;
  305. case 16: /* RGB 888 */
  306. ((u32 *)(p->pseudo_palette))[regno] =
  307. (red << 16) |
  308. (green << 8) |
  309. (blue);
  310. break;
  311. }
  312. }
  313. return 0;
  314. }
  315. struct chips_init_reg {
  316. unsigned char addr;
  317. unsigned char data;
  318. };
  319. static struct chips_init_reg chips_init_sr[] =
  320. {
  321. {0x00, 0x03}, /* Reset register */
  322. {0x01, 0x01}, /* Clocking mode */
  323. {0x02, 0x0f}, /* Plane mask */
  324. {0x04, 0x0e} /* Memory mode */
  325. };
  326. static struct chips_init_reg chips_init_gr[] =
  327. {
  328. {0x03, 0x00}, /* Data rotate */
  329. {0x05, 0x00}, /* Graphics mode */
  330. {0x06, 0x01}, /* Miscellaneous */
  331. {0x08, 0x00} /* Bit mask */
  332. };
  333. static struct chips_init_reg chips_init_ar[] =
  334. {
  335. {0x10, 0x01}, /* Mode control */
  336. {0x11, 0x00}, /* Overscan */
  337. {0x12, 0x0f}, /* Memory plane enable */
  338. {0x13, 0x00} /* Horizontal pixel panning */
  339. };
  340. static struct chips_init_reg chips_init_cr[] =
  341. {
  342. {0x0c, 0x00}, /* Start address high */
  343. {0x0d, 0x00}, /* Start address low */
  344. {0x40, 0x00}, /* Extended Start Address */
  345. {0x41, 0x00}, /* Extended Start Address */
  346. {0x14, 0x00}, /* Underline location */
  347. {0x17, 0xe3}, /* CRT mode control */
  348. {0x70, 0x00} /* Interlace control */
  349. };
  350. static struct chips_init_reg chips_init_fr[] =
  351. {
  352. {0x01, 0x02},
  353. {0x03, 0x08},
  354. {0x08, 0xcc},
  355. {0x0a, 0x08},
  356. {0x18, 0x00},
  357. {0x1e, 0x80},
  358. {0x40, 0x83},
  359. {0x41, 0x00},
  360. {0x48, 0x13},
  361. {0x4d, 0x60},
  362. {0x4e, 0x0f},
  363. {0x0b, 0x01},
  364. {0x21, 0x51},
  365. {0x22, 0x1d},
  366. {0x23, 0x5f},
  367. {0x20, 0x4f},
  368. {0x34, 0x00},
  369. {0x24, 0x51},
  370. {0x25, 0x00},
  371. {0x27, 0x0b},
  372. {0x26, 0x00},
  373. {0x37, 0x80},
  374. {0x33, 0x0b},
  375. {0x35, 0x11},
  376. {0x36, 0x02},
  377. {0x31, 0xea},
  378. {0x32, 0x0c},
  379. {0x30, 0xdf},
  380. {0x10, 0x0c},
  381. {0x11, 0xe0},
  382. {0x12, 0x50},
  383. {0x13, 0x00},
  384. {0x16, 0x03},
  385. {0x17, 0xbd},
  386. {0x1a, 0x00},
  387. };
  388. static struct chips_init_reg chips_init_xr[] =
  389. {
  390. {0xce, 0x00}, /* set default memory clock */
  391. {0xcc, 200 }, /* MCLK ratio M */
  392. {0xcd, 18 }, /* MCLK ratio N */
  393. {0xce, 0x90}, /* MCLK divisor = 2 */
  394. {0xc4, 209 },
  395. {0xc5, 118 },
  396. {0xc7, 32 },
  397. {0xcf, 0x06},
  398. {0x09, 0x01}, /* IO Control - CRT controller extensions */
  399. {0x0a, 0x02}, /* Frame buffer mapping */
  400. {0x0b, 0x01}, /* PCI burst write */
  401. {0x40, 0x03}, /* Memory access control */
  402. {0x80, 0x82}, /* Pixel pipeline configuration 0 */
  403. {0x81, 0x12}, /* Pixel pipeline configuration 1 */
  404. {0x82, 0x08}, /* Pixel pipeline configuration 2 */
  405. {0xd0, 0x0f},
  406. {0xd1, 0x01},
  407. };
  408. static void __devinit chips_hw_init(struct fb_info *p)
  409. {
  410. int i;
  411. for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
  412. write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
  413. write_xr(0x81, 0x12);
  414. write_xr(0x82, 0x08);
  415. write_xr(0x20, 0x00);
  416. for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
  417. write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
  418. for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
  419. write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
  420. for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
  421. write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
  422. /* Enable video output in attribute index register */
  423. writeb(0x20, mmio_base + 0x780);
  424. for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
  425. write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
  426. for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
  427. write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
  428. }
  429. static struct fb_fix_screeninfo asiliantfb_fix __devinitdata = {
  430. .id = "Asiliant 69000",
  431. .type = FB_TYPE_PACKED_PIXELS,
  432. .visual = FB_VISUAL_PSEUDOCOLOR,
  433. .accel = FB_ACCEL_NONE,
  434. .line_length = 640,
  435. .smem_len = 0x200000, /* 2MB */
  436. };
  437. static struct fb_var_screeninfo asiliantfb_var __devinitdata = {
  438. .xres = 640,
  439. .yres = 480,
  440. .xres_virtual = 640,
  441. .yres_virtual = 480,
  442. .bits_per_pixel = 8,
  443. .red = { .length = 8 },
  444. .green = { .length = 8 },
  445. .blue = { .length = 8 },
  446. .height = -1,
  447. .width = -1,
  448. .vmode = FB_VMODE_NONINTERLACED,
  449. .pixclock = 39722,
  450. .left_margin = 48,
  451. .right_margin = 16,
  452. .upper_margin = 33,
  453. .lower_margin = 10,
  454. .hsync_len = 96,
  455. .vsync_len = 2,
  456. };
  457. static void __devinit init_asiliant(struct fb_info *p, unsigned long addr)
  458. {
  459. p->fix = asiliantfb_fix;
  460. p->fix.smem_start = addr;
  461. p->var = asiliantfb_var;
  462. p->fbops = &asiliantfb_ops;
  463. p->flags = FBINFO_DEFAULT;
  464. fb_alloc_cmap(&p->cmap, 256, 0);
  465. if (register_framebuffer(p) < 0) {
  466. printk(KERN_ERR "C&T 69000 framebuffer failed to register\n");
  467. return;
  468. }
  469. printk(KERN_INFO "fb%d: Asiliant 69000 frame buffer (%dK RAM detected)\n",
  470. p->node, p->fix.smem_len / 1024);
  471. writeb(0xff, mmio_base + 0x78c);
  472. chips_hw_init(p);
  473. }
  474. static int __devinit
  475. asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
  476. {
  477. unsigned long addr, size;
  478. struct fb_info *p;
  479. if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
  480. return -ENODEV;
  481. addr = pci_resource_start(dp, 0);
  482. size = pci_resource_len(dp, 0);
  483. if (addr == 0)
  484. return -ENODEV;
  485. if (!request_mem_region(addr, size, "asiliantfb"))
  486. return -EBUSY;
  487. p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev);
  488. if (!p) {
  489. release_mem_region(addr, size);
  490. return -ENOMEM;
  491. }
  492. p->pseudo_palette = p->par;
  493. p->par = NULL;
  494. p->screen_base = ioremap(addr, 0x800000);
  495. if (p->screen_base == NULL) {
  496. release_mem_region(addr, size);
  497. framebuffer_release(p);
  498. return -ENOMEM;
  499. }
  500. pci_write_config_dword(dp, 4, 0x02800083);
  501. writeb(3, p->screen_base + 0x400784);
  502. init_asiliant(p, addr);
  503. pci_set_drvdata(dp, p);
  504. return 0;
  505. }
  506. static void __devexit asiliantfb_remove(struct pci_dev *dp)
  507. {
  508. struct fb_info *p = pci_get_drvdata(dp);
  509. unregister_framebuffer(p);
  510. iounmap(p->screen_base);
  511. release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));
  512. pci_set_drvdata(dp, NULL);
  513. framebuffer_release(p);
  514. }
  515. static struct pci_device_id asiliantfb_pci_tbl[] __devinitdata = {
  516. { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID },
  517. { 0 }
  518. };
  519. MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl);
  520. static struct pci_driver asiliantfb_driver = {
  521. .name = "asiliantfb",
  522. .id_table = asiliantfb_pci_tbl,
  523. .probe = asiliantfb_pci_init,
  524. .remove = __devexit_p(asiliantfb_remove),
  525. };
  526. static int __init asiliantfb_init(void)
  527. {
  528. if (fb_get_options("asiliantfb", NULL))
  529. return -ENODEV;
  530. return pci_register_driver(&asiliantfb_driver);
  531. }
  532. module_init(asiliantfb_init);
  533. static void __exit asiliantfb_exit(void)
  534. {
  535. pci_unregister_driver(&asiliantfb_driver);
  536. }
  537. MODULE_LICENSE("GPL");