acornfb.h 4.7 KB

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  1. /*
  2. * linux/drivers/video/acornfb.h
  3. *
  4. * Copyright (C) 1998,1999 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Frame buffer code for Acorn platforms
  11. */
  12. #if defined(HAS_VIDC20)
  13. #include <asm/hardware/iomd.h>
  14. #define VIDC_PALETTE_SIZE 256
  15. #define VIDC_NAME "VIDC20"
  16. #elif defined(HAS_VIDC)
  17. #include <asm/hardware/memc.h>
  18. #define VIDC_PALETTE_SIZE 16
  19. #define VIDC_NAME "VIDC"
  20. #endif
  21. #define EXTEND8(x) ((x)|(x)<<8)
  22. #define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12)
  23. struct vidc20_palette {
  24. u_int red:8;
  25. u_int green:8;
  26. u_int blue:8;
  27. u_int ext:4;
  28. u_int unused:4;
  29. };
  30. struct vidc_palette {
  31. u_int red:4;
  32. u_int green:4;
  33. u_int blue:4;
  34. u_int trans:1;
  35. u_int sbz1:13;
  36. u_int reg:4;
  37. u_int sbz2:2;
  38. };
  39. union palette {
  40. struct vidc20_palette vidc20;
  41. struct vidc_palette vidc;
  42. u_int p;
  43. };
  44. struct acornfb_par {
  45. struct device *dev;
  46. unsigned long screen_end;
  47. unsigned int dram_size;
  48. unsigned int vram_half_sam;
  49. unsigned int palette_size;
  50. signed int montype;
  51. unsigned int using_vram : 1;
  52. unsigned int dpms : 1;
  53. union palette palette[VIDC_PALETTE_SIZE];
  54. u32 pseudo_palette[16];
  55. };
  56. struct vidc_timing {
  57. u_int h_cycle;
  58. u_int h_sync_width;
  59. u_int h_border_start;
  60. u_int h_display_start;
  61. u_int h_display_end;
  62. u_int h_border_end;
  63. u_int h_interlace;
  64. u_int v_cycle;
  65. u_int v_sync_width;
  66. u_int v_border_start;
  67. u_int v_display_start;
  68. u_int v_display_end;
  69. u_int v_border_end;
  70. u_int control;
  71. /* VIDC20 only */
  72. u_int pll_ctl;
  73. };
  74. struct modey_params {
  75. u_int y_res;
  76. u_int u_margin;
  77. u_int b_margin;
  78. u_int vsync_len;
  79. u_int vf;
  80. };
  81. struct modex_params {
  82. u_int x_res;
  83. u_int l_margin;
  84. u_int r_margin;
  85. u_int hsync_len;
  86. u_int clock;
  87. u_int hf;
  88. const struct modey_params *modey;
  89. };
  90. #ifdef HAS_VIDC
  91. #define VID_CTL_VS_NVSYNC (1 << 3)
  92. #define VID_CTL_HS_NHSYNC (1 << 2)
  93. #define VID_CTL_24MHz (0)
  94. #define VID_CTL_25MHz (1)
  95. #define VID_CTL_36MHz (2)
  96. #define VIDC_CTRL_CSYNC (1 << 7)
  97. #define VIDC_CTRL_INTERLACE (1 << 6)
  98. #define VIDC_CTRL_FIFO_0_4 (0 << 4)
  99. #define VIDC_CTRL_FIFO_1_5 (1 << 4)
  100. #define VIDC_CTRL_FIFO_2_6 (2 << 4)
  101. #define VIDC_CTRL_FIFO_3_7 (3 << 4)
  102. #define VIDC_CTRL_1BPP (0 << 2)
  103. #define VIDC_CTRL_2BPP (1 << 2)
  104. #define VIDC_CTRL_4BPP (2 << 2)
  105. #define VIDC_CTRL_8BPP (3 << 2)
  106. #define VIDC_CTRL_DIV3 (0 << 0)
  107. #define VIDC_CTRL_DIV2 (1 << 0)
  108. #define VIDC_CTRL_DIV1_5 (2 << 0)
  109. #define VIDC_CTRL_DIV1 (3 << 0)
  110. #endif
  111. #ifdef HAS_VIDC20
  112. /*
  113. * VIDC20 registers
  114. */
  115. #define VIDC20_CTRL 0xe0000000
  116. #define VIDC20_CTRL_PIX_VCLK (0 << 0)
  117. #define VIDC20_CTRL_PIX_HCLK (1 << 0)
  118. #define VIDC20_CTRL_PIX_RCLK (2 << 0)
  119. #define VIDC20_CTRL_PIX_CK (0 << 2)
  120. #define VIDC20_CTRL_PIX_CK2 (1 << 2)
  121. #define VIDC20_CTRL_PIX_CK3 (2 << 2)
  122. #define VIDC20_CTRL_PIX_CK4 (3 << 2)
  123. #define VIDC20_CTRL_PIX_CK5 (4 << 2)
  124. #define VIDC20_CTRL_PIX_CK6 (5 << 2)
  125. #define VIDC20_CTRL_PIX_CK7 (6 << 2)
  126. #define VIDC20_CTRL_PIX_CK8 (7 << 2)
  127. #define VIDC20_CTRL_1BPP (0 << 5)
  128. #define VIDC20_CTRL_2BPP (1 << 5)
  129. #define VIDC20_CTRL_4BPP (2 << 5)
  130. #define VIDC20_CTRL_8BPP (3 << 5)
  131. #define VIDC20_CTRL_16BPP (4 << 5)
  132. #define VIDC20_CTRL_32BPP (6 << 5)
  133. #define VIDC20_CTRL_FIFO_NS (0 << 8)
  134. #define VIDC20_CTRL_FIFO_4 (1 << 8)
  135. #define VIDC20_CTRL_FIFO_8 (2 << 8)
  136. #define VIDC20_CTRL_FIFO_12 (3 << 8)
  137. #define VIDC20_CTRL_FIFO_16 (4 << 8)
  138. #define VIDC20_CTRL_FIFO_20 (5 << 8)
  139. #define VIDC20_CTRL_FIFO_24 (6 << 8)
  140. #define VIDC20_CTRL_FIFO_28 (7 << 8)
  141. #define VIDC20_CTRL_INT (1 << 12)
  142. #define VIDC20_CTRL_DUP (1 << 13)
  143. #define VIDC20_CTRL_PDOWN (1 << 14)
  144. #define VIDC20_ECTL 0xc0000000
  145. #define VIDC20_ECTL_REG(x) ((x) & 0xf3)
  146. #define VIDC20_ECTL_ECK (1 << 2)
  147. #define VIDC20_ECTL_REDPED (1 << 8)
  148. #define VIDC20_ECTL_GREENPED (1 << 9)
  149. #define VIDC20_ECTL_BLUEPED (1 << 10)
  150. #define VIDC20_ECTL_DAC (1 << 12)
  151. #define VIDC20_ECTL_LCDGS (1 << 13)
  152. #define VIDC20_ECTL_HRM (1 << 14)
  153. #define VIDC20_ECTL_HS_MASK (3 << 16)
  154. #define VIDC20_ECTL_HS_HSYNC (0 << 16)
  155. #define VIDC20_ECTL_HS_NHSYNC (1 << 16)
  156. #define VIDC20_ECTL_HS_CSYNC (2 << 16)
  157. #define VIDC20_ECTL_HS_NCSYNC (3 << 16)
  158. #define VIDC20_ECTL_VS_MASK (3 << 18)
  159. #define VIDC20_ECTL_VS_VSYNC (0 << 18)
  160. #define VIDC20_ECTL_VS_NVSYNC (1 << 18)
  161. #define VIDC20_ECTL_VS_CSYNC (2 << 18)
  162. #define VIDC20_ECTL_VS_NCSYNC (3 << 18)
  163. #define VIDC20_DCTL 0xf0000000
  164. /* 0-9 = number of words in scanline */
  165. #define VIDC20_DCTL_SNA (1 << 12)
  166. #define VIDC20_DCTL_HDIS (1 << 13)
  167. #define VIDC20_DCTL_BUS_NS (0 << 16)
  168. #define VIDC20_DCTL_BUS_D31_0 (1 << 16)
  169. #define VIDC20_DCTL_BUS_D63_32 (2 << 16)
  170. #define VIDC20_DCTL_BUS_D63_0 (3 << 16)
  171. #define VIDC20_DCTL_VRAM_DIS (0 << 18)
  172. #define VIDC20_DCTL_VRAM_PXCLK (1 << 18)
  173. #define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18)
  174. #define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18)
  175. #endif