sunzilog.h 8.6 KB

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  1. #ifndef _SUNZILOG_H
  2. #define _SUNZILOG_H
  3. struct zilog_channel {
  4. volatile unsigned char control;
  5. volatile unsigned char __pad1;
  6. volatile unsigned char data;
  7. volatile unsigned char __pad2;
  8. };
  9. struct zilog_layout {
  10. struct zilog_channel channelB;
  11. struct zilog_channel channelA;
  12. };
  13. #define NUM_ZSREGS 16
  14. /* Conversion routines to/from brg time constants from/to bits
  15. * per second.
  16. */
  17. #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
  18. #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
  19. /* The Zilog register set */
  20. #define FLAG 0x7e
  21. /* Write Register 0 */
  22. #define R0 0 /* Register selects */
  23. #define R1 1
  24. #define R2 2
  25. #define R3 3
  26. #define R4 4
  27. #define R5 5
  28. #define R6 6
  29. #define R7 7
  30. #define R8 8
  31. #define R9 9
  32. #define R10 10
  33. #define R11 11
  34. #define R12 12
  35. #define R13 13
  36. #define R14 14
  37. #define R15 15
  38. #define NULLCODE 0 /* Null Code */
  39. #define POINT_HIGH 0x8 /* Select upper half of registers */
  40. #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
  41. #define SEND_ABORT 0x18 /* HDLC Abort */
  42. #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
  43. #define RES_Tx_P 0x28 /* Reset TxINT Pending */
  44. #define ERR_RES 0x30 /* Error Reset */
  45. #define RES_H_IUS 0x38 /* Reset highest IUS */
  46. #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
  47. #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
  48. #define RES_EOM_L 0xC0 /* Reset EOM latch */
  49. /* Write Register 1 */
  50. #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
  51. #define TxINT_ENAB 0x2 /* Tx Int Enable */
  52. #define PAR_SPEC 0x4 /* Parity is special condition */
  53. #define RxINT_DISAB 0 /* Rx Int Disable */
  54. #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
  55. #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
  56. #define INT_ERR_Rx 0x18 /* Int on error only */
  57. #define RxINT_MASK 0x18
  58. #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
  59. #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
  60. #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
  61. /* Write Register #2 (Interrupt Vector) */
  62. /* Write Register 3 */
  63. #define RxENAB 0x1 /* Rx Enable */
  64. #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
  65. #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
  66. #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
  67. #define ENT_HM 0x10 /* Enter Hunt Mode */
  68. #define AUTO_ENAB 0x20 /* Auto Enables */
  69. #define Rx5 0x0 /* Rx 5 Bits/Character */
  70. #define Rx7 0x40 /* Rx 7 Bits/Character */
  71. #define Rx6 0x80 /* Rx 6 Bits/Character */
  72. #define Rx8 0xc0 /* Rx 8 Bits/Character */
  73. #define RxN_MASK 0xc0
  74. /* Write Register 4 */
  75. #define PAR_ENAB 0x1 /* Parity Enable */
  76. #define PAR_EVEN 0x2 /* Parity Even/Odd* */
  77. #define SYNC_ENAB 0 /* Sync Modes Enable */
  78. #define SB1 0x4 /* 1 stop bit/char */
  79. #define SB15 0x8 /* 1.5 stop bits/char */
  80. #define SB2 0xc /* 2 stop bits/char */
  81. #define MONSYNC 0 /* 8 Bit Sync character */
  82. #define BISYNC 0x10 /* 16 bit sync character */
  83. #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
  84. #define EXTSYNC 0x30 /* External Sync Mode */
  85. #define X1CLK 0x0 /* x1 clock mode */
  86. #define X16CLK 0x40 /* x16 clock mode */
  87. #define X32CLK 0x80 /* x32 clock mode */
  88. #define X64CLK 0xC0 /* x64 clock mode */
  89. #define XCLK_MASK 0xC0
  90. /* Write Register 5 */
  91. #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
  92. #define RTS 0x2 /* RTS */
  93. #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
  94. #define TxENAB 0x8 /* Tx Enable */
  95. #define SND_BRK 0x10 /* Send Break */
  96. #define Tx5 0x0 /* Tx 5 bits (or less)/character */
  97. #define Tx7 0x20 /* Tx 7 bits/character */
  98. #define Tx6 0x40 /* Tx 6 bits/character */
  99. #define Tx8 0x60 /* Tx 8 bits/character */
  100. #define TxN_MASK 0x60
  101. #define DTR 0x80 /* DTR */
  102. /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
  103. /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
  104. /* Write Register 8 (transmit buffer) */
  105. /* Write Register 9 (Master interrupt control) */
  106. #define VIS 1 /* Vector Includes Status */
  107. #define NV 2 /* No Vector */
  108. #define DLC 4 /* Disable Lower Chain */
  109. #define MIE 8 /* Master Interrupt Enable */
  110. #define STATHI 0x10 /* Status high */
  111. #define NORESET 0 /* No reset on write to R9 */
  112. #define CHRB 0x40 /* Reset channel B */
  113. #define CHRA 0x80 /* Reset channel A */
  114. #define FHWRES 0xc0 /* Force hardware reset */
  115. /* Write Register 10 (misc control bits) */
  116. #define BIT6 1 /* 6 bit/8bit sync */
  117. #define LOOPMODE 2 /* SDLC Loop mode */
  118. #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
  119. #define MARKIDLE 8 /* Mark/flag on idle */
  120. #define GAOP 0x10 /* Go active on poll */
  121. #define NRZ 0 /* NRZ mode */
  122. #define NRZI 0x20 /* NRZI mode */
  123. #define FM1 0x40 /* FM1 (transition = 1) */
  124. #define FM0 0x60 /* FM0 (transition = 0) */
  125. #define CRCPS 0x80 /* CRC Preset I/O */
  126. /* Write Register 11 (Clock Mode control) */
  127. #define TRxCXT 0 /* TRxC = Xtal output */
  128. #define TRxCTC 1 /* TRxC = Transmit clock */
  129. #define TRxCBR 2 /* TRxC = BR Generator Output */
  130. #define TRxCDP 3 /* TRxC = DPLL output */
  131. #define TRxCOI 4 /* TRxC O/I */
  132. #define TCRTxCP 0 /* Transmit clock = RTxC pin */
  133. #define TCTRxCP 8 /* Transmit clock = TRxC pin */
  134. #define TCBR 0x10 /* Transmit clock = BR Generator output */
  135. #define TCDPLL 0x18 /* Transmit clock = DPLL output */
  136. #define RCRTxCP 0 /* Receive clock = RTxC pin */
  137. #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
  138. #define RCBR 0x40 /* Receive clock = BR Generator output */
  139. #define RCDPLL 0x60 /* Receive clock = DPLL output */
  140. #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
  141. /* Write Register 12 (lower byte of baud rate generator time constant) */
  142. /* Write Register 13 (upper byte of baud rate generator time constant) */
  143. /* Write Register 14 (Misc control bits) */
  144. #define BRENAB 1 /* Baud rate generator enable */
  145. #define BRSRC 2 /* Baud rate generator source */
  146. #define DTRREQ 4 /* DTR/Request function */
  147. #define AUTOECHO 8 /* Auto Echo */
  148. #define LOOPBAK 0x10 /* Local loopback */
  149. #define SEARCH 0x20 /* Enter search mode */
  150. #define RMC 0x40 /* Reset missing clock */
  151. #define DISDPLL 0x60 /* Disable DPLL */
  152. #define SSBR 0x80 /* Set DPLL source = BR generator */
  153. #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
  154. #define SFMM 0xc0 /* Set FM mode */
  155. #define SNRZI 0xe0 /* Set NRZI mode */
  156. /* Write Register 15 (external/status interrupt control) */
  157. #define ZCIE 2 /* Zero count IE */
  158. #define DCDIE 8 /* DCD IE */
  159. #define SYNCIE 0x10 /* Sync/hunt IE */
  160. #define CTSIE 0x20 /* CTS IE */
  161. #define TxUIE 0x40 /* Tx Underrun/EOM IE */
  162. #define BRKIE 0x80 /* Break/Abort IE */
  163. /* Read Register 0 */
  164. #define Rx_CH_AV 0x1 /* Rx Character Available */
  165. #define ZCOUNT 0x2 /* Zero count */
  166. #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
  167. #define DCD 0x8 /* DCD */
  168. #define SYNC 0x10 /* Sync/hunt */
  169. #define CTS 0x20 /* CTS */
  170. #define TxEOM 0x40 /* Tx underrun */
  171. #define BRK_ABRT 0x80 /* Break/Abort */
  172. /* Read Register 1 */
  173. #define ALL_SNT 0x1 /* All sent */
  174. /* Residue Data for 8 Rx bits/char programmed */
  175. #define RES3 0x8 /* 0/3 */
  176. #define RES4 0x4 /* 0/4 */
  177. #define RES5 0xc /* 0/5 */
  178. #define RES6 0x2 /* 0/6 */
  179. #define RES7 0xa /* 0/7 */
  180. #define RES8 0x6 /* 0/8 */
  181. #define RES18 0xe /* 1/8 */
  182. #define RES28 0x0 /* 2/8 */
  183. /* Special Rx Condition Interrupts */
  184. #define PAR_ERR 0x10 /* Parity error */
  185. #define Rx_OVR 0x20 /* Rx Overrun Error */
  186. #define CRC_ERR 0x40 /* CRC/Framing Error */
  187. #define END_FR 0x80 /* End of Frame (SDLC) */
  188. /* Read Register 2 (channel b only) - Interrupt vector */
  189. #define CHB_Tx_EMPTY 0x00
  190. #define CHB_EXT_STAT 0x02
  191. #define CHB_Rx_AVAIL 0x04
  192. #define CHB_SPECIAL 0x06
  193. #define CHA_Tx_EMPTY 0x08
  194. #define CHA_EXT_STAT 0x0a
  195. #define CHA_Rx_AVAIL 0x0c
  196. #define CHA_SPECIAL 0x0e
  197. #define STATUS_MASK 0x0e
  198. /* Read Register 3 (interrupt pending register) ch a only */
  199. #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
  200. #define CHBTxIP 0x2 /* Channel B Tx IP */
  201. #define CHBRxIP 0x4 /* Channel B Rx IP */
  202. #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
  203. #define CHATxIP 0x10 /* Channel A Tx IP */
  204. #define CHARxIP 0x20 /* Channel A Rx IP */
  205. /* Read Register 8 (receive data register) */
  206. /* Read Register 10 (misc status bits) */
  207. #define ONLOOP 2 /* On loop */
  208. #define LOOPSEND 0x10 /* Loop sending */
  209. #define CLK2MIS 0x40 /* Two clocks missing */
  210. #define CLK1MIS 0x80 /* One clock missing */
  211. /* Read Register 12 (lower byte of baud rate generator constant) */
  212. /* Read Register 13 (upper byte of baud rate generator constant) */
  213. /* Read Register 15 (value of WR 15) */
  214. /* Misc macros */
  215. #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
  216. udelay(5); } while(0)
  217. #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
  218. udelay(5); } while(0)
  219. #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
  220. udelay(2); \
  221. sbus_readb(&channel->data); \
  222. udelay(2); \
  223. sbus_readb(&channel->data); \
  224. udelay(2); } while(0)
  225. #endif /* _SUNZILOG_H */