sunzilog.c 37 KB

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  1. /* sunzilog.c: Zilog serial driver for Sparc systems.
  2. *
  3. * Driver for Zilog serial chips found on Sun workstations and
  4. * servers. This driver could actually be made more generic.
  5. *
  6. * This is based on the old drivers/sbus/char/zs.c code. A lot
  7. * of code has been simply moved over directly from there but
  8. * much has been rewritten. Credits therefore go out to Eddie
  9. * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
  10. * work there.
  11. *
  12. * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/errno.h>
  17. #include <linux/delay.h>
  18. #include <linux/tty.h>
  19. #include <linux/tty_flip.h>
  20. #include <linux/major.h>
  21. #include <linux/string.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/ioport.h>
  24. #include <linux/slab.h>
  25. #include <linux/circ_buf.h>
  26. #include <linux/serial.h>
  27. #include <linux/sysrq.h>
  28. #include <linux/console.h>
  29. #include <linux/spinlock.h>
  30. #ifdef CONFIG_SERIO
  31. #include <linux/serio.h>
  32. #endif
  33. #include <linux/init.h>
  34. #include <asm/io.h>
  35. #include <asm/irq.h>
  36. #include <asm/prom.h>
  37. #include <asm/of_device.h>
  38. #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  39. #define SUPPORT_SYSRQ
  40. #endif
  41. #include <linux/serial_core.h>
  42. #include "suncore.h"
  43. #include "sunzilog.h"
  44. /* On 32-bit sparcs we need to delay after register accesses
  45. * to accommodate sun4 systems, but we do not need to flush writes.
  46. * On 64-bit sparc we only need to flush single writes to ensure
  47. * completion.
  48. */
  49. #ifndef CONFIG_SPARC64
  50. #define ZSDELAY() udelay(5)
  51. #define ZSDELAY_LONG() udelay(20)
  52. #define ZS_WSYNC(channel) do { } while (0)
  53. #else
  54. #define ZSDELAY()
  55. #define ZSDELAY_LONG()
  56. #define ZS_WSYNC(__channel) \
  57. readb(&((__channel)->control))
  58. #endif
  59. static int num_sunzilog;
  60. #define NUM_SUNZILOG num_sunzilog
  61. #define NUM_CHANNELS (NUM_SUNZILOG * 2)
  62. #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
  63. #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
  64. /*
  65. * We wrap our port structure around the generic uart_port.
  66. */
  67. struct uart_sunzilog_port {
  68. struct uart_port port;
  69. /* IRQ servicing chain. */
  70. struct uart_sunzilog_port *next;
  71. /* Current values of Zilog write registers. */
  72. unsigned char curregs[NUM_ZSREGS];
  73. unsigned int flags;
  74. #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
  75. #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
  76. #define SUNZILOG_FLAG_IS_CONS 0x00000004
  77. #define SUNZILOG_FLAG_IS_KGDB 0x00000008
  78. #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
  79. #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
  80. #define SUNZILOG_FLAG_REGS_HELD 0x00000040
  81. #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
  82. #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
  83. unsigned int cflag;
  84. unsigned char parity_mask;
  85. unsigned char prev_status;
  86. #ifdef CONFIG_SERIO
  87. struct serio serio;
  88. int serio_open;
  89. #endif
  90. };
  91. #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
  92. #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
  93. #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
  94. #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
  95. #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
  96. #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
  97. #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
  98. #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
  99. #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
  100. #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
  101. #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
  102. /* Reading and writing Zilog8530 registers. The delays are to make this
  103. * driver work on the Sun4 which needs a settling delay after each chip
  104. * register access, other machines handle this in hardware via auxiliary
  105. * flip-flops which implement the settle time we do in software.
  106. *
  107. * The port lock must be held and local IRQs must be disabled
  108. * when {read,write}_zsreg is invoked.
  109. */
  110. static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
  111. unsigned char reg)
  112. {
  113. unsigned char retval;
  114. writeb(reg, &channel->control);
  115. ZSDELAY();
  116. retval = readb(&channel->control);
  117. ZSDELAY();
  118. return retval;
  119. }
  120. static void write_zsreg(struct zilog_channel __iomem *channel,
  121. unsigned char reg, unsigned char value)
  122. {
  123. writeb(reg, &channel->control);
  124. ZSDELAY();
  125. writeb(value, &channel->control);
  126. ZSDELAY();
  127. }
  128. static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
  129. {
  130. int i;
  131. for (i = 0; i < 32; i++) {
  132. unsigned char regval;
  133. regval = readb(&channel->control);
  134. ZSDELAY();
  135. if (regval & Rx_CH_AV)
  136. break;
  137. regval = read_zsreg(channel, R1);
  138. readb(&channel->data);
  139. ZSDELAY();
  140. if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
  141. writeb(ERR_RES, &channel->control);
  142. ZSDELAY();
  143. ZS_WSYNC(channel);
  144. }
  145. }
  146. }
  147. /* This function must only be called when the TX is not busy. The UART
  148. * port lock must be held and local interrupts disabled.
  149. */
  150. static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
  151. {
  152. int i;
  153. /* Let pending transmits finish. */
  154. for (i = 0; i < 1000; i++) {
  155. unsigned char stat = read_zsreg(channel, R1);
  156. if (stat & ALL_SNT)
  157. break;
  158. udelay(100);
  159. }
  160. writeb(ERR_RES, &channel->control);
  161. ZSDELAY();
  162. ZS_WSYNC(channel);
  163. sunzilog_clear_fifo(channel);
  164. /* Disable all interrupts. */
  165. write_zsreg(channel, R1,
  166. regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
  167. /* Set parity, sync config, stop bits, and clock divisor. */
  168. write_zsreg(channel, R4, regs[R4]);
  169. /* Set misc. TX/RX control bits. */
  170. write_zsreg(channel, R10, regs[R10]);
  171. /* Set TX/RX controls sans the enable bits. */
  172. write_zsreg(channel, R3, regs[R3] & ~RxENAB);
  173. write_zsreg(channel, R5, regs[R5] & ~TxENAB);
  174. /* Synchronous mode config. */
  175. write_zsreg(channel, R6, regs[R6]);
  176. write_zsreg(channel, R7, regs[R7]);
  177. /* Don't mess with the interrupt vector (R2, unused by us) and
  178. * master interrupt control (R9). We make sure this is setup
  179. * properly at probe time then never touch it again.
  180. */
  181. /* Disable baud generator. */
  182. write_zsreg(channel, R14, regs[R14] & ~BRENAB);
  183. /* Clock mode control. */
  184. write_zsreg(channel, R11, regs[R11]);
  185. /* Lower and upper byte of baud rate generator divisor. */
  186. write_zsreg(channel, R12, regs[R12]);
  187. write_zsreg(channel, R13, regs[R13]);
  188. /* Now rewrite R14, with BRENAB (if set). */
  189. write_zsreg(channel, R14, regs[R14]);
  190. /* External status interrupt control. */
  191. write_zsreg(channel, R15, regs[R15]);
  192. /* Reset external status interrupts. */
  193. write_zsreg(channel, R0, RES_EXT_INT);
  194. write_zsreg(channel, R0, RES_EXT_INT);
  195. /* Rewrite R3/R5, this time without enables masked. */
  196. write_zsreg(channel, R3, regs[R3]);
  197. write_zsreg(channel, R5, regs[R5]);
  198. /* Rewrite R1, this time without IRQ enabled masked. */
  199. write_zsreg(channel, R1, regs[R1]);
  200. }
  201. /* Reprogram the Zilog channel HW registers with the copies found in the
  202. * software state struct. If the transmitter is busy, we defer this update
  203. * until the next TX complete interrupt. Else, we do it right now.
  204. *
  205. * The UART port lock must be held and local interrupts disabled.
  206. */
  207. static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
  208. struct zilog_channel __iomem *channel)
  209. {
  210. if (!ZS_REGS_HELD(up)) {
  211. if (ZS_TX_ACTIVE(up)) {
  212. up->flags |= SUNZILOG_FLAG_REGS_HELD;
  213. } else {
  214. __load_zsregs(channel, up->curregs);
  215. }
  216. }
  217. }
  218. static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
  219. {
  220. unsigned int cur_cflag = up->cflag;
  221. int brg, new_baud;
  222. up->cflag &= ~CBAUD;
  223. up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
  224. brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  225. up->curregs[R12] = (brg & 0xff);
  226. up->curregs[R13] = (brg >> 8) & 0xff;
  227. sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
  228. }
  229. static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
  230. unsigned char ch, int is_break)
  231. {
  232. if (ZS_IS_KEYB(up)) {
  233. /* Stop-A is handled by drivers/char/keyboard.c now. */
  234. #ifdef CONFIG_SERIO
  235. if (up->serio_open)
  236. serio_interrupt(&up->serio, ch, 0);
  237. #endif
  238. } else if (ZS_IS_MOUSE(up)) {
  239. int ret = suncore_mouse_baud_detection(ch, is_break);
  240. switch (ret) {
  241. case 2:
  242. sunzilog_change_mouse_baud(up);
  243. /* fallthru */
  244. case 1:
  245. break;
  246. case 0:
  247. #ifdef CONFIG_SERIO
  248. if (up->serio_open)
  249. serio_interrupt(&up->serio, ch, 0);
  250. #endif
  251. break;
  252. };
  253. }
  254. }
  255. static struct tty_struct *
  256. sunzilog_receive_chars(struct uart_sunzilog_port *up,
  257. struct zilog_channel __iomem *channel)
  258. {
  259. struct tty_struct *tty;
  260. unsigned char ch, r1, flag;
  261. tty = NULL;
  262. if (up->port.info != NULL && /* Unopened serial console */
  263. up->port.info->tty != NULL) /* Keyboard || mouse */
  264. tty = up->port.info->tty;
  265. for (;;) {
  266. r1 = read_zsreg(channel, R1);
  267. if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
  268. writeb(ERR_RES, &channel->control);
  269. ZSDELAY();
  270. ZS_WSYNC(channel);
  271. }
  272. ch = readb(&channel->control);
  273. ZSDELAY();
  274. /* This funny hack depends upon BRK_ABRT not interfering
  275. * with the other bits we care about in R1.
  276. */
  277. if (ch & BRK_ABRT)
  278. r1 |= BRK_ABRT;
  279. if (!(ch & Rx_CH_AV))
  280. break;
  281. ch = readb(&channel->data);
  282. ZSDELAY();
  283. ch &= up->parity_mask;
  284. if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
  285. sunzilog_kbdms_receive_chars(up, ch, 0);
  286. continue;
  287. }
  288. if (tty == NULL) {
  289. uart_handle_sysrq_char(&up->port, ch);
  290. continue;
  291. }
  292. /* A real serial line, record the character and status. */
  293. flag = TTY_NORMAL;
  294. up->port.icount.rx++;
  295. if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
  296. if (r1 & BRK_ABRT) {
  297. r1 &= ~(PAR_ERR | CRC_ERR);
  298. up->port.icount.brk++;
  299. if (uart_handle_break(&up->port))
  300. continue;
  301. }
  302. else if (r1 & PAR_ERR)
  303. up->port.icount.parity++;
  304. else if (r1 & CRC_ERR)
  305. up->port.icount.frame++;
  306. if (r1 & Rx_OVR)
  307. up->port.icount.overrun++;
  308. r1 &= up->port.read_status_mask;
  309. if (r1 & BRK_ABRT)
  310. flag = TTY_BREAK;
  311. else if (r1 & PAR_ERR)
  312. flag = TTY_PARITY;
  313. else if (r1 & CRC_ERR)
  314. flag = TTY_FRAME;
  315. }
  316. if (uart_handle_sysrq_char(&up->port, ch))
  317. continue;
  318. if (up->port.ignore_status_mask == 0xff ||
  319. (r1 & up->port.ignore_status_mask) == 0) {
  320. tty_insert_flip_char(tty, ch, flag);
  321. }
  322. if (r1 & Rx_OVR)
  323. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  324. }
  325. return tty;
  326. }
  327. static void sunzilog_status_handle(struct uart_sunzilog_port *up,
  328. struct zilog_channel __iomem *channel)
  329. {
  330. unsigned char status;
  331. status = readb(&channel->control);
  332. ZSDELAY();
  333. writeb(RES_EXT_INT, &channel->control);
  334. ZSDELAY();
  335. ZS_WSYNC(channel);
  336. if (status & BRK_ABRT) {
  337. if (ZS_IS_MOUSE(up))
  338. sunzilog_kbdms_receive_chars(up, 0, 1);
  339. if (ZS_IS_CONS(up)) {
  340. /* Wait for BREAK to deassert to avoid potentially
  341. * confusing the PROM.
  342. */
  343. while (1) {
  344. status = readb(&channel->control);
  345. ZSDELAY();
  346. if (!(status & BRK_ABRT))
  347. break;
  348. }
  349. sun_do_break();
  350. return;
  351. }
  352. }
  353. if (ZS_WANTS_MODEM_STATUS(up)) {
  354. if (status & SYNC)
  355. up->port.icount.dsr++;
  356. /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
  357. * But it does not tell us which bit has changed, we have to keep
  358. * track of this ourselves.
  359. */
  360. if ((status ^ up->prev_status) ^ DCD)
  361. uart_handle_dcd_change(&up->port,
  362. (status & DCD));
  363. if ((status ^ up->prev_status) ^ CTS)
  364. uart_handle_cts_change(&up->port,
  365. (status & CTS));
  366. wake_up_interruptible(&up->port.info->delta_msr_wait);
  367. }
  368. up->prev_status = status;
  369. }
  370. static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
  371. struct zilog_channel __iomem *channel)
  372. {
  373. struct circ_buf *xmit;
  374. if (ZS_IS_CONS(up)) {
  375. unsigned char status = readb(&channel->control);
  376. ZSDELAY();
  377. /* TX still busy? Just wait for the next TX done interrupt.
  378. *
  379. * It can occur because of how we do serial console writes. It would
  380. * be nice to transmit console writes just like we normally would for
  381. * a TTY line. (ie. buffered and TX interrupt driven). That is not
  382. * easy because console writes cannot sleep. One solution might be
  383. * to poll on enough port->xmit space becomming free. -DaveM
  384. */
  385. if (!(status & Tx_BUF_EMP))
  386. return;
  387. }
  388. up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
  389. if (ZS_REGS_HELD(up)) {
  390. __load_zsregs(channel, up->curregs);
  391. up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
  392. }
  393. if (ZS_TX_STOPPED(up)) {
  394. up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
  395. goto ack_tx_int;
  396. }
  397. if (up->port.x_char) {
  398. up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
  399. writeb(up->port.x_char, &channel->data);
  400. ZSDELAY();
  401. ZS_WSYNC(channel);
  402. up->port.icount.tx++;
  403. up->port.x_char = 0;
  404. return;
  405. }
  406. if (up->port.info == NULL)
  407. goto ack_tx_int;
  408. xmit = &up->port.info->xmit;
  409. if (uart_circ_empty(xmit))
  410. goto ack_tx_int;
  411. if (uart_tx_stopped(&up->port))
  412. goto ack_tx_int;
  413. up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
  414. writeb(xmit->buf[xmit->tail], &channel->data);
  415. ZSDELAY();
  416. ZS_WSYNC(channel);
  417. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  418. up->port.icount.tx++;
  419. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  420. uart_write_wakeup(&up->port);
  421. return;
  422. ack_tx_int:
  423. writeb(RES_Tx_P, &channel->control);
  424. ZSDELAY();
  425. ZS_WSYNC(channel);
  426. }
  427. static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
  428. {
  429. struct uart_sunzilog_port *up = dev_id;
  430. while (up) {
  431. struct zilog_channel __iomem *channel
  432. = ZILOG_CHANNEL_FROM_PORT(&up->port);
  433. struct tty_struct *tty;
  434. unsigned char r3;
  435. spin_lock(&up->port.lock);
  436. r3 = read_zsreg(channel, R3);
  437. /* Channel A */
  438. tty = NULL;
  439. if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
  440. writeb(RES_H_IUS, &channel->control);
  441. ZSDELAY();
  442. ZS_WSYNC(channel);
  443. if (r3 & CHARxIP)
  444. tty = sunzilog_receive_chars(up, channel);
  445. if (r3 & CHAEXT)
  446. sunzilog_status_handle(up, channel);
  447. if (r3 & CHATxIP)
  448. sunzilog_transmit_chars(up, channel);
  449. }
  450. spin_unlock(&up->port.lock);
  451. if (tty)
  452. tty_flip_buffer_push(tty);
  453. /* Channel B */
  454. up = up->next;
  455. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  456. spin_lock(&up->port.lock);
  457. tty = NULL;
  458. if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
  459. writeb(RES_H_IUS, &channel->control);
  460. ZSDELAY();
  461. ZS_WSYNC(channel);
  462. if (r3 & CHBRxIP)
  463. tty = sunzilog_receive_chars(up, channel);
  464. if (r3 & CHBEXT)
  465. sunzilog_status_handle(up, channel);
  466. if (r3 & CHBTxIP)
  467. sunzilog_transmit_chars(up, channel);
  468. }
  469. spin_unlock(&up->port.lock);
  470. if (tty)
  471. tty_flip_buffer_push(tty);
  472. up = up->next;
  473. }
  474. return IRQ_HANDLED;
  475. }
  476. /* A convenient way to quickly get R0 status. The caller must _not_ hold the
  477. * port lock, it is acquired here.
  478. */
  479. static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
  480. {
  481. struct zilog_channel __iomem *channel;
  482. unsigned char status;
  483. channel = ZILOG_CHANNEL_FROM_PORT(port);
  484. status = readb(&channel->control);
  485. ZSDELAY();
  486. return status;
  487. }
  488. /* The port lock is not held. */
  489. static unsigned int sunzilog_tx_empty(struct uart_port *port)
  490. {
  491. unsigned long flags;
  492. unsigned char status;
  493. unsigned int ret;
  494. spin_lock_irqsave(&port->lock, flags);
  495. status = sunzilog_read_channel_status(port);
  496. spin_unlock_irqrestore(&port->lock, flags);
  497. if (status & Tx_BUF_EMP)
  498. ret = TIOCSER_TEMT;
  499. else
  500. ret = 0;
  501. return ret;
  502. }
  503. /* The port lock is held and interrupts are disabled. */
  504. static unsigned int sunzilog_get_mctrl(struct uart_port *port)
  505. {
  506. unsigned char status;
  507. unsigned int ret;
  508. status = sunzilog_read_channel_status(port);
  509. ret = 0;
  510. if (status & DCD)
  511. ret |= TIOCM_CAR;
  512. if (status & SYNC)
  513. ret |= TIOCM_DSR;
  514. if (status & CTS)
  515. ret |= TIOCM_CTS;
  516. return ret;
  517. }
  518. /* The port lock is held and interrupts are disabled. */
  519. static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
  520. {
  521. struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
  522. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  523. unsigned char set_bits, clear_bits;
  524. set_bits = clear_bits = 0;
  525. if (mctrl & TIOCM_RTS)
  526. set_bits |= RTS;
  527. else
  528. clear_bits |= RTS;
  529. if (mctrl & TIOCM_DTR)
  530. set_bits |= DTR;
  531. else
  532. clear_bits |= DTR;
  533. /* NOTE: Not subject to 'transmitter active' rule. */
  534. up->curregs[R5] |= set_bits;
  535. up->curregs[R5] &= ~clear_bits;
  536. write_zsreg(channel, R5, up->curregs[R5]);
  537. }
  538. /* The port lock is held and interrupts are disabled. */
  539. static void sunzilog_stop_tx(struct uart_port *port)
  540. {
  541. struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
  542. up->flags |= SUNZILOG_FLAG_TX_STOPPED;
  543. }
  544. /* The port lock is held and interrupts are disabled. */
  545. static void sunzilog_start_tx(struct uart_port *port)
  546. {
  547. struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
  548. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  549. unsigned char status;
  550. up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
  551. up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
  552. status = readb(&channel->control);
  553. ZSDELAY();
  554. /* TX busy? Just wait for the TX done interrupt. */
  555. if (!(status & Tx_BUF_EMP))
  556. return;
  557. /* Send the first character to jump-start the TX done
  558. * IRQ sending engine.
  559. */
  560. if (port->x_char) {
  561. writeb(port->x_char, &channel->data);
  562. ZSDELAY();
  563. ZS_WSYNC(channel);
  564. port->icount.tx++;
  565. port->x_char = 0;
  566. } else {
  567. struct circ_buf *xmit = &port->info->xmit;
  568. writeb(xmit->buf[xmit->tail], &channel->data);
  569. ZSDELAY();
  570. ZS_WSYNC(channel);
  571. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  572. port->icount.tx++;
  573. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  574. uart_write_wakeup(&up->port);
  575. }
  576. }
  577. /* The port lock is held. */
  578. static void sunzilog_stop_rx(struct uart_port *port)
  579. {
  580. struct uart_sunzilog_port *up = UART_ZILOG(port);
  581. struct zilog_channel __iomem *channel;
  582. if (ZS_IS_CONS(up))
  583. return;
  584. channel = ZILOG_CHANNEL_FROM_PORT(port);
  585. /* Disable all RX interrupts. */
  586. up->curregs[R1] &= ~RxINT_MASK;
  587. sunzilog_maybe_update_regs(up, channel);
  588. }
  589. /* The port lock is held. */
  590. static void sunzilog_enable_ms(struct uart_port *port)
  591. {
  592. struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
  593. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  594. unsigned char new_reg;
  595. new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
  596. if (new_reg != up->curregs[R15]) {
  597. up->curregs[R15] = new_reg;
  598. /* NOTE: Not subject to 'transmitter active' rule. */
  599. write_zsreg(channel, R15, up->curregs[R15]);
  600. }
  601. }
  602. /* The port lock is not held. */
  603. static void sunzilog_break_ctl(struct uart_port *port, int break_state)
  604. {
  605. struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
  606. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  607. unsigned char set_bits, clear_bits, new_reg;
  608. unsigned long flags;
  609. set_bits = clear_bits = 0;
  610. if (break_state)
  611. set_bits |= SND_BRK;
  612. else
  613. clear_bits |= SND_BRK;
  614. spin_lock_irqsave(&port->lock, flags);
  615. new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
  616. if (new_reg != up->curregs[R5]) {
  617. up->curregs[R5] = new_reg;
  618. /* NOTE: Not subject to 'transmitter active' rule. */
  619. write_zsreg(channel, R5, up->curregs[R5]);
  620. }
  621. spin_unlock_irqrestore(&port->lock, flags);
  622. }
  623. static void __sunzilog_startup(struct uart_sunzilog_port *up)
  624. {
  625. struct zilog_channel __iomem *channel;
  626. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  627. up->prev_status = readb(&channel->control);
  628. /* Enable receiver and transmitter. */
  629. up->curregs[R3] |= RxENAB;
  630. up->curregs[R5] |= TxENAB;
  631. up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
  632. sunzilog_maybe_update_regs(up, channel);
  633. }
  634. static int sunzilog_startup(struct uart_port *port)
  635. {
  636. struct uart_sunzilog_port *up = UART_ZILOG(port);
  637. unsigned long flags;
  638. if (ZS_IS_CONS(up))
  639. return 0;
  640. spin_lock_irqsave(&port->lock, flags);
  641. __sunzilog_startup(up);
  642. spin_unlock_irqrestore(&port->lock, flags);
  643. return 0;
  644. }
  645. /*
  646. * The test for ZS_IS_CONS is explained by the following e-mail:
  647. *****
  648. * From: Russell King <rmk@arm.linux.org.uk>
  649. * Date: Sun, 8 Dec 2002 10:18:38 +0000
  650. *
  651. * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
  652. * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
  653. * > and I noticed that something is not right with reference
  654. * > counting in this case. It seems that when the console
  655. * > is open by kernel initially, this is not accounted
  656. * > as an open, and uart_startup is not called.
  657. *
  658. * That is correct. We are unable to call uart_startup when the serial
  659. * console is initialised because it may need to allocate memory (as
  660. * request_irq does) and the memory allocators may not have been
  661. * initialised.
  662. *
  663. * 1. initialise the port into a state where it can send characters in the
  664. * console write method.
  665. *
  666. * 2. don't do the actual hardware shutdown in your shutdown() method (but
  667. * do the normal software shutdown - ie, free irqs etc)
  668. *****
  669. */
  670. static void sunzilog_shutdown(struct uart_port *port)
  671. {
  672. struct uart_sunzilog_port *up = UART_ZILOG(port);
  673. struct zilog_channel __iomem *channel;
  674. unsigned long flags;
  675. if (ZS_IS_CONS(up))
  676. return;
  677. spin_lock_irqsave(&port->lock, flags);
  678. channel = ZILOG_CHANNEL_FROM_PORT(port);
  679. /* Disable receiver and transmitter. */
  680. up->curregs[R3] &= ~RxENAB;
  681. up->curregs[R5] &= ~TxENAB;
  682. /* Disable all interrupts and BRK assertion. */
  683. up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
  684. up->curregs[R5] &= ~SND_BRK;
  685. sunzilog_maybe_update_regs(up, channel);
  686. spin_unlock_irqrestore(&port->lock, flags);
  687. }
  688. /* Shared by TTY driver and serial console setup. The port lock is held
  689. * and local interrupts are disabled.
  690. */
  691. static void
  692. sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
  693. unsigned int iflag, int brg)
  694. {
  695. up->curregs[R10] = NRZ;
  696. up->curregs[R11] = TCBR | RCBR;
  697. /* Program BAUD and clock source. */
  698. up->curregs[R4] &= ~XCLK_MASK;
  699. up->curregs[R4] |= X16CLK;
  700. up->curregs[R12] = brg & 0xff;
  701. up->curregs[R13] = (brg >> 8) & 0xff;
  702. up->curregs[R14] = BRSRC | BRENAB;
  703. /* Character size, stop bits, and parity. */
  704. up->curregs[3] &= ~RxN_MASK;
  705. up->curregs[5] &= ~TxN_MASK;
  706. switch (cflag & CSIZE) {
  707. case CS5:
  708. up->curregs[3] |= Rx5;
  709. up->curregs[5] |= Tx5;
  710. up->parity_mask = 0x1f;
  711. break;
  712. case CS6:
  713. up->curregs[3] |= Rx6;
  714. up->curregs[5] |= Tx6;
  715. up->parity_mask = 0x3f;
  716. break;
  717. case CS7:
  718. up->curregs[3] |= Rx7;
  719. up->curregs[5] |= Tx7;
  720. up->parity_mask = 0x7f;
  721. break;
  722. case CS8:
  723. default:
  724. up->curregs[3] |= Rx8;
  725. up->curregs[5] |= Tx8;
  726. up->parity_mask = 0xff;
  727. break;
  728. };
  729. up->curregs[4] &= ~0x0c;
  730. if (cflag & CSTOPB)
  731. up->curregs[4] |= SB2;
  732. else
  733. up->curregs[4] |= SB1;
  734. if (cflag & PARENB)
  735. up->curregs[4] |= PAR_ENAB;
  736. else
  737. up->curregs[4] &= ~PAR_ENAB;
  738. if (!(cflag & PARODD))
  739. up->curregs[4] |= PAR_EVEN;
  740. else
  741. up->curregs[4] &= ~PAR_EVEN;
  742. up->port.read_status_mask = Rx_OVR;
  743. if (iflag & INPCK)
  744. up->port.read_status_mask |= CRC_ERR | PAR_ERR;
  745. if (iflag & (BRKINT | PARMRK))
  746. up->port.read_status_mask |= BRK_ABRT;
  747. up->port.ignore_status_mask = 0;
  748. if (iflag & IGNPAR)
  749. up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
  750. if (iflag & IGNBRK) {
  751. up->port.ignore_status_mask |= BRK_ABRT;
  752. if (iflag & IGNPAR)
  753. up->port.ignore_status_mask |= Rx_OVR;
  754. }
  755. if ((cflag & CREAD) == 0)
  756. up->port.ignore_status_mask = 0xff;
  757. }
  758. /* The port lock is not held. */
  759. static void
  760. sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
  761. struct ktermios *old)
  762. {
  763. struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
  764. unsigned long flags;
  765. int baud, brg;
  766. baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
  767. spin_lock_irqsave(&up->port.lock, flags);
  768. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  769. sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
  770. if (UART_ENABLE_MS(&up->port, termios->c_cflag))
  771. up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
  772. else
  773. up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
  774. up->cflag = termios->c_cflag;
  775. sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
  776. uart_update_timeout(port, termios->c_cflag, baud);
  777. spin_unlock_irqrestore(&up->port.lock, flags);
  778. }
  779. static const char *sunzilog_type(struct uart_port *port)
  780. {
  781. return "zs";
  782. }
  783. /* We do not request/release mappings of the registers here, this
  784. * happens at early serial probe time.
  785. */
  786. static void sunzilog_release_port(struct uart_port *port)
  787. {
  788. }
  789. static int sunzilog_request_port(struct uart_port *port)
  790. {
  791. return 0;
  792. }
  793. /* These do not need to do anything interesting either. */
  794. static void sunzilog_config_port(struct uart_port *port, int flags)
  795. {
  796. }
  797. /* We do not support letting the user mess with the divisor, IRQ, etc. */
  798. static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
  799. {
  800. return -EINVAL;
  801. }
  802. static struct uart_ops sunzilog_pops = {
  803. .tx_empty = sunzilog_tx_empty,
  804. .set_mctrl = sunzilog_set_mctrl,
  805. .get_mctrl = sunzilog_get_mctrl,
  806. .stop_tx = sunzilog_stop_tx,
  807. .start_tx = sunzilog_start_tx,
  808. .stop_rx = sunzilog_stop_rx,
  809. .enable_ms = sunzilog_enable_ms,
  810. .break_ctl = sunzilog_break_ctl,
  811. .startup = sunzilog_startup,
  812. .shutdown = sunzilog_shutdown,
  813. .set_termios = sunzilog_set_termios,
  814. .type = sunzilog_type,
  815. .release_port = sunzilog_release_port,
  816. .request_port = sunzilog_request_port,
  817. .config_port = sunzilog_config_port,
  818. .verify_port = sunzilog_verify_port,
  819. };
  820. static struct uart_sunzilog_port *sunzilog_port_table;
  821. static struct zilog_layout __iomem **sunzilog_chip_regs;
  822. static struct uart_sunzilog_port *sunzilog_irq_chain;
  823. static struct uart_driver sunzilog_reg = {
  824. .owner = THIS_MODULE,
  825. .driver_name = "ttyS",
  826. .dev_name = "ttyS",
  827. .major = TTY_MAJOR,
  828. };
  829. static int __init sunzilog_alloc_tables(void)
  830. {
  831. struct uart_sunzilog_port *up;
  832. unsigned long size;
  833. int i;
  834. size = NUM_CHANNELS * sizeof(struct uart_sunzilog_port);
  835. sunzilog_port_table = kzalloc(size, GFP_KERNEL);
  836. if (!sunzilog_port_table)
  837. return -ENOMEM;
  838. for (i = 0; i < NUM_CHANNELS; i++) {
  839. up = &sunzilog_port_table[i];
  840. spin_lock_init(&up->port.lock);
  841. if (i == 0)
  842. sunzilog_irq_chain = up;
  843. if (i < NUM_CHANNELS - 1)
  844. up->next = up + 1;
  845. else
  846. up->next = NULL;
  847. }
  848. size = NUM_SUNZILOG * sizeof(struct zilog_layout __iomem *);
  849. sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
  850. if (!sunzilog_chip_regs) {
  851. kfree(sunzilog_port_table);
  852. sunzilog_irq_chain = NULL;
  853. return -ENOMEM;
  854. }
  855. return 0;
  856. }
  857. static void sunzilog_free_tables(void)
  858. {
  859. kfree(sunzilog_port_table);
  860. sunzilog_irq_chain = NULL;
  861. kfree(sunzilog_chip_regs);
  862. }
  863. #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
  864. static void sunzilog_putchar(struct uart_port *port, int ch)
  865. {
  866. struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
  867. int loops = ZS_PUT_CHAR_MAX_DELAY;
  868. /* This is a timed polling loop so do not switch the explicit
  869. * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
  870. */
  871. do {
  872. unsigned char val = readb(&channel->control);
  873. if (val & Tx_BUF_EMP) {
  874. ZSDELAY();
  875. break;
  876. }
  877. udelay(5);
  878. } while (--loops);
  879. writeb(ch, &channel->data);
  880. ZSDELAY();
  881. ZS_WSYNC(channel);
  882. }
  883. #ifdef CONFIG_SERIO
  884. static DEFINE_SPINLOCK(sunzilog_serio_lock);
  885. static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
  886. {
  887. struct uart_sunzilog_port *up = serio->port_data;
  888. unsigned long flags;
  889. spin_lock_irqsave(&sunzilog_serio_lock, flags);
  890. sunzilog_putchar(&up->port, ch);
  891. spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
  892. return 0;
  893. }
  894. static int sunzilog_serio_open(struct serio *serio)
  895. {
  896. struct uart_sunzilog_port *up = serio->port_data;
  897. unsigned long flags;
  898. int ret;
  899. spin_lock_irqsave(&sunzilog_serio_lock, flags);
  900. if (!up->serio_open) {
  901. up->serio_open = 1;
  902. ret = 0;
  903. } else
  904. ret = -EBUSY;
  905. spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
  906. return ret;
  907. }
  908. static void sunzilog_serio_close(struct serio *serio)
  909. {
  910. struct uart_sunzilog_port *up = serio->port_data;
  911. unsigned long flags;
  912. spin_lock_irqsave(&sunzilog_serio_lock, flags);
  913. up->serio_open = 0;
  914. spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
  915. }
  916. #endif /* CONFIG_SERIO */
  917. #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
  918. static void
  919. sunzilog_console_write(struct console *con, const char *s, unsigned int count)
  920. {
  921. struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
  922. unsigned long flags;
  923. spin_lock_irqsave(&up->port.lock, flags);
  924. uart_console_write(&up->port, s, count, sunzilog_putchar);
  925. udelay(2);
  926. spin_unlock_irqrestore(&up->port.lock, flags);
  927. }
  928. static int __init sunzilog_console_setup(struct console *con, char *options)
  929. {
  930. struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
  931. unsigned long flags;
  932. int baud, brg;
  933. if (up->port.type != PORT_SUNZILOG)
  934. return -1;
  935. printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
  936. (sunzilog_reg.minor - 64) + con->index, con->index);
  937. /* Get firmware console settings. */
  938. sunserial_console_termios(con);
  939. /* Firmware console speed is limited to 150-->38400 baud so
  940. * this hackish cflag thing is OK.
  941. */
  942. switch (con->cflag & CBAUD) {
  943. case B150: baud = 150; break;
  944. case B300: baud = 300; break;
  945. case B600: baud = 600; break;
  946. case B1200: baud = 1200; break;
  947. case B2400: baud = 2400; break;
  948. case B4800: baud = 4800; break;
  949. default: case B9600: baud = 9600; break;
  950. case B19200: baud = 19200; break;
  951. case B38400: baud = 38400; break;
  952. };
  953. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  954. spin_lock_irqsave(&up->port.lock, flags);
  955. up->curregs[R15] = BRKIE;
  956. sunzilog_convert_to_zs(up, con->cflag, 0, brg);
  957. sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
  958. __sunzilog_startup(up);
  959. spin_unlock_irqrestore(&up->port.lock, flags);
  960. return 0;
  961. }
  962. static struct console sunzilog_console_ops = {
  963. .name = "ttyS",
  964. .write = sunzilog_console_write,
  965. .device = uart_console_device,
  966. .setup = sunzilog_console_setup,
  967. .flags = CON_PRINTBUFFER,
  968. .index = -1,
  969. .data = &sunzilog_reg,
  970. };
  971. static inline struct console *SUNZILOG_CONSOLE(void)
  972. {
  973. int i;
  974. if (con_is_present())
  975. return NULL;
  976. for (i = 0; i < NUM_CHANNELS; i++) {
  977. int this_minor = sunzilog_reg.minor + i;
  978. if ((this_minor - 64) == (serial_console - 1))
  979. break;
  980. }
  981. if (i == NUM_CHANNELS)
  982. return NULL;
  983. sunzilog_console_ops.index = i;
  984. sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
  985. return &sunzilog_console_ops;
  986. }
  987. #else
  988. #define SUNZILOG_CONSOLE() (NULL)
  989. #endif
  990. static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
  991. {
  992. int baud, brg;
  993. if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
  994. up->cflag = B1200 | CS8 | CLOCAL | CREAD;
  995. baud = 1200;
  996. } else {
  997. up->cflag = B4800 | CS8 | CLOCAL | CREAD;
  998. baud = 4800;
  999. }
  1000. up->curregs[R15] = BRKIE;
  1001. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  1002. sunzilog_convert_to_zs(up, up->cflag, 0, brg);
  1003. sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
  1004. __sunzilog_startup(up);
  1005. }
  1006. #ifdef CONFIG_SERIO
  1007. static void __init sunzilog_register_serio(struct uart_sunzilog_port *up)
  1008. {
  1009. struct serio *serio = &up->serio;
  1010. serio->port_data = up;
  1011. serio->id.type = SERIO_RS232;
  1012. if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
  1013. serio->id.proto = SERIO_SUNKBD;
  1014. strlcpy(serio->name, "zskbd", sizeof(serio->name));
  1015. } else {
  1016. serio->id.proto = SERIO_SUN;
  1017. serio->id.extra = 1;
  1018. strlcpy(serio->name, "zsms", sizeof(serio->name));
  1019. }
  1020. strlcpy(serio->phys,
  1021. ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
  1022. "zs/serio0" : "zs/serio1"),
  1023. sizeof(serio->phys));
  1024. serio->write = sunzilog_serio_write;
  1025. serio->open = sunzilog_serio_open;
  1026. serio->close = sunzilog_serio_close;
  1027. serio->dev.parent = up->port.dev;
  1028. serio_register_port(serio);
  1029. }
  1030. #endif
  1031. static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
  1032. {
  1033. struct zilog_channel __iomem *channel;
  1034. unsigned long flags;
  1035. int baud, brg;
  1036. channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
  1037. spin_lock_irqsave(&up->port.lock, flags);
  1038. if (ZS_IS_CHANNEL_A(up)) {
  1039. write_zsreg(channel, R9, FHWRES);
  1040. ZSDELAY_LONG();
  1041. (void) read_zsreg(channel, R0);
  1042. }
  1043. if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
  1044. SUNZILOG_FLAG_CONS_MOUSE)) {
  1045. sunzilog_init_kbdms(up, up->port.line);
  1046. up->curregs[R9] |= (NV | MIE);
  1047. write_zsreg(channel, R9, up->curregs[R9]);
  1048. } else {
  1049. /* Normal serial TTY. */
  1050. up->parity_mask = 0xff;
  1051. up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
  1052. up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
  1053. up->curregs[R3] = RxENAB | Rx8;
  1054. up->curregs[R5] = TxENAB | Tx8;
  1055. up->curregs[R9] = NV | MIE;
  1056. up->curregs[R10] = NRZ;
  1057. up->curregs[R11] = TCBR | RCBR;
  1058. baud = 9600;
  1059. brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
  1060. up->curregs[R12] = (brg & 0xff);
  1061. up->curregs[R13] = (brg >> 8) & 0xff;
  1062. up->curregs[R14] = BRSRC | BRENAB;
  1063. __load_zsregs(channel, up->curregs);
  1064. write_zsreg(channel, R9, up->curregs[R9]);
  1065. }
  1066. spin_unlock_irqrestore(&up->port.lock, flags);
  1067. #ifdef CONFIG_SERIO
  1068. if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
  1069. SUNZILOG_FLAG_CONS_MOUSE))
  1070. sunzilog_register_serio(up);
  1071. #endif
  1072. }
  1073. static int zilog_irq = -1;
  1074. static int __devinit zs_probe(struct of_device *op, const struct of_device_id *match)
  1075. {
  1076. static int inst;
  1077. struct uart_sunzilog_port *up;
  1078. struct zilog_layout __iomem *rp;
  1079. int keyboard_mouse;
  1080. int err;
  1081. keyboard_mouse = 0;
  1082. if (of_find_property(op->node, "keyboard", NULL))
  1083. keyboard_mouse = 1;
  1084. sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
  1085. sizeof(struct zilog_layout),
  1086. "zs");
  1087. if (!sunzilog_chip_regs[inst])
  1088. return -ENOMEM;
  1089. rp = sunzilog_chip_regs[inst];
  1090. if (zilog_irq == -1)
  1091. zilog_irq = op->irqs[0];
  1092. up = &sunzilog_port_table[inst * 2];
  1093. /* Channel A */
  1094. up[0].port.mapbase = op->resource[0].start + 0x00;
  1095. up[0].port.membase = (void __iomem *) &rp->channelA;
  1096. up[0].port.iotype = UPIO_MEM;
  1097. up[0].port.irq = op->irqs[0];
  1098. up[0].port.uartclk = ZS_CLOCK;
  1099. up[0].port.fifosize = 1;
  1100. up[0].port.ops = &sunzilog_pops;
  1101. up[0].port.type = PORT_SUNZILOG;
  1102. up[0].port.flags = 0;
  1103. up[0].port.line = (inst * 2) + 0;
  1104. up[0].port.dev = &op->dev;
  1105. up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
  1106. if (keyboard_mouse)
  1107. up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
  1108. sunzilog_init_hw(&up[0]);
  1109. /* Channel B */
  1110. up[1].port.mapbase = op->resource[0].start + 0x04;
  1111. up[1].port.membase = (void __iomem *) &rp->channelB;
  1112. up[1].port.iotype = UPIO_MEM;
  1113. up[1].port.irq = op->irqs[0];
  1114. up[1].port.uartclk = ZS_CLOCK;
  1115. up[1].port.fifosize = 1;
  1116. up[1].port.ops = &sunzilog_pops;
  1117. up[1].port.type = PORT_SUNZILOG;
  1118. up[1].port.flags = 0;
  1119. up[1].port.line = (inst * 2) + 1;
  1120. up[1].port.dev = &op->dev;
  1121. up[1].flags |= 0;
  1122. if (keyboard_mouse)
  1123. up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
  1124. sunzilog_init_hw(&up[1]);
  1125. if (!keyboard_mouse) {
  1126. err = uart_add_one_port(&sunzilog_reg, &up[0].port);
  1127. if (err) {
  1128. of_iounmap(&op->resource[0],
  1129. rp, sizeof(struct zilog_layout));
  1130. return err;
  1131. }
  1132. err = uart_add_one_port(&sunzilog_reg, &up[1].port);
  1133. if (err) {
  1134. uart_remove_one_port(&sunzilog_reg, &up[0].port);
  1135. of_iounmap(&op->resource[0],
  1136. rp, sizeof(struct zilog_layout));
  1137. return err;
  1138. }
  1139. } else {
  1140. printk(KERN_INFO "%s: Keyboard at MMIO %lx (irq = %d) "
  1141. "is a zs\n",
  1142. op->dev.bus_id, up[0].port.mapbase, op->irqs[0]);
  1143. printk(KERN_INFO "%s: Mouse at MMIO %lx (irq = %d) "
  1144. "is a zs\n",
  1145. op->dev.bus_id, up[1].port.mapbase, op->irqs[0]);
  1146. }
  1147. dev_set_drvdata(&op->dev, &up[0]);
  1148. inst++;
  1149. return 0;
  1150. }
  1151. static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
  1152. {
  1153. if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
  1154. #ifdef CONFIG_SERIO
  1155. serio_unregister_port(&up->serio);
  1156. #endif
  1157. } else
  1158. uart_remove_one_port(&sunzilog_reg, &up->port);
  1159. }
  1160. static int __devexit zs_remove(struct of_device *op)
  1161. {
  1162. struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
  1163. struct zilog_layout __iomem *regs;
  1164. zs_remove_one(&up[0]);
  1165. zs_remove_one(&up[1]);
  1166. regs = sunzilog_chip_regs[up[0].port.line / 2];
  1167. of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
  1168. dev_set_drvdata(&op->dev, NULL);
  1169. return 0;
  1170. }
  1171. static struct of_device_id zs_match[] = {
  1172. {
  1173. .name = "zs",
  1174. },
  1175. {},
  1176. };
  1177. MODULE_DEVICE_TABLE(of, zs_match);
  1178. static struct of_platform_driver zs_driver = {
  1179. .name = "zs",
  1180. .match_table = zs_match,
  1181. .probe = zs_probe,
  1182. .remove = __devexit_p(zs_remove),
  1183. };
  1184. static int __init sunzilog_init(void)
  1185. {
  1186. struct device_node *dp;
  1187. int err, uart_count;
  1188. int num_keybms;
  1189. NUM_SUNZILOG = 0;
  1190. num_keybms = 0;
  1191. for_each_node_by_name(dp, "zs") {
  1192. NUM_SUNZILOG++;
  1193. if (of_find_property(dp, "keyboard", NULL))
  1194. num_keybms++;
  1195. }
  1196. uart_count = 0;
  1197. if (NUM_SUNZILOG) {
  1198. int uart_count;
  1199. err = sunzilog_alloc_tables();
  1200. if (err)
  1201. goto out;
  1202. uart_count = (NUM_SUNZILOG * 2) - (2 * num_keybms);
  1203. sunzilog_reg.nr = uart_count;
  1204. sunzilog_reg.minor = sunserial_current_minor;
  1205. err = uart_register_driver(&sunzilog_reg);
  1206. if (err)
  1207. goto out_free_tables;
  1208. sunzilog_reg.tty_driver->name_base = sunzilog_reg.minor - 64;
  1209. sunzilog_reg.cons = SUNZILOG_CONSOLE();
  1210. sunserial_current_minor += uart_count;
  1211. }
  1212. err = of_register_driver(&zs_driver, &of_bus_type);
  1213. if (err)
  1214. goto out_unregister_uart;
  1215. if (zilog_irq != -1) {
  1216. err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
  1217. "zs", sunzilog_irq_chain);
  1218. if (err)
  1219. goto out_unregister_driver;
  1220. }
  1221. out:
  1222. return err;
  1223. out_unregister_driver:
  1224. of_unregister_driver(&zs_driver);
  1225. out_unregister_uart:
  1226. if (NUM_SUNZILOG) {
  1227. uart_unregister_driver(&sunzilog_reg);
  1228. sunzilog_reg.cons = NULL;
  1229. }
  1230. out_free_tables:
  1231. sunzilog_free_tables();
  1232. goto out;
  1233. }
  1234. static void __exit sunzilog_exit(void)
  1235. {
  1236. of_unregister_driver(&zs_driver);
  1237. if (zilog_irq != -1) {
  1238. free_irq(zilog_irq, sunzilog_irq_chain);
  1239. zilog_irq = -1;
  1240. }
  1241. if (NUM_SUNZILOG) {
  1242. uart_unregister_driver(&sunzilog_reg);
  1243. sunzilog_free_tables();
  1244. }
  1245. }
  1246. module_init(sunzilog_init);
  1247. module_exit(sunzilog_exit);
  1248. MODULE_AUTHOR("David S. Miller");
  1249. MODULE_DESCRIPTION("Sun Zilog serial port driver");
  1250. MODULE_VERSION("2.0");
  1251. MODULE_LICENSE("GPL");