mpsc.c 52 KB

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  1. /*
  2. * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
  3. * GT64260, MV64340, MV64360, GT96100, ... ).
  4. *
  5. * Author: Mark A. Greer <mgreer@mvista.com>
  6. *
  7. * Based on an old MPSC driver that was in the linuxppc tree. It appears to
  8. * have been created by Chris Zankel (formerly of MontaVista) but there
  9. * is no proper Copyright so I'm not sure. Apparently, parts were also
  10. * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
  11. * by Russell King.
  12. *
  13. * 2004 (c) MontaVista, Software, Inc. This file is licensed under
  14. * the terms of the GNU General Public License version 2. This program
  15. * is licensed "as is" without any warranty of any kind, whether express
  16. * or implied.
  17. */
  18. /*
  19. * The MPSC interface is much like a typical network controller's interface.
  20. * That is, you set up separate rings of descriptors for transmitting and
  21. * receiving data. There is also a pool of buffers with (one buffer per
  22. * descriptor) that incoming data are dma'd into or outgoing data are dma'd
  23. * out of.
  24. *
  25. * The MPSC requires two other controllers to be able to work. The Baud Rate
  26. * Generator (BRG) provides a clock at programmable frequencies which determines
  27. * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
  28. * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
  29. * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
  30. * transmit and receive "engines" going (i.e., indicate data has been
  31. * transmitted or received).
  32. *
  33. * NOTES:
  34. *
  35. * 1) Some chips have an erratum where several regs cannot be
  36. * read. To work around that, we keep a local copy of those regs in
  37. * 'mpsc_port_info'.
  38. *
  39. * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
  40. * accesses system mem with coherency enabled. For that reason, the driver
  41. * assumes that coherency for that ctlr has been disabled. This means
  42. * that when in a cache coherent system, the driver has to manually manage
  43. * the data cache on the areas that it touches because the dma_* macro are
  44. * basically no-ops.
  45. *
  46. * 3) There is an erratum (on PPC) where you can't use the instruction to do
  47. * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
  48. * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
  49. *
  50. * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
  51. */
  52. #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  53. #define SUPPORT_SYSRQ
  54. #endif
  55. #include <linux/module.h>
  56. #include <linux/moduleparam.h>
  57. #include <linux/tty.h>
  58. #include <linux/tty_flip.h>
  59. #include <linux/ioport.h>
  60. #include <linux/init.h>
  61. #include <linux/console.h>
  62. #include <linux/sysrq.h>
  63. #include <linux/serial.h>
  64. #include <linux/serial_core.h>
  65. #include <linux/delay.h>
  66. #include <linux/device.h>
  67. #include <linux/dma-mapping.h>
  68. #include <linux/mv643xx.h>
  69. #include <linux/platform_device.h>
  70. #include <asm/io.h>
  71. #include <asm/irq.h>
  72. #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  73. #define SUPPORT_SYSRQ
  74. #endif
  75. #define MPSC_NUM_CTLRS 2
  76. /*
  77. * Descriptors and buffers must be cache line aligned.
  78. * Buffers lengths must be multiple of cache line size.
  79. * Number of Tx & Rx descriptors must be powers of 2.
  80. */
  81. #define MPSC_RXR_ENTRIES 32
  82. #define MPSC_RXRE_SIZE dma_get_cache_alignment()
  83. #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
  84. #define MPSC_RXBE_SIZE dma_get_cache_alignment()
  85. #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
  86. #define MPSC_TXR_ENTRIES 32
  87. #define MPSC_TXRE_SIZE dma_get_cache_alignment()
  88. #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
  89. #define MPSC_TXBE_SIZE dma_get_cache_alignment()
  90. #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
  91. #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
  92. MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
  93. dma_get_cache_alignment() /* for alignment */)
  94. /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
  95. struct mpsc_rx_desc {
  96. u16 bufsize;
  97. u16 bytecnt;
  98. u32 cmdstat;
  99. u32 link;
  100. u32 buf_ptr;
  101. } __attribute((packed));
  102. struct mpsc_tx_desc {
  103. u16 bytecnt;
  104. u16 shadow;
  105. u32 cmdstat;
  106. u32 link;
  107. u32 buf_ptr;
  108. } __attribute((packed));
  109. /*
  110. * Some regs that have the erratum that you can't read them are are shared
  111. * between the two MPSC controllers. This struct contains those shared regs.
  112. */
  113. struct mpsc_shared_regs {
  114. phys_addr_t mpsc_routing_base_p;
  115. phys_addr_t sdma_intr_base_p;
  116. void __iomem *mpsc_routing_base;
  117. void __iomem *sdma_intr_base;
  118. u32 MPSC_MRR_m;
  119. u32 MPSC_RCRR_m;
  120. u32 MPSC_TCRR_m;
  121. u32 SDMA_INTR_CAUSE_m;
  122. u32 SDMA_INTR_MASK_m;
  123. };
  124. /* The main driver data structure */
  125. struct mpsc_port_info {
  126. struct uart_port port; /* Overlay uart_port structure */
  127. /* Internal driver state for this ctlr */
  128. u8 ready;
  129. u8 rcv_data;
  130. tcflag_t c_iflag; /* save termios->c_iflag */
  131. tcflag_t c_cflag; /* save termios->c_cflag */
  132. /* Info passed in from platform */
  133. u8 mirror_regs; /* Need to mirror regs? */
  134. u8 cache_mgmt; /* Need manual cache mgmt? */
  135. u8 brg_can_tune; /* BRG has baud tuning? */
  136. u32 brg_clk_src;
  137. u16 mpsc_max_idle;
  138. int default_baud;
  139. int default_bits;
  140. int default_parity;
  141. int default_flow;
  142. /* Physical addresses of various blocks of registers (from platform) */
  143. phys_addr_t mpsc_base_p;
  144. phys_addr_t sdma_base_p;
  145. phys_addr_t brg_base_p;
  146. /* Virtual addresses of various blocks of registers (from platform) */
  147. void __iomem *mpsc_base;
  148. void __iomem *sdma_base;
  149. void __iomem *brg_base;
  150. /* Descriptor ring and buffer allocations */
  151. void *dma_region;
  152. dma_addr_t dma_region_p;
  153. dma_addr_t rxr; /* Rx descriptor ring */
  154. dma_addr_t rxr_p; /* Phys addr of rxr */
  155. u8 *rxb; /* Rx Ring I/O buf */
  156. u8 *rxb_p; /* Phys addr of rxb */
  157. u32 rxr_posn; /* First desc w/ Rx data */
  158. dma_addr_t txr; /* Tx descriptor ring */
  159. dma_addr_t txr_p; /* Phys addr of txr */
  160. u8 *txb; /* Tx Ring I/O buf */
  161. u8 *txb_p; /* Phys addr of txb */
  162. int txr_head; /* Where new data goes */
  163. int txr_tail; /* Where sent data comes off */
  164. /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
  165. u32 MPSC_MPCR_m;
  166. u32 MPSC_CHR_1_m;
  167. u32 MPSC_CHR_2_m;
  168. u32 MPSC_CHR_10_m;
  169. u32 BRG_BCR_m;
  170. struct mpsc_shared_regs *shared_regs;
  171. };
  172. /* Hooks to platform-specific code */
  173. int mpsc_platform_register_driver(void);
  174. void mpsc_platform_unregister_driver(void);
  175. /* Hooks back in to mpsc common to be called by platform-specific code */
  176. struct mpsc_port_info *mpsc_device_probe(int index);
  177. struct mpsc_port_info *mpsc_device_remove(int index);
  178. /* Main MPSC Configuration Register Offsets */
  179. #define MPSC_MMCRL 0x0000
  180. #define MPSC_MMCRH 0x0004
  181. #define MPSC_MPCR 0x0008
  182. #define MPSC_CHR_1 0x000c
  183. #define MPSC_CHR_2 0x0010
  184. #define MPSC_CHR_3 0x0014
  185. #define MPSC_CHR_4 0x0018
  186. #define MPSC_CHR_5 0x001c
  187. #define MPSC_CHR_6 0x0020
  188. #define MPSC_CHR_7 0x0024
  189. #define MPSC_CHR_8 0x0028
  190. #define MPSC_CHR_9 0x002c
  191. #define MPSC_CHR_10 0x0030
  192. #define MPSC_CHR_11 0x0034
  193. #define MPSC_MPCR_FRZ (1 << 9)
  194. #define MPSC_MPCR_CL_5 0
  195. #define MPSC_MPCR_CL_6 1
  196. #define MPSC_MPCR_CL_7 2
  197. #define MPSC_MPCR_CL_8 3
  198. #define MPSC_MPCR_SBL_1 0
  199. #define MPSC_MPCR_SBL_2 1
  200. #define MPSC_CHR_2_TEV (1<<1)
  201. #define MPSC_CHR_2_TA (1<<7)
  202. #define MPSC_CHR_2_TTCS (1<<9)
  203. #define MPSC_CHR_2_REV (1<<17)
  204. #define MPSC_CHR_2_RA (1<<23)
  205. #define MPSC_CHR_2_CRD (1<<25)
  206. #define MPSC_CHR_2_EH (1<<31)
  207. #define MPSC_CHR_2_PAR_ODD 0
  208. #define MPSC_CHR_2_PAR_SPACE 1
  209. #define MPSC_CHR_2_PAR_EVEN 2
  210. #define MPSC_CHR_2_PAR_MARK 3
  211. /* MPSC Signal Routing */
  212. #define MPSC_MRR 0x0000
  213. #define MPSC_RCRR 0x0004
  214. #define MPSC_TCRR 0x0008
  215. /* Serial DMA Controller Interface Registers */
  216. #define SDMA_SDC 0x0000
  217. #define SDMA_SDCM 0x0008
  218. #define SDMA_RX_DESC 0x0800
  219. #define SDMA_RX_BUF_PTR 0x0808
  220. #define SDMA_SCRDP 0x0810
  221. #define SDMA_TX_DESC 0x0c00
  222. #define SDMA_SCTDP 0x0c10
  223. #define SDMA_SFTDP 0x0c14
  224. #define SDMA_DESC_CMDSTAT_PE (1<<0)
  225. #define SDMA_DESC_CMDSTAT_CDL (1<<1)
  226. #define SDMA_DESC_CMDSTAT_FR (1<<3)
  227. #define SDMA_DESC_CMDSTAT_OR (1<<6)
  228. #define SDMA_DESC_CMDSTAT_BR (1<<9)
  229. #define SDMA_DESC_CMDSTAT_MI (1<<10)
  230. #define SDMA_DESC_CMDSTAT_A (1<<11)
  231. #define SDMA_DESC_CMDSTAT_AM (1<<12)
  232. #define SDMA_DESC_CMDSTAT_CT (1<<13)
  233. #define SDMA_DESC_CMDSTAT_C (1<<14)
  234. #define SDMA_DESC_CMDSTAT_ES (1<<15)
  235. #define SDMA_DESC_CMDSTAT_L (1<<16)
  236. #define SDMA_DESC_CMDSTAT_F (1<<17)
  237. #define SDMA_DESC_CMDSTAT_P (1<<18)
  238. #define SDMA_DESC_CMDSTAT_EI (1<<23)
  239. #define SDMA_DESC_CMDSTAT_O (1<<31)
  240. #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
  241. SDMA_DESC_CMDSTAT_EI)
  242. #define SDMA_SDC_RFT (1<<0)
  243. #define SDMA_SDC_SFM (1<<1)
  244. #define SDMA_SDC_BLMR (1<<6)
  245. #define SDMA_SDC_BLMT (1<<7)
  246. #define SDMA_SDC_POVR (1<<8)
  247. #define SDMA_SDC_RIFB (1<<9)
  248. #define SDMA_SDCM_ERD (1<<7)
  249. #define SDMA_SDCM_AR (1<<15)
  250. #define SDMA_SDCM_STD (1<<16)
  251. #define SDMA_SDCM_TXD (1<<23)
  252. #define SDMA_SDCM_AT (1<<31)
  253. #define SDMA_0_CAUSE_RXBUF (1<<0)
  254. #define SDMA_0_CAUSE_RXERR (1<<1)
  255. #define SDMA_0_CAUSE_TXBUF (1<<2)
  256. #define SDMA_0_CAUSE_TXEND (1<<3)
  257. #define SDMA_1_CAUSE_RXBUF (1<<8)
  258. #define SDMA_1_CAUSE_RXERR (1<<9)
  259. #define SDMA_1_CAUSE_TXBUF (1<<10)
  260. #define SDMA_1_CAUSE_TXEND (1<<11)
  261. #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
  262. SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
  263. #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
  264. SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
  265. /* SDMA Interrupt registers */
  266. #define SDMA_INTR_CAUSE 0x0000
  267. #define SDMA_INTR_MASK 0x0080
  268. /* Baud Rate Generator Interface Registers */
  269. #define BRG_BCR 0x0000
  270. #define BRG_BTR 0x0004
  271. /*
  272. * Define how this driver is known to the outside (we've been assigned a
  273. * range on the "Low-density serial ports" major).
  274. */
  275. #define MPSC_MAJOR 204
  276. #define MPSC_MINOR_START 44
  277. #define MPSC_DRIVER_NAME "MPSC"
  278. #define MPSC_DEV_NAME "ttyMM"
  279. #define MPSC_VERSION "1.00"
  280. static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
  281. static struct mpsc_shared_regs mpsc_shared_regs;
  282. static struct uart_driver mpsc_reg;
  283. static void mpsc_start_rx(struct mpsc_port_info *pi);
  284. static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
  285. static void mpsc_release_port(struct uart_port *port);
  286. /*
  287. ******************************************************************************
  288. *
  289. * Baud Rate Generator Routines (BRG)
  290. *
  291. ******************************************************************************
  292. */
  293. static void
  294. mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
  295. {
  296. u32 v;
  297. v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
  298. v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
  299. if (pi->brg_can_tune)
  300. v &= ~(1 << 25);
  301. if (pi->mirror_regs)
  302. pi->BRG_BCR_m = v;
  303. writel(v, pi->brg_base + BRG_BCR);
  304. writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
  305. pi->brg_base + BRG_BTR);
  306. return;
  307. }
  308. static void
  309. mpsc_brg_enable(struct mpsc_port_info *pi)
  310. {
  311. u32 v;
  312. v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
  313. v |= (1 << 16);
  314. if (pi->mirror_regs)
  315. pi->BRG_BCR_m = v;
  316. writel(v, pi->brg_base + BRG_BCR);
  317. return;
  318. }
  319. static void
  320. mpsc_brg_disable(struct mpsc_port_info *pi)
  321. {
  322. u32 v;
  323. v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
  324. v &= ~(1 << 16);
  325. if (pi->mirror_regs)
  326. pi->BRG_BCR_m = v;
  327. writel(v, pi->brg_base + BRG_BCR);
  328. return;
  329. }
  330. static inline void
  331. mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
  332. {
  333. /*
  334. * To set the baud, we adjust the CDV field in the BRG_BCR reg.
  335. * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
  336. * However, the input clock is divided by 16 in the MPSC b/c of how
  337. * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
  338. * calculation by 16 to account for that. So the real calculation
  339. * that accounts for the way the mpsc is set up is:
  340. * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
  341. */
  342. u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
  343. u32 v;
  344. mpsc_brg_disable(pi);
  345. v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
  346. v = (v & 0xffff0000) | (cdv & 0xffff);
  347. if (pi->mirror_regs)
  348. pi->BRG_BCR_m = v;
  349. writel(v, pi->brg_base + BRG_BCR);
  350. mpsc_brg_enable(pi);
  351. return;
  352. }
  353. /*
  354. ******************************************************************************
  355. *
  356. * Serial DMA Routines (SDMA)
  357. *
  358. ******************************************************************************
  359. */
  360. static void
  361. mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
  362. {
  363. u32 v;
  364. pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
  365. pi->port.line, burst_size);
  366. burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
  367. if (burst_size < 2)
  368. v = 0x0; /* 1 64-bit word */
  369. else if (burst_size < 4)
  370. v = 0x1; /* 2 64-bit words */
  371. else if (burst_size < 8)
  372. v = 0x2; /* 4 64-bit words */
  373. else
  374. v = 0x3; /* 8 64-bit words */
  375. writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
  376. pi->sdma_base + SDMA_SDC);
  377. return;
  378. }
  379. static void
  380. mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
  381. {
  382. pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
  383. burst_size);
  384. writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
  385. pi->sdma_base + SDMA_SDC);
  386. mpsc_sdma_burstsize(pi, burst_size);
  387. return;
  388. }
  389. static inline u32
  390. mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
  391. {
  392. u32 old, v;
  393. pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
  394. old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
  395. readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
  396. mask &= 0xf;
  397. if (pi->port.line)
  398. mask <<= 8;
  399. v &= ~mask;
  400. if (pi->mirror_regs)
  401. pi->shared_regs->SDMA_INTR_MASK_m = v;
  402. writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
  403. if (pi->port.line)
  404. old >>= 8;
  405. return old & 0xf;
  406. }
  407. static inline void
  408. mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
  409. {
  410. u32 v;
  411. pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
  412. v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
  413. readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
  414. mask &= 0xf;
  415. if (pi->port.line)
  416. mask <<= 8;
  417. v |= mask;
  418. if (pi->mirror_regs)
  419. pi->shared_regs->SDMA_INTR_MASK_m = v;
  420. writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
  421. return;
  422. }
  423. static inline void
  424. mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
  425. {
  426. pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
  427. if (pi->mirror_regs)
  428. pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
  429. writel(0, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE);
  430. return;
  431. }
  432. static inline void
  433. mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p)
  434. {
  435. pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
  436. pi->port.line, (u32) rxre_p);
  437. writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
  438. return;
  439. }
  440. static inline void
  441. mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p)
  442. {
  443. writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
  444. writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
  445. return;
  446. }
  447. static inline void
  448. mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
  449. {
  450. u32 v;
  451. v = readl(pi->sdma_base + SDMA_SDCM);
  452. if (val)
  453. v |= val;
  454. else
  455. v = 0;
  456. wmb();
  457. writel(v, pi->sdma_base + SDMA_SDCM);
  458. wmb();
  459. return;
  460. }
  461. static inline uint
  462. mpsc_sdma_tx_active(struct mpsc_port_info *pi)
  463. {
  464. return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
  465. }
  466. static inline void
  467. mpsc_sdma_start_tx(struct mpsc_port_info *pi)
  468. {
  469. struct mpsc_tx_desc *txre, *txre_p;
  470. /* If tx isn't running & there's a desc ready to go, start it */
  471. if (!mpsc_sdma_tx_active(pi)) {
  472. txre = (struct mpsc_tx_desc *)(pi->txr +
  473. (pi->txr_tail * MPSC_TXRE_SIZE));
  474. dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
  475. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  476. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  477. invalidate_dcache_range((ulong)txre,
  478. (ulong)txre + MPSC_TXRE_SIZE);
  479. #endif
  480. if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
  481. txre_p = (struct mpsc_tx_desc *)(pi->txr_p +
  482. (pi->txr_tail *
  483. MPSC_TXRE_SIZE));
  484. mpsc_sdma_set_tx_ring(pi, txre_p);
  485. mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
  486. }
  487. }
  488. return;
  489. }
  490. static inline void
  491. mpsc_sdma_stop(struct mpsc_port_info *pi)
  492. {
  493. pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
  494. /* Abort any SDMA transfers */
  495. mpsc_sdma_cmd(pi, 0);
  496. mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
  497. /* Clear the SDMA current and first TX and RX pointers */
  498. mpsc_sdma_set_tx_ring(pi, NULL);
  499. mpsc_sdma_set_rx_ring(pi, NULL);
  500. /* Disable interrupts */
  501. mpsc_sdma_intr_mask(pi, 0xf);
  502. mpsc_sdma_intr_ack(pi);
  503. return;
  504. }
  505. /*
  506. ******************************************************************************
  507. *
  508. * Multi-Protocol Serial Controller Routines (MPSC)
  509. *
  510. ******************************************************************************
  511. */
  512. static void
  513. mpsc_hw_init(struct mpsc_port_info *pi)
  514. {
  515. u32 v;
  516. pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
  517. /* Set up clock routing */
  518. if (pi->mirror_regs) {
  519. v = pi->shared_regs->MPSC_MRR_m;
  520. v &= ~0x1c7;
  521. pi->shared_regs->MPSC_MRR_m = v;
  522. writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
  523. v = pi->shared_regs->MPSC_RCRR_m;
  524. v = (v & ~0xf0f) | 0x100;
  525. pi->shared_regs->MPSC_RCRR_m = v;
  526. writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
  527. v = pi->shared_regs->MPSC_TCRR_m;
  528. v = (v & ~0xf0f) | 0x100;
  529. pi->shared_regs->MPSC_TCRR_m = v;
  530. writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
  531. }
  532. else {
  533. v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
  534. v &= ~0x1c7;
  535. writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
  536. v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
  537. v = (v & ~0xf0f) | 0x100;
  538. writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
  539. v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
  540. v = (v & ~0xf0f) | 0x100;
  541. writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
  542. }
  543. /* Put MPSC in UART mode & enabel Tx/Rx egines */
  544. writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
  545. /* No preamble, 16x divider, low-latency, */
  546. writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
  547. if (pi->mirror_regs) {
  548. pi->MPSC_CHR_1_m = 0;
  549. pi->MPSC_CHR_2_m = 0;
  550. }
  551. writel(0, pi->mpsc_base + MPSC_CHR_1);
  552. writel(0, pi->mpsc_base + MPSC_CHR_2);
  553. writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
  554. writel(0, pi->mpsc_base + MPSC_CHR_4);
  555. writel(0, pi->mpsc_base + MPSC_CHR_5);
  556. writel(0, pi->mpsc_base + MPSC_CHR_6);
  557. writel(0, pi->mpsc_base + MPSC_CHR_7);
  558. writel(0, pi->mpsc_base + MPSC_CHR_8);
  559. writel(0, pi->mpsc_base + MPSC_CHR_9);
  560. writel(0, pi->mpsc_base + MPSC_CHR_10);
  561. return;
  562. }
  563. static inline void
  564. mpsc_enter_hunt(struct mpsc_port_info *pi)
  565. {
  566. pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
  567. if (pi->mirror_regs) {
  568. writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
  569. pi->mpsc_base + MPSC_CHR_2);
  570. /* Erratum prevents reading CHR_2 so just delay for a while */
  571. udelay(100);
  572. }
  573. else {
  574. writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
  575. pi->mpsc_base + MPSC_CHR_2);
  576. while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
  577. udelay(10);
  578. }
  579. return;
  580. }
  581. static inline void
  582. mpsc_freeze(struct mpsc_port_info *pi)
  583. {
  584. u32 v;
  585. pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
  586. v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
  587. readl(pi->mpsc_base + MPSC_MPCR);
  588. v |= MPSC_MPCR_FRZ;
  589. if (pi->mirror_regs)
  590. pi->MPSC_MPCR_m = v;
  591. writel(v, pi->mpsc_base + MPSC_MPCR);
  592. return;
  593. }
  594. static inline void
  595. mpsc_unfreeze(struct mpsc_port_info *pi)
  596. {
  597. u32 v;
  598. v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
  599. readl(pi->mpsc_base + MPSC_MPCR);
  600. v &= ~MPSC_MPCR_FRZ;
  601. if (pi->mirror_regs)
  602. pi->MPSC_MPCR_m = v;
  603. writel(v, pi->mpsc_base + MPSC_MPCR);
  604. pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
  605. return;
  606. }
  607. static inline void
  608. mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
  609. {
  610. u32 v;
  611. pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
  612. v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
  613. readl(pi->mpsc_base + MPSC_MPCR);
  614. v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
  615. if (pi->mirror_regs)
  616. pi->MPSC_MPCR_m = v;
  617. writel(v, pi->mpsc_base + MPSC_MPCR);
  618. return;
  619. }
  620. static inline void
  621. mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
  622. {
  623. u32 v;
  624. pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
  625. pi->port.line, len);
  626. v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
  627. readl(pi->mpsc_base + MPSC_MPCR);
  628. v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
  629. if (pi->mirror_regs)
  630. pi->MPSC_MPCR_m = v;
  631. writel(v, pi->mpsc_base + MPSC_MPCR);
  632. return;
  633. }
  634. static inline void
  635. mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
  636. {
  637. u32 v;
  638. pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
  639. v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
  640. readl(pi->mpsc_base + MPSC_CHR_2);
  641. p &= 0x3;
  642. v = (v & ~0xc000c) | (p << 18) | (p << 2);
  643. if (pi->mirror_regs)
  644. pi->MPSC_CHR_2_m = v;
  645. writel(v, pi->mpsc_base + MPSC_CHR_2);
  646. return;
  647. }
  648. /*
  649. ******************************************************************************
  650. *
  651. * Driver Init Routines
  652. *
  653. ******************************************************************************
  654. */
  655. static void
  656. mpsc_init_hw(struct mpsc_port_info *pi)
  657. {
  658. pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
  659. mpsc_brg_init(pi, pi->brg_clk_src);
  660. mpsc_brg_enable(pi);
  661. mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
  662. mpsc_sdma_stop(pi);
  663. mpsc_hw_init(pi);
  664. return;
  665. }
  666. static int
  667. mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
  668. {
  669. int rc = 0;
  670. pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
  671. pi->port.line);
  672. if (!pi->dma_region) {
  673. if (!dma_supported(pi->port.dev, 0xffffffff)) {
  674. printk(KERN_ERR "MPSC: Inadequate DMA support\n");
  675. rc = -ENXIO;
  676. }
  677. else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
  678. MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL))
  679. == NULL) {
  680. printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
  681. rc = -ENOMEM;
  682. }
  683. }
  684. return rc;
  685. }
  686. static void
  687. mpsc_free_ring_mem(struct mpsc_port_info *pi)
  688. {
  689. pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
  690. if (pi->dma_region) {
  691. dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
  692. pi->dma_region, pi->dma_region_p);
  693. pi->dma_region = NULL;
  694. pi->dma_region_p = (dma_addr_t) NULL;
  695. }
  696. return;
  697. }
  698. static void
  699. mpsc_init_rings(struct mpsc_port_info *pi)
  700. {
  701. struct mpsc_rx_desc *rxre;
  702. struct mpsc_tx_desc *txre;
  703. dma_addr_t dp, dp_p;
  704. u8 *bp, *bp_p;
  705. int i;
  706. pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
  707. BUG_ON(pi->dma_region == NULL);
  708. memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
  709. /*
  710. * Descriptors & buffers are multiples of cacheline size and must be
  711. * cacheline aligned.
  712. */
  713. dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment());
  714. dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment());
  715. /*
  716. * Partition dma region into rx ring descriptor, rx buffers,
  717. * tx ring descriptors, and tx buffers.
  718. */
  719. pi->rxr = dp;
  720. pi->rxr_p = dp_p;
  721. dp += MPSC_RXR_SIZE;
  722. dp_p += MPSC_RXR_SIZE;
  723. pi->rxb = (u8 *) dp;
  724. pi->rxb_p = (u8 *) dp_p;
  725. dp += MPSC_RXB_SIZE;
  726. dp_p += MPSC_RXB_SIZE;
  727. pi->rxr_posn = 0;
  728. pi->txr = dp;
  729. pi->txr_p = dp_p;
  730. dp += MPSC_TXR_SIZE;
  731. dp_p += MPSC_TXR_SIZE;
  732. pi->txb = (u8 *) dp;
  733. pi->txb_p = (u8 *) dp_p;
  734. pi->txr_head = 0;
  735. pi->txr_tail = 0;
  736. /* Init rx ring descriptors */
  737. dp = pi->rxr;
  738. dp_p = pi->rxr_p;
  739. bp = pi->rxb;
  740. bp_p = pi->rxb_p;
  741. for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
  742. rxre = (struct mpsc_rx_desc *)dp;
  743. rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
  744. rxre->bytecnt = cpu_to_be16(0);
  745. rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
  746. SDMA_DESC_CMDSTAT_EI |
  747. SDMA_DESC_CMDSTAT_F |
  748. SDMA_DESC_CMDSTAT_L);
  749. rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
  750. rxre->buf_ptr = cpu_to_be32(bp_p);
  751. dp += MPSC_RXRE_SIZE;
  752. dp_p += MPSC_RXRE_SIZE;
  753. bp += MPSC_RXBE_SIZE;
  754. bp_p += MPSC_RXBE_SIZE;
  755. }
  756. rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
  757. /* Init tx ring descriptors */
  758. dp = pi->txr;
  759. dp_p = pi->txr_p;
  760. bp = pi->txb;
  761. bp_p = pi->txb_p;
  762. for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
  763. txre = (struct mpsc_tx_desc *)dp;
  764. txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
  765. txre->buf_ptr = cpu_to_be32(bp_p);
  766. dp += MPSC_TXRE_SIZE;
  767. dp_p += MPSC_TXRE_SIZE;
  768. bp += MPSC_TXBE_SIZE;
  769. bp_p += MPSC_TXBE_SIZE;
  770. }
  771. txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
  772. dma_cache_sync(pi->port.dev, (void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE,
  773. DMA_BIDIRECTIONAL);
  774. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  775. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  776. flush_dcache_range((ulong)pi->dma_region,
  777. (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE);
  778. #endif
  779. return;
  780. }
  781. static void
  782. mpsc_uninit_rings(struct mpsc_port_info *pi)
  783. {
  784. pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
  785. BUG_ON(pi->dma_region == NULL);
  786. pi->rxr = 0;
  787. pi->rxr_p = 0;
  788. pi->rxb = NULL;
  789. pi->rxb_p = NULL;
  790. pi->rxr_posn = 0;
  791. pi->txr = 0;
  792. pi->txr_p = 0;
  793. pi->txb = NULL;
  794. pi->txb_p = NULL;
  795. pi->txr_head = 0;
  796. pi->txr_tail = 0;
  797. return;
  798. }
  799. static int
  800. mpsc_make_ready(struct mpsc_port_info *pi)
  801. {
  802. int rc;
  803. pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
  804. if (!pi->ready) {
  805. mpsc_init_hw(pi);
  806. if ((rc = mpsc_alloc_ring_mem(pi)))
  807. return rc;
  808. mpsc_init_rings(pi);
  809. pi->ready = 1;
  810. }
  811. return 0;
  812. }
  813. /*
  814. ******************************************************************************
  815. *
  816. * Interrupt Handling Routines
  817. *
  818. ******************************************************************************
  819. */
  820. static inline int
  821. mpsc_rx_intr(struct mpsc_port_info *pi)
  822. {
  823. struct mpsc_rx_desc *rxre;
  824. struct tty_struct *tty = pi->port.info->tty;
  825. u32 cmdstat, bytes_in, i;
  826. int rc = 0;
  827. u8 *bp;
  828. char flag = TTY_NORMAL;
  829. pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
  830. rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
  831. dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
  832. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  833. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  834. invalidate_dcache_range((ulong)rxre,
  835. (ulong)rxre + MPSC_RXRE_SIZE);
  836. #endif
  837. /*
  838. * Loop through Rx descriptors handling ones that have been completed.
  839. */
  840. while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){
  841. bytes_in = be16_to_cpu(rxre->bytecnt);
  842. /* Following use of tty struct directly is deprecated */
  843. if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) {
  844. if (tty->low_latency)
  845. tty_flip_buffer_push(tty);
  846. /*
  847. * If this failed then we will throw away the bytes
  848. * but must do so to clear interrupts.
  849. */
  850. }
  851. bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
  852. dma_cache_sync(pi->port.dev, (void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
  853. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  854. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  855. invalidate_dcache_range((ulong)bp,
  856. (ulong)bp + MPSC_RXBE_SIZE);
  857. #endif
  858. /*
  859. * Other than for parity error, the manual provides little
  860. * info on what data will be in a frame flagged by any of
  861. * these errors. For parity error, it is the last byte in
  862. * the buffer that had the error. As for the rest, I guess
  863. * we'll assume there is no data in the buffer.
  864. * If there is...it gets lost.
  865. */
  866. if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
  867. SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) {
  868. pi->port.icount.rx++;
  869. if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
  870. pi->port.icount.brk++;
  871. if (uart_handle_break(&pi->port))
  872. goto next_frame;
  873. }
  874. else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */
  875. pi->port.icount.frame++;
  876. else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */
  877. pi->port.icount.overrun++;
  878. cmdstat &= pi->port.read_status_mask;
  879. if (cmdstat & SDMA_DESC_CMDSTAT_BR)
  880. flag = TTY_BREAK;
  881. else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
  882. flag = TTY_FRAME;
  883. else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
  884. flag = TTY_OVERRUN;
  885. else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
  886. flag = TTY_PARITY;
  887. }
  888. if (uart_handle_sysrq_char(&pi->port, *bp)) {
  889. bp++;
  890. bytes_in--;
  891. goto next_frame;
  892. }
  893. if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
  894. SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
  895. !(cmdstat & pi->port.ignore_status_mask))
  896. tty_insert_flip_char(tty, *bp, flag);
  897. else {
  898. for (i=0; i<bytes_in; i++)
  899. tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
  900. pi->port.icount.rx += bytes_in;
  901. }
  902. next_frame:
  903. rxre->bytecnt = cpu_to_be16(0);
  904. wmb();
  905. rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
  906. SDMA_DESC_CMDSTAT_EI |
  907. SDMA_DESC_CMDSTAT_F |
  908. SDMA_DESC_CMDSTAT_L);
  909. wmb();
  910. dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
  911. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  912. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  913. flush_dcache_range((ulong)rxre,
  914. (ulong)rxre + MPSC_RXRE_SIZE);
  915. #endif
  916. /* Advance to next descriptor */
  917. pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
  918. rxre = (struct mpsc_rx_desc *)(pi->rxr +
  919. (pi->rxr_posn * MPSC_RXRE_SIZE));
  920. dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
  921. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  922. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  923. invalidate_dcache_range((ulong)rxre,
  924. (ulong)rxre + MPSC_RXRE_SIZE);
  925. #endif
  926. rc = 1;
  927. }
  928. /* Restart rx engine, if its stopped */
  929. if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
  930. mpsc_start_rx(pi);
  931. tty_flip_buffer_push(tty);
  932. return rc;
  933. }
  934. static inline void
  935. mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
  936. {
  937. struct mpsc_tx_desc *txre;
  938. txre = (struct mpsc_tx_desc *)(pi->txr +
  939. (pi->txr_head * MPSC_TXRE_SIZE));
  940. txre->bytecnt = cpu_to_be16(count);
  941. txre->shadow = txre->bytecnt;
  942. wmb(); /* ensure cmdstat is last field updated */
  943. txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F |
  944. SDMA_DESC_CMDSTAT_L | ((intr) ?
  945. SDMA_DESC_CMDSTAT_EI
  946. : 0));
  947. wmb();
  948. dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL);
  949. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  950. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  951. flush_dcache_range((ulong)txre,
  952. (ulong)txre + MPSC_TXRE_SIZE);
  953. #endif
  954. return;
  955. }
  956. static inline void
  957. mpsc_copy_tx_data(struct mpsc_port_info *pi)
  958. {
  959. struct circ_buf *xmit = &pi->port.info->xmit;
  960. u8 *bp;
  961. u32 i;
  962. /* Make sure the desc ring isn't full */
  963. while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) <
  964. (MPSC_TXR_ENTRIES - 1)) {
  965. if (pi->port.x_char) {
  966. /*
  967. * Ideally, we should use the TCS field in
  968. * CHR_1 to put the x_char out immediately but
  969. * errata prevents us from being able to read
  970. * CHR_2 to know that its safe to write to
  971. * CHR_1. Instead, just put it in-band with
  972. * all the other Tx data.
  973. */
  974. bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
  975. *bp = pi->port.x_char;
  976. pi->port.x_char = 0;
  977. i = 1;
  978. }
  979. else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){
  980. i = min((u32) MPSC_TXBE_SIZE,
  981. (u32) uart_circ_chars_pending(xmit));
  982. i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail,
  983. UART_XMIT_SIZE));
  984. bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
  985. memcpy(bp, &xmit->buf[xmit->tail], i);
  986. xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
  987. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  988. uart_write_wakeup(&pi->port);
  989. }
  990. else /* All tx data copied into ring bufs */
  991. return;
  992. dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
  993. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  994. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  995. flush_dcache_range((ulong)bp,
  996. (ulong)bp + MPSC_TXBE_SIZE);
  997. #endif
  998. mpsc_setup_tx_desc(pi, i, 1);
  999. /* Advance to next descriptor */
  1000. pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
  1001. }
  1002. return;
  1003. }
  1004. static inline int
  1005. mpsc_tx_intr(struct mpsc_port_info *pi)
  1006. {
  1007. struct mpsc_tx_desc *txre;
  1008. int rc = 0;
  1009. if (!mpsc_sdma_tx_active(pi)) {
  1010. txre = (struct mpsc_tx_desc *)(pi->txr +
  1011. (pi->txr_tail * MPSC_TXRE_SIZE));
  1012. dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
  1013. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  1014. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  1015. invalidate_dcache_range((ulong)txre,
  1016. (ulong)txre + MPSC_TXRE_SIZE);
  1017. #endif
  1018. while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
  1019. rc = 1;
  1020. pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
  1021. pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
  1022. /* If no more data to tx, fall out of loop */
  1023. if (pi->txr_head == pi->txr_tail)
  1024. break;
  1025. txre = (struct mpsc_tx_desc *)(pi->txr +
  1026. (pi->txr_tail * MPSC_TXRE_SIZE));
  1027. dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE,
  1028. DMA_FROM_DEVICE);
  1029. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  1030. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  1031. invalidate_dcache_range((ulong)txre,
  1032. (ulong)txre + MPSC_TXRE_SIZE);
  1033. #endif
  1034. }
  1035. mpsc_copy_tx_data(pi);
  1036. mpsc_sdma_start_tx(pi); /* start next desc if ready */
  1037. }
  1038. return rc;
  1039. }
  1040. /*
  1041. * This is the driver's interrupt handler. To avoid a race, we first clear
  1042. * the interrupt, then handle any completed Rx/Tx descriptors. When done
  1043. * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
  1044. */
  1045. static irqreturn_t
  1046. mpsc_sdma_intr(int irq, void *dev_id)
  1047. {
  1048. struct mpsc_port_info *pi = dev_id;
  1049. ulong iflags;
  1050. int rc = IRQ_NONE;
  1051. pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
  1052. spin_lock_irqsave(&pi->port.lock, iflags);
  1053. mpsc_sdma_intr_ack(pi);
  1054. if (mpsc_rx_intr(pi))
  1055. rc = IRQ_HANDLED;
  1056. if (mpsc_tx_intr(pi))
  1057. rc = IRQ_HANDLED;
  1058. spin_unlock_irqrestore(&pi->port.lock, iflags);
  1059. pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
  1060. return rc;
  1061. }
  1062. /*
  1063. ******************************************************************************
  1064. *
  1065. * serial_core.c Interface routines
  1066. *
  1067. ******************************************************************************
  1068. */
  1069. static uint
  1070. mpsc_tx_empty(struct uart_port *port)
  1071. {
  1072. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1073. ulong iflags;
  1074. uint rc;
  1075. spin_lock_irqsave(&pi->port.lock, iflags);
  1076. rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
  1077. spin_unlock_irqrestore(&pi->port.lock, iflags);
  1078. return rc;
  1079. }
  1080. static void
  1081. mpsc_set_mctrl(struct uart_port *port, uint mctrl)
  1082. {
  1083. /* Have no way to set modem control lines AFAICT */
  1084. return;
  1085. }
  1086. static uint
  1087. mpsc_get_mctrl(struct uart_port *port)
  1088. {
  1089. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1090. u32 mflags, status;
  1091. status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
  1092. readl(pi->mpsc_base + MPSC_CHR_10);
  1093. mflags = 0;
  1094. if (status & 0x1)
  1095. mflags |= TIOCM_CTS;
  1096. if (status & 0x2)
  1097. mflags |= TIOCM_CAR;
  1098. return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
  1099. }
  1100. static void
  1101. mpsc_stop_tx(struct uart_port *port)
  1102. {
  1103. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1104. pr_debug("mpsc_stop_tx[%d]\n", port->line);
  1105. mpsc_freeze(pi);
  1106. return;
  1107. }
  1108. static void
  1109. mpsc_start_tx(struct uart_port *port)
  1110. {
  1111. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1112. mpsc_unfreeze(pi);
  1113. mpsc_copy_tx_data(pi);
  1114. mpsc_sdma_start_tx(pi);
  1115. pr_debug("mpsc_start_tx[%d]\n", port->line);
  1116. return;
  1117. }
  1118. static void
  1119. mpsc_start_rx(struct mpsc_port_info *pi)
  1120. {
  1121. pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
  1122. /* Issue a Receive Abort to clear any receive errors */
  1123. writel(MPSC_CHR_2_RA, pi->mpsc_base + MPSC_CHR_2);
  1124. if (pi->rcv_data) {
  1125. mpsc_enter_hunt(pi);
  1126. mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
  1127. }
  1128. return;
  1129. }
  1130. static void
  1131. mpsc_stop_rx(struct uart_port *port)
  1132. {
  1133. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1134. pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
  1135. mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
  1136. return;
  1137. }
  1138. static void
  1139. mpsc_enable_ms(struct uart_port *port)
  1140. {
  1141. return; /* Not supported */
  1142. }
  1143. static void
  1144. mpsc_break_ctl(struct uart_port *port, int ctl)
  1145. {
  1146. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1147. ulong flags;
  1148. u32 v;
  1149. v = ctl ? 0x00ff0000 : 0;
  1150. spin_lock_irqsave(&pi->port.lock, flags);
  1151. if (pi->mirror_regs)
  1152. pi->MPSC_CHR_1_m = v;
  1153. writel(v, pi->mpsc_base + MPSC_CHR_1);
  1154. spin_unlock_irqrestore(&pi->port.lock, flags);
  1155. return;
  1156. }
  1157. static int
  1158. mpsc_startup(struct uart_port *port)
  1159. {
  1160. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1161. u32 flag = 0;
  1162. int rc;
  1163. pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
  1164. port->line, pi->port.irq);
  1165. if ((rc = mpsc_make_ready(pi)) == 0) {
  1166. /* Setup IRQ handler */
  1167. mpsc_sdma_intr_ack(pi);
  1168. /* If irq's are shared, need to set flag */
  1169. if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
  1170. flag = IRQF_SHARED;
  1171. if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
  1172. "mpsc-sdma", pi))
  1173. printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
  1174. pi->port.irq);
  1175. mpsc_sdma_intr_unmask(pi, 0xf);
  1176. mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p +
  1177. (pi->rxr_posn * MPSC_RXRE_SIZE)));
  1178. }
  1179. return rc;
  1180. }
  1181. static void
  1182. mpsc_shutdown(struct uart_port *port)
  1183. {
  1184. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1185. pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
  1186. mpsc_sdma_stop(pi);
  1187. free_irq(pi->port.irq, pi);
  1188. return;
  1189. }
  1190. static void
  1191. mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
  1192. struct ktermios *old)
  1193. {
  1194. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1195. u32 baud;
  1196. ulong flags;
  1197. u32 chr_bits, stop_bits, par;
  1198. pi->c_iflag = termios->c_iflag;
  1199. pi->c_cflag = termios->c_cflag;
  1200. switch (termios->c_cflag & CSIZE) {
  1201. case CS5:
  1202. chr_bits = MPSC_MPCR_CL_5;
  1203. break;
  1204. case CS6:
  1205. chr_bits = MPSC_MPCR_CL_6;
  1206. break;
  1207. case CS7:
  1208. chr_bits = MPSC_MPCR_CL_7;
  1209. break;
  1210. case CS8:
  1211. default:
  1212. chr_bits = MPSC_MPCR_CL_8;
  1213. break;
  1214. }
  1215. if (termios->c_cflag & CSTOPB)
  1216. stop_bits = MPSC_MPCR_SBL_2;
  1217. else
  1218. stop_bits = MPSC_MPCR_SBL_1;
  1219. par = MPSC_CHR_2_PAR_EVEN;
  1220. if (termios->c_cflag & PARENB)
  1221. if (termios->c_cflag & PARODD)
  1222. par = MPSC_CHR_2_PAR_ODD;
  1223. #ifdef CMSPAR
  1224. if (termios->c_cflag & CMSPAR) {
  1225. if (termios->c_cflag & PARODD)
  1226. par = MPSC_CHR_2_PAR_MARK;
  1227. else
  1228. par = MPSC_CHR_2_PAR_SPACE;
  1229. }
  1230. #endif
  1231. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
  1232. spin_lock_irqsave(&pi->port.lock, flags);
  1233. uart_update_timeout(port, termios->c_cflag, baud);
  1234. mpsc_set_char_length(pi, chr_bits);
  1235. mpsc_set_stop_bit_length(pi, stop_bits);
  1236. mpsc_set_parity(pi, par);
  1237. mpsc_set_baudrate(pi, baud);
  1238. /* Characters/events to read */
  1239. pi->rcv_data = 1;
  1240. pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
  1241. if (termios->c_iflag & INPCK)
  1242. pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
  1243. SDMA_DESC_CMDSTAT_FR;
  1244. if (termios->c_iflag & (BRKINT | PARMRK))
  1245. pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
  1246. /* Characters/events to ignore */
  1247. pi->port.ignore_status_mask = 0;
  1248. if (termios->c_iflag & IGNPAR)
  1249. pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE |
  1250. SDMA_DESC_CMDSTAT_FR;
  1251. if (termios->c_iflag & IGNBRK) {
  1252. pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
  1253. if (termios->c_iflag & IGNPAR)
  1254. pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
  1255. }
  1256. /* Ignore all chars if CREAD not set */
  1257. if (!(termios->c_cflag & CREAD))
  1258. pi->rcv_data = 0;
  1259. else
  1260. mpsc_start_rx(pi);
  1261. spin_unlock_irqrestore(&pi->port.lock, flags);
  1262. return;
  1263. }
  1264. static const char *
  1265. mpsc_type(struct uart_port *port)
  1266. {
  1267. pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
  1268. return MPSC_DRIVER_NAME;
  1269. }
  1270. static int
  1271. mpsc_request_port(struct uart_port *port)
  1272. {
  1273. /* Should make chip/platform specific call */
  1274. return 0;
  1275. }
  1276. static void
  1277. mpsc_release_port(struct uart_port *port)
  1278. {
  1279. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1280. if (pi->ready) {
  1281. mpsc_uninit_rings(pi);
  1282. mpsc_free_ring_mem(pi);
  1283. pi->ready = 0;
  1284. }
  1285. return;
  1286. }
  1287. static void
  1288. mpsc_config_port(struct uart_port *port, int flags)
  1289. {
  1290. return;
  1291. }
  1292. static int
  1293. mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
  1294. {
  1295. struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
  1296. int rc = 0;
  1297. pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
  1298. if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
  1299. rc = -EINVAL;
  1300. else if (pi->port.irq != ser->irq)
  1301. rc = -EINVAL;
  1302. else if (ser->io_type != SERIAL_IO_MEM)
  1303. rc = -EINVAL;
  1304. else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
  1305. rc = -EINVAL;
  1306. else if ((void *)pi->port.mapbase != ser->iomem_base)
  1307. rc = -EINVAL;
  1308. else if (pi->port.iobase != ser->port)
  1309. rc = -EINVAL;
  1310. else if (ser->hub6 != 0)
  1311. rc = -EINVAL;
  1312. return rc;
  1313. }
  1314. static struct uart_ops mpsc_pops = {
  1315. .tx_empty = mpsc_tx_empty,
  1316. .set_mctrl = mpsc_set_mctrl,
  1317. .get_mctrl = mpsc_get_mctrl,
  1318. .stop_tx = mpsc_stop_tx,
  1319. .start_tx = mpsc_start_tx,
  1320. .stop_rx = mpsc_stop_rx,
  1321. .enable_ms = mpsc_enable_ms,
  1322. .break_ctl = mpsc_break_ctl,
  1323. .startup = mpsc_startup,
  1324. .shutdown = mpsc_shutdown,
  1325. .set_termios = mpsc_set_termios,
  1326. .type = mpsc_type,
  1327. .release_port = mpsc_release_port,
  1328. .request_port = mpsc_request_port,
  1329. .config_port = mpsc_config_port,
  1330. .verify_port = mpsc_verify_port,
  1331. };
  1332. /*
  1333. ******************************************************************************
  1334. *
  1335. * Console Interface Routines
  1336. *
  1337. ******************************************************************************
  1338. */
  1339. #ifdef CONFIG_SERIAL_MPSC_CONSOLE
  1340. static void
  1341. mpsc_console_write(struct console *co, const char *s, uint count)
  1342. {
  1343. struct mpsc_port_info *pi = &mpsc_ports[co->index];
  1344. u8 *bp, *dp, add_cr = 0;
  1345. int i;
  1346. while (mpsc_sdma_tx_active(pi))
  1347. udelay(100);
  1348. while (count > 0) {
  1349. bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
  1350. for (i = 0; i < MPSC_TXBE_SIZE; i++) {
  1351. if (count == 0)
  1352. break;
  1353. if (add_cr) {
  1354. *(dp++) = '\r';
  1355. add_cr = 0;
  1356. }
  1357. else {
  1358. *(dp++) = *s;
  1359. if (*(s++) == '\n') { /* add '\r' after '\n' */
  1360. add_cr = 1;
  1361. count++;
  1362. }
  1363. }
  1364. count--;
  1365. }
  1366. dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
  1367. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  1368. if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
  1369. flush_dcache_range((ulong)bp,
  1370. (ulong)bp + MPSC_TXBE_SIZE);
  1371. #endif
  1372. mpsc_setup_tx_desc(pi, i, 0);
  1373. pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
  1374. mpsc_sdma_start_tx(pi);
  1375. while (mpsc_sdma_tx_active(pi))
  1376. udelay(100);
  1377. pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
  1378. }
  1379. return;
  1380. }
  1381. static int __init
  1382. mpsc_console_setup(struct console *co, char *options)
  1383. {
  1384. struct mpsc_port_info *pi;
  1385. int baud, bits, parity, flow;
  1386. pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
  1387. if (co->index >= MPSC_NUM_CTLRS)
  1388. co->index = 0;
  1389. pi = &mpsc_ports[co->index];
  1390. baud = pi->default_baud;
  1391. bits = pi->default_bits;
  1392. parity = pi->default_parity;
  1393. flow = pi->default_flow;
  1394. if (!pi->port.ops)
  1395. return -ENODEV;
  1396. spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
  1397. if (options)
  1398. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1399. return uart_set_options(&pi->port, co, baud, parity, bits, flow);
  1400. }
  1401. static struct console mpsc_console = {
  1402. .name = MPSC_DEV_NAME,
  1403. .write = mpsc_console_write,
  1404. .device = uart_console_device,
  1405. .setup = mpsc_console_setup,
  1406. .flags = CON_PRINTBUFFER,
  1407. .index = -1,
  1408. .data = &mpsc_reg,
  1409. };
  1410. static int __init
  1411. mpsc_late_console_init(void)
  1412. {
  1413. pr_debug("mpsc_late_console_init: Enter\n");
  1414. if (!(mpsc_console.flags & CON_ENABLED))
  1415. register_console(&mpsc_console);
  1416. return 0;
  1417. }
  1418. late_initcall(mpsc_late_console_init);
  1419. #define MPSC_CONSOLE &mpsc_console
  1420. #else
  1421. #define MPSC_CONSOLE NULL
  1422. #endif
  1423. /*
  1424. ******************************************************************************
  1425. *
  1426. * Dummy Platform Driver to extract & map shared register regions
  1427. *
  1428. ******************************************************************************
  1429. */
  1430. static void
  1431. mpsc_resource_err(char *s)
  1432. {
  1433. printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
  1434. return;
  1435. }
  1436. static int
  1437. mpsc_shared_map_regs(struct platform_device *pd)
  1438. {
  1439. struct resource *r;
  1440. if ((r = platform_get_resource(pd, IORESOURCE_MEM,
  1441. MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start,
  1442. MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) {
  1443. mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
  1444. MPSC_ROUTING_REG_BLOCK_SIZE);
  1445. mpsc_shared_regs.mpsc_routing_base_p = r->start;
  1446. }
  1447. else {
  1448. mpsc_resource_err("MPSC routing base");
  1449. return -ENOMEM;
  1450. }
  1451. if ((r = platform_get_resource(pd, IORESOURCE_MEM,
  1452. MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start,
  1453. MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) {
  1454. mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
  1455. MPSC_SDMA_INTR_REG_BLOCK_SIZE);
  1456. mpsc_shared_regs.sdma_intr_base_p = r->start;
  1457. }
  1458. else {
  1459. iounmap(mpsc_shared_regs.mpsc_routing_base);
  1460. release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
  1461. MPSC_ROUTING_REG_BLOCK_SIZE);
  1462. mpsc_resource_err("SDMA intr base");
  1463. return -ENOMEM;
  1464. }
  1465. return 0;
  1466. }
  1467. static void
  1468. mpsc_shared_unmap_regs(void)
  1469. {
  1470. if (!mpsc_shared_regs.mpsc_routing_base) {
  1471. iounmap(mpsc_shared_regs.mpsc_routing_base);
  1472. release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
  1473. MPSC_ROUTING_REG_BLOCK_SIZE);
  1474. }
  1475. if (!mpsc_shared_regs.sdma_intr_base) {
  1476. iounmap(mpsc_shared_regs.sdma_intr_base);
  1477. release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
  1478. MPSC_SDMA_INTR_REG_BLOCK_SIZE);
  1479. }
  1480. mpsc_shared_regs.mpsc_routing_base = NULL;
  1481. mpsc_shared_regs.sdma_intr_base = NULL;
  1482. mpsc_shared_regs.mpsc_routing_base_p = 0;
  1483. mpsc_shared_regs.sdma_intr_base_p = 0;
  1484. return;
  1485. }
  1486. static int
  1487. mpsc_shared_drv_probe(struct platform_device *dev)
  1488. {
  1489. struct mpsc_shared_pdata *pdata;
  1490. int rc = -ENODEV;
  1491. if (dev->id == 0) {
  1492. if (!(rc = mpsc_shared_map_regs(dev))) {
  1493. pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data;
  1494. mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
  1495. mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
  1496. mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
  1497. mpsc_shared_regs.SDMA_INTR_CAUSE_m =
  1498. pdata->intr_cause_val;
  1499. mpsc_shared_regs.SDMA_INTR_MASK_m =
  1500. pdata->intr_mask_val;
  1501. rc = 0;
  1502. }
  1503. }
  1504. return rc;
  1505. }
  1506. static int
  1507. mpsc_shared_drv_remove(struct platform_device *dev)
  1508. {
  1509. int rc = -ENODEV;
  1510. if (dev->id == 0) {
  1511. mpsc_shared_unmap_regs();
  1512. mpsc_shared_regs.MPSC_MRR_m = 0;
  1513. mpsc_shared_regs.MPSC_RCRR_m = 0;
  1514. mpsc_shared_regs.MPSC_TCRR_m = 0;
  1515. mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
  1516. mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
  1517. rc = 0;
  1518. }
  1519. return rc;
  1520. }
  1521. static struct platform_driver mpsc_shared_driver = {
  1522. .probe = mpsc_shared_drv_probe,
  1523. .remove = mpsc_shared_drv_remove,
  1524. .driver = {
  1525. .name = MPSC_SHARED_NAME,
  1526. },
  1527. };
  1528. /*
  1529. ******************************************************************************
  1530. *
  1531. * Driver Interface Routines
  1532. *
  1533. ******************************************************************************
  1534. */
  1535. static struct uart_driver mpsc_reg = {
  1536. .owner = THIS_MODULE,
  1537. .driver_name = MPSC_DRIVER_NAME,
  1538. .dev_name = MPSC_DEV_NAME,
  1539. .major = MPSC_MAJOR,
  1540. .minor = MPSC_MINOR_START,
  1541. .nr = MPSC_NUM_CTLRS,
  1542. .cons = MPSC_CONSOLE,
  1543. };
  1544. static int
  1545. mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd)
  1546. {
  1547. struct resource *r;
  1548. if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) &&
  1549. request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){
  1550. pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
  1551. pi->mpsc_base_p = r->start;
  1552. }
  1553. else {
  1554. mpsc_resource_err("MPSC base");
  1555. return -ENOMEM;
  1556. }
  1557. if ((r = platform_get_resource(pd, IORESOURCE_MEM,
  1558. MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start,
  1559. MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
  1560. pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
  1561. pi->sdma_base_p = r->start;
  1562. }
  1563. else {
  1564. mpsc_resource_err("SDMA base");
  1565. if (pi->mpsc_base) {
  1566. iounmap(pi->mpsc_base);
  1567. pi->mpsc_base = NULL;
  1568. }
  1569. return -ENOMEM;
  1570. }
  1571. if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
  1572. && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE,
  1573. "brg_regs")) {
  1574. pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
  1575. pi->brg_base_p = r->start;
  1576. }
  1577. else {
  1578. mpsc_resource_err("BRG base");
  1579. if (pi->mpsc_base) {
  1580. iounmap(pi->mpsc_base);
  1581. pi->mpsc_base = NULL;
  1582. }
  1583. if (pi->sdma_base) {
  1584. iounmap(pi->sdma_base);
  1585. pi->sdma_base = NULL;
  1586. }
  1587. return -ENOMEM;
  1588. }
  1589. return 0;
  1590. }
  1591. static void
  1592. mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
  1593. {
  1594. if (!pi->mpsc_base) {
  1595. iounmap(pi->mpsc_base);
  1596. release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
  1597. }
  1598. if (!pi->sdma_base) {
  1599. iounmap(pi->sdma_base);
  1600. release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
  1601. }
  1602. if (!pi->brg_base) {
  1603. iounmap(pi->brg_base);
  1604. release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
  1605. }
  1606. pi->mpsc_base = NULL;
  1607. pi->sdma_base = NULL;
  1608. pi->brg_base = NULL;
  1609. pi->mpsc_base_p = 0;
  1610. pi->sdma_base_p = 0;
  1611. pi->brg_base_p = 0;
  1612. return;
  1613. }
  1614. static void
  1615. mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
  1616. struct platform_device *pd, int num)
  1617. {
  1618. struct mpsc_pdata *pdata;
  1619. pdata = (struct mpsc_pdata *)pd->dev.platform_data;
  1620. pi->port.uartclk = pdata->brg_clk_freq;
  1621. pi->port.iotype = UPIO_MEM;
  1622. pi->port.line = num;
  1623. pi->port.type = PORT_MPSC;
  1624. pi->port.fifosize = MPSC_TXBE_SIZE;
  1625. pi->port.membase = pi->mpsc_base;
  1626. pi->port.mapbase = (ulong)pi->mpsc_base;
  1627. pi->port.ops = &mpsc_pops;
  1628. pi->mirror_regs = pdata->mirror_regs;
  1629. pi->cache_mgmt = pdata->cache_mgmt;
  1630. pi->brg_can_tune = pdata->brg_can_tune;
  1631. pi->brg_clk_src = pdata->brg_clk_src;
  1632. pi->mpsc_max_idle = pdata->max_idle;
  1633. pi->default_baud = pdata->default_baud;
  1634. pi->default_bits = pdata->default_bits;
  1635. pi->default_parity = pdata->default_parity;
  1636. pi->default_flow = pdata->default_flow;
  1637. /* Initial values of mirrored regs */
  1638. pi->MPSC_CHR_1_m = pdata->chr_1_val;
  1639. pi->MPSC_CHR_2_m = pdata->chr_2_val;
  1640. pi->MPSC_CHR_10_m = pdata->chr_10_val;
  1641. pi->MPSC_MPCR_m = pdata->mpcr_val;
  1642. pi->BRG_BCR_m = pdata->bcr_val;
  1643. pi->shared_regs = &mpsc_shared_regs;
  1644. pi->port.irq = platform_get_irq(pd, 0);
  1645. return;
  1646. }
  1647. static int
  1648. mpsc_drv_probe(struct platform_device *dev)
  1649. {
  1650. struct mpsc_port_info *pi;
  1651. int rc = -ENODEV;
  1652. pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
  1653. if (dev->id < MPSC_NUM_CTLRS) {
  1654. pi = &mpsc_ports[dev->id];
  1655. if (!(rc = mpsc_drv_map_regs(pi, dev))) {
  1656. mpsc_drv_get_platform_data(pi, dev, dev->id);
  1657. if (!(rc = mpsc_make_ready(pi)))
  1658. if (!(rc = uart_add_one_port(&mpsc_reg,
  1659. &pi->port)))
  1660. rc = 0;
  1661. else {
  1662. mpsc_release_port(
  1663. (struct uart_port *)pi);
  1664. mpsc_drv_unmap_regs(pi);
  1665. }
  1666. else
  1667. mpsc_drv_unmap_regs(pi);
  1668. }
  1669. }
  1670. return rc;
  1671. }
  1672. static int
  1673. mpsc_drv_remove(struct platform_device *dev)
  1674. {
  1675. pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
  1676. if (dev->id < MPSC_NUM_CTLRS) {
  1677. uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
  1678. mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port);
  1679. mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
  1680. return 0;
  1681. }
  1682. else
  1683. return -ENODEV;
  1684. }
  1685. static struct platform_driver mpsc_driver = {
  1686. .probe = mpsc_drv_probe,
  1687. .remove = mpsc_drv_remove,
  1688. .driver = {
  1689. .name = MPSC_CTLR_NAME,
  1690. },
  1691. };
  1692. static int __init
  1693. mpsc_drv_init(void)
  1694. {
  1695. int rc;
  1696. printk(KERN_INFO "Serial: MPSC driver $Revision: 1.1.1.1 $\n");
  1697. memset(mpsc_ports, 0, sizeof(mpsc_ports));
  1698. memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
  1699. if (!(rc = uart_register_driver(&mpsc_reg))) {
  1700. if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
  1701. if ((rc = platform_driver_register(&mpsc_driver))) {
  1702. platform_driver_unregister(&mpsc_shared_driver);
  1703. uart_unregister_driver(&mpsc_reg);
  1704. }
  1705. }
  1706. else
  1707. uart_unregister_driver(&mpsc_reg);
  1708. }
  1709. return rc;
  1710. }
  1711. static void __exit
  1712. mpsc_drv_exit(void)
  1713. {
  1714. platform_driver_unregister(&mpsc_driver);
  1715. platform_driver_unregister(&mpsc_shared_driver);
  1716. uart_unregister_driver(&mpsc_reg);
  1717. memset(mpsc_ports, 0, sizeof(mpsc_ports));
  1718. memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
  1719. return;
  1720. }
  1721. module_init(mpsc_drv_init);
  1722. module_exit(mpsc_drv_exit);
  1723. MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
  1724. MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.1.1.1 $");
  1725. MODULE_VERSION(MPSC_VERSION);
  1726. MODULE_LICENSE("GPL");
  1727. MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);