m32r_sio.c 27 KB

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  1. /*
  2. * m32r_sio.c
  3. *
  4. * Driver for M32R serial ports
  5. *
  6. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7. * Based on drivers/serial/8250.c.
  8. *
  9. * Copyright (C) 2001 Russell King.
  10. * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. */
  17. /*
  18. * A note about mapbase / membase
  19. *
  20. * mapbase is the physical address of the IO port. Currently, we don't
  21. * support this very well, and it may well be dropped from this driver
  22. * in future. As such, mapbase should be NULL.
  23. *
  24. * membase is an 'ioremapped' cookie. This is compatible with the old
  25. * serial.c driver, and is currently the preferred form.
  26. */
  27. #if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28. #define SUPPORT_SYSRQ
  29. #endif
  30. #include <linux/module.h>
  31. #include <linux/tty.h>
  32. #include <linux/ioport.h>
  33. #include <linux/init.h>
  34. #include <linux/console.h>
  35. #include <linux/sysrq.h>
  36. #include <linux/serial.h>
  37. #include <linux/serialP.h>
  38. #include <linux/delay.h>
  39. #include <asm/m32r.h>
  40. #include <asm/io.h>
  41. #include <asm/irq.h>
  42. #define PORT_M32R_BASE PORT_M32R_SIO
  43. #define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
  44. #define BAUD_RATE 115200
  45. #include <linux/serial_core.h>
  46. #include "m32r_sio.h"
  47. #include "m32r_sio_reg.h"
  48. /*
  49. * Debugging.
  50. */
  51. #if 0
  52. #define DEBUG_AUTOCONF(fmt...) printk(fmt)
  53. #else
  54. #define DEBUG_AUTOCONF(fmt...) do { } while (0)
  55. #endif
  56. #if 0
  57. #define DEBUG_INTR(fmt...) printk(fmt)
  58. #else
  59. #define DEBUG_INTR(fmt...) do { } while (0)
  60. #endif
  61. #define PASS_LIMIT 256
  62. /*
  63. * We default to IRQ0 for the "no irq" hack. Some
  64. * machine types want others as well - they're free
  65. * to redefine this in their header file.
  66. */
  67. #define is_real_interrupt(irq) ((irq) != 0)
  68. #define BASE_BAUD 115200
  69. /* Standard COM flags */
  70. #define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
  71. /*
  72. * SERIAL_PORT_DFNS tells us about built-in ports that have no
  73. * standard enumeration mechanism. Platforms that can find all
  74. * serial ports via mechanisms like ACPI or PCI need not supply it.
  75. */
  76. #if defined(CONFIG_PLAT_USRV)
  77. #define SERIAL_PORT_DFNS \
  78. /* UART CLK PORT IRQ FLAGS */ \
  79. { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
  80. { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
  81. #else /* !CONFIG_PLAT_USRV */
  82. #if defined(CONFIG_SERIAL_M32R_PLDSIO)
  83. #define SERIAL_PORT_DFNS \
  84. { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
  85. STD_COM_FLAGS }, /* ttyS0 */
  86. #else
  87. #define SERIAL_PORT_DFNS \
  88. { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
  89. STD_COM_FLAGS }, /* ttyS0 */
  90. #endif
  91. #endif /* !CONFIG_PLAT_USRV */
  92. static struct old_serial_port old_serial_port[] = {
  93. SERIAL_PORT_DFNS
  94. };
  95. #define UART_NR ARRAY_SIZE(old_serial_port)
  96. struct uart_sio_port {
  97. struct uart_port port;
  98. struct timer_list timer; /* "no irq" timer */
  99. struct list_head list; /* ports on this IRQ */
  100. unsigned short rev;
  101. unsigned char acr;
  102. unsigned char ier;
  103. unsigned char lcr;
  104. unsigned char mcr_mask; /* mask of user bits */
  105. unsigned char mcr_force; /* mask of forced bits */
  106. unsigned char lsr_break_flag;
  107. /*
  108. * We provide a per-port pm hook.
  109. */
  110. void (*pm)(struct uart_port *port,
  111. unsigned int state, unsigned int old);
  112. };
  113. struct irq_info {
  114. spinlock_t lock;
  115. struct list_head *head;
  116. };
  117. static struct irq_info irq_lists[NR_IRQS];
  118. /*
  119. * Here we define the default xmit fifo size used for each type of UART.
  120. */
  121. static const struct serial_uart_config uart_config[] = {
  122. [PORT_UNKNOWN] = {
  123. .name = "unknown",
  124. .dfl_xmit_fifo_size = 1,
  125. .flags = 0,
  126. },
  127. [PORT_INDEX(PORT_M32R_SIO)] = {
  128. .name = "M32RSIO",
  129. .dfl_xmit_fifo_size = 1,
  130. .flags = 0,
  131. },
  132. };
  133. #ifdef CONFIG_SERIAL_M32R_PLDSIO
  134. #define __sio_in(x) inw((unsigned long)(x))
  135. #define __sio_out(v,x) outw((v),(unsigned long)(x))
  136. static inline void sio_set_baud_rate(unsigned long baud)
  137. {
  138. unsigned short sbaud;
  139. sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
  140. __sio_out(sbaud, PLD_ESIO0BAUR);
  141. }
  142. static void sio_reset(void)
  143. {
  144. unsigned short tmp;
  145. tmp = __sio_in(PLD_ESIO0RXB);
  146. tmp = __sio_in(PLD_ESIO0RXB);
  147. tmp = __sio_in(PLD_ESIO0CR);
  148. sio_set_baud_rate(BAUD_RATE);
  149. __sio_out(0x0300, PLD_ESIO0CR);
  150. __sio_out(0x0003, PLD_ESIO0CR);
  151. }
  152. static void sio_init(void)
  153. {
  154. unsigned short tmp;
  155. tmp = __sio_in(PLD_ESIO0RXB);
  156. tmp = __sio_in(PLD_ESIO0RXB);
  157. tmp = __sio_in(PLD_ESIO0CR);
  158. __sio_out(0x0300, PLD_ESIO0CR);
  159. __sio_out(0x0003, PLD_ESIO0CR);
  160. }
  161. static void sio_error(int *status)
  162. {
  163. printk("SIO0 error[%04x]\n", *status);
  164. do {
  165. sio_init();
  166. } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
  167. }
  168. #else /* not CONFIG_SERIAL_M32R_PLDSIO */
  169. #define __sio_in(x) inl(x)
  170. #define __sio_out(v,x) outl((v),(x))
  171. static inline void sio_set_baud_rate(unsigned long baud)
  172. {
  173. unsigned long i, j;
  174. i = boot_cpu_data.bus_clock / (baud * 16);
  175. j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
  176. i -= 1;
  177. j = (j + 1) >> 1;
  178. __sio_out(i, M32R_SIO0_BAUR_PORTL);
  179. __sio_out(j, M32R_SIO0_RBAUR_PORTL);
  180. }
  181. static void sio_reset(void)
  182. {
  183. __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
  184. __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
  185. __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
  186. sio_set_baud_rate(BAUD_RATE);
  187. __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
  188. __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
  189. }
  190. static void sio_init(void)
  191. {
  192. unsigned int tmp;
  193. tmp = __sio_in(M32R_SIO0_RXB_PORTL);
  194. tmp = __sio_in(M32R_SIO0_RXB_PORTL);
  195. tmp = __sio_in(M32R_SIO0_STS_PORTL);
  196. __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
  197. }
  198. static void sio_error(int *status)
  199. {
  200. printk("SIO0 error[%04x]\n", *status);
  201. do {
  202. sio_init();
  203. } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
  204. }
  205. #endif /* CONFIG_SERIAL_M32R_PLDSIO */
  206. static unsigned int sio_in(struct uart_sio_port *up, int offset)
  207. {
  208. return __sio_in(up->port.iobase + offset);
  209. }
  210. static void sio_out(struct uart_sio_port *up, int offset, int value)
  211. {
  212. __sio_out(value, up->port.iobase + offset);
  213. }
  214. static unsigned int serial_in(struct uart_sio_port *up, int offset)
  215. {
  216. if (!offset)
  217. return 0;
  218. return __sio_in(offset);
  219. }
  220. static void serial_out(struct uart_sio_port *up, int offset, int value)
  221. {
  222. if (!offset)
  223. return;
  224. __sio_out(value, offset);
  225. }
  226. static void m32r_sio_stop_tx(struct uart_port *port)
  227. {
  228. struct uart_sio_port *up = (struct uart_sio_port *)port;
  229. if (up->ier & UART_IER_THRI) {
  230. up->ier &= ~UART_IER_THRI;
  231. serial_out(up, UART_IER, up->ier);
  232. }
  233. }
  234. static void m32r_sio_start_tx(struct uart_port *port)
  235. {
  236. #ifdef CONFIG_SERIAL_M32R_PLDSIO
  237. struct uart_sio_port *up = (struct uart_sio_port *)port;
  238. struct circ_buf *xmit = &up->port.info->xmit;
  239. if (!(up->ier & UART_IER_THRI)) {
  240. up->ier |= UART_IER_THRI;
  241. serial_out(up, UART_IER, up->ier);
  242. serial_out(up, UART_TX, xmit->buf[xmit->tail]);
  243. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  244. up->port.icount.tx++;
  245. }
  246. while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
  247. #else
  248. struct uart_sio_port *up = (struct uart_sio_port *)port;
  249. if (!(up->ier & UART_IER_THRI)) {
  250. up->ier |= UART_IER_THRI;
  251. serial_out(up, UART_IER, up->ier);
  252. }
  253. #endif
  254. }
  255. static void m32r_sio_stop_rx(struct uart_port *port)
  256. {
  257. struct uart_sio_port *up = (struct uart_sio_port *)port;
  258. up->ier &= ~UART_IER_RLSI;
  259. up->port.read_status_mask &= ~UART_LSR_DR;
  260. serial_out(up, UART_IER, up->ier);
  261. }
  262. static void m32r_sio_enable_ms(struct uart_port *port)
  263. {
  264. struct uart_sio_port *up = (struct uart_sio_port *)port;
  265. up->ier |= UART_IER_MSI;
  266. serial_out(up, UART_IER, up->ier);
  267. }
  268. static void receive_chars(struct uart_sio_port *up, int *status)
  269. {
  270. struct tty_struct *tty = up->port.info->tty;
  271. unsigned char ch;
  272. unsigned char flag;
  273. int max_count = 256;
  274. do {
  275. ch = sio_in(up, SIORXB);
  276. flag = TTY_NORMAL;
  277. up->port.icount.rx++;
  278. if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
  279. UART_LSR_FE | UART_LSR_OE))) {
  280. /*
  281. * For statistics only
  282. */
  283. if (*status & UART_LSR_BI) {
  284. *status &= ~(UART_LSR_FE | UART_LSR_PE);
  285. up->port.icount.brk++;
  286. /*
  287. * We do the SysRQ and SAK checking
  288. * here because otherwise the break
  289. * may get masked by ignore_status_mask
  290. * or read_status_mask.
  291. */
  292. if (uart_handle_break(&up->port))
  293. goto ignore_char;
  294. } else if (*status & UART_LSR_PE)
  295. up->port.icount.parity++;
  296. else if (*status & UART_LSR_FE)
  297. up->port.icount.frame++;
  298. if (*status & UART_LSR_OE)
  299. up->port.icount.overrun++;
  300. /*
  301. * Mask off conditions which should be ingored.
  302. */
  303. *status &= up->port.read_status_mask;
  304. if (up->port.line == up->port.cons->index) {
  305. /* Recover the break flag from console xmit */
  306. *status |= up->lsr_break_flag;
  307. up->lsr_break_flag = 0;
  308. }
  309. if (*status & UART_LSR_BI) {
  310. DEBUG_INTR("handling break....");
  311. flag = TTY_BREAK;
  312. } else if (*status & UART_LSR_PE)
  313. flag = TTY_PARITY;
  314. else if (*status & UART_LSR_FE)
  315. flag = TTY_FRAME;
  316. }
  317. if (uart_handle_sysrq_char(&up->port, ch))
  318. goto ignore_char;
  319. if ((*status & up->port.ignore_status_mask) == 0)
  320. tty_insert_flip_char(tty, ch, flag);
  321. if (*status & UART_LSR_OE) {
  322. /*
  323. * Overrun is special, since it's reported
  324. * immediately, and doesn't affect the current
  325. * character.
  326. */
  327. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  328. }
  329. ignore_char:
  330. *status = serial_in(up, UART_LSR);
  331. } while ((*status & UART_LSR_DR) && (max_count-- > 0));
  332. tty_flip_buffer_push(tty);
  333. }
  334. static void transmit_chars(struct uart_sio_port *up)
  335. {
  336. struct circ_buf *xmit = &up->port.info->xmit;
  337. int count;
  338. if (up->port.x_char) {
  339. #ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
  340. serial_out(up, UART_TX, up->port.x_char);
  341. #endif
  342. up->port.icount.tx++;
  343. up->port.x_char = 0;
  344. return;
  345. }
  346. if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
  347. m32r_sio_stop_tx(&up->port);
  348. return;
  349. }
  350. count = up->port.fifosize;
  351. do {
  352. serial_out(up, UART_TX, xmit->buf[xmit->tail]);
  353. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  354. up->port.icount.tx++;
  355. if (uart_circ_empty(xmit))
  356. break;
  357. while (!serial_in(up, UART_LSR) & UART_LSR_THRE);
  358. } while (--count > 0);
  359. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  360. uart_write_wakeup(&up->port);
  361. DEBUG_INTR("THRE...");
  362. if (uart_circ_empty(xmit))
  363. m32r_sio_stop_tx(&up->port);
  364. }
  365. /*
  366. * This handles the interrupt from one port.
  367. */
  368. static inline void m32r_sio_handle_port(struct uart_sio_port *up,
  369. unsigned int status)
  370. {
  371. DEBUG_INTR("status = %x...", status);
  372. if (status & 0x04)
  373. receive_chars(up, &status);
  374. if (status & 0x01)
  375. transmit_chars(up);
  376. }
  377. /*
  378. * This is the serial driver's interrupt routine.
  379. *
  380. * Arjan thinks the old way was overly complex, so it got simplified.
  381. * Alan disagrees, saying that need the complexity to handle the weird
  382. * nature of ISA shared interrupts. (This is a special exception.)
  383. *
  384. * In order to handle ISA shared interrupts properly, we need to check
  385. * that all ports have been serviced, and therefore the ISA interrupt
  386. * line has been de-asserted.
  387. *
  388. * This means we need to loop through all ports. checking that they
  389. * don't have an interrupt pending.
  390. */
  391. static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id)
  392. {
  393. struct irq_info *i = dev_id;
  394. struct list_head *l, *end = NULL;
  395. int pass_counter = 0;
  396. DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
  397. #ifdef CONFIG_SERIAL_M32R_PLDSIO
  398. // if (irq == PLD_IRQ_SIO0_SND)
  399. // irq = PLD_IRQ_SIO0_RCV;
  400. #else
  401. if (irq == M32R_IRQ_SIO0_S)
  402. irq = M32R_IRQ_SIO0_R;
  403. #endif
  404. spin_lock(&i->lock);
  405. l = i->head;
  406. do {
  407. struct uart_sio_port *up;
  408. unsigned int sts;
  409. up = list_entry(l, struct uart_sio_port, list);
  410. sts = sio_in(up, SIOSTS);
  411. if (sts & 0x5) {
  412. spin_lock(&up->port.lock);
  413. m32r_sio_handle_port(up, sts);
  414. spin_unlock(&up->port.lock);
  415. end = NULL;
  416. } else if (end == NULL)
  417. end = l;
  418. l = l->next;
  419. if (l == i->head && pass_counter++ > PASS_LIMIT) {
  420. if (sts & 0xe0)
  421. sio_error(&sts);
  422. break;
  423. }
  424. } while (l != end);
  425. spin_unlock(&i->lock);
  426. DEBUG_INTR("end.\n");
  427. return IRQ_HANDLED;
  428. }
  429. /*
  430. * To support ISA shared interrupts, we need to have one interrupt
  431. * handler that ensures that the IRQ line has been deasserted
  432. * before returning. Failing to do this will result in the IRQ
  433. * line being stuck active, and, since ISA irqs are edge triggered,
  434. * no more IRQs will be seen.
  435. */
  436. static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
  437. {
  438. spin_lock_irq(&i->lock);
  439. if (!list_empty(i->head)) {
  440. if (i->head == &up->list)
  441. i->head = i->head->next;
  442. list_del(&up->list);
  443. } else {
  444. BUG_ON(i->head != &up->list);
  445. i->head = NULL;
  446. }
  447. spin_unlock_irq(&i->lock);
  448. }
  449. static int serial_link_irq_chain(struct uart_sio_port *up)
  450. {
  451. struct irq_info *i = irq_lists + up->port.irq;
  452. int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
  453. spin_lock_irq(&i->lock);
  454. if (i->head) {
  455. list_add(&up->list, i->head);
  456. spin_unlock_irq(&i->lock);
  457. ret = 0;
  458. } else {
  459. INIT_LIST_HEAD(&up->list);
  460. i->head = &up->list;
  461. spin_unlock_irq(&i->lock);
  462. ret = request_irq(up->port.irq, m32r_sio_interrupt,
  463. irq_flags, "SIO0-RX", i);
  464. ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
  465. irq_flags, "SIO0-TX", i);
  466. if (ret < 0)
  467. serial_do_unlink(i, up);
  468. }
  469. return ret;
  470. }
  471. static void serial_unlink_irq_chain(struct uart_sio_port *up)
  472. {
  473. struct irq_info *i = irq_lists + up->port.irq;
  474. BUG_ON(i->head == NULL);
  475. if (list_empty(i->head)) {
  476. free_irq(up->port.irq, i);
  477. free_irq(up->port.irq + 1, i);
  478. }
  479. serial_do_unlink(i, up);
  480. }
  481. /*
  482. * This function is used to handle ports that do not have an interrupt.
  483. */
  484. static void m32r_sio_timeout(unsigned long data)
  485. {
  486. struct uart_sio_port *up = (struct uart_sio_port *)data;
  487. unsigned int timeout;
  488. unsigned int sts;
  489. sts = sio_in(up, SIOSTS);
  490. if (sts & 0x5) {
  491. spin_lock(&up->port.lock);
  492. m32r_sio_handle_port(up, sts);
  493. spin_unlock(&up->port.lock);
  494. }
  495. timeout = up->port.timeout;
  496. timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
  497. mod_timer(&up->timer, jiffies + timeout);
  498. }
  499. static unsigned int m32r_sio_tx_empty(struct uart_port *port)
  500. {
  501. struct uart_sio_port *up = (struct uart_sio_port *)port;
  502. unsigned long flags;
  503. unsigned int ret;
  504. spin_lock_irqsave(&up->port.lock, flags);
  505. ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
  506. spin_unlock_irqrestore(&up->port.lock, flags);
  507. return ret;
  508. }
  509. static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
  510. {
  511. return 0;
  512. }
  513. static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
  514. {
  515. }
  516. static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
  517. {
  518. }
  519. static int m32r_sio_startup(struct uart_port *port)
  520. {
  521. struct uart_sio_port *up = (struct uart_sio_port *)port;
  522. int retval;
  523. sio_init();
  524. /*
  525. * If the "interrupt" for this port doesn't correspond with any
  526. * hardware interrupt, we use a timer-based system. The original
  527. * driver used to do this with IRQ0.
  528. */
  529. if (!is_real_interrupt(up->port.irq)) {
  530. unsigned int timeout = up->port.timeout;
  531. timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
  532. up->timer.data = (unsigned long)up;
  533. mod_timer(&up->timer, jiffies + timeout);
  534. } else {
  535. retval = serial_link_irq_chain(up);
  536. if (retval)
  537. return retval;
  538. }
  539. /*
  540. * Finally, enable interrupts. Note: Modem status interrupts
  541. * are set via set_termios(), which will be occurring imminently
  542. * anyway, so we don't enable them here.
  543. * - M32R_SIO: 0x0c
  544. * - M32R_PLDSIO: 0x04
  545. */
  546. up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
  547. sio_out(up, SIOTRCR, up->ier);
  548. /*
  549. * And clear the interrupt registers again for luck.
  550. */
  551. sio_reset();
  552. return 0;
  553. }
  554. static void m32r_sio_shutdown(struct uart_port *port)
  555. {
  556. struct uart_sio_port *up = (struct uart_sio_port *)port;
  557. /*
  558. * Disable interrupts from this port
  559. */
  560. up->ier = 0;
  561. sio_out(up, SIOTRCR, 0);
  562. /*
  563. * Disable break condition and FIFOs
  564. */
  565. sio_init();
  566. if (!is_real_interrupt(up->port.irq))
  567. del_timer_sync(&up->timer);
  568. else
  569. serial_unlink_irq_chain(up);
  570. }
  571. static unsigned int m32r_sio_get_divisor(struct uart_port *port,
  572. unsigned int baud)
  573. {
  574. return uart_get_divisor(port, baud);
  575. }
  576. static void m32r_sio_set_termios(struct uart_port *port,
  577. struct ktermios *termios, struct ktermios *old)
  578. {
  579. struct uart_sio_port *up = (struct uart_sio_port *)port;
  580. unsigned char cval = 0;
  581. unsigned long flags;
  582. unsigned int baud, quot;
  583. switch (termios->c_cflag & CSIZE) {
  584. case CS5:
  585. cval = UART_LCR_WLEN5;
  586. break;
  587. case CS6:
  588. cval = UART_LCR_WLEN6;
  589. break;
  590. case CS7:
  591. cval = UART_LCR_WLEN7;
  592. break;
  593. default:
  594. case CS8:
  595. cval = UART_LCR_WLEN8;
  596. break;
  597. }
  598. if (termios->c_cflag & CSTOPB)
  599. cval |= UART_LCR_STOP;
  600. if (termios->c_cflag & PARENB)
  601. cval |= UART_LCR_PARITY;
  602. if (!(termios->c_cflag & PARODD))
  603. cval |= UART_LCR_EPAR;
  604. #ifdef CMSPAR
  605. if (termios->c_cflag & CMSPAR)
  606. cval |= UART_LCR_SPAR;
  607. #endif
  608. /*
  609. * Ask the core to calculate the divisor for us.
  610. */
  611. #ifdef CONFIG_SERIAL_M32R_PLDSIO
  612. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
  613. #else
  614. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  615. #endif
  616. quot = m32r_sio_get_divisor(port, baud);
  617. /*
  618. * Ok, we're now changing the port state. Do it with
  619. * interrupts disabled.
  620. */
  621. spin_lock_irqsave(&up->port.lock, flags);
  622. sio_set_baud_rate(baud);
  623. /*
  624. * Update the per-port timeout.
  625. */
  626. uart_update_timeout(port, termios->c_cflag, baud);
  627. up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
  628. if (termios->c_iflag & INPCK)
  629. up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
  630. if (termios->c_iflag & (BRKINT | PARMRK))
  631. up->port.read_status_mask |= UART_LSR_BI;
  632. /*
  633. * Characteres to ignore
  634. */
  635. up->port.ignore_status_mask = 0;
  636. if (termios->c_iflag & IGNPAR)
  637. up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
  638. if (termios->c_iflag & IGNBRK) {
  639. up->port.ignore_status_mask |= UART_LSR_BI;
  640. /*
  641. * If we're ignoring parity and break indicators,
  642. * ignore overruns too (for real raw support).
  643. */
  644. if (termios->c_iflag & IGNPAR)
  645. up->port.ignore_status_mask |= UART_LSR_OE;
  646. }
  647. /*
  648. * ignore all characters if CREAD is not set
  649. */
  650. if ((termios->c_cflag & CREAD) == 0)
  651. up->port.ignore_status_mask |= UART_LSR_DR;
  652. /*
  653. * CTS flow control flag and modem status interrupts
  654. */
  655. up->ier &= ~UART_IER_MSI;
  656. if (UART_ENABLE_MS(&up->port, termios->c_cflag))
  657. up->ier |= UART_IER_MSI;
  658. serial_out(up, UART_IER, up->ier);
  659. up->lcr = cval; /* Save LCR */
  660. spin_unlock_irqrestore(&up->port.lock, flags);
  661. }
  662. static void m32r_sio_pm(struct uart_port *port, unsigned int state,
  663. unsigned int oldstate)
  664. {
  665. struct uart_sio_port *up = (struct uart_sio_port *)port;
  666. if (up->pm)
  667. up->pm(port, state, oldstate);
  668. }
  669. /*
  670. * Resource handling. This is complicated by the fact that resources
  671. * depend on the port type. Maybe we should be claiming the standard
  672. * 8250 ports, and then trying to get other resources as necessary?
  673. */
  674. static int
  675. m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
  676. {
  677. unsigned int size = 8 << up->port.regshift;
  678. #ifndef CONFIG_SERIAL_M32R_PLDSIO
  679. unsigned long start;
  680. #endif
  681. int ret = 0;
  682. switch (up->port.iotype) {
  683. case UPIO_MEM:
  684. if (up->port.mapbase) {
  685. #ifdef CONFIG_SERIAL_M32R_PLDSIO
  686. *res = request_mem_region(up->port.mapbase, size, "serial");
  687. #else
  688. start = up->port.mapbase;
  689. *res = request_mem_region(start, size, "serial");
  690. #endif
  691. if (!*res)
  692. ret = -EBUSY;
  693. }
  694. break;
  695. case UPIO_PORT:
  696. *res = request_region(up->port.iobase, size, "serial");
  697. if (!*res)
  698. ret = -EBUSY;
  699. break;
  700. }
  701. return ret;
  702. }
  703. static void m32r_sio_release_port(struct uart_port *port)
  704. {
  705. struct uart_sio_port *up = (struct uart_sio_port *)port;
  706. unsigned long start, offset = 0, size = 0;
  707. size <<= up->port.regshift;
  708. switch (up->port.iotype) {
  709. case UPIO_MEM:
  710. if (up->port.mapbase) {
  711. /*
  712. * Unmap the area.
  713. */
  714. iounmap(up->port.membase);
  715. up->port.membase = NULL;
  716. start = up->port.mapbase;
  717. if (size)
  718. release_mem_region(start + offset, size);
  719. release_mem_region(start, 8 << up->port.regshift);
  720. }
  721. break;
  722. case UPIO_PORT:
  723. start = up->port.iobase;
  724. if (size)
  725. release_region(start + offset, size);
  726. release_region(start + offset, 8 << up->port.regshift);
  727. break;
  728. default:
  729. break;
  730. }
  731. }
  732. static int m32r_sio_request_port(struct uart_port *port)
  733. {
  734. struct uart_sio_port *up = (struct uart_sio_port *)port;
  735. struct resource *res = NULL;
  736. int ret = 0;
  737. ret = m32r_sio_request_std_resource(up, &res);
  738. /*
  739. * If we have a mapbase, then request that as well.
  740. */
  741. if (ret == 0 && up->port.flags & UPF_IOREMAP) {
  742. int size = res->end - res->start + 1;
  743. up->port.membase = ioremap(up->port.mapbase, size);
  744. if (!up->port.membase)
  745. ret = -ENOMEM;
  746. }
  747. if (ret < 0) {
  748. if (res)
  749. release_resource(res);
  750. }
  751. return ret;
  752. }
  753. static void m32r_sio_config_port(struct uart_port *port, int flags)
  754. {
  755. struct uart_sio_port *up = (struct uart_sio_port *)port;
  756. spin_lock_irqsave(&up->port.lock, flags);
  757. up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
  758. up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
  759. spin_unlock_irqrestore(&up->port.lock, flags);
  760. }
  761. static int
  762. m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
  763. {
  764. if (ser->irq >= NR_IRQS || ser->irq < 0 ||
  765. ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
  766. ser->type >= ARRAY_SIZE(uart_config))
  767. return -EINVAL;
  768. return 0;
  769. }
  770. static const char *
  771. m32r_sio_type(struct uart_port *port)
  772. {
  773. int type = port->type;
  774. if (type >= ARRAY_SIZE(uart_config))
  775. type = 0;
  776. return uart_config[type].name;
  777. }
  778. static struct uart_ops m32r_sio_pops = {
  779. .tx_empty = m32r_sio_tx_empty,
  780. .set_mctrl = m32r_sio_set_mctrl,
  781. .get_mctrl = m32r_sio_get_mctrl,
  782. .stop_tx = m32r_sio_stop_tx,
  783. .start_tx = m32r_sio_start_tx,
  784. .stop_rx = m32r_sio_stop_rx,
  785. .enable_ms = m32r_sio_enable_ms,
  786. .break_ctl = m32r_sio_break_ctl,
  787. .startup = m32r_sio_startup,
  788. .shutdown = m32r_sio_shutdown,
  789. .set_termios = m32r_sio_set_termios,
  790. .pm = m32r_sio_pm,
  791. .type = m32r_sio_type,
  792. .release_port = m32r_sio_release_port,
  793. .request_port = m32r_sio_request_port,
  794. .config_port = m32r_sio_config_port,
  795. .verify_port = m32r_sio_verify_port,
  796. };
  797. static struct uart_sio_port m32r_sio_ports[UART_NR];
  798. static void __init m32r_sio_init_ports(void)
  799. {
  800. struct uart_sio_port *up;
  801. static int first = 1;
  802. int i;
  803. if (!first)
  804. return;
  805. first = 0;
  806. for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
  807. i++, up++) {
  808. up->port.iobase = old_serial_port[i].port;
  809. up->port.irq = irq_canonicalize(old_serial_port[i].irq);
  810. up->port.uartclk = old_serial_port[i].baud_base * 16;
  811. up->port.flags = old_serial_port[i].flags;
  812. up->port.membase = old_serial_port[i].iomem_base;
  813. up->port.iotype = old_serial_port[i].io_type;
  814. up->port.regshift = old_serial_port[i].iomem_reg_shift;
  815. up->port.ops = &m32r_sio_pops;
  816. }
  817. }
  818. static void __init m32r_sio_register_ports(struct uart_driver *drv)
  819. {
  820. int i;
  821. m32r_sio_init_ports();
  822. for (i = 0; i < UART_NR; i++) {
  823. struct uart_sio_port *up = &m32r_sio_ports[i];
  824. up->port.line = i;
  825. up->port.ops = &m32r_sio_pops;
  826. init_timer(&up->timer);
  827. up->timer.function = m32r_sio_timeout;
  828. /*
  829. * ALPHA_KLUDGE_MCR needs to be killed.
  830. */
  831. up->mcr_mask = ~ALPHA_KLUDGE_MCR;
  832. up->mcr_force = ALPHA_KLUDGE_MCR;
  833. uart_add_one_port(drv, &up->port);
  834. }
  835. }
  836. #ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
  837. /*
  838. * Wait for transmitter & holding register to empty
  839. */
  840. static inline void wait_for_xmitr(struct uart_sio_port *up)
  841. {
  842. unsigned int status, tmout = 10000;
  843. /* Wait up to 10ms for the character(s) to be sent. */
  844. do {
  845. status = sio_in(up, SIOSTS);
  846. if (--tmout == 0)
  847. break;
  848. udelay(1);
  849. } while ((status & UART_EMPTY) != UART_EMPTY);
  850. /* Wait up to 1s for flow control if necessary */
  851. if (up->port.flags & UPF_CONS_FLOW) {
  852. tmout = 1000000;
  853. while (--tmout)
  854. udelay(1);
  855. }
  856. }
  857. static void m32r_sio_console_putchar(struct uart_port *port, int ch)
  858. {
  859. struct uart_sio_port *up = (struct uart_sio_port *)port;
  860. wait_for_xmitr(up);
  861. sio_out(up, SIOTXB, ch);
  862. }
  863. /*
  864. * Print a string to the serial port trying not to disturb
  865. * any possible real use of the port...
  866. *
  867. * The console_lock must be held when we get here.
  868. */
  869. static void m32r_sio_console_write(struct console *co, const char *s,
  870. unsigned int count)
  871. {
  872. struct uart_sio_port *up = &m32r_sio_ports[co->index];
  873. unsigned int ier;
  874. /*
  875. * First save the UER then disable the interrupts
  876. */
  877. ier = sio_in(up, SIOTRCR);
  878. sio_out(up, SIOTRCR, 0);
  879. uart_console_write(&up->port, s, count, m32r_sio_console_putchar);
  880. /*
  881. * Finally, wait for transmitter to become empty
  882. * and restore the IER
  883. */
  884. wait_for_xmitr(up);
  885. sio_out(up, SIOTRCR, ier);
  886. }
  887. static int __init m32r_sio_console_setup(struct console *co, char *options)
  888. {
  889. struct uart_port *port;
  890. int baud = 9600;
  891. int bits = 8;
  892. int parity = 'n';
  893. int flow = 'n';
  894. /*
  895. * Check whether an invalid uart number has been specified, and
  896. * if so, search for the first available port that does have
  897. * console support.
  898. */
  899. if (co->index >= UART_NR)
  900. co->index = 0;
  901. port = &m32r_sio_ports[co->index].port;
  902. /*
  903. * Temporary fix.
  904. */
  905. spin_lock_init(&port->lock);
  906. if (options)
  907. uart_parse_options(options, &baud, &parity, &bits, &flow);
  908. return uart_set_options(port, co, baud, parity, bits, flow);
  909. }
  910. static struct uart_driver m32r_sio_reg;
  911. static struct console m32r_sio_console = {
  912. .name = "ttyS",
  913. .write = m32r_sio_console_write,
  914. .device = uart_console_device,
  915. .setup = m32r_sio_console_setup,
  916. .flags = CON_PRINTBUFFER,
  917. .index = -1,
  918. .data = &m32r_sio_reg,
  919. };
  920. static int __init m32r_sio_console_init(void)
  921. {
  922. sio_reset();
  923. sio_init();
  924. m32r_sio_init_ports();
  925. register_console(&m32r_sio_console);
  926. return 0;
  927. }
  928. console_initcall(m32r_sio_console_init);
  929. #define M32R_SIO_CONSOLE &m32r_sio_console
  930. #else
  931. #define M32R_SIO_CONSOLE NULL
  932. #endif
  933. static struct uart_driver m32r_sio_reg = {
  934. .owner = THIS_MODULE,
  935. .driver_name = "sio",
  936. .dev_name = "ttyS",
  937. .major = TTY_MAJOR,
  938. .minor = 64,
  939. .nr = UART_NR,
  940. .cons = M32R_SIO_CONSOLE,
  941. };
  942. /**
  943. * m32r_sio_suspend_port - suspend one serial port
  944. * @line: serial line number
  945. *
  946. * Suspend one serial port.
  947. */
  948. void m32r_sio_suspend_port(int line)
  949. {
  950. uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
  951. }
  952. /**
  953. * m32r_sio_resume_port - resume one serial port
  954. * @line: serial line number
  955. *
  956. * Resume one serial port.
  957. */
  958. void m32r_sio_resume_port(int line)
  959. {
  960. uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
  961. }
  962. static int __init m32r_sio_init(void)
  963. {
  964. int ret, i;
  965. printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.1.1.1 $ ");
  966. for (i = 0; i < NR_IRQS; i++)
  967. spin_lock_init(&irq_lists[i].lock);
  968. ret = uart_register_driver(&m32r_sio_reg);
  969. if (ret >= 0)
  970. m32r_sio_register_ports(&m32r_sio_reg);
  971. return ret;
  972. }
  973. static void __exit m32r_sio_exit(void)
  974. {
  975. int i;
  976. for (i = 0; i < UART_NR; i++)
  977. uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
  978. uart_unregister_driver(&m32r_sio_reg);
  979. }
  980. module_init(m32r_sio_init);
  981. module_exit(m32r_sio_exit);
  982. EXPORT_SYMBOL(m32r_sio_suspend_port);
  983. EXPORT_SYMBOL(m32r_sio_resume_port);
  984. MODULE_LICENSE("GPL");
  985. MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.1.1.1 $");