8250_pci.c 60 KB

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  1. /*
  2. * linux/drivers/char/8250_pci.c
  3. *
  4. * Probe module for 8250/16550-type PCI serial ports.
  5. *
  6. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7. *
  8. * Copyright (C) 2001 Russell King, All Rights Reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License.
  13. *
  14. * $Id: 8250_pci.c,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/pci.h>
  19. #include <linux/string.h>
  20. #include <linux/kernel.h>
  21. #include <linux/slab.h>
  22. #include <linux/delay.h>
  23. #include <linux/tty.h>
  24. #include <linux/serial_core.h>
  25. #include <linux/8250_pci.h>
  26. #include <linux/bitops.h>
  27. #include <asm/byteorder.h>
  28. #include <asm/io.h>
  29. #include "8250.h"
  30. #undef SERIAL_DEBUG_PCI
  31. /*
  32. * init function returns:
  33. * > 0 - number of ports
  34. * = 0 - use board->num_ports
  35. * < 0 - error
  36. */
  37. struct pci_serial_quirk {
  38. u32 vendor;
  39. u32 device;
  40. u32 subvendor;
  41. u32 subdevice;
  42. int (*init)(struct pci_dev *dev);
  43. int (*setup)(struct serial_private *, struct pciserial_board *,
  44. struct uart_port *, int);
  45. void (*exit)(struct pci_dev *dev);
  46. };
  47. #define PCI_NUM_BAR_RESOURCES 6
  48. struct serial_private {
  49. struct pci_dev *dev;
  50. unsigned int nr;
  51. void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
  52. struct pci_serial_quirk *quirk;
  53. int line[0];
  54. };
  55. static void moan_device(const char *str, struct pci_dev *dev)
  56. {
  57. printk(KERN_WARNING "%s: %s\n"
  58. KERN_WARNING "Please send the output of lspci -vv, this\n"
  59. KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  60. KERN_WARNING "manufacturer and name of serial board or\n"
  61. KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  62. pci_name(dev), str, dev->vendor, dev->device,
  63. dev->subsystem_vendor, dev->subsystem_device);
  64. }
  65. static int
  66. setup_port(struct serial_private *priv, struct uart_port *port,
  67. int bar, int offset, int regshift)
  68. {
  69. struct pci_dev *dev = priv->dev;
  70. unsigned long base, len;
  71. if (bar >= PCI_NUM_BAR_RESOURCES)
  72. return -EINVAL;
  73. base = pci_resource_start(dev, bar);
  74. if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  75. len = pci_resource_len(dev, bar);
  76. if (!priv->remapped_bar[bar])
  77. priv->remapped_bar[bar] = ioremap(base, len);
  78. if (!priv->remapped_bar[bar])
  79. return -ENOMEM;
  80. port->iotype = UPIO_MEM;
  81. port->iobase = 0;
  82. port->mapbase = base + offset;
  83. port->membase = priv->remapped_bar[bar] + offset;
  84. port->regshift = regshift;
  85. } else {
  86. port->iotype = UPIO_PORT;
  87. port->iobase = base + offset;
  88. port->mapbase = 0;
  89. port->membase = NULL;
  90. port->regshift = 0;
  91. }
  92. return 0;
  93. }
  94. /*
  95. * AFAVLAB uses a different mixture of BARs and offsets
  96. * Not that ugly ;) -- HW
  97. */
  98. static int
  99. afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
  100. struct uart_port *port, int idx)
  101. {
  102. unsigned int bar, offset = board->first_offset;
  103. bar = FL_GET_BASE(board->flags);
  104. if (idx < 4)
  105. bar += idx;
  106. else {
  107. bar = 4;
  108. offset += (idx - 4) * board->uart_offset;
  109. }
  110. return setup_port(priv, port, bar, offset, board->reg_shift);
  111. }
  112. /*
  113. * HP's Remote Management Console. The Diva chip came in several
  114. * different versions. N-class, L2000 and A500 have two Diva chips, each
  115. * with 3 UARTs (the third UART on the second chip is unused). Superdome
  116. * and Keystone have one Diva chip with 3 UARTs. Some later machines have
  117. * one Diva chip, but it has been expanded to 5 UARTs.
  118. */
  119. static int pci_hp_diva_init(struct pci_dev *dev)
  120. {
  121. int rc = 0;
  122. switch (dev->subsystem_device) {
  123. case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
  124. case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
  125. case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
  126. case PCI_DEVICE_ID_HP_DIVA_EVEREST:
  127. rc = 3;
  128. break;
  129. case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
  130. rc = 2;
  131. break;
  132. case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
  133. rc = 4;
  134. break;
  135. case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
  136. case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
  137. rc = 1;
  138. break;
  139. }
  140. return rc;
  141. }
  142. /*
  143. * HP's Diva chip puts the 4th/5th serial port further out, and
  144. * some serial ports are supposed to be hidden on certain models.
  145. */
  146. static int
  147. pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
  148. struct uart_port *port, int idx)
  149. {
  150. unsigned int offset = board->first_offset;
  151. unsigned int bar = FL_GET_BASE(board->flags);
  152. switch (priv->dev->subsystem_device) {
  153. case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
  154. if (idx == 3)
  155. idx++;
  156. break;
  157. case PCI_DEVICE_ID_HP_DIVA_EVEREST:
  158. if (idx > 0)
  159. idx++;
  160. if (idx > 2)
  161. idx++;
  162. break;
  163. }
  164. if (idx > 2)
  165. offset = 0x18;
  166. offset += idx * board->uart_offset;
  167. return setup_port(priv, port, bar, offset, board->reg_shift);
  168. }
  169. /*
  170. * Added for EKF Intel i960 serial boards
  171. */
  172. static int pci_inteli960ni_init(struct pci_dev *dev)
  173. {
  174. unsigned long oldval;
  175. if (!(dev->subsystem_device & 0x1000))
  176. return -ENODEV;
  177. /* is firmware started? */
  178. pci_read_config_dword(dev, 0x44, (void*) &oldval);
  179. if (oldval == 0x00001000L) { /* RESET value */
  180. printk(KERN_DEBUG "Local i960 firmware missing");
  181. return -ENODEV;
  182. }
  183. return 0;
  184. }
  185. /*
  186. * Some PCI serial cards using the PLX 9050 PCI interface chip require
  187. * that the card interrupt be explicitly enabled or disabled. This
  188. * seems to be mainly needed on card using the PLX which also use I/O
  189. * mapped memory.
  190. */
  191. static int pci_plx9050_init(struct pci_dev *dev)
  192. {
  193. u8 irq_config;
  194. void __iomem *p;
  195. if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
  196. moan_device("no memory in bar 0", dev);
  197. return 0;
  198. }
  199. irq_config = 0x41;
  200. if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
  201. dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
  202. irq_config = 0x43;
  203. }
  204. if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
  205. (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
  206. /*
  207. * As the megawolf cards have the int pins active
  208. * high, and have 2 UART chips, both ints must be
  209. * enabled on the 9050. Also, the UARTS are set in
  210. * 16450 mode by default, so we have to enable the
  211. * 16C950 'enhanced' mode so that we can use the
  212. * deep FIFOs
  213. */
  214. irq_config = 0x5b;
  215. }
  216. /*
  217. * enable/disable interrupts
  218. */
  219. p = ioremap(pci_resource_start(dev, 0), 0x80);
  220. if (p == NULL)
  221. return -ENOMEM;
  222. writel(irq_config, p + 0x4c);
  223. /*
  224. * Read the register back to ensure that it took effect.
  225. */
  226. readl(p + 0x4c);
  227. iounmap(p);
  228. return 0;
  229. }
  230. static void __devexit pci_plx9050_exit(struct pci_dev *dev)
  231. {
  232. u8 __iomem *p;
  233. if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
  234. return;
  235. /*
  236. * disable interrupts
  237. */
  238. p = ioremap(pci_resource_start(dev, 0), 0x80);
  239. if (p != NULL) {
  240. writel(0, p + 0x4c);
  241. /*
  242. * Read the register back to ensure that it took effect.
  243. */
  244. readl(p + 0x4c);
  245. iounmap(p);
  246. }
  247. }
  248. /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
  249. static int
  250. sbs_setup(struct serial_private *priv, struct pciserial_board *board,
  251. struct uart_port *port, int idx)
  252. {
  253. unsigned int bar, offset = board->first_offset;
  254. bar = 0;
  255. if (idx < 4) {
  256. /* first four channels map to 0, 0x100, 0x200, 0x300 */
  257. offset += idx * board->uart_offset;
  258. } else if (idx < 8) {
  259. /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
  260. offset += idx * board->uart_offset + 0xC00;
  261. } else /* we have only 8 ports on PMC-OCTALPRO */
  262. return 1;
  263. return setup_port(priv, port, bar, offset, board->reg_shift);
  264. }
  265. /*
  266. * This does initialization for PMC OCTALPRO cards:
  267. * maps the device memory, resets the UARTs (needed, bc
  268. * if the module is removed and inserted again, the card
  269. * is in the sleep mode) and enables global interrupt.
  270. */
  271. /* global control register offset for SBS PMC-OctalPro */
  272. #define OCT_REG_CR_OFF 0x500
  273. static int sbs_init(struct pci_dev *dev)
  274. {
  275. u8 __iomem *p;
  276. p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
  277. if (p == NULL)
  278. return -ENOMEM;
  279. /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
  280. writeb(0x10,p + OCT_REG_CR_OFF);
  281. udelay(50);
  282. writeb(0x0,p + OCT_REG_CR_OFF);
  283. /* Set bit-2 (INTENABLE) of Control Register */
  284. writeb(0x4, p + OCT_REG_CR_OFF);
  285. iounmap(p);
  286. return 0;
  287. }
  288. /*
  289. * Disables the global interrupt of PMC-OctalPro
  290. */
  291. static void __devexit sbs_exit(struct pci_dev *dev)
  292. {
  293. u8 __iomem *p;
  294. p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
  295. if (p != NULL) {
  296. writeb(0, p + OCT_REG_CR_OFF);
  297. }
  298. iounmap(p);
  299. }
  300. /*
  301. * SIIG serial cards have an PCI interface chip which also controls
  302. * the UART clocking frequency. Each UART can be clocked independently
  303. * (except cards equiped with 4 UARTs) and initial clocking settings
  304. * are stored in the EEPROM chip. It can cause problems because this
  305. * version of serial driver doesn't support differently clocked UART's
  306. * on single PCI card. To prevent this, initialization functions set
  307. * high frequency clocking for all UART's on given card. It is safe (I
  308. * hope) because it doesn't touch EEPROM settings to prevent conflicts
  309. * with other OSes (like M$ DOS).
  310. *
  311. * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
  312. *
  313. * There is two family of SIIG serial cards with different PCI
  314. * interface chip and different configuration methods:
  315. * - 10x cards have control registers in IO and/or memory space;
  316. * - 20x cards have control registers in standard PCI configuration space.
  317. *
  318. * Note: all 10x cards have PCI device ids 0x10..
  319. * all 20x cards have PCI device ids 0x20..
  320. *
  321. * There are also Quartet Serial cards which use Oxford Semiconductor
  322. * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
  323. *
  324. * Note: some SIIG cards are probed by the parport_serial object.
  325. */
  326. #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
  327. #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
  328. static int pci_siig10x_init(struct pci_dev *dev)
  329. {
  330. u16 data;
  331. void __iomem *p;
  332. switch (dev->device & 0xfff8) {
  333. case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
  334. data = 0xffdf;
  335. break;
  336. case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
  337. data = 0xf7ff;
  338. break;
  339. default: /* 1S1P, 4S */
  340. data = 0xfffb;
  341. break;
  342. }
  343. p = ioremap(pci_resource_start(dev, 0), 0x80);
  344. if (p == NULL)
  345. return -ENOMEM;
  346. writew(readw(p + 0x28) & data, p + 0x28);
  347. readw(p + 0x28);
  348. iounmap(p);
  349. return 0;
  350. }
  351. #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
  352. #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
  353. static int pci_siig20x_init(struct pci_dev *dev)
  354. {
  355. u8 data;
  356. /* Change clock frequency for the first UART. */
  357. pci_read_config_byte(dev, 0x6f, &data);
  358. pci_write_config_byte(dev, 0x6f, data & 0xef);
  359. /* If this card has 2 UART, we have to do the same with second UART. */
  360. if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
  361. ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
  362. pci_read_config_byte(dev, 0x73, &data);
  363. pci_write_config_byte(dev, 0x73, data & 0xef);
  364. }
  365. return 0;
  366. }
  367. static int pci_siig_init(struct pci_dev *dev)
  368. {
  369. unsigned int type = dev->device & 0xff00;
  370. if (type == 0x1000)
  371. return pci_siig10x_init(dev);
  372. else if (type == 0x2000)
  373. return pci_siig20x_init(dev);
  374. moan_device("Unknown SIIG card", dev);
  375. return -ENODEV;
  376. }
  377. static int pci_siig_setup(struct serial_private *priv,
  378. struct pciserial_board *board,
  379. struct uart_port *port, int idx)
  380. {
  381. unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
  382. if (idx > 3) {
  383. bar = 4;
  384. offset = (idx - 4) * 8;
  385. }
  386. return setup_port(priv, port, bar, offset, 0);
  387. }
  388. /*
  389. * Timedia has an explosion of boards, and to avoid the PCI table from
  390. * growing *huge*, we use this function to collapse some 70 entries
  391. * in the PCI table into one, for sanity's and compactness's sake.
  392. */
  393. static const unsigned short timedia_single_port[] = {
  394. 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
  395. };
  396. static const unsigned short timedia_dual_port[] = {
  397. 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
  398. 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
  399. 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
  400. 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
  401. 0xD079, 0
  402. };
  403. static const unsigned short timedia_quad_port[] = {
  404. 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
  405. 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
  406. 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
  407. 0xB157, 0
  408. };
  409. static const unsigned short timedia_eight_port[] = {
  410. 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
  411. 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
  412. };
  413. static const struct timedia_struct {
  414. int num;
  415. const unsigned short *ids;
  416. } timedia_data[] = {
  417. { 1, timedia_single_port },
  418. { 2, timedia_dual_port },
  419. { 4, timedia_quad_port },
  420. { 8, timedia_eight_port }
  421. };
  422. static int pci_timedia_init(struct pci_dev *dev)
  423. {
  424. const unsigned short *ids;
  425. int i, j;
  426. for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
  427. ids = timedia_data[i].ids;
  428. for (j = 0; ids[j]; j++)
  429. if (dev->subsystem_device == ids[j])
  430. return timedia_data[i].num;
  431. }
  432. return 0;
  433. }
  434. /*
  435. * Timedia/SUNIX uses a mixture of BARs and offsets
  436. * Ugh, this is ugly as all hell --- TYT
  437. */
  438. static int
  439. pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
  440. struct uart_port *port, int idx)
  441. {
  442. unsigned int bar = 0, offset = board->first_offset;
  443. switch (idx) {
  444. case 0:
  445. bar = 0;
  446. break;
  447. case 1:
  448. offset = board->uart_offset;
  449. bar = 0;
  450. break;
  451. case 2:
  452. bar = 1;
  453. break;
  454. case 3:
  455. offset = board->uart_offset;
  456. /* FALLTHROUGH */
  457. case 4: /* BAR 2 */
  458. case 5: /* BAR 3 */
  459. case 6: /* BAR 4 */
  460. case 7: /* BAR 5 */
  461. bar = idx - 2;
  462. }
  463. return setup_port(priv, port, bar, offset, board->reg_shift);
  464. }
  465. /*
  466. * Some Titan cards are also a little weird
  467. */
  468. static int
  469. titan_400l_800l_setup(struct serial_private *priv,
  470. struct pciserial_board *board,
  471. struct uart_port *port, int idx)
  472. {
  473. unsigned int bar, offset = board->first_offset;
  474. switch (idx) {
  475. case 0:
  476. bar = 1;
  477. break;
  478. case 1:
  479. bar = 2;
  480. break;
  481. default:
  482. bar = 4;
  483. offset = (idx - 2) * board->uart_offset;
  484. }
  485. return setup_port(priv, port, bar, offset, board->reg_shift);
  486. }
  487. static int pci_xircom_init(struct pci_dev *dev)
  488. {
  489. msleep(100);
  490. return 0;
  491. }
  492. static int pci_netmos_init(struct pci_dev *dev)
  493. {
  494. /* subdevice 0x00PS means <P> parallel, <S> serial */
  495. unsigned int num_serial = dev->subsystem_device & 0xf;
  496. if (num_serial == 0)
  497. return -ENODEV;
  498. return num_serial;
  499. }
  500. static int
  501. pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
  502. struct uart_port *port, int idx)
  503. {
  504. unsigned int bar, offset = board->first_offset, maxnr;
  505. bar = FL_GET_BASE(board->flags);
  506. if (board->flags & FL_BASE_BARS)
  507. bar += idx;
  508. else
  509. offset += idx * board->uart_offset;
  510. maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
  511. (board->reg_shift + 3);
  512. if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
  513. return 1;
  514. return setup_port(priv, port, bar, offset, board->reg_shift);
  515. }
  516. /* This should be in linux/pci_ids.h */
  517. #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
  518. #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
  519. #define PCI_DEVICE_ID_OCTPRO 0x0001
  520. #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
  521. #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
  522. #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
  523. #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
  524. /*
  525. * Master list of serial port init/setup/exit quirks.
  526. * This does not describe the general nature of the port.
  527. * (ie, baud base, number and location of ports, etc)
  528. *
  529. * This list is ordered alphabetically by vendor then device.
  530. * Specific entries must come before more generic entries.
  531. */
  532. static struct pci_serial_quirk pci_serial_quirks[] = {
  533. /*
  534. * AFAVLAB cards - these may be called via parport_serial
  535. * It is not clear whether this applies to all products.
  536. */
  537. {
  538. .vendor = PCI_VENDOR_ID_AFAVLAB,
  539. .device = PCI_ANY_ID,
  540. .subvendor = PCI_ANY_ID,
  541. .subdevice = PCI_ANY_ID,
  542. .setup = afavlab_setup,
  543. },
  544. /*
  545. * HP Diva
  546. */
  547. {
  548. .vendor = PCI_VENDOR_ID_HP,
  549. .device = PCI_DEVICE_ID_HP_DIVA,
  550. .subvendor = PCI_ANY_ID,
  551. .subdevice = PCI_ANY_ID,
  552. .init = pci_hp_diva_init,
  553. .setup = pci_hp_diva_setup,
  554. },
  555. /*
  556. * Intel
  557. */
  558. {
  559. .vendor = PCI_VENDOR_ID_INTEL,
  560. .device = PCI_DEVICE_ID_INTEL_80960_RP,
  561. .subvendor = 0xe4bf,
  562. .subdevice = PCI_ANY_ID,
  563. .init = pci_inteli960ni_init,
  564. .setup = pci_default_setup,
  565. },
  566. /*
  567. * Panacom
  568. */
  569. {
  570. .vendor = PCI_VENDOR_ID_PANACOM,
  571. .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
  572. .subvendor = PCI_ANY_ID,
  573. .subdevice = PCI_ANY_ID,
  574. .init = pci_plx9050_init,
  575. .setup = pci_default_setup,
  576. .exit = __devexit_p(pci_plx9050_exit),
  577. },
  578. {
  579. .vendor = PCI_VENDOR_ID_PANACOM,
  580. .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
  581. .subvendor = PCI_ANY_ID,
  582. .subdevice = PCI_ANY_ID,
  583. .init = pci_plx9050_init,
  584. .setup = pci_default_setup,
  585. .exit = __devexit_p(pci_plx9050_exit),
  586. },
  587. /*
  588. * PLX
  589. */
  590. {
  591. .vendor = PCI_VENDOR_ID_PLX,
  592. .device = PCI_DEVICE_ID_PLX_9030,
  593. .subvendor = PCI_SUBVENDOR_ID_PERLE,
  594. .subdevice = PCI_ANY_ID,
  595. .setup = pci_default_setup,
  596. },
  597. {
  598. .vendor = PCI_VENDOR_ID_PLX,
  599. .device = PCI_DEVICE_ID_PLX_9050,
  600. .subvendor = PCI_SUBVENDOR_ID_EXSYS,
  601. .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
  602. .init = pci_plx9050_init,
  603. .setup = pci_default_setup,
  604. .exit = __devexit_p(pci_plx9050_exit),
  605. },
  606. {
  607. .vendor = PCI_VENDOR_ID_PLX,
  608. .device = PCI_DEVICE_ID_PLX_9050,
  609. .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
  610. .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
  611. .init = pci_plx9050_init,
  612. .setup = pci_default_setup,
  613. .exit = __devexit_p(pci_plx9050_exit),
  614. },
  615. {
  616. .vendor = PCI_VENDOR_ID_PLX,
  617. .device = PCI_DEVICE_ID_PLX_ROMULUS,
  618. .subvendor = PCI_VENDOR_ID_PLX,
  619. .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
  620. .init = pci_plx9050_init,
  621. .setup = pci_default_setup,
  622. .exit = __devexit_p(pci_plx9050_exit),
  623. },
  624. /*
  625. * SBS Technologies, Inc., PMC-OCTALPRO 232
  626. */
  627. {
  628. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  629. .device = PCI_DEVICE_ID_OCTPRO,
  630. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  631. .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
  632. .init = sbs_init,
  633. .setup = sbs_setup,
  634. .exit = __devexit_p(sbs_exit),
  635. },
  636. /*
  637. * SBS Technologies, Inc., PMC-OCTALPRO 422
  638. */
  639. {
  640. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  641. .device = PCI_DEVICE_ID_OCTPRO,
  642. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  643. .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
  644. .init = sbs_init,
  645. .setup = sbs_setup,
  646. .exit = __devexit_p(sbs_exit),
  647. },
  648. /*
  649. * SBS Technologies, Inc., P-Octal 232
  650. */
  651. {
  652. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  653. .device = PCI_DEVICE_ID_OCTPRO,
  654. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  655. .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
  656. .init = sbs_init,
  657. .setup = sbs_setup,
  658. .exit = __devexit_p(sbs_exit),
  659. },
  660. /*
  661. * SBS Technologies, Inc., P-Octal 422
  662. */
  663. {
  664. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  665. .device = PCI_DEVICE_ID_OCTPRO,
  666. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  667. .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
  668. .init = sbs_init,
  669. .setup = sbs_setup,
  670. .exit = __devexit_p(sbs_exit),
  671. },
  672. /*
  673. * SIIG cards - these may be called via parport_serial
  674. */
  675. {
  676. .vendor = PCI_VENDOR_ID_SIIG,
  677. .device = PCI_ANY_ID,
  678. .subvendor = PCI_ANY_ID,
  679. .subdevice = PCI_ANY_ID,
  680. .init = pci_siig_init,
  681. .setup = pci_siig_setup,
  682. },
  683. /*
  684. * Titan cards
  685. */
  686. {
  687. .vendor = PCI_VENDOR_ID_TITAN,
  688. .device = PCI_DEVICE_ID_TITAN_400L,
  689. .subvendor = PCI_ANY_ID,
  690. .subdevice = PCI_ANY_ID,
  691. .setup = titan_400l_800l_setup,
  692. },
  693. {
  694. .vendor = PCI_VENDOR_ID_TITAN,
  695. .device = PCI_DEVICE_ID_TITAN_800L,
  696. .subvendor = PCI_ANY_ID,
  697. .subdevice = PCI_ANY_ID,
  698. .setup = titan_400l_800l_setup,
  699. },
  700. /*
  701. * Timedia cards
  702. */
  703. {
  704. .vendor = PCI_VENDOR_ID_TIMEDIA,
  705. .device = PCI_DEVICE_ID_TIMEDIA_1889,
  706. .subvendor = PCI_VENDOR_ID_TIMEDIA,
  707. .subdevice = PCI_ANY_ID,
  708. .init = pci_timedia_init,
  709. .setup = pci_timedia_setup,
  710. },
  711. {
  712. .vendor = PCI_VENDOR_ID_TIMEDIA,
  713. .device = PCI_ANY_ID,
  714. .subvendor = PCI_ANY_ID,
  715. .subdevice = PCI_ANY_ID,
  716. .setup = pci_timedia_setup,
  717. },
  718. /*
  719. * Xircom cards
  720. */
  721. {
  722. .vendor = PCI_VENDOR_ID_XIRCOM,
  723. .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
  724. .subvendor = PCI_ANY_ID,
  725. .subdevice = PCI_ANY_ID,
  726. .init = pci_xircom_init,
  727. .setup = pci_default_setup,
  728. },
  729. /*
  730. * Netmos cards - these may be called via parport_serial
  731. */
  732. {
  733. .vendor = PCI_VENDOR_ID_NETMOS,
  734. .device = PCI_ANY_ID,
  735. .subvendor = PCI_ANY_ID,
  736. .subdevice = PCI_ANY_ID,
  737. .init = pci_netmos_init,
  738. .setup = pci_default_setup,
  739. },
  740. /*
  741. * Default "match everything" terminator entry
  742. */
  743. {
  744. .vendor = PCI_ANY_ID,
  745. .device = PCI_ANY_ID,
  746. .subvendor = PCI_ANY_ID,
  747. .subdevice = PCI_ANY_ID,
  748. .setup = pci_default_setup,
  749. }
  750. };
  751. static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
  752. {
  753. return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
  754. }
  755. static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
  756. {
  757. struct pci_serial_quirk *quirk;
  758. for (quirk = pci_serial_quirks; ; quirk++)
  759. if (quirk_id_matches(quirk->vendor, dev->vendor) &&
  760. quirk_id_matches(quirk->device, dev->device) &&
  761. quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
  762. quirk_id_matches(quirk->subdevice, dev->subsystem_device))
  763. break;
  764. return quirk;
  765. }
  766. static inline int get_pci_irq(struct pci_dev *dev,
  767. struct pciserial_board *board)
  768. {
  769. if (board->flags & FL_NOIRQ)
  770. return 0;
  771. else
  772. return dev->irq;
  773. }
  774. /*
  775. * This is the configuration table for all of the PCI serial boards
  776. * which we support. It is directly indexed by the pci_board_num_t enum
  777. * value, which is encoded in the pci_device_id PCI probe table's
  778. * driver_data member.
  779. *
  780. * The makeup of these names are:
  781. * pbn_bn{_bt}_n_baud{_offsetinhex}
  782. *
  783. * bn = PCI BAR number
  784. * bt = Index using PCI BARs
  785. * n = number of serial ports
  786. * baud = baud rate
  787. * offsetinhex = offset for each sequential port (in hex)
  788. *
  789. * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
  790. *
  791. * Please note: in theory if n = 1, _bt infix should make no difference.
  792. * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
  793. */
  794. enum pci_board_num_t {
  795. pbn_default = 0,
  796. pbn_b0_1_115200,
  797. pbn_b0_2_115200,
  798. pbn_b0_4_115200,
  799. pbn_b0_5_115200,
  800. pbn_b0_1_921600,
  801. pbn_b0_2_921600,
  802. pbn_b0_4_921600,
  803. pbn_b0_2_1130000,
  804. pbn_b0_4_1152000,
  805. pbn_b0_2_1843200,
  806. pbn_b0_4_1843200,
  807. pbn_b0_2_1843200_200,
  808. pbn_b0_4_1843200_200,
  809. pbn_b0_8_1843200_200,
  810. pbn_b0_bt_1_115200,
  811. pbn_b0_bt_2_115200,
  812. pbn_b0_bt_8_115200,
  813. pbn_b0_bt_1_460800,
  814. pbn_b0_bt_2_460800,
  815. pbn_b0_bt_4_460800,
  816. pbn_b0_bt_1_921600,
  817. pbn_b0_bt_2_921600,
  818. pbn_b0_bt_4_921600,
  819. pbn_b0_bt_8_921600,
  820. pbn_b1_1_115200,
  821. pbn_b1_2_115200,
  822. pbn_b1_4_115200,
  823. pbn_b1_8_115200,
  824. pbn_b1_1_921600,
  825. pbn_b1_2_921600,
  826. pbn_b1_4_921600,
  827. pbn_b1_8_921600,
  828. pbn_b1_2_1250000,
  829. pbn_b1_bt_2_921600,
  830. pbn_b1_1_1382400,
  831. pbn_b1_2_1382400,
  832. pbn_b1_4_1382400,
  833. pbn_b1_8_1382400,
  834. pbn_b2_1_115200,
  835. pbn_b2_2_115200,
  836. pbn_b2_4_115200,
  837. pbn_b2_8_115200,
  838. pbn_b2_1_460800,
  839. pbn_b2_4_460800,
  840. pbn_b2_8_460800,
  841. pbn_b2_16_460800,
  842. pbn_b2_1_921600,
  843. pbn_b2_4_921600,
  844. pbn_b2_8_921600,
  845. pbn_b2_bt_1_115200,
  846. pbn_b2_bt_2_115200,
  847. pbn_b2_bt_4_115200,
  848. pbn_b2_bt_2_921600,
  849. pbn_b2_bt_4_921600,
  850. pbn_b3_2_115200,
  851. pbn_b3_4_115200,
  852. pbn_b3_8_115200,
  853. /*
  854. * Board-specific versions.
  855. */
  856. pbn_panacom,
  857. pbn_panacom2,
  858. pbn_panacom4,
  859. pbn_exsys_4055,
  860. pbn_plx_romulus,
  861. pbn_oxsemi,
  862. pbn_intel_i960,
  863. pbn_sgi_ioc3,
  864. pbn_nec_nile4,
  865. pbn_computone_4,
  866. pbn_computone_6,
  867. pbn_computone_8,
  868. pbn_sbsxrsio,
  869. pbn_exar_XR17C152,
  870. pbn_exar_XR17C154,
  871. pbn_exar_XR17C158,
  872. };
  873. /*
  874. * uart_offset - the space between channels
  875. * reg_shift - describes how the UART registers are mapped
  876. * to PCI memory by the card.
  877. * For example IER register on SBS, Inc. PMC-OctPro is located at
  878. * offset 0x10 from the UART base, while UART_IER is defined as 1
  879. * in include/linux/serial_reg.h,
  880. * see first lines of serial_in() and serial_out() in 8250.c
  881. */
  882. static struct pciserial_board pci_boards[] __devinitdata = {
  883. [pbn_default] = {
  884. .flags = FL_BASE0,
  885. .num_ports = 1,
  886. .base_baud = 115200,
  887. .uart_offset = 8,
  888. },
  889. [pbn_b0_1_115200] = {
  890. .flags = FL_BASE0,
  891. .num_ports = 1,
  892. .base_baud = 115200,
  893. .uart_offset = 8,
  894. },
  895. [pbn_b0_2_115200] = {
  896. .flags = FL_BASE0,
  897. .num_ports = 2,
  898. .base_baud = 115200,
  899. .uart_offset = 8,
  900. },
  901. [pbn_b0_4_115200] = {
  902. .flags = FL_BASE0,
  903. .num_ports = 4,
  904. .base_baud = 115200,
  905. .uart_offset = 8,
  906. },
  907. [pbn_b0_5_115200] = {
  908. .flags = FL_BASE0,
  909. .num_ports = 5,
  910. .base_baud = 115200,
  911. .uart_offset = 8,
  912. },
  913. [pbn_b0_1_921600] = {
  914. .flags = FL_BASE0,
  915. .num_ports = 1,
  916. .base_baud = 921600,
  917. .uart_offset = 8,
  918. },
  919. [pbn_b0_2_921600] = {
  920. .flags = FL_BASE0,
  921. .num_ports = 2,
  922. .base_baud = 921600,
  923. .uart_offset = 8,
  924. },
  925. [pbn_b0_4_921600] = {
  926. .flags = FL_BASE0,
  927. .num_ports = 4,
  928. .base_baud = 921600,
  929. .uart_offset = 8,
  930. },
  931. [pbn_b0_2_1130000] = {
  932. .flags = FL_BASE0,
  933. .num_ports = 2,
  934. .base_baud = 1130000,
  935. .uart_offset = 8,
  936. },
  937. [pbn_b0_4_1152000] = {
  938. .flags = FL_BASE0,
  939. .num_ports = 4,
  940. .base_baud = 1152000,
  941. .uart_offset = 8,
  942. },
  943. [pbn_b0_2_1843200] = {
  944. .flags = FL_BASE0,
  945. .num_ports = 2,
  946. .base_baud = 1843200,
  947. .uart_offset = 8,
  948. },
  949. [pbn_b0_4_1843200] = {
  950. .flags = FL_BASE0,
  951. .num_ports = 4,
  952. .base_baud = 1843200,
  953. .uart_offset = 8,
  954. },
  955. [pbn_b0_2_1843200_200] = {
  956. .flags = FL_BASE0,
  957. .num_ports = 2,
  958. .base_baud = 1843200,
  959. .uart_offset = 0x200,
  960. },
  961. [pbn_b0_4_1843200_200] = {
  962. .flags = FL_BASE0,
  963. .num_ports = 4,
  964. .base_baud = 1843200,
  965. .uart_offset = 0x200,
  966. },
  967. [pbn_b0_8_1843200_200] = {
  968. .flags = FL_BASE0,
  969. .num_ports = 8,
  970. .base_baud = 1843200,
  971. .uart_offset = 0x200,
  972. },
  973. [pbn_b0_bt_1_115200] = {
  974. .flags = FL_BASE0|FL_BASE_BARS,
  975. .num_ports = 1,
  976. .base_baud = 115200,
  977. .uart_offset = 8,
  978. },
  979. [pbn_b0_bt_2_115200] = {
  980. .flags = FL_BASE0|FL_BASE_BARS,
  981. .num_ports = 2,
  982. .base_baud = 115200,
  983. .uart_offset = 8,
  984. },
  985. [pbn_b0_bt_8_115200] = {
  986. .flags = FL_BASE0|FL_BASE_BARS,
  987. .num_ports = 8,
  988. .base_baud = 115200,
  989. .uart_offset = 8,
  990. },
  991. [pbn_b0_bt_1_460800] = {
  992. .flags = FL_BASE0|FL_BASE_BARS,
  993. .num_ports = 1,
  994. .base_baud = 460800,
  995. .uart_offset = 8,
  996. },
  997. [pbn_b0_bt_2_460800] = {
  998. .flags = FL_BASE0|FL_BASE_BARS,
  999. .num_ports = 2,
  1000. .base_baud = 460800,
  1001. .uart_offset = 8,
  1002. },
  1003. [pbn_b0_bt_4_460800] = {
  1004. .flags = FL_BASE0|FL_BASE_BARS,
  1005. .num_ports = 4,
  1006. .base_baud = 460800,
  1007. .uart_offset = 8,
  1008. },
  1009. [pbn_b0_bt_1_921600] = {
  1010. .flags = FL_BASE0|FL_BASE_BARS,
  1011. .num_ports = 1,
  1012. .base_baud = 921600,
  1013. .uart_offset = 8,
  1014. },
  1015. [pbn_b0_bt_2_921600] = {
  1016. .flags = FL_BASE0|FL_BASE_BARS,
  1017. .num_ports = 2,
  1018. .base_baud = 921600,
  1019. .uart_offset = 8,
  1020. },
  1021. [pbn_b0_bt_4_921600] = {
  1022. .flags = FL_BASE0|FL_BASE_BARS,
  1023. .num_ports = 4,
  1024. .base_baud = 921600,
  1025. .uart_offset = 8,
  1026. },
  1027. [pbn_b0_bt_8_921600] = {
  1028. .flags = FL_BASE0|FL_BASE_BARS,
  1029. .num_ports = 8,
  1030. .base_baud = 921600,
  1031. .uart_offset = 8,
  1032. },
  1033. [pbn_b1_1_115200] = {
  1034. .flags = FL_BASE1,
  1035. .num_ports = 1,
  1036. .base_baud = 115200,
  1037. .uart_offset = 8,
  1038. },
  1039. [pbn_b1_2_115200] = {
  1040. .flags = FL_BASE1,
  1041. .num_ports = 2,
  1042. .base_baud = 115200,
  1043. .uart_offset = 8,
  1044. },
  1045. [pbn_b1_4_115200] = {
  1046. .flags = FL_BASE1,
  1047. .num_ports = 4,
  1048. .base_baud = 115200,
  1049. .uart_offset = 8,
  1050. },
  1051. [pbn_b1_8_115200] = {
  1052. .flags = FL_BASE1,
  1053. .num_ports = 8,
  1054. .base_baud = 115200,
  1055. .uart_offset = 8,
  1056. },
  1057. [pbn_b1_1_921600] = {
  1058. .flags = FL_BASE1,
  1059. .num_ports = 1,
  1060. .base_baud = 921600,
  1061. .uart_offset = 8,
  1062. },
  1063. [pbn_b1_2_921600] = {
  1064. .flags = FL_BASE1,
  1065. .num_ports = 2,
  1066. .base_baud = 921600,
  1067. .uart_offset = 8,
  1068. },
  1069. [pbn_b1_4_921600] = {
  1070. .flags = FL_BASE1,
  1071. .num_ports = 4,
  1072. .base_baud = 921600,
  1073. .uart_offset = 8,
  1074. },
  1075. [pbn_b1_8_921600] = {
  1076. .flags = FL_BASE1,
  1077. .num_ports = 8,
  1078. .base_baud = 921600,
  1079. .uart_offset = 8,
  1080. },
  1081. [pbn_b1_2_1250000] = {
  1082. .flags = FL_BASE1,
  1083. .num_ports = 2,
  1084. .base_baud = 1250000,
  1085. .uart_offset = 8,
  1086. },
  1087. [pbn_b1_bt_2_921600] = {
  1088. .flags = FL_BASE1|FL_BASE_BARS,
  1089. .num_ports = 2,
  1090. .base_baud = 921600,
  1091. .uart_offset = 8,
  1092. },
  1093. [pbn_b1_1_1382400] = {
  1094. .flags = FL_BASE1,
  1095. .num_ports = 1,
  1096. .base_baud = 1382400,
  1097. .uart_offset = 8,
  1098. },
  1099. [pbn_b1_2_1382400] = {
  1100. .flags = FL_BASE1,
  1101. .num_ports = 2,
  1102. .base_baud = 1382400,
  1103. .uart_offset = 8,
  1104. },
  1105. [pbn_b1_4_1382400] = {
  1106. .flags = FL_BASE1,
  1107. .num_ports = 4,
  1108. .base_baud = 1382400,
  1109. .uart_offset = 8,
  1110. },
  1111. [pbn_b1_8_1382400] = {
  1112. .flags = FL_BASE1,
  1113. .num_ports = 8,
  1114. .base_baud = 1382400,
  1115. .uart_offset = 8,
  1116. },
  1117. [pbn_b2_1_115200] = {
  1118. .flags = FL_BASE2,
  1119. .num_ports = 1,
  1120. .base_baud = 115200,
  1121. .uart_offset = 8,
  1122. },
  1123. [pbn_b2_2_115200] = {
  1124. .flags = FL_BASE2,
  1125. .num_ports = 2,
  1126. .base_baud = 115200,
  1127. .uart_offset = 8,
  1128. },
  1129. [pbn_b2_4_115200] = {
  1130. .flags = FL_BASE2,
  1131. .num_ports = 4,
  1132. .base_baud = 115200,
  1133. .uart_offset = 8,
  1134. },
  1135. [pbn_b2_8_115200] = {
  1136. .flags = FL_BASE2,
  1137. .num_ports = 8,
  1138. .base_baud = 115200,
  1139. .uart_offset = 8,
  1140. },
  1141. [pbn_b2_1_460800] = {
  1142. .flags = FL_BASE2,
  1143. .num_ports = 1,
  1144. .base_baud = 460800,
  1145. .uart_offset = 8,
  1146. },
  1147. [pbn_b2_4_460800] = {
  1148. .flags = FL_BASE2,
  1149. .num_ports = 4,
  1150. .base_baud = 460800,
  1151. .uart_offset = 8,
  1152. },
  1153. [pbn_b2_8_460800] = {
  1154. .flags = FL_BASE2,
  1155. .num_ports = 8,
  1156. .base_baud = 460800,
  1157. .uart_offset = 8,
  1158. },
  1159. [pbn_b2_16_460800] = {
  1160. .flags = FL_BASE2,
  1161. .num_ports = 16,
  1162. .base_baud = 460800,
  1163. .uart_offset = 8,
  1164. },
  1165. [pbn_b2_1_921600] = {
  1166. .flags = FL_BASE2,
  1167. .num_ports = 1,
  1168. .base_baud = 921600,
  1169. .uart_offset = 8,
  1170. },
  1171. [pbn_b2_4_921600] = {
  1172. .flags = FL_BASE2,
  1173. .num_ports = 4,
  1174. .base_baud = 921600,
  1175. .uart_offset = 8,
  1176. },
  1177. [pbn_b2_8_921600] = {
  1178. .flags = FL_BASE2,
  1179. .num_ports = 8,
  1180. .base_baud = 921600,
  1181. .uart_offset = 8,
  1182. },
  1183. [pbn_b2_bt_1_115200] = {
  1184. .flags = FL_BASE2|FL_BASE_BARS,
  1185. .num_ports = 1,
  1186. .base_baud = 115200,
  1187. .uart_offset = 8,
  1188. },
  1189. [pbn_b2_bt_2_115200] = {
  1190. .flags = FL_BASE2|FL_BASE_BARS,
  1191. .num_ports = 2,
  1192. .base_baud = 115200,
  1193. .uart_offset = 8,
  1194. },
  1195. [pbn_b2_bt_4_115200] = {
  1196. .flags = FL_BASE2|FL_BASE_BARS,
  1197. .num_ports = 4,
  1198. .base_baud = 115200,
  1199. .uart_offset = 8,
  1200. },
  1201. [pbn_b2_bt_2_921600] = {
  1202. .flags = FL_BASE2|FL_BASE_BARS,
  1203. .num_ports = 2,
  1204. .base_baud = 921600,
  1205. .uart_offset = 8,
  1206. },
  1207. [pbn_b2_bt_4_921600] = {
  1208. .flags = FL_BASE2|FL_BASE_BARS,
  1209. .num_ports = 4,
  1210. .base_baud = 921600,
  1211. .uart_offset = 8,
  1212. },
  1213. [pbn_b3_2_115200] = {
  1214. .flags = FL_BASE3,
  1215. .num_ports = 2,
  1216. .base_baud = 115200,
  1217. .uart_offset = 8,
  1218. },
  1219. [pbn_b3_4_115200] = {
  1220. .flags = FL_BASE3,
  1221. .num_ports = 4,
  1222. .base_baud = 115200,
  1223. .uart_offset = 8,
  1224. },
  1225. [pbn_b3_8_115200] = {
  1226. .flags = FL_BASE3,
  1227. .num_ports = 8,
  1228. .base_baud = 115200,
  1229. .uart_offset = 8,
  1230. },
  1231. /*
  1232. * Entries following this are board-specific.
  1233. */
  1234. /*
  1235. * Panacom - IOMEM
  1236. */
  1237. [pbn_panacom] = {
  1238. .flags = FL_BASE2,
  1239. .num_ports = 2,
  1240. .base_baud = 921600,
  1241. .uart_offset = 0x400,
  1242. .reg_shift = 7,
  1243. },
  1244. [pbn_panacom2] = {
  1245. .flags = FL_BASE2|FL_BASE_BARS,
  1246. .num_ports = 2,
  1247. .base_baud = 921600,
  1248. .uart_offset = 0x400,
  1249. .reg_shift = 7,
  1250. },
  1251. [pbn_panacom4] = {
  1252. .flags = FL_BASE2|FL_BASE_BARS,
  1253. .num_ports = 4,
  1254. .base_baud = 921600,
  1255. .uart_offset = 0x400,
  1256. .reg_shift = 7,
  1257. },
  1258. [pbn_exsys_4055] = {
  1259. .flags = FL_BASE2,
  1260. .num_ports = 4,
  1261. .base_baud = 115200,
  1262. .uart_offset = 8,
  1263. },
  1264. /* I think this entry is broken - the first_offset looks wrong --rmk */
  1265. [pbn_plx_romulus] = {
  1266. .flags = FL_BASE2,
  1267. .num_ports = 4,
  1268. .base_baud = 921600,
  1269. .uart_offset = 8 << 2,
  1270. .reg_shift = 2,
  1271. .first_offset = 0x03,
  1272. },
  1273. /*
  1274. * This board uses the size of PCI Base region 0 to
  1275. * signal now many ports are available
  1276. */
  1277. [pbn_oxsemi] = {
  1278. .flags = FL_BASE0|FL_REGION_SZ_CAP,
  1279. .num_ports = 32,
  1280. .base_baud = 115200,
  1281. .uart_offset = 8,
  1282. },
  1283. /*
  1284. * EKF addition for i960 Boards form EKF with serial port.
  1285. * Max 256 ports.
  1286. */
  1287. [pbn_intel_i960] = {
  1288. .flags = FL_BASE0,
  1289. .num_ports = 32,
  1290. .base_baud = 921600,
  1291. .uart_offset = 8 << 2,
  1292. .reg_shift = 2,
  1293. .first_offset = 0x10000,
  1294. },
  1295. [pbn_sgi_ioc3] = {
  1296. .flags = FL_BASE0|FL_NOIRQ,
  1297. .num_ports = 1,
  1298. .base_baud = 458333,
  1299. .uart_offset = 8,
  1300. .reg_shift = 0,
  1301. .first_offset = 0x20178,
  1302. },
  1303. /*
  1304. * NEC Vrc-5074 (Nile 4) builtin UART.
  1305. */
  1306. [pbn_nec_nile4] = {
  1307. .flags = FL_BASE0,
  1308. .num_ports = 1,
  1309. .base_baud = 520833,
  1310. .uart_offset = 8 << 3,
  1311. .reg_shift = 3,
  1312. .first_offset = 0x300,
  1313. },
  1314. /*
  1315. * Computone - uses IOMEM.
  1316. */
  1317. [pbn_computone_4] = {
  1318. .flags = FL_BASE0,
  1319. .num_ports = 4,
  1320. .base_baud = 921600,
  1321. .uart_offset = 0x40,
  1322. .reg_shift = 2,
  1323. .first_offset = 0x200,
  1324. },
  1325. [pbn_computone_6] = {
  1326. .flags = FL_BASE0,
  1327. .num_ports = 6,
  1328. .base_baud = 921600,
  1329. .uart_offset = 0x40,
  1330. .reg_shift = 2,
  1331. .first_offset = 0x200,
  1332. },
  1333. [pbn_computone_8] = {
  1334. .flags = FL_BASE0,
  1335. .num_ports = 8,
  1336. .base_baud = 921600,
  1337. .uart_offset = 0x40,
  1338. .reg_shift = 2,
  1339. .first_offset = 0x200,
  1340. },
  1341. [pbn_sbsxrsio] = {
  1342. .flags = FL_BASE0,
  1343. .num_ports = 8,
  1344. .base_baud = 460800,
  1345. .uart_offset = 256,
  1346. .reg_shift = 4,
  1347. },
  1348. /*
  1349. * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
  1350. * Only basic 16550A support.
  1351. * XR17C15[24] are not tested, but they should work.
  1352. */
  1353. [pbn_exar_XR17C152] = {
  1354. .flags = FL_BASE0,
  1355. .num_ports = 2,
  1356. .base_baud = 921600,
  1357. .uart_offset = 0x200,
  1358. },
  1359. [pbn_exar_XR17C154] = {
  1360. .flags = FL_BASE0,
  1361. .num_ports = 4,
  1362. .base_baud = 921600,
  1363. .uart_offset = 0x200,
  1364. },
  1365. [pbn_exar_XR17C158] = {
  1366. .flags = FL_BASE0,
  1367. .num_ports = 8,
  1368. .base_baud = 921600,
  1369. .uart_offset = 0x200,
  1370. },
  1371. };
  1372. /*
  1373. * Given a complete unknown PCI device, try to use some heuristics to
  1374. * guess what the configuration might be, based on the pitiful PCI
  1375. * serial specs. Returns 0 on success, 1 on failure.
  1376. */
  1377. static int __devinit
  1378. serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
  1379. {
  1380. int num_iomem, num_port, first_port = -1, i;
  1381. /*
  1382. * If it is not a communications device or the programming
  1383. * interface is greater than 6, give up.
  1384. *
  1385. * (Should we try to make guesses for multiport serial devices
  1386. * later?)
  1387. */
  1388. if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
  1389. ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
  1390. (dev->class & 0xff) > 6)
  1391. return -ENODEV;
  1392. num_iomem = num_port = 0;
  1393. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  1394. if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
  1395. num_port++;
  1396. if (first_port == -1)
  1397. first_port = i;
  1398. }
  1399. if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
  1400. num_iomem++;
  1401. }
  1402. /*
  1403. * If there is 1 or 0 iomem regions, and exactly one port,
  1404. * use it. We guess the number of ports based on the IO
  1405. * region size.
  1406. */
  1407. if (num_iomem <= 1 && num_port == 1) {
  1408. board->flags = first_port;
  1409. board->num_ports = pci_resource_len(dev, first_port) / 8;
  1410. return 0;
  1411. }
  1412. /*
  1413. * Now guess if we've got a board which indexes by BARs.
  1414. * Each IO BAR should be 8 bytes, and they should follow
  1415. * consecutively.
  1416. */
  1417. first_port = -1;
  1418. num_port = 0;
  1419. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  1420. if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
  1421. pci_resource_len(dev, i) == 8 &&
  1422. (first_port == -1 || (first_port + num_port) == i)) {
  1423. num_port++;
  1424. if (first_port == -1)
  1425. first_port = i;
  1426. }
  1427. }
  1428. if (num_port > 1) {
  1429. board->flags = first_port | FL_BASE_BARS;
  1430. board->num_ports = num_port;
  1431. return 0;
  1432. }
  1433. return -ENODEV;
  1434. }
  1435. static inline int
  1436. serial_pci_matches(struct pciserial_board *board,
  1437. struct pciserial_board *guessed)
  1438. {
  1439. return
  1440. board->num_ports == guessed->num_ports &&
  1441. board->base_baud == guessed->base_baud &&
  1442. board->uart_offset == guessed->uart_offset &&
  1443. board->reg_shift == guessed->reg_shift &&
  1444. board->first_offset == guessed->first_offset;
  1445. }
  1446. struct serial_private *
  1447. pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
  1448. {
  1449. struct uart_port serial_port;
  1450. struct serial_private *priv;
  1451. struct pci_serial_quirk *quirk;
  1452. int rc, nr_ports, i;
  1453. nr_ports = board->num_ports;
  1454. /*
  1455. * Find an init and setup quirks.
  1456. */
  1457. quirk = find_quirk(dev);
  1458. /*
  1459. * Run the new-style initialization function.
  1460. * The initialization function returns:
  1461. * <0 - error
  1462. * 0 - use board->num_ports
  1463. * >0 - number of ports
  1464. */
  1465. if (quirk->init) {
  1466. rc = quirk->init(dev);
  1467. if (rc < 0) {
  1468. priv = ERR_PTR(rc);
  1469. goto err_out;
  1470. }
  1471. if (rc)
  1472. nr_ports = rc;
  1473. }
  1474. priv = kzalloc(sizeof(struct serial_private) +
  1475. sizeof(unsigned int) * nr_ports,
  1476. GFP_KERNEL);
  1477. if (!priv) {
  1478. priv = ERR_PTR(-ENOMEM);
  1479. goto err_deinit;
  1480. }
  1481. priv->dev = dev;
  1482. priv->quirk = quirk;
  1483. memset(&serial_port, 0, sizeof(struct uart_port));
  1484. serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
  1485. serial_port.uartclk = board->base_baud * 16;
  1486. serial_port.irq = get_pci_irq(dev, board);
  1487. serial_port.dev = &dev->dev;
  1488. for (i = 0; i < nr_ports; i++) {
  1489. if (quirk->setup(priv, board, &serial_port, i))
  1490. break;
  1491. #ifdef SERIAL_DEBUG_PCI
  1492. printk("Setup PCI port: port %x, irq %d, type %d\n",
  1493. serial_port.iobase, serial_port.irq, serial_port.iotype);
  1494. #endif
  1495. priv->line[i] = serial8250_register_port(&serial_port);
  1496. if (priv->line[i] < 0) {
  1497. printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
  1498. break;
  1499. }
  1500. }
  1501. priv->nr = i;
  1502. return priv;
  1503. err_deinit:
  1504. if (quirk->exit)
  1505. quirk->exit(dev);
  1506. err_out:
  1507. return priv;
  1508. }
  1509. EXPORT_SYMBOL_GPL(pciserial_init_ports);
  1510. void pciserial_remove_ports(struct serial_private *priv)
  1511. {
  1512. struct pci_serial_quirk *quirk;
  1513. int i;
  1514. for (i = 0; i < priv->nr; i++)
  1515. serial8250_unregister_port(priv->line[i]);
  1516. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  1517. if (priv->remapped_bar[i])
  1518. iounmap(priv->remapped_bar[i]);
  1519. priv->remapped_bar[i] = NULL;
  1520. }
  1521. /*
  1522. * Find the exit quirks.
  1523. */
  1524. quirk = find_quirk(priv->dev);
  1525. if (quirk->exit)
  1526. quirk->exit(priv->dev);
  1527. kfree(priv);
  1528. }
  1529. EXPORT_SYMBOL_GPL(pciserial_remove_ports);
  1530. void pciserial_suspend_ports(struct serial_private *priv)
  1531. {
  1532. int i;
  1533. for (i = 0; i < priv->nr; i++)
  1534. if (priv->line[i] >= 0)
  1535. serial8250_suspend_port(priv->line[i]);
  1536. }
  1537. EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
  1538. void pciserial_resume_ports(struct serial_private *priv)
  1539. {
  1540. int i;
  1541. /*
  1542. * Ensure that the board is correctly configured.
  1543. */
  1544. if (priv->quirk->init)
  1545. priv->quirk->init(priv->dev);
  1546. for (i = 0; i < priv->nr; i++)
  1547. if (priv->line[i] >= 0)
  1548. serial8250_resume_port(priv->line[i]);
  1549. }
  1550. EXPORT_SYMBOL_GPL(pciserial_resume_ports);
  1551. /*
  1552. * Probe one serial board. Unfortunately, there is no rhyme nor reason
  1553. * to the arrangement of serial ports on a PCI card.
  1554. */
  1555. static int __devinit
  1556. pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
  1557. {
  1558. struct serial_private *priv;
  1559. struct pciserial_board *board, tmp;
  1560. int rc;
  1561. if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
  1562. printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
  1563. ent->driver_data);
  1564. return -EINVAL;
  1565. }
  1566. board = &pci_boards[ent->driver_data];
  1567. rc = pci_enable_device(dev);
  1568. if (rc)
  1569. return rc;
  1570. if (ent->driver_data == pbn_default) {
  1571. /*
  1572. * Use a copy of the pci_board entry for this;
  1573. * avoid changing entries in the table.
  1574. */
  1575. memcpy(&tmp, board, sizeof(struct pciserial_board));
  1576. board = &tmp;
  1577. /*
  1578. * We matched one of our class entries. Try to
  1579. * determine the parameters of this board.
  1580. */
  1581. rc = serial_pci_guess_board(dev, board);
  1582. if (rc)
  1583. goto disable;
  1584. } else {
  1585. /*
  1586. * We matched an explicit entry. If we are able to
  1587. * detect this boards settings with our heuristic,
  1588. * then we no longer need this entry.
  1589. */
  1590. memcpy(&tmp, &pci_boards[pbn_default],
  1591. sizeof(struct pciserial_board));
  1592. rc = serial_pci_guess_board(dev, &tmp);
  1593. if (rc == 0 && serial_pci_matches(board, &tmp))
  1594. moan_device("Redundant entry in serial pci_table.",
  1595. dev);
  1596. }
  1597. priv = pciserial_init_ports(dev, board);
  1598. if (!IS_ERR(priv)) {
  1599. pci_set_drvdata(dev, priv);
  1600. return 0;
  1601. }
  1602. rc = PTR_ERR(priv);
  1603. disable:
  1604. pci_disable_device(dev);
  1605. return rc;
  1606. }
  1607. static void __devexit pciserial_remove_one(struct pci_dev *dev)
  1608. {
  1609. struct serial_private *priv = pci_get_drvdata(dev);
  1610. pci_set_drvdata(dev, NULL);
  1611. pciserial_remove_ports(priv);
  1612. pci_disable_device(dev);
  1613. }
  1614. #ifdef CONFIG_PM
  1615. static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
  1616. {
  1617. struct serial_private *priv = pci_get_drvdata(dev);
  1618. if (priv)
  1619. pciserial_suspend_ports(priv);
  1620. pci_save_state(dev);
  1621. pci_set_power_state(dev, pci_choose_state(dev, state));
  1622. return 0;
  1623. }
  1624. static int pciserial_resume_one(struct pci_dev *dev)
  1625. {
  1626. struct serial_private *priv = pci_get_drvdata(dev);
  1627. pci_set_power_state(dev, PCI_D0);
  1628. pci_restore_state(dev);
  1629. if (priv) {
  1630. /*
  1631. * The device may have been disabled. Re-enable it.
  1632. */
  1633. pci_enable_device(dev);
  1634. pciserial_resume_ports(priv);
  1635. }
  1636. return 0;
  1637. }
  1638. #endif
  1639. static struct pci_device_id serial_pci_tbl[] = {
  1640. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  1641. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1642. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
  1643. pbn_b1_8_1382400 },
  1644. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  1645. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1646. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
  1647. pbn_b1_4_1382400 },
  1648. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  1649. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1650. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
  1651. pbn_b1_2_1382400 },
  1652. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1653. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1654. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
  1655. pbn_b1_8_1382400 },
  1656. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1657. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1658. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
  1659. pbn_b1_4_1382400 },
  1660. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1661. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1662. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
  1663. pbn_b1_2_1382400 },
  1664. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1665. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1666. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
  1667. pbn_b1_8_921600 },
  1668. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1669. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1670. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
  1671. pbn_b1_8_921600 },
  1672. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1673. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1674. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
  1675. pbn_b1_4_921600 },
  1676. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1677. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1678. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
  1679. pbn_b1_4_921600 },
  1680. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1681. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1682. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
  1683. pbn_b1_2_921600 },
  1684. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1685. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1686. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
  1687. pbn_b1_8_921600 },
  1688. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1689. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1690. PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
  1691. pbn_b1_8_921600 },
  1692. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1693. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1694. PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
  1695. pbn_b1_4_921600 },
  1696. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1697. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1698. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
  1699. pbn_b1_2_1250000 },
  1700. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1701. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1702. PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
  1703. pbn_b0_2_1843200 },
  1704. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1705. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1706. PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
  1707. pbn_b0_4_1843200 },
  1708. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1709. PCI_VENDOR_ID_AFAVLAB,
  1710. PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
  1711. pbn_b0_4_1152000 },
  1712. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  1713. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1714. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
  1715. pbn_b0_2_1843200_200 },
  1716. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  1717. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1718. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
  1719. pbn_b0_4_1843200_200 },
  1720. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  1721. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1722. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
  1723. pbn_b0_8_1843200_200 },
  1724. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  1725. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1726. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
  1727. pbn_b0_2_1843200_200 },
  1728. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  1729. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1730. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
  1731. pbn_b0_4_1843200_200 },
  1732. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  1733. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1734. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
  1735. pbn_b0_8_1843200_200 },
  1736. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  1737. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1738. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
  1739. pbn_b0_2_1843200_200 },
  1740. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  1741. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1742. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
  1743. pbn_b0_4_1843200_200 },
  1744. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  1745. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1746. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
  1747. pbn_b0_8_1843200_200 },
  1748. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  1749. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1750. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
  1751. pbn_b0_2_1843200_200 },
  1752. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  1753. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1754. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
  1755. pbn_b0_4_1843200_200 },
  1756. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  1757. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1758. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
  1759. pbn_b0_8_1843200_200 },
  1760. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
  1761. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1762. pbn_b2_bt_1_115200 },
  1763. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
  1764. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1765. pbn_b2_bt_2_115200 },
  1766. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
  1767. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1768. pbn_b2_bt_4_115200 },
  1769. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
  1770. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1771. pbn_b2_bt_2_115200 },
  1772. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
  1773. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1774. pbn_b2_bt_4_115200 },
  1775. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
  1776. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1777. pbn_b2_8_115200 },
  1778. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
  1779. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1780. pbn_b2_8_115200 },
  1781. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
  1782. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1783. pbn_b2_bt_2_115200 },
  1784. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
  1785. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1786. pbn_b2_bt_2_921600 },
  1787. /*
  1788. * VScom SPCOM800, from sl@s.pl
  1789. */
  1790. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
  1791. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1792. pbn_b2_8_921600 },
  1793. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
  1794. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1795. pbn_b2_4_921600 },
  1796. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1797. PCI_SUBVENDOR_ID_KEYSPAN,
  1798. PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
  1799. pbn_panacom },
  1800. { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
  1801. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1802. pbn_panacom4 },
  1803. { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
  1804. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1805. pbn_panacom2 },
  1806. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
  1807. PCI_VENDOR_ID_ESDGMBH,
  1808. PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
  1809. pbn_b2_4_115200 },
  1810. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1811. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1812. PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
  1813. pbn_b2_4_460800 },
  1814. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1815. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1816. PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
  1817. pbn_b2_8_460800 },
  1818. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1819. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1820. PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
  1821. pbn_b2_16_460800 },
  1822. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1823. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1824. PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
  1825. pbn_b2_16_460800 },
  1826. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1827. PCI_SUBVENDOR_ID_CHASE_PCIRAS,
  1828. PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
  1829. pbn_b2_4_460800 },
  1830. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1831. PCI_SUBVENDOR_ID_CHASE_PCIRAS,
  1832. PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
  1833. pbn_b2_8_460800 },
  1834. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1835. PCI_SUBVENDOR_ID_EXSYS,
  1836. PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
  1837. pbn_exsys_4055 },
  1838. /*
  1839. * Megawolf Romulus PCI Serial Card, from Mike Hudson
  1840. * (Exoray@isys.ca)
  1841. */
  1842. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
  1843. 0x10b5, 0x106a, 0, 0,
  1844. pbn_plx_romulus },
  1845. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
  1846. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1847. pbn_b1_4_115200 },
  1848. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
  1849. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1850. pbn_b1_2_115200 },
  1851. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
  1852. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1853. pbn_b1_8_115200 },
  1854. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
  1855. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1856. pbn_b1_8_115200 },
  1857. { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1858. PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
  1859. pbn_b0_4_921600 },
  1860. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1861. PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
  1862. pbn_b0_4_1152000 },
  1863. /*
  1864. * The below card is a little controversial since it is the
  1865. * subject of a PCI vendor/device ID clash. (See
  1866. * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
  1867. * For now just used the hex ID 0x950a.
  1868. */
  1869. { PCI_VENDOR_ID_OXSEMI, 0x950a,
  1870. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1871. pbn_b0_2_1130000 },
  1872. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1873. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1874. pbn_b0_4_115200 },
  1875. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
  1876. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1877. pbn_b0_bt_2_921600 },
  1878. /*
  1879. * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
  1880. * from skokodyn@yahoo.com
  1881. */
  1882. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1883. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
  1884. pbn_sbsxrsio },
  1885. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1886. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
  1887. pbn_sbsxrsio },
  1888. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1889. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
  1890. pbn_sbsxrsio },
  1891. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1892. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
  1893. pbn_sbsxrsio },
  1894. /*
  1895. * Digitan DS560-558, from jimd@esoft.com
  1896. */
  1897. { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
  1898. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1899. pbn_b1_1_115200 },
  1900. /*
  1901. * Titan Electronic cards
  1902. * The 400L and 800L have a custom setup quirk.
  1903. */
  1904. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
  1905. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1906. pbn_b0_1_921600 },
  1907. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
  1908. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1909. pbn_b0_2_921600 },
  1910. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
  1911. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1912. pbn_b0_4_921600 },
  1913. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
  1914. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1915. pbn_b0_4_921600 },
  1916. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
  1917. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1918. pbn_b1_1_921600 },
  1919. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
  1920. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1921. pbn_b1_bt_2_921600 },
  1922. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
  1923. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1924. pbn_b0_bt_4_921600 },
  1925. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
  1926. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1927. pbn_b0_bt_8_921600 },
  1928. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
  1929. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1930. pbn_b2_1_460800 },
  1931. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
  1932. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1933. pbn_b2_1_460800 },
  1934. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
  1935. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1936. pbn_b2_1_460800 },
  1937. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
  1938. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1939. pbn_b2_bt_2_921600 },
  1940. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
  1941. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1942. pbn_b2_bt_2_921600 },
  1943. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
  1944. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1945. pbn_b2_bt_2_921600 },
  1946. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
  1947. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1948. pbn_b2_bt_4_921600 },
  1949. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
  1950. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1951. pbn_b2_bt_4_921600 },
  1952. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
  1953. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1954. pbn_b2_bt_4_921600 },
  1955. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
  1956. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1957. pbn_b0_1_921600 },
  1958. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
  1959. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1960. pbn_b0_1_921600 },
  1961. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
  1962. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1963. pbn_b0_1_921600 },
  1964. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
  1965. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1966. pbn_b0_bt_2_921600 },
  1967. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
  1968. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1969. pbn_b0_bt_2_921600 },
  1970. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
  1971. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1972. pbn_b0_bt_2_921600 },
  1973. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
  1974. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1975. pbn_b0_bt_4_921600 },
  1976. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
  1977. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1978. pbn_b0_bt_4_921600 },
  1979. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
  1980. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1981. pbn_b0_bt_4_921600 },
  1982. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
  1983. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1984. pbn_b0_bt_8_921600 },
  1985. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
  1986. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1987. pbn_b0_bt_8_921600 },
  1988. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
  1989. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1990. pbn_b0_bt_8_921600 },
  1991. /*
  1992. * Computone devices submitted by Doug McNash dmcnash@computone.com
  1993. */
  1994. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  1995. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
  1996. 0, 0, pbn_computone_4 },
  1997. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  1998. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
  1999. 0, 0, pbn_computone_8 },
  2000. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  2001. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
  2002. 0, 0, pbn_computone_6 },
  2003. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
  2004. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2005. pbn_oxsemi },
  2006. { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
  2007. PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
  2008. pbn_b0_bt_1_921600 },
  2009. /*
  2010. * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
  2011. */
  2012. { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
  2013. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2014. pbn_b0_bt_8_115200 },
  2015. { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
  2016. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2017. pbn_b0_bt_8_115200 },
  2018. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
  2019. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2020. pbn_b0_bt_2_115200 },
  2021. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
  2022. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2023. pbn_b0_bt_2_115200 },
  2024. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
  2025. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2026. pbn_b0_bt_2_115200 },
  2027. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
  2028. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2029. pbn_b0_bt_4_460800 },
  2030. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
  2031. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2032. pbn_b0_bt_4_460800 },
  2033. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
  2034. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2035. pbn_b0_bt_2_460800 },
  2036. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
  2037. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2038. pbn_b0_bt_2_460800 },
  2039. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
  2040. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2041. pbn_b0_bt_2_460800 },
  2042. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
  2043. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2044. pbn_b0_bt_1_115200 },
  2045. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
  2046. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2047. pbn_b0_bt_1_460800 },
  2048. /*
  2049. * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
  2050. * Cards are identified by their subsystem vendor IDs, which
  2051. * (in hex) match the model number.
  2052. *
  2053. * Note that JC140x are RS422/485 cards which require ox950
  2054. * ACR = 0x10, and as such are not currently fully supported.
  2055. */
  2056. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  2057. 0x1204, 0x0004, 0, 0,
  2058. pbn_b0_4_921600 },
  2059. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  2060. 0x1208, 0x0004, 0, 0,
  2061. pbn_b0_4_921600 },
  2062. /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  2063. 0x1402, 0x0002, 0, 0,
  2064. pbn_b0_2_921600 }, */
  2065. /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  2066. 0x1404, 0x0004, 0, 0,
  2067. pbn_b0_4_921600 }, */
  2068. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
  2069. 0x1208, 0x0004, 0, 0,
  2070. pbn_b0_4_921600 },
  2071. /*
  2072. * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
  2073. */
  2074. { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
  2075. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2076. pbn_b1_1_1382400 },
  2077. /*
  2078. * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
  2079. */
  2080. { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
  2081. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2082. pbn_b1_1_1382400 },
  2083. /*
  2084. * RAStel 2 port modem, gerg@moreton.com.au
  2085. */
  2086. { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
  2087. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2088. pbn_b2_bt_2_115200 },
  2089. /*
  2090. * EKF addition for i960 Boards form EKF with serial port
  2091. */
  2092. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
  2093. 0xE4BF, PCI_ANY_ID, 0, 0,
  2094. pbn_intel_i960 },
  2095. /*
  2096. * Xircom Cardbus/Ethernet combos
  2097. */
  2098. { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
  2099. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2100. pbn_b0_1_115200 },
  2101. /*
  2102. * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
  2103. */
  2104. { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
  2105. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2106. pbn_b0_1_115200 },
  2107. /*
  2108. * Untested PCI modems, sent in from various folks...
  2109. */
  2110. /*
  2111. * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
  2112. */
  2113. { PCI_VENDOR_ID_ROCKWELL, 0x1004,
  2114. 0x1048, 0x1500, 0, 0,
  2115. pbn_b1_1_115200 },
  2116. { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
  2117. 0xFF00, 0, 0, 0,
  2118. pbn_sgi_ioc3 },
  2119. /*
  2120. * HP Diva card
  2121. */
  2122. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
  2123. PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
  2124. pbn_b1_1_115200 },
  2125. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
  2126. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2127. pbn_b0_5_115200 },
  2128. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
  2129. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2130. pbn_b2_1_115200 },
  2131. /*
  2132. * NEC Vrc-5074 (Nile 4) builtin UART.
  2133. */
  2134. { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
  2135. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2136. pbn_nec_nile4 },
  2137. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
  2138. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2139. pbn_b3_2_115200 },
  2140. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
  2141. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2142. pbn_b3_4_115200 },
  2143. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
  2144. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2145. pbn_b3_8_115200 },
  2146. /*
  2147. * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
  2148. */
  2149. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  2150. PCI_ANY_ID, PCI_ANY_ID,
  2151. 0,
  2152. 0, pbn_exar_XR17C152 },
  2153. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  2154. PCI_ANY_ID, PCI_ANY_ID,
  2155. 0,
  2156. 0, pbn_exar_XR17C154 },
  2157. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  2158. PCI_ANY_ID, PCI_ANY_ID,
  2159. 0,
  2160. 0, pbn_exar_XR17C158 },
  2161. /*
  2162. * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
  2163. */
  2164. { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
  2165. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  2166. pbn_b0_1_115200 },
  2167. /*
  2168. * IntaShield IS-200
  2169. */
  2170. { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
  2171. PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
  2172. pbn_b2_2_115200 },
  2173. /*
  2174. * Perle PCI-RAS cards
  2175. */
  2176. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
  2177. PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
  2178. 0, 0, pbn_b2_4_921600 },
  2179. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
  2180. PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
  2181. 0, 0, pbn_b2_8_921600 },
  2182. /*
  2183. * These entries match devices with class COMMUNICATION_SERIAL,
  2184. * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
  2185. */
  2186. { PCI_ANY_ID, PCI_ANY_ID,
  2187. PCI_ANY_ID, PCI_ANY_ID,
  2188. PCI_CLASS_COMMUNICATION_SERIAL << 8,
  2189. 0xffff00, pbn_default },
  2190. { PCI_ANY_ID, PCI_ANY_ID,
  2191. PCI_ANY_ID, PCI_ANY_ID,
  2192. PCI_CLASS_COMMUNICATION_MODEM << 8,
  2193. 0xffff00, pbn_default },
  2194. { PCI_ANY_ID, PCI_ANY_ID,
  2195. PCI_ANY_ID, PCI_ANY_ID,
  2196. PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
  2197. 0xffff00, pbn_default },
  2198. { 0, }
  2199. };
  2200. static struct pci_driver serial_pci_driver = {
  2201. .name = "serial",
  2202. .probe = pciserial_init_one,
  2203. .remove = __devexit_p(pciserial_remove_one),
  2204. #ifdef CONFIG_PM
  2205. .suspend = pciserial_suspend_one,
  2206. .resume = pciserial_resume_one,
  2207. #endif
  2208. .id_table = serial_pci_tbl,
  2209. };
  2210. static int __init serial8250_pci_init(void)
  2211. {
  2212. return pci_register_driver(&serial_pci_driver);
  2213. }
  2214. static void __exit serial8250_pci_exit(void)
  2215. {
  2216. pci_unregister_driver(&serial_pci_driver);
  2217. }
  2218. module_init(serial8250_pci_init);
  2219. module_exit(serial8250_pci_exit);
  2220. MODULE_LICENSE("GPL");
  2221. MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
  2222. MODULE_DEVICE_TABLE(pci, serial_pci_tbl);