ncr53c8xx.h 40 KB

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  1. /******************************************************************************
  2. ** Device driver for the PCI-SCSI NCR538XX controller family.
  3. **
  4. ** Copyright (C) 1994 Wolfgang Stanglmeier
  5. ** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
  6. **
  7. ** This program is free software; you can redistribute it and/or modify
  8. ** it under the terms of the GNU General Public License as published by
  9. ** the Free Software Foundation; either version 2 of the License, or
  10. ** (at your option) any later version.
  11. **
  12. ** This program is distributed in the hope that it will be useful,
  13. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. ** GNU General Public License for more details.
  16. **
  17. ** You should have received a copy of the GNU General Public License
  18. ** along with this program; if not, write to the Free Software
  19. ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. **
  21. **-----------------------------------------------------------------------------
  22. **
  23. ** This driver has been ported to Linux from the FreeBSD NCR53C8XX driver
  24. ** and is currently maintained by
  25. **
  26. ** Gerard Roudier <groudier@free.fr>
  27. **
  28. ** Being given that this driver originates from the FreeBSD version, and
  29. ** in order to keep synergy on both, any suggested enhancements and corrections
  30. ** received on Linux are automatically a potential candidate for the FreeBSD
  31. ** version.
  32. **
  33. ** The original driver has been written for 386bsd and FreeBSD by
  34. ** Wolfgang Stanglmeier <wolf@cologne.de>
  35. ** Stefan Esser <se@mi.Uni-Koeln.de>
  36. **
  37. ** And has been ported to NetBSD by
  38. ** Charles M. Hannum <mycroft@gnu.ai.mit.edu>
  39. **
  40. ** NVRAM detection and reading.
  41. ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
  42. **
  43. ** Added support for MIPS big endian systems.
  44. ** Carsten Langgaard, carstenl@mips.com
  45. ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  46. **
  47. ** Added support for HP PARISC big endian systems.
  48. ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  49. **
  50. *******************************************************************************
  51. */
  52. #ifndef NCR53C8XX_H
  53. #define NCR53C8XX_H
  54. #include <scsi/scsi_host.h>
  55. /*
  56. ** If you want a driver as small as possible, donnot define the
  57. ** following options.
  58. */
  59. #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
  60. #define SCSI_NCR_DEBUG_INFO_SUPPORT
  61. /*
  62. ** To disable integrity checking, do not define the
  63. ** following option.
  64. */
  65. #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
  66. # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
  67. #endif
  68. /* ---------------------------------------------------------------------
  69. ** Take into account kernel configured parameters.
  70. ** Most of these options can be overridden at startup by a command line.
  71. ** ---------------------------------------------------------------------
  72. */
  73. /*
  74. * For Ultra2 and Ultra3 SCSI support option, use special features.
  75. *
  76. * Value (default) means:
  77. * bit 0 : all features enabled, except:
  78. * bit 1 : PCI Write And Invalidate.
  79. * bit 2 : Data Phase Mismatch handling from SCRIPTS.
  80. *
  81. * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
  82. * enabled by the driver.
  83. */
  84. #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
  85. #define SCSI_NCR_MAX_SYNC (80)
  86. /*
  87. * Allow tags from 2 to 256, default 8
  88. */
  89. #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
  90. #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
  91. #define SCSI_NCR_MAX_TAGS (2)
  92. #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
  93. #define SCSI_NCR_MAX_TAGS (256)
  94. #else
  95. #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
  96. #endif
  97. #else
  98. #define SCSI_NCR_MAX_TAGS (8)
  99. #endif
  100. /*
  101. * Allow tagged command queuing support if configured with default number
  102. * of tags set to max (see above).
  103. */
  104. #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
  105. #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
  106. #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
  107. #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
  108. #else
  109. #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
  110. #endif
  111. /*
  112. * Immediate arbitration
  113. */
  114. #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
  115. #define SCSI_NCR_IARB_SUPPORT
  116. #endif
  117. /*
  118. * Sync transfer frequency at startup.
  119. * Allow from 5Mhz to 80Mhz default 20 Mhz.
  120. */
  121. #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
  122. #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
  123. #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
  124. #undef CONFIG_SCSI_NCR53C8XX_SYNC
  125. #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
  126. #endif
  127. #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
  128. #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
  129. #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
  130. #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
  131. #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
  132. #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
  133. #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
  134. #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
  135. #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
  136. #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
  137. #else
  138. #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
  139. #endif
  140. /*
  141. * Disallow disconnections at boot-up
  142. */
  143. #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
  144. #define SCSI_NCR_SETUP_DISCONNECTION (0)
  145. #else
  146. #define SCSI_NCR_SETUP_DISCONNECTION (1)
  147. #endif
  148. /*
  149. * Force synchronous negotiation for all targets
  150. */
  151. #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
  152. #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
  153. #else
  154. #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
  155. #endif
  156. /*
  157. * Disable master parity checking (flawed hardwares need that)
  158. */
  159. #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
  160. #define SCSI_NCR_SETUP_MASTER_PARITY (0)
  161. #else
  162. #define SCSI_NCR_SETUP_MASTER_PARITY (1)
  163. #endif
  164. /*
  165. * Disable scsi parity checking (flawed devices may need that)
  166. */
  167. #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
  168. #define SCSI_NCR_SETUP_SCSI_PARITY (0)
  169. #else
  170. #define SCSI_NCR_SETUP_SCSI_PARITY (1)
  171. #endif
  172. /*
  173. * Settle time after reset at boot-up
  174. */
  175. #define SCSI_NCR_SETUP_SETTLE_TIME (2)
  176. /*
  177. ** Bridge quirks work-around option defaulted to 1.
  178. */
  179. #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
  180. #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
  181. #endif
  182. /*
  183. ** Work-around common bridge misbehaviour.
  184. **
  185. ** - Do not flush posted writes in the opposite
  186. ** direction on read.
  187. ** - May reorder DMA writes to memory.
  188. **
  189. ** This option should not affect performances
  190. ** significantly, so it is the default.
  191. */
  192. #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
  193. #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
  194. #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
  195. #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
  196. /*
  197. ** Same as option 1, but also deal with
  198. ** misconfigured interrupts.
  199. **
  200. ** - Edge triggered instead of level sensitive.
  201. ** - No interrupt line connected.
  202. ** - IRQ number misconfigured.
  203. **
  204. ** If no interrupt is delivered, the driver will
  205. ** catch the interrupt conditions 10 times per
  206. ** second. No need to say that this option is
  207. ** not recommended.
  208. */
  209. #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
  210. #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
  211. #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
  212. #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
  213. #define SCSI_NCR_PCIQ_BROKEN_INTR
  214. /*
  215. ** Some bridge designers decided to flush
  216. ** everything prior to deliver the interrupt.
  217. ** This option tries to deal with such a
  218. ** behaviour.
  219. */
  220. #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
  221. #define SCSI_NCR_PCIQ_SYNC_ON_INTR
  222. #endif
  223. /*
  224. ** Other parameters not configurable with "make config"
  225. ** Avoid to change these constants, unless you know what you are doing.
  226. */
  227. #define SCSI_NCR_ALWAYS_SIMPLE_TAG
  228. #define SCSI_NCR_MAX_SCATTER (127)
  229. #define SCSI_NCR_MAX_TARGET (16)
  230. /*
  231. ** Compute some desirable value for CAN_QUEUE
  232. ** and CMD_PER_LUN.
  233. ** The driver will use lower values if these
  234. ** ones appear to be too large.
  235. */
  236. #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
  237. #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
  238. #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
  239. #define SCSI_NCR_TIMER_INTERVAL (HZ)
  240. #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
  241. #define SCSI_NCR_MAX_LUN (16)
  242. #else
  243. #define SCSI_NCR_MAX_LUN (1)
  244. #endif
  245. /*
  246. * IO functions definition for big/little endian CPU support.
  247. * For now, the NCR is only supported in little endian addressing mode,
  248. */
  249. #ifdef __BIG_ENDIAN
  250. #define inw_l2b inw
  251. #define inl_l2b inl
  252. #define outw_b2l outw
  253. #define outl_b2l outl
  254. #define readb_raw readb
  255. #define writeb_raw writeb
  256. #if defined(SCSI_NCR_BIG_ENDIAN)
  257. #define readw_l2b __raw_readw
  258. #define readl_l2b __raw_readl
  259. #define writew_b2l __raw_writew
  260. #define writel_b2l __raw_writel
  261. #define readw_raw __raw_readw
  262. #define readl_raw __raw_readl
  263. #define writew_raw __raw_writew
  264. #define writel_raw __raw_writel
  265. #else /* Other big-endian */
  266. #define readw_l2b readw
  267. #define readl_l2b readl
  268. #define writew_b2l writew
  269. #define writel_b2l writel
  270. #define readw_raw readw
  271. #define readl_raw readl
  272. #define writew_raw writew
  273. #define writel_raw writel
  274. #endif
  275. #else /* little endian */
  276. #define inw_raw inw
  277. #define inl_raw inl
  278. #define outw_raw outw
  279. #define outl_raw outl
  280. #define readb_raw readb
  281. #define readw_raw readw
  282. #define readl_raw readl
  283. #define writeb_raw writeb
  284. #define writew_raw writew
  285. #define writel_raw writel
  286. #endif
  287. #if !defined(__hppa__) && !defined(__mips__)
  288. #ifdef SCSI_NCR_BIG_ENDIAN
  289. #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
  290. #endif
  291. #endif
  292. #define MEMORY_BARRIER() mb()
  293. /*
  294. * If the NCR uses big endian addressing mode over the
  295. * PCI, actual io register addresses for byte and word
  296. * accesses must be changed according to lane routing.
  297. * Btw, ncr_offb() and ncr_offw() macros only apply to
  298. * constants and so donnot generate bloated code.
  299. */
  300. #if defined(SCSI_NCR_BIG_ENDIAN)
  301. #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
  302. #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
  303. #else
  304. #define ncr_offb(o) (o)
  305. #define ncr_offw(o) (o)
  306. #endif
  307. /*
  308. * If the CPU and the NCR use same endian-ness addressing,
  309. * no byte reordering is needed for script patching.
  310. * Macro cpu_to_scr() is to be used for script patching.
  311. * Macro scr_to_cpu() is to be used for getting a DWORD
  312. * from the script.
  313. */
  314. #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
  315. #define cpu_to_scr(dw) cpu_to_le32(dw)
  316. #define scr_to_cpu(dw) le32_to_cpu(dw)
  317. #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
  318. #define cpu_to_scr(dw) cpu_to_be32(dw)
  319. #define scr_to_cpu(dw) be32_to_cpu(dw)
  320. #else
  321. #define cpu_to_scr(dw) (dw)
  322. #define scr_to_cpu(dw) (dw)
  323. #endif
  324. /*
  325. * Access to the controller chip.
  326. *
  327. * If the CPU and the NCR use same endian-ness addressing,
  328. * no byte reordering is needed for accessing chip io
  329. * registers. Functions suffixed by '_raw' are assumed
  330. * to access the chip over the PCI without doing byte
  331. * reordering. Functions suffixed by '_l2b' are
  332. * assumed to perform little-endian to big-endian byte
  333. * reordering, those suffixed by '_b2l' blah, blah,
  334. * blah, ...
  335. */
  336. /*
  337. * MEMORY mapped IO input / output
  338. */
  339. #define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o))
  340. #define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
  341. #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
  342. #define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o))
  343. #define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o))
  344. #define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
  345. #define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o))
  346. #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
  347. #define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o))
  348. #define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o))
  349. #define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
  350. #define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o))
  351. #else
  352. #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
  353. /* Only 8 or 32 bit transfers allowed */
  354. #define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
  355. #else
  356. #define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o))
  357. #endif
  358. #define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))
  359. #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
  360. /* Only 8 or 32 bit transfers allowed */
  361. #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
  362. #else
  363. #define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
  364. #endif
  365. #define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o))
  366. #endif
  367. #define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
  368. #define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
  369. #define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
  370. #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
  371. #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
  372. #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
  373. /*
  374. * Set bit field ON, OFF
  375. */
  376. #define OUTONB(r, m) OUTB(r, INB(r) | (m))
  377. #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
  378. #define OUTONW(r, m) OUTW(r, INW(r) | (m))
  379. #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
  380. #define OUTONL(r, m) OUTL(r, INL(r) | (m))
  381. #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
  382. /*
  383. * We normally want the chip to have a consistent view
  384. * of driver internal data structures when we restart it.
  385. * Thus these macros.
  386. */
  387. #define OUTL_DSP(v) \
  388. do { \
  389. MEMORY_BARRIER(); \
  390. OUTL (nc_dsp, (v)); \
  391. } while (0)
  392. #define OUTONB_STD() \
  393. do { \
  394. MEMORY_BARRIER(); \
  395. OUTONB (nc_dcntl, (STD|NOCOM)); \
  396. } while (0)
  397. /*
  398. ** NCR53C8XX devices features table.
  399. */
  400. struct ncr_chip {
  401. unsigned short revision_id;
  402. unsigned char burst_max; /* log-base-2 of max burst */
  403. unsigned char offset_max;
  404. unsigned char nr_divisor;
  405. unsigned int features;
  406. #define FE_LED0 (1<<0)
  407. #define FE_WIDE (1<<1) /* Wide data transfers */
  408. #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
  409. #define FE_DBLR (1<<4) /* Clock doubler present */
  410. #define FE_QUAD (1<<5) /* Clock quadrupler present */
  411. #define FE_ERL (1<<6) /* Enable read line */
  412. #define FE_CLSE (1<<7) /* Cache line size enable */
  413. #define FE_WRIE (1<<8) /* Write & Invalidate enable */
  414. #define FE_ERMP (1<<9) /* Enable read multiple */
  415. #define FE_BOF (1<<10) /* Burst opcode fetch */
  416. #define FE_DFS (1<<11) /* DMA fifo size */
  417. #define FE_PFEN (1<<12) /* Prefetch enable */
  418. #define FE_LDSTR (1<<13) /* Load/Store supported */
  419. #define FE_RAM (1<<14) /* On chip RAM present */
  420. #define FE_VARCLK (1<<15) /* SCSI clock may vary */
  421. #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
  422. #define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
  423. #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
  424. #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
  425. #define FE_LEDC (1<<20) /* Hardware control of LED */
  426. #define FE_DIFF (1<<21) /* Support Differential SCSI */
  427. #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
  428. #define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
  429. #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
  430. #define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
  431. #define FE_EHP (1<<27) /* 720: Even host parity */
  432. #define FE_MUX (1<<28) /* 720: Multiplexed bus */
  433. #define FE_EA (1<<29) /* 720: Enable Ack */
  434. #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
  435. #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
  436. #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
  437. };
  438. /*
  439. ** Driver setup structure.
  440. **
  441. ** This structure is initialized from linux config options.
  442. ** It can be overridden at boot-up by the boot command line.
  443. */
  444. #define SCSI_NCR_MAX_EXCLUDES 8
  445. struct ncr_driver_setup {
  446. u8 master_parity;
  447. u8 scsi_parity;
  448. u8 disconnection;
  449. u8 special_features;
  450. u8 force_sync_nego;
  451. u8 reverse_probe;
  452. u8 pci_fix_up;
  453. u8 use_nvram;
  454. u8 verbose;
  455. u8 default_tags;
  456. u16 default_sync;
  457. u16 debug;
  458. u8 burst_max;
  459. u8 led_pin;
  460. u8 max_wide;
  461. u8 settle_delay;
  462. u8 diff_support;
  463. u8 irqm;
  464. u8 bus_check;
  465. u8 optimize;
  466. u8 recovery;
  467. u8 host_id;
  468. u16 iarb;
  469. u32 excludes[SCSI_NCR_MAX_EXCLUDES];
  470. char tag_ctrl[100];
  471. };
  472. /*
  473. ** Initial setup.
  474. ** Can be overridden at startup by a command line.
  475. */
  476. #define SCSI_NCR_DRIVER_SETUP \
  477. { \
  478. SCSI_NCR_SETUP_MASTER_PARITY, \
  479. SCSI_NCR_SETUP_SCSI_PARITY, \
  480. SCSI_NCR_SETUP_DISCONNECTION, \
  481. SCSI_NCR_SETUP_SPECIAL_FEATURES, \
  482. SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
  483. 0, \
  484. 0, \
  485. 1, \
  486. 0, \
  487. SCSI_NCR_SETUP_DEFAULT_TAGS, \
  488. SCSI_NCR_SETUP_DEFAULT_SYNC, \
  489. 0x00, \
  490. 7, \
  491. 0, \
  492. 1, \
  493. SCSI_NCR_SETUP_SETTLE_TIME, \
  494. 0, \
  495. 0, \
  496. 1, \
  497. 0, \
  498. 0, \
  499. 255, \
  500. 0x00 \
  501. }
  502. /*
  503. ** Boot fail safe setup.
  504. ** Override initial setup from boot command line:
  505. ** ncr53c8xx=safe:y
  506. */
  507. #define SCSI_NCR_DRIVER_SAFE_SETUP \
  508. { \
  509. 0, \
  510. 1, \
  511. 0, \
  512. 0, \
  513. 0, \
  514. 0, \
  515. 0, \
  516. 1, \
  517. 2, \
  518. 0, \
  519. 255, \
  520. 0x00, \
  521. 255, \
  522. 0, \
  523. 0, \
  524. 10, \
  525. 1, \
  526. 1, \
  527. 1, \
  528. 0, \
  529. 0, \
  530. 255 \
  531. }
  532. /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
  533. /*-----------------------------------------------------------------
  534. **
  535. ** The ncr 53c810 register structure.
  536. **
  537. **-----------------------------------------------------------------
  538. */
  539. struct ncr_reg {
  540. /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
  541. /*01*/ u8 nc_scntl1; /* no reset */
  542. #define ISCON 0x10 /* connected to scsi */
  543. #define CRST 0x08 /* force reset */
  544. #define IARB 0x02 /* immediate arbitration */
  545. /*02*/ u8 nc_scntl2; /* no disconnect expected */
  546. #define SDU 0x80 /* cmd: disconnect will raise error */
  547. #define CHM 0x40 /* sta: chained mode */
  548. #define WSS 0x08 /* sta: wide scsi send [W]*/
  549. #define WSR 0x01 /* sta: wide scsi received [W]*/
  550. /*03*/ u8 nc_scntl3; /* cnf system clock dependent */
  551. #define EWS 0x08 /* cmd: enable wide scsi [W]*/
  552. #define ULTRA 0x80 /* cmd: ULTRA enable */
  553. /* bits 0-2, 7 rsvd for C1010 */
  554. /*04*/ u8 nc_scid; /* cnf host adapter scsi address */
  555. #define RRE 0x40 /* r/w:e enable response to resel. */
  556. #define SRE 0x20 /* r/w:e enable response to select */
  557. /*05*/ u8 nc_sxfer; /* ### Sync speed and count */
  558. /* bits 6-7 rsvd for C1010 */
  559. /*06*/ u8 nc_sdid; /* ### Destination-ID */
  560. /*07*/ u8 nc_gpreg; /* ??? IO-Pins */
  561. /*08*/ u8 nc_sfbr; /* ### First byte in phase */
  562. /*09*/ u8 nc_socl;
  563. #define CREQ 0x80 /* r/w: SCSI-REQ */
  564. #define CACK 0x40 /* r/w: SCSI-ACK */
  565. #define CBSY 0x20 /* r/w: SCSI-BSY */
  566. #define CSEL 0x10 /* r/w: SCSI-SEL */
  567. #define CATN 0x08 /* r/w: SCSI-ATN */
  568. #define CMSG 0x04 /* r/w: SCSI-MSG */
  569. #define CC_D 0x02 /* r/w: SCSI-C_D */
  570. #define CI_O 0x01 /* r/w: SCSI-I_O */
  571. /*0a*/ u8 nc_ssid;
  572. /*0b*/ u8 nc_sbcl;
  573. /*0c*/ u8 nc_dstat;
  574. #define DFE 0x80 /* sta: dma fifo empty */
  575. #define MDPE 0x40 /* int: master data parity error */
  576. #define BF 0x20 /* int: script: bus fault */
  577. #define ABRT 0x10 /* int: script: command aborted */
  578. #define SSI 0x08 /* int: script: single step */
  579. #define SIR 0x04 /* int: script: interrupt instruct. */
  580. #define IID 0x01 /* int: script: illegal instruct. */
  581. /*0d*/ u8 nc_sstat0;
  582. #define ILF 0x80 /* sta: data in SIDL register lsb */
  583. #define ORF 0x40 /* sta: data in SODR register lsb */
  584. #define OLF 0x20 /* sta: data in SODL register lsb */
  585. #define AIP 0x10 /* sta: arbitration in progress */
  586. #define LOA 0x08 /* sta: arbitration lost */
  587. #define WOA 0x04 /* sta: arbitration won */
  588. #define IRST 0x02 /* sta: scsi reset signal */
  589. #define SDP 0x01 /* sta: scsi parity signal */
  590. /*0e*/ u8 nc_sstat1;
  591. #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
  592. /*0f*/ u8 nc_sstat2;
  593. #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
  594. #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
  595. #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
  596. #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
  597. #define LDSC 0x02 /* sta: disconnect & reconnect */
  598. /*10*/ u8 nc_dsa; /* --> Base page */
  599. /*11*/ u8 nc_dsa1;
  600. /*12*/ u8 nc_dsa2;
  601. /*13*/ u8 nc_dsa3;
  602. /*14*/ u8 nc_istat; /* --> Main Command and status */
  603. #define CABRT 0x80 /* cmd: abort current operation */
  604. #define SRST 0x40 /* mod: reset chip */
  605. #define SIGP 0x20 /* r/w: message from host to ncr */
  606. #define SEM 0x10 /* r/w: message between host + ncr */
  607. #define CON 0x08 /* sta: connected to scsi */
  608. #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
  609. #define SIP 0x02 /* sta: scsi-interrupt */
  610. #define DIP 0x01 /* sta: host/script interrupt */
  611. /*15*/ u8 nc_istat1; /* 896 and later cores only */
  612. #define FLSH 0x04 /* sta: chip is flushing */
  613. #define SRUN 0x02 /* sta: scripts are running */
  614. #define SIRQD 0x01 /* r/w: disable INT pin */
  615. /*16*/ u8 nc_mbox0; /* 896 and later cores only */
  616. /*17*/ u8 nc_mbox1; /* 896 and later cores only */
  617. /*18*/ u8 nc_ctest0;
  618. #define EHP 0x04 /* 720 even host parity */
  619. /*19*/ u8 nc_ctest1;
  620. /*1a*/ u8 nc_ctest2;
  621. #define CSIGP 0x40
  622. /* bits 0-2,7 rsvd for C1010 */
  623. /*1b*/ u8 nc_ctest3;
  624. #define FLF 0x08 /* cmd: flush dma fifo */
  625. #define CLF 0x04 /* cmd: clear dma fifo */
  626. #define FM 0x02 /* mod: fetch pin mode */
  627. #define WRIE 0x01 /* mod: write and invalidate enable */
  628. /* bits 4-7 rsvd for C1010 */
  629. /*1c*/ u32 nc_temp; /* ### Temporary stack */
  630. /*20*/ u8 nc_dfifo;
  631. /*21*/ u8 nc_ctest4;
  632. #define MUX 0x80 /* 720 host bus multiplex mode */
  633. #define BDIS 0x80 /* mod: burst disable */
  634. #define MPEE 0x08 /* mod: master parity error enable */
  635. /*22*/ u8 nc_ctest5;
  636. #define DFS 0x20 /* mod: dma fifo size */
  637. /* bits 0-1, 3-7 rsvd for C1010 */
  638. /*23*/ u8 nc_ctest6;
  639. /*24*/ u32 nc_dbc; /* ### Byte count and command */
  640. /*28*/ u32 nc_dnad; /* ### Next command register */
  641. /*2c*/ u32 nc_dsp; /* --> Script Pointer */
  642. /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
  643. /*34*/ u8 nc_scratcha; /* Temporary register a */
  644. /*35*/ u8 nc_scratcha1;
  645. /*36*/ u8 nc_scratcha2;
  646. /*37*/ u8 nc_scratcha3;
  647. /*38*/ u8 nc_dmode;
  648. #define BL_2 0x80 /* mod: burst length shift value +2 */
  649. #define BL_1 0x40 /* mod: burst length shift value +1 */
  650. #define ERL 0x08 /* mod: enable read line */
  651. #define ERMP 0x04 /* mod: enable read multiple */
  652. #define BOF 0x02 /* mod: burst op code fetch */
  653. /*39*/ u8 nc_dien;
  654. /*3a*/ u8 nc_sbr;
  655. /*3b*/ u8 nc_dcntl; /* --> Script execution control */
  656. #define CLSE 0x80 /* mod: cache line size enable */
  657. #define PFF 0x40 /* cmd: pre-fetch flush */
  658. #define PFEN 0x20 /* mod: pre-fetch enable */
  659. #define EA 0x20 /* mod: 720 enable-ack */
  660. #define SSM 0x10 /* mod: single step mode */
  661. #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
  662. #define STD 0x04 /* cmd: start dma mode */
  663. #define IRQD 0x02 /* mod: irq disable */
  664. #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
  665. /* bits 0-1 rsvd for C1010 */
  666. /*3c*/ u32 nc_adder;
  667. /*40*/ u16 nc_sien; /* -->: interrupt enable */
  668. /*42*/ u16 nc_sist; /* <--: interrupt status */
  669. #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
  670. #define STO 0x0400/* sta: timeout (select) */
  671. #define GEN 0x0200/* sta: timeout (general) */
  672. #define HTH 0x0100/* sta: timeout (handshake) */
  673. #define MA 0x80 /* sta: phase mismatch */
  674. #define CMP 0x40 /* sta: arbitration complete */
  675. #define SEL 0x20 /* sta: selected by another device */
  676. #define RSL 0x10 /* sta: reselected by another device*/
  677. #define SGE 0x08 /* sta: gross error (over/underflow)*/
  678. #define UDC 0x04 /* sta: unexpected disconnect */
  679. #define RST 0x02 /* sta: scsi bus reset detected */
  680. #define PAR 0x01 /* sta: scsi parity error */
  681. /*44*/ u8 nc_slpar;
  682. /*45*/ u8 nc_swide;
  683. /*46*/ u8 nc_macntl;
  684. /*47*/ u8 nc_gpcntl;
  685. /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
  686. /*49*/ u8 nc_stime1; /* cmd: timeout user defined */
  687. /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
  688. /*4c*/ u8 nc_stest0;
  689. /*4d*/ u8 nc_stest1;
  690. #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
  691. #define DBLEN 0x08 /* clock doubler running */
  692. #define DBLSEL 0x04 /* clock doubler selected */
  693. /*4e*/ u8 nc_stest2;
  694. #define ROF 0x40 /* reset scsi offset (after gross error!) */
  695. #define DIF 0x20 /* 720 SCSI differential mode */
  696. #define EXT 0x02 /* extended filtering */
  697. /*4f*/ u8 nc_stest3;
  698. #define TE 0x80 /* c: tolerAnt enable */
  699. #define HSC 0x20 /* c: Halt SCSI Clock */
  700. #define CSF 0x02 /* c: clear scsi fifo */
  701. /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
  702. /*52*/ u8 nc_stest4;
  703. #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
  704. #define SMODE_HVD 0x40 /* High Voltage Differential */
  705. #define SMODE_SE 0x80 /* Single Ended */
  706. #define SMODE_LVD 0xc0 /* Low Voltage Differential */
  707. #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
  708. /* bits 0-5 rsvd for C1010 */
  709. /*53*/ u8 nc_53_;
  710. /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
  711. /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
  712. #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
  713. #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
  714. #define ENNDJ 0x20 /* Enable Non Data PM Jump */
  715. #define DISFC 0x10 /* Disable Auto FIFO Clear */
  716. #define DILS 0x02 /* Disable Internal Load/Store */
  717. #define DPR 0x01 /* Disable Pipe Req */
  718. /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
  719. #define ZMOD 0x80 /* High Impedance Mode */
  720. #define DIC 0x10 /* Disable Internal Cycles */
  721. #define DDAC 0x08 /* Disable Dual Address Cycle */
  722. #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
  723. #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
  724. #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
  725. /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
  726. /*5a*/ u16 nc_5a_;
  727. /*5c*/ u8 nc_scr0; /* Working register B */
  728. /*5d*/ u8 nc_scr1; /* */
  729. /*5e*/ u8 nc_scr2; /* */
  730. /*5f*/ u8 nc_scr3; /* */
  731. /*60*/ u8 nc_scrx[64]; /* Working register C-R */
  732. /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
  733. /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
  734. /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
  735. /*ac*/ u32 nc_drs; /* DSA Relative Selector */
  736. /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
  737. /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
  738. /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
  739. /*bc*/ u16 nc_scntl4; /* C1010 only */
  740. #define U3EN 0x80 /* Enable Ultra 3 */
  741. #define AIPEN 0x40 /* Allow check upper byte lanes */
  742. #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
  743. transfer edge */
  744. #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
  745. transfer edge */
  746. /*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
  747. /*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
  748. /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
  749. /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
  750. /*c8*/ u8 nc_rbc; /* Remaining Byte Count */
  751. /*c9*/ u8 nc_rbc1; /* */
  752. /*ca*/ u8 nc_rbc2; /* */
  753. /*cb*/ u8 nc_rbc3; /* */
  754. /*cc*/ u8 nc_ua; /* Updated Address */
  755. /*cd*/ u8 nc_ua1; /* */
  756. /*ce*/ u8 nc_ua2; /* */
  757. /*cf*/ u8 nc_ua3; /* */
  758. /*d0*/ u32 nc_esa; /* Entry Storage Address */
  759. /*d4*/ u8 nc_ia; /* Instruction Address */
  760. /*d5*/ u8 nc_ia1;
  761. /*d6*/ u8 nc_ia2;
  762. /*d7*/ u8 nc_ia3;
  763. /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
  764. /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
  765. /* Following for C1010 only */
  766. /*e0*/ u16 nc_crcpad; /* CRC Value */
  767. /*e2*/ u8 nc_crccntl0; /* CRC control register */
  768. #define SNDCRC 0x10 /* Send CRC Request */
  769. /*e3*/ u8 nc_crccntl1; /* CRC control register */
  770. /*e4*/ u32 nc_crcdata; /* CRC data register */
  771. /*e8*/ u32 nc_e8_; /* rsvd */
  772. /*ec*/ u32 nc_ec_; /* rsvd */
  773. /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
  774. };
  775. /*-----------------------------------------------------------
  776. **
  777. ** Utility macros for the script.
  778. **
  779. **-----------------------------------------------------------
  780. */
  781. #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
  782. #define REG(r) REGJ (nc_, r)
  783. typedef u32 ncrcmd;
  784. /*-----------------------------------------------------------
  785. **
  786. ** SCSI phases
  787. **
  788. ** DT phases illegal for ncr driver.
  789. **
  790. **-----------------------------------------------------------
  791. */
  792. #define SCR_DATA_OUT 0x00000000
  793. #define SCR_DATA_IN 0x01000000
  794. #define SCR_COMMAND 0x02000000
  795. #define SCR_STATUS 0x03000000
  796. #define SCR_DT_DATA_OUT 0x04000000
  797. #define SCR_DT_DATA_IN 0x05000000
  798. #define SCR_MSG_OUT 0x06000000
  799. #define SCR_MSG_IN 0x07000000
  800. #define SCR_ILG_OUT 0x04000000
  801. #define SCR_ILG_IN 0x05000000
  802. /*-----------------------------------------------------------
  803. **
  804. ** Data transfer via SCSI.
  805. **
  806. **-----------------------------------------------------------
  807. **
  808. ** MOVE_ABS (LEN)
  809. ** <<start address>>
  810. **
  811. ** MOVE_IND (LEN)
  812. ** <<dnad_offset>>
  813. **
  814. ** MOVE_TBL
  815. ** <<dnad_offset>>
  816. **
  817. **-----------------------------------------------------------
  818. */
  819. #define OPC_MOVE 0x08000000
  820. #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
  821. #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
  822. #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
  823. #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
  824. #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
  825. #define SCR_CHMOV_TBL (0x10000000)
  826. struct scr_tblmove {
  827. u32 size;
  828. u32 addr;
  829. };
  830. /*-----------------------------------------------------------
  831. **
  832. ** Selection
  833. **
  834. **-----------------------------------------------------------
  835. **
  836. ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
  837. ** <<alternate_address>>
  838. **
  839. ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
  840. ** <<alternate_address>>
  841. **
  842. **-----------------------------------------------------------
  843. */
  844. #define SCR_SEL_ABS 0x40000000
  845. #define SCR_SEL_ABS_ATN 0x41000000
  846. #define SCR_SEL_TBL 0x42000000
  847. #define SCR_SEL_TBL_ATN 0x43000000
  848. #ifdef SCSI_NCR_BIG_ENDIAN
  849. struct scr_tblsel {
  850. u8 sel_scntl3;
  851. u8 sel_id;
  852. u8 sel_sxfer;
  853. u8 sel_scntl4;
  854. };
  855. #else
  856. struct scr_tblsel {
  857. u8 sel_scntl4;
  858. u8 sel_sxfer;
  859. u8 sel_id;
  860. u8 sel_scntl3;
  861. };
  862. #endif
  863. #define SCR_JMP_REL 0x04000000
  864. #define SCR_ID(id) (((u32)(id)) << 16)
  865. /*-----------------------------------------------------------
  866. **
  867. ** Waiting for Disconnect or Reselect
  868. **
  869. **-----------------------------------------------------------
  870. **
  871. ** WAIT_DISC
  872. ** dummy: <<alternate_address>>
  873. **
  874. ** WAIT_RESEL
  875. ** <<alternate_address>>
  876. **
  877. **-----------------------------------------------------------
  878. */
  879. #define SCR_WAIT_DISC 0x48000000
  880. #define SCR_WAIT_RESEL 0x50000000
  881. /*-----------------------------------------------------------
  882. **
  883. ** Bit Set / Reset
  884. **
  885. **-----------------------------------------------------------
  886. **
  887. ** SET (flags {|.. })
  888. **
  889. ** CLR (flags {|.. })
  890. **
  891. **-----------------------------------------------------------
  892. */
  893. #define SCR_SET(f) (0x58000000 | (f))
  894. #define SCR_CLR(f) (0x60000000 | (f))
  895. #define SCR_CARRY 0x00000400
  896. #define SCR_TRG 0x00000200
  897. #define SCR_ACK 0x00000040
  898. #define SCR_ATN 0x00000008
  899. /*-----------------------------------------------------------
  900. **
  901. ** Memory to memory move
  902. **
  903. **-----------------------------------------------------------
  904. **
  905. ** COPY (bytecount)
  906. ** << source_address >>
  907. ** << destination_address >>
  908. **
  909. ** SCR_COPY sets the NO FLUSH option by default.
  910. ** SCR_COPY_F does not set this option.
  911. **
  912. ** For chips which do not support this option,
  913. ** ncr_copy_and_bind() will remove this bit.
  914. **-----------------------------------------------------------
  915. */
  916. #define SCR_NO_FLUSH 0x01000000
  917. #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
  918. #define SCR_COPY_F(n) (0xc0000000 | (n))
  919. /*-----------------------------------------------------------
  920. **
  921. ** Register move and binary operations
  922. **
  923. **-----------------------------------------------------------
  924. **
  925. ** SFBR_REG (reg, op, data) reg = SFBR op data
  926. ** << 0 >>
  927. **
  928. ** REG_SFBR (reg, op, data) SFBR = reg op data
  929. ** << 0 >>
  930. **
  931. ** REG_REG (reg, op, data) reg = reg op data
  932. ** << 0 >>
  933. **
  934. **-----------------------------------------------------------
  935. ** On 810A, 860, 825A, 875, 895 and 896 chips the content
  936. ** of SFBR register can be used as data (SCR_SFBR_DATA).
  937. ** The 896 has additional IO registers starting at
  938. ** offset 0x80. Bit 7 of register offset is stored in
  939. ** bit 7 of the SCRIPTS instruction first DWORD.
  940. **-----------------------------------------------------------
  941. */
  942. #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
  943. #define SCR_SFBR_REG(reg,op,data) \
  944. (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  945. #define SCR_REG_SFBR(reg,op,data) \
  946. (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  947. #define SCR_REG_REG(reg,op,data) \
  948. (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  949. #define SCR_LOAD 0x00000000
  950. #define SCR_SHL 0x01000000
  951. #define SCR_OR 0x02000000
  952. #define SCR_XOR 0x03000000
  953. #define SCR_AND 0x04000000
  954. #define SCR_SHR 0x05000000
  955. #define SCR_ADD 0x06000000
  956. #define SCR_ADDC 0x07000000
  957. #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
  958. /*-----------------------------------------------------------
  959. **
  960. ** FROM_REG (reg) SFBR = reg
  961. ** << 0 >>
  962. **
  963. ** TO_REG (reg) reg = SFBR
  964. ** << 0 >>
  965. **
  966. ** LOAD_REG (reg, data) reg = <data>
  967. ** << 0 >>
  968. **
  969. ** LOAD_SFBR(data) SFBR = <data>
  970. ** << 0 >>
  971. **
  972. **-----------------------------------------------------------
  973. */
  974. #define SCR_FROM_REG(reg) \
  975. SCR_REG_SFBR(reg,SCR_OR,0)
  976. #define SCR_TO_REG(reg) \
  977. SCR_SFBR_REG(reg,SCR_OR,0)
  978. #define SCR_LOAD_REG(reg,data) \
  979. SCR_REG_REG(reg,SCR_LOAD,data)
  980. #define SCR_LOAD_SFBR(data) \
  981. (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
  982. /*-----------------------------------------------------------
  983. **
  984. ** LOAD from memory to register.
  985. ** STORE from register to memory.
  986. **
  987. ** Only supported by 810A, 860, 825A, 875, 895 and 896.
  988. **
  989. **-----------------------------------------------------------
  990. **
  991. ** LOAD_ABS (LEN)
  992. ** <<start address>>
  993. **
  994. ** LOAD_REL (LEN) (DSA relative)
  995. ** <<dsa_offset>>
  996. **
  997. **-----------------------------------------------------------
  998. */
  999. #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
  1000. #define SCR_NO_FLUSH2 0x02000000
  1001. #define SCR_DSA_REL2 0x10000000
  1002. #define SCR_LOAD_R(reg, how, n) \
  1003. (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  1004. #define SCR_STORE_R(reg, how, n) \
  1005. (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  1006. #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
  1007. #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
  1008. #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
  1009. #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
  1010. #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
  1011. #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
  1012. #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
  1013. #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
  1014. /*-----------------------------------------------------------
  1015. **
  1016. ** Waiting for Disconnect or Reselect
  1017. **
  1018. **-----------------------------------------------------------
  1019. **
  1020. ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
  1021. ** <<address>>
  1022. **
  1023. ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
  1024. ** <<distance>>
  1025. **
  1026. ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
  1027. ** <<address>>
  1028. **
  1029. ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
  1030. ** <<distance>>
  1031. **
  1032. ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
  1033. ** <<dummy>>
  1034. **
  1035. ** INT [ | IFTRUE/IFFALSE ( ... ) ]
  1036. ** <<ident>>
  1037. **
  1038. ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
  1039. ** <<ident>>
  1040. **
  1041. ** Conditions:
  1042. ** WHEN (phase)
  1043. ** IF (phase)
  1044. ** CARRYSET
  1045. ** DATA (data, mask)
  1046. **
  1047. **-----------------------------------------------------------
  1048. */
  1049. #define SCR_NO_OP 0x80000000
  1050. #define SCR_JUMP 0x80080000
  1051. #define SCR_JUMP64 0x80480000
  1052. #define SCR_JUMPR 0x80880000
  1053. #define SCR_CALL 0x88080000
  1054. #define SCR_CALLR 0x88880000
  1055. #define SCR_RETURN 0x90080000
  1056. #define SCR_INT 0x98080000
  1057. #define SCR_INT_FLY 0x98180000
  1058. #define IFFALSE(arg) (0x00080000 | (arg))
  1059. #define IFTRUE(arg) (0x00000000 | (arg))
  1060. #define WHEN(phase) (0x00030000 | (phase))
  1061. #define IF(phase) (0x00020000 | (phase))
  1062. #define DATA(D) (0x00040000 | ((D) & 0xff))
  1063. #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
  1064. #define CARRYSET (0x00200000)
  1065. /*-----------------------------------------------------------
  1066. **
  1067. ** SCSI constants.
  1068. **
  1069. **-----------------------------------------------------------
  1070. */
  1071. /*
  1072. ** Status
  1073. */
  1074. #define S_GOOD (0x00)
  1075. #define S_CHECK_COND (0x02)
  1076. #define S_COND_MET (0x04)
  1077. #define S_BUSY (0x08)
  1078. #define S_INT (0x10)
  1079. #define S_INT_COND_MET (0x14)
  1080. #define S_CONFLICT (0x18)
  1081. #define S_TERMINATED (0x20)
  1082. #define S_QUEUE_FULL (0x28)
  1083. #define S_ILLEGAL (0xff)
  1084. #define S_SENSE (0x80)
  1085. /*
  1086. * End of ncrreg from FreeBSD
  1087. */
  1088. /*
  1089. Build a scatter/gather entry.
  1090. see sym53c8xx_2/sym_hipd.h for more detailed sym_build_sge()
  1091. implementation ;)
  1092. */
  1093. #define ncr_build_sge(np, data, badd, len) \
  1094. do { \
  1095. (data)->addr = cpu_to_scr(badd); \
  1096. (data)->size = cpu_to_scr(len); \
  1097. } while (0)
  1098. /*==========================================================
  1099. **
  1100. ** Structures used by the detection routine to transmit
  1101. ** device configuration to the attach function.
  1102. **
  1103. **==========================================================
  1104. */
  1105. struct ncr_slot {
  1106. u_long base;
  1107. u_long base_2;
  1108. u_long base_c;
  1109. u_long base_2_c;
  1110. void __iomem *base_v;
  1111. void __iomem *base_2_v;
  1112. int irq;
  1113. /* port and reg fields to use INB, OUTB macros */
  1114. volatile struct ncr_reg __iomem *reg;
  1115. };
  1116. /*==========================================================
  1117. **
  1118. ** Structure used by detection routine to save data on
  1119. ** each detected board for attach.
  1120. **
  1121. **==========================================================
  1122. */
  1123. struct ncr_device {
  1124. struct device *dev;
  1125. struct ncr_slot slot;
  1126. struct ncr_chip chip;
  1127. u_char host_id;
  1128. u8 differential;
  1129. };
  1130. extern struct Scsi_Host *ncr_attach(struct scsi_host_template *tpnt, int unit, struct ncr_device *device);
  1131. extern int ncr53c8xx_release(struct Scsi_Host *host);
  1132. irqreturn_t ncr53c8xx_intr(int irq, void *dev_id);
  1133. extern int ncr53c8xx_init(void);
  1134. extern void ncr53c8xx_exit(void);
  1135. #endif /* NCR53C8XX_H */