mac53c94.h 4.9 KB

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  1. /*
  2. * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor
  3. * found on Power Macintosh computers, controlling the external SCSI chain.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. */
  7. #ifndef _MAC53C94_H
  8. #define _MAC53C94_H
  9. /*
  10. * Registers in the 53C94 controller.
  11. */
  12. struct mac53c94_regs {
  13. unsigned char count_lo;
  14. char pad0[15];
  15. unsigned char count_mid;
  16. char pad1[15];
  17. unsigned char fifo;
  18. char pad2[15];
  19. unsigned char command;
  20. char pad3[15];
  21. unsigned char status;
  22. char pad4[15];
  23. unsigned char interrupt;
  24. char pad5[15];
  25. unsigned char seqstep;
  26. char pad6[15];
  27. unsigned char flags;
  28. char pad7[15];
  29. unsigned char config1;
  30. char pad8[15];
  31. unsigned char clk_factor;
  32. char pad9[15];
  33. unsigned char test;
  34. char pad10[15];
  35. unsigned char config2;
  36. char pad11[15];
  37. unsigned char config3;
  38. char pad12[15];
  39. unsigned char config4;
  40. char pad13[15];
  41. unsigned char count_hi;
  42. char pad14[15];
  43. unsigned char fifo_res;
  44. char pad15[15];
  45. };
  46. /*
  47. * Alternate functions for some registers.
  48. */
  49. #define dest_id status
  50. #define sel_timeout interrupt
  51. #define sync_period seqstep
  52. #define sync_offset flags
  53. /*
  54. * Bits in command register.
  55. */
  56. #define CMD_DMA_MODE 0x80
  57. #define CMD_MODE_MASK 0x70
  58. #define CMD_MODE_INIT 0x10
  59. #define CMD_MODE_TARG 0x20
  60. #define CMD_MODE_DISC 0x40
  61. #define CMD_NOP 0
  62. #define CMD_FLUSH 1
  63. #define CMD_RESET 2
  64. #define CMD_SCSI_RESET 3
  65. #define CMD_XFER_DATA 0x10
  66. #define CMD_I_COMPLETE 0x11
  67. #define CMD_ACCEPT_MSG 0x12
  68. #define CMD_XFER_PAD 0x18
  69. #define CMD_SET_ATN 0x1a
  70. #define CMD_CLR_ATN 0x1b
  71. #define CMD_SEND_MSG 0x20
  72. #define CMD_SEND_STATUS 0x21
  73. #define CMD_SEND_DATA 0x22
  74. #define CMD_DISC_SEQ 0x23
  75. #define CMD_TERMINATE 0x24
  76. #define CMD_T_COMPLETE 0x25
  77. #define CMD_DISCONNECT 0x27
  78. #define CMD_RECV_MSG 0x28
  79. #define CMD_RECV_CDB 0x29
  80. #define CMD_RECV_DATA 0x2a
  81. #define CMD_RECV_CMD 0x2b
  82. #define CMD_ABORT_DMA 0x04
  83. #define CMD_RESELECT 0x40
  84. #define CMD_SELECT 0x41
  85. #define CMD_SELECT_ATN 0x42
  86. #define CMD_SELATN_STOP 0x43
  87. #define CMD_ENABLE_SEL 0x44
  88. #define CMD_DISABLE_SEL 0x45
  89. #define CMD_SEL_ATN3 0x46
  90. #define CMD_RESEL_ATN3 0x47
  91. /*
  92. * Bits in status register.
  93. */
  94. #define STAT_IRQ 0x80
  95. #define STAT_ERROR 0x40
  96. #define STAT_PARITY 0x20
  97. #define STAT_TC_ZERO 0x10
  98. #define STAT_DONE 0x08
  99. #define STAT_PHASE 0x07
  100. #define STAT_MSG 0x04
  101. #define STAT_CD 0x02
  102. #define STAT_IO 0x01
  103. /*
  104. * Bits in interrupt register.
  105. */
  106. #define INTR_RESET 0x80 /* SCSI bus was reset */
  107. #define INTR_ILL_CMD 0x40 /* illegal command */
  108. #define INTR_DISCONNECT 0x20 /* we got disconnected */
  109. #define INTR_BUS_SERV 0x10 /* bus service requested */
  110. #define INTR_DONE 0x08 /* function completed */
  111. #define INTR_RESELECTED 0x04 /* we were reselected */
  112. #define INTR_SEL_ATN 0x02 /* we were selected, ATN asserted */
  113. #define INTR_SELECT 0x01 /* we were selected, ATN negated */
  114. /*
  115. * Encoding for the select timeout.
  116. */
  117. #define TIMO_VAL(x) ((x) * 5000 / 7682)
  118. /*
  119. * Bits in sequence step register.
  120. */
  121. #define SS_MASK 7
  122. #define SS_ARB_SEL 0 /* Selection & arbitration complete */
  123. #define SS_MSG_SENT 1 /* One message byte sent */
  124. #define SS_NOT_CMD 2 /* Not in command phase */
  125. #define SS_PHASE_CHG 3 /* Early phase change, cmd bytes lost */
  126. #define SS_DONE 4 /* Command was sent OK */
  127. /*
  128. * Encoding for sync transfer period.
  129. */
  130. #define SYNCP_MASK 0x1f
  131. #define SYNCP_MIN 4
  132. #define SYNCP_MAX 31
  133. /*
  134. * Bits in flags register.
  135. */
  136. #define FLAGS_FIFO_LEV 0x1f
  137. #define FLAGS_SEQ_STEP 0xe0
  138. /*
  139. * Encoding for sync offset.
  140. */
  141. #define SYNCO_MASK 0x0f
  142. #define SYNCO_ASS_CTRL 0x30 /* REQ/ACK assertion control */
  143. #define SYNCO_NEG_CTRL 0xc0 /* REQ/ACK negation control */
  144. /*
  145. * Bits in config1 register.
  146. */
  147. #define CF1_SLOW_CABLE 0x80 /* Slow cable mode */
  148. #define CF1_NO_RES_REP 0x40 /* Disable SCSI reset reports */
  149. #define CF1_PAR_TEST 0x20 /* Parity test mode enable */
  150. #define CF1_PAR_ENABLE 0x10 /* Enable parity checks */
  151. #define CF1_TEST 0x08 /* Chip tests */
  152. #define CF1_MY_ID 0x07 /* Controller's address on bus */
  153. /*
  154. * Encoding for clk_factor register.
  155. */
  156. #define CLKF_MASK 7
  157. #define CLKF_VAL(freq) ((((freq) + 4999999) / 5000000) & CLKF_MASK)
  158. /*
  159. * Bits in test mode register.
  160. */
  161. #define TEST_TARGET 1 /* target test mode */
  162. #define TEST_INITIATOR 2 /* initiator test mode */
  163. #define TEST_TRISTATE 4 /* tristate (hi-z) test mode */
  164. /*
  165. * Bits in config2 register.
  166. */
  167. #define CF2_RFB 0x80
  168. #define CF2_FEATURE_EN 0x40 /* enable features / phase latch */
  169. #define CF2_BYTECTRL 0x20
  170. #define CF2_DREQ_HIZ 0x10
  171. #define CF2_SCSI2 0x08
  172. #define CF2_PAR_ABORT 0x04 /* bad parity target abort */
  173. #define CF2_REG_PARERR 0x02 /* register parity error */
  174. #define CF2_DMA_PARERR 0x01 /* DMA parity error */
  175. /*
  176. * Bits in the config3 register.
  177. */
  178. #define CF3_ID_MSG_CHK 0x80
  179. #define CF3_3B_MSGS 0x40
  180. #define CF3_CDB10 0x20
  181. #define CF3_FASTSCSI 0x10 /* enable fast SCSI support */
  182. #define CF3_FASTCLOCK 0x08
  183. #define CF3_SAVERESID 0x04
  184. #define CF3_ALT_DMA 0x02
  185. #define CF3_THRESH_8 0x01
  186. /*
  187. * Bits in the config4 register.
  188. */
  189. #define CF4_EAN 0x04
  190. #define CF4_TEST 0x02
  191. #define CF4_BBTE 0x01
  192. #endif /* _MAC53C94_H */