dc395x.h 25 KB

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  1. /************************************************************************/
  2. /* */
  3. /* dc395x.h */
  4. /* */
  5. /* Device Driver for Tekram DC395(U/UW/F), DC315(U) */
  6. /* PCI SCSI Bus Master Host Adapter */
  7. /* (SCSI chip set used Tekram ASIC TRM-S1040) */
  8. /* */
  9. /************************************************************************/
  10. #ifndef DC395x_H
  11. #define DC395x_H
  12. /************************************************************************/
  13. /* */
  14. /* Initial values */
  15. /* */
  16. /************************************************************************/
  17. #define DC395x_MAX_CMD_QUEUE 32
  18. /* #define DC395x_MAX_QTAGS 32 */
  19. #define DC395x_MAX_QTAGS 16
  20. #define DC395x_MAX_SCSI_ID 16
  21. #define DC395x_MAX_CMD_PER_LUN DC395x_MAX_QTAGS
  22. #define DC395x_MAX_SG_TABLESIZE 64 /* HW limitation */
  23. #define DC395x_MAX_SG_LISTENTRY 64 /* Must be equal or lower to previous */
  24. /* item */
  25. #define DC395x_MAX_SRB_CNT 63
  26. /* #define DC395x_MAX_CAN_QUEUE 7 * DC395x_MAX_QTAGS */
  27. #define DC395x_MAX_CAN_QUEUE DC395x_MAX_SRB_CNT
  28. #define DC395x_END_SCAN 2
  29. #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
  30. #define DC395x_MAX_RETRIES 3
  31. #if 0
  32. #define SYNC_FIRST
  33. #endif
  34. #define NORM_REC_LVL 0
  35. /************************************************************************/
  36. /* */
  37. /* Various definitions */
  38. /* */
  39. /************************************************************************/
  40. #define BIT31 0x80000000
  41. #define BIT30 0x40000000
  42. #define BIT29 0x20000000
  43. #define BIT28 0x10000000
  44. #define BIT27 0x08000000
  45. #define BIT26 0x04000000
  46. #define BIT25 0x02000000
  47. #define BIT24 0x01000000
  48. #define BIT23 0x00800000
  49. #define BIT22 0x00400000
  50. #define BIT21 0x00200000
  51. #define BIT20 0x00100000
  52. #define BIT19 0x00080000
  53. #define BIT18 0x00040000
  54. #define BIT17 0x00020000
  55. #define BIT16 0x00010000
  56. #define BIT15 0x00008000
  57. #define BIT14 0x00004000
  58. #define BIT13 0x00002000
  59. #define BIT12 0x00001000
  60. #define BIT11 0x00000800
  61. #define BIT10 0x00000400
  62. #define BIT9 0x00000200
  63. #define BIT8 0x00000100
  64. #define BIT7 0x00000080
  65. #define BIT6 0x00000040
  66. #define BIT5 0x00000020
  67. #define BIT4 0x00000010
  68. #define BIT3 0x00000008
  69. #define BIT2 0x00000004
  70. #define BIT1 0x00000002
  71. #define BIT0 0x00000001
  72. /* UnitCtrlFlag */
  73. #define UNIT_ALLOCATED BIT0
  74. #define UNIT_INFO_CHANGED BIT1
  75. #define FORMATING_MEDIA BIT2
  76. #define UNIT_RETRY BIT3
  77. /* UnitFlags */
  78. #define DASD_SUPPORT BIT0
  79. #define SCSI_SUPPORT BIT1
  80. #define ASPI_SUPPORT BIT2
  81. /* SRBState machine definition */
  82. #define SRB_FREE 0x0000
  83. #define SRB_WAIT 0x0001
  84. #define SRB_READY 0x0002
  85. #define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */
  86. #define SRB_MSGIN 0x0008
  87. #define SRB_EXTEND_MSGIN 0x0010
  88. #define SRB_COMMAND 0x0020
  89. #define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */
  90. #define SRB_DISCONNECT 0x0080
  91. #define SRB_DATA_XFER 0x0100
  92. #define SRB_XFERPAD 0x0200
  93. #define SRB_STATUS 0x0400
  94. #define SRB_COMPLETED 0x0800
  95. #define SRB_ABORT_SENT 0x1000
  96. #define SRB_DO_SYNC_NEGO 0x2000
  97. #define SRB_DO_WIDE_NEGO 0x4000
  98. #define SRB_UNEXPECT_RESEL 0x8000
  99. /************************************************************************/
  100. /* */
  101. /* ACB Config */
  102. /* */
  103. /************************************************************************/
  104. #define HCC_WIDE_CARD 0x20
  105. #define HCC_SCSI_RESET 0x10
  106. #define HCC_PARITY 0x08
  107. #define HCC_AUTOTERM 0x04
  108. #define HCC_LOW8TERM 0x02
  109. #define HCC_UP8TERM 0x01
  110. /* ACBFlag */
  111. #define RESET_DEV BIT0
  112. #define RESET_DETECT BIT1
  113. #define RESET_DONE BIT2
  114. /* DCBFlag */
  115. #define ABORT_DEV_ BIT0
  116. /* SRBstatus */
  117. #define SRB_OK BIT0
  118. #define ABORTION BIT1
  119. #define OVER_RUN BIT2
  120. #define UNDER_RUN BIT3
  121. #define PARITY_ERROR BIT4
  122. #define SRB_ERROR BIT5
  123. /* SRBFlag */
  124. #define DATAOUT BIT7
  125. #define DATAIN BIT6
  126. #define RESIDUAL_VALID BIT5
  127. #define ENABLE_TIMER BIT4
  128. #define RESET_DEV0 BIT2
  129. #define ABORT_DEV BIT1
  130. #define AUTO_REQSENSE BIT0
  131. /* Adapter status */
  132. #define H_STATUS_GOOD 0
  133. #define H_SEL_TIMEOUT 0x11
  134. #define H_OVER_UNDER_RUN 0x12
  135. #define H_UNEXP_BUS_FREE 0x13
  136. #define H_TARGET_PHASE_F 0x14
  137. #define H_INVALID_CCB_OP 0x16
  138. #define H_LINK_CCB_BAD 0x17
  139. #define H_BAD_TARGET_DIR 0x18
  140. #define H_DUPLICATE_CCB 0x19
  141. #define H_BAD_CCB_OR_SG 0x1A
  142. #define H_ABORT 0x0FF
  143. /* SCSI BUS Status byte codes */
  144. #define SCSI_STAT_GOOD 0x0 /* Good status */
  145. #define SCSI_STAT_CHECKCOND 0x02 /* SCSI Check Condition */
  146. #define SCSI_STAT_CONDMET 0x04 /* Condition Met */
  147. #define SCSI_STAT_BUSY 0x08 /* Target busy status */
  148. #define SCSI_STAT_INTER 0x10 /* Intermediate status */
  149. #define SCSI_STAT_INTERCONDMET 0x14 /* Intermediate condition met */
  150. #define SCSI_STAT_RESCONFLICT 0x18 /* Reservation conflict */
  151. #define SCSI_STAT_CMDTERM 0x22 /* Command Terminated */
  152. #define SCSI_STAT_QUEUEFULL 0x28 /* Queue Full */
  153. #define SCSI_STAT_UNEXP_BUS_F 0xFD /* Unexpect Bus Free */
  154. #define SCSI_STAT_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */
  155. #define SCSI_STAT_SEL_TIMEOUT 0xFF /* Selection Time out */
  156. /* Sync_Mode */
  157. #define SYNC_WIDE_TAG_ATNT_DISABLE 0
  158. #define SYNC_NEGO_ENABLE BIT0
  159. #define SYNC_NEGO_DONE BIT1
  160. #define WIDE_NEGO_ENABLE BIT2
  161. #define WIDE_NEGO_DONE BIT3
  162. #define WIDE_NEGO_STATE BIT4
  163. #define EN_TAG_QUEUEING BIT5
  164. #define EN_ATN_STOP BIT6
  165. #define SYNC_NEGO_OFFSET 15
  166. /* SCSI MSG BYTE */
  167. #define MSG_COMPLETE 0x00
  168. #define MSG_EXTENDED 0x01
  169. #define MSG_SAVE_PTR 0x02
  170. #define MSG_RESTORE_PTR 0x03
  171. #define MSG_DISCONNECT 0x04
  172. #define MSG_INITIATOR_ERROR 0x05
  173. #define MSG_ABORT 0x06
  174. #define MSG_REJECT_ 0x07
  175. #define MSG_NOP 0x08
  176. #define MSG_PARITY_ERROR 0x09
  177. #define MSG_LINK_CMD_COMPL 0x0A
  178. #define MSG_LINK_CMD_COMPL_FLG 0x0B
  179. #define MSG_BUS_RESET 0x0C
  180. #define MSG_ABORT_TAG 0x0D
  181. #define MSG_SIMPLE_QTAG 0x20
  182. #define MSG_HEAD_QTAG 0x21
  183. #define MSG_ORDER_QTAG 0x22
  184. #define MSG_IGNOREWIDE 0x23
  185. #define MSG_IDENTIFY 0x80
  186. #define MSG_HOST_ID 0xC0
  187. /* SCSI STATUS BYTE */
  188. #define STATUS_GOOD 0x00
  189. #define CHECK_CONDITION_ 0x02
  190. #define STATUS_BUSY 0x08
  191. #define STATUS_INTERMEDIATE 0x10
  192. #define RESERVE_CONFLICT 0x18
  193. /* cmd->result */
  194. #define STATUS_MASK_ 0xFF
  195. #define MSG_MASK 0xFF00
  196. #define RETURN_MASK 0xFF0000
  197. /************************************************************************/
  198. /* */
  199. /* Inquiry Data format */
  200. /* */
  201. /************************************************************************/
  202. struct ScsiInqData
  203. { /* INQ */
  204. u8 DevType; /* Periph Qualifier & Periph Dev Type */
  205. u8 RMB_TypeMod; /* rem media bit & Dev Type Modifier */
  206. u8 Vers; /* ISO, ECMA, & ANSI versions */
  207. u8 RDF; /* AEN, TRMIOP, & response data format */
  208. u8 AddLen; /* length of additional data */
  209. u8 Res1; /* reserved */
  210. u8 Res2; /* reserved */
  211. u8 Flags; /* RelADr, Wbus32, Wbus16, Sync, etc. */
  212. u8 VendorID[8]; /* Vendor Identification */
  213. u8 ProductID[16]; /* Product Identification */
  214. u8 ProductRev[4]; /* Product Revision */
  215. };
  216. /* Inquiry byte 0 masks */
  217. #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
  218. #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
  219. /* Inquiry byte 1 mask */
  220. #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
  221. /* Peripheral Device Type definitions */
  222. /* See include/scsi/scsi.h */
  223. #define TYPE_NODEV SCSI_DEVTYPE /* Unknown or no device type */
  224. #ifndef TYPE_PRINTER /* */
  225. # define TYPE_PRINTER 0x02 /* Printer device */
  226. #endif /* */
  227. #ifndef TYPE_COMM /* */
  228. # define TYPE_COMM 0x09 /* Communications device */
  229. #endif
  230. /************************************************************************/
  231. /* */
  232. /* Inquiry flag definitions (Inq data byte 7) */
  233. /* */
  234. /************************************************************************/
  235. #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing */
  236. #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
  237. #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
  238. #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
  239. #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
  240. #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
  241. #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
  242. #define ENABLE_CE 1
  243. #define DISABLE_CE 0
  244. #define EEPROM_READ 0x80
  245. /************************************************************************/
  246. /* */
  247. /* The PCI configuration register offset for TRM_S1040 */
  248. /* */
  249. /************************************************************************/
  250. #define TRM_S1040_ID 0x00 /* Vendor and Device ID */
  251. #define TRM_S1040_COMMAND 0x04 /* PCI command register */
  252. #define TRM_S1040_IOBASE 0x10 /* I/O Space base address */
  253. #define TRM_S1040_ROMBASE 0x30 /* Expansion ROM Base Address */
  254. #define TRM_S1040_INTLINE 0x3C /* Interrupt line */
  255. /************************************************************************/
  256. /* */
  257. /* The SCSI register offset for TRM_S1040 */
  258. /* */
  259. /************************************************************************/
  260. #define TRM_S1040_SCSI_STATUS 0x80 /* SCSI Status (R) */
  261. #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
  262. #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
  263. #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
  264. #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
  265. #define COMMANDABORT 0x0040 /* SCSI command abort */
  266. #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
  267. #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
  268. #define PARITYERROR 0x0008 /* SCSI parity error */
  269. #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
  270. #define PH_DATA_OUT 0x00 /* Data out phase */
  271. #define PH_DATA_IN 0x01 /* Data in phase */
  272. #define PH_COMMAND 0x02 /* Command phase */
  273. #define PH_STATUS 0x03 /* Status phase */
  274. #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */
  275. #define PH_MSG_OUT 0x06 /* Message out phase */
  276. #define PH_MSG_IN 0x07 /* Message in phase */
  277. #define TRM_S1040_SCSI_CONTROL 0x80 /* SCSI Control (W) */
  278. #define DO_CLRATN 0x0400 /* Clear ATN */
  279. #define DO_SETATN 0x0200 /* Set ATN */
  280. #define DO_CMDABORT 0x0100 /* Abort SCSI command */
  281. #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
  282. #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
  283. #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
  284. #define DO_DATALATCH 0x0002 /* Enable SCSI bus data input (latched) */
  285. /* #define DO_DATALATCH 0x0000 */ /* KG: DISable SCSI bus data latch */
  286. #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
  287. #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
  288. #define TRM_S1040_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
  289. #define TRM_S1040_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
  290. #define INT_SCAM 0x80 /* SCAM selection interrupt */
  291. #define INT_SELECT 0x40 /* Selection interrupt */
  292. #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
  293. #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
  294. #define INT_RESELECTED 0x08 /* Reselected interrupt */
  295. #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */
  296. #define INT_BUSSERVICE 0x02 /* Bus service interrupt */
  297. #define INT_CMDDONE 0x01 /* SCSI command done interrupt */
  298. #define TRM_S1040_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
  299. /************************************************************************/
  300. /* */
  301. /* Bit Name Definition */
  302. /* --------- ------------- ---------------------------- */
  303. /* 07-05 0 RSVD Reversed. Always 0. */
  304. /* 04 0 OFFSET4 Reversed for LVDS. Always 0. */
  305. /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */
  306. /* */
  307. /************************************************************************/
  308. #define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */
  309. #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
  310. #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */
  311. #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
  312. /************************************************************************/
  313. /* */
  314. /* SYNCM 7 6 5 4 3 2 1 0 */
  315. /* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 */
  316. /* Default 0 0 0 0 0 0 0 0 */
  317. /* */
  318. /* Bit Name Definition */
  319. /* --------- ------------- --------------------------- */
  320. /* 07-06 0 RSVD Reversed. Always read 0 */
  321. /* 05 0 LVDS Reversed. Always read 0 */
  322. /* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI */
  323. /* transfer. */
  324. /* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. */
  325. /* */
  326. /* @@ When this bit is set, */
  327. /* the synchronous period bits 2:0 */
  328. /* in the Synchronous Mode register */
  329. /* are used to transfer data */
  330. /* at the Fast-20 rate. */
  331. /* @@ When this bit is unset, */
  332. /* the synchronous period bits 2:0 */
  333. /* in the Synchronous Mode Register */
  334. /* are used to transfer data */
  335. /* at the Fast-10 rate (or Fast-40 w/ LVDS). */
  336. /* */
  337. /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
  338. /* SXPD[02:00] These 3 bits specify */
  339. /* the Synchronous SCSI Transfer */
  340. /* Rate for Fast-20 and Fast-10. */
  341. /* These bits are also reset */
  342. /* by a SCSI Bus reset. */
  343. /* */
  344. /* For Fast-10 bit ALTPD = 0 and LVDS = 0 */
  345. /* and bit2,bit1,bit0 is defined as follows : */
  346. /* */
  347. /* 000 100ns, 10.0 MHz */
  348. /* 001 150ns, 6.6 MHz */
  349. /* 010 200ns, 5.0 MHz */
  350. /* 011 250ns, 4.0 MHz */
  351. /* 100 300ns, 3.3 MHz */
  352. /* 101 350ns, 2.8 MHz */
  353. /* 110 400ns, 2.5 MHz */
  354. /* 111 450ns, 2.2 MHz */
  355. /* */
  356. /* For Fast-20 bit ALTPD = 1 and LVDS = 0 */
  357. /* and bit2,bit1,bit0 is defined as follows : */
  358. /* */
  359. /* 000 50ns, 20.0 MHz */
  360. /* 001 75ns, 13.3 MHz */
  361. /* 010 100ns, 10.0 MHz */
  362. /* 011 125ns, 8.0 MHz */
  363. /* 100 150ns, 6.6 MHz */
  364. /* 101 175ns, 5.7 MHz */
  365. /* 110 200ns, 5.0 MHz */
  366. /* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */
  367. /* */
  368. /* For Fast-40 bit ALTPD = 0 and LVDS = 1 */
  369. /* and bit2,bit1,bit0 is defined as follows : */
  370. /* */
  371. /* 000 25ns, 40.0 MHz */
  372. /* 001 50ns, 20.0 MHz */
  373. /* 010 75ns, 13.3 MHz */
  374. /* 011 100ns, 10.0 MHz */
  375. /* 100 125ns, 8.0 MHz */
  376. /* 101 150ns, 6.6 MHz */
  377. /* 110 175ns, 5.7 MHz */
  378. /* 111 200ns, 5.0 MHz */
  379. /* */
  380. /************************************************************************/
  381. #define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
  382. #define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
  383. #define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
  384. #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
  385. #define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
  386. #define EN_SCAM 0x80 /* Enable SCAM selection interrupt */
  387. #define EN_SELECT 0x40 /* Enable selection interrupt */
  388. #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */
  389. #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */
  390. #define EN_RESELECTED 0x08 /* Enable reselected interrupt */
  391. #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt */
  392. #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */
  393. #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */
  394. #define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
  395. #define PHASELATCH 0x40 /* Enable phase latch */
  396. #define INITIATOR 0x20 /* Enable initiator mode */
  397. #define PARITYCHECK 0x10 /* Enable parity check */
  398. #define BLOCKRST 0x01 /* Disable SCSI reset1 */
  399. #define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
  400. #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
  401. #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
  402. #define FAST_FILTER 0x04 /* ? */
  403. #define ACTIVE_NEG 0x02 /* Enable active negation */
  404. #define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */
  405. #define CFG2_WIDEFIFO 0x02 /* */
  406. #define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
  407. #define SCMD_COMP 0x12 /* Command complete */
  408. #define SCMD_SEL_ATN 0x60 /* Selection with ATN */
  409. #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
  410. #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
  411. #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
  412. #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
  413. #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
  414. #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
  415. #define SCMD_MSGACCEPT 0xD8 /* Message accept */
  416. /************************************************************************/
  417. /* */
  418. /* Code Command Description */
  419. /* ---- ---------------------------------------- */
  420. /* 02 Enable reselection with FIFO */
  421. /* 40 Select without ATN with FIFO */
  422. /* 60 Select with ATN with FIFO */
  423. /* 64 Select with ATN3 with FIFO */
  424. /* A0 Select with ATN and stop with FIFO */
  425. /* C0 Transfer information out with FIFO */
  426. /* C1 Transfer information out with DMA */
  427. /* C2 Transfer information in with FIFO */
  428. /* C3 Transfer information in with DMA */
  429. /* 12 Initiator command complete with FIFO */
  430. /* 50 Initiator transfer information out sequence without ATN */
  431. /* with FIFO */
  432. /* 70 Initiator transfer information out sequence with ATN */
  433. /* with FIFO */
  434. /* 74 Initiator transfer information out sequence with ATN3 */
  435. /* with FIFO */
  436. /* 52 Initiator transfer information in sequence without ATN */
  437. /* with FIFO */
  438. /* 72 Initiator transfer information in sequence with ATN */
  439. /* with FIFO */
  440. /* 76 Initiator transfer information in sequence with ATN3 */
  441. /* with FIFO */
  442. /* 90 Initiator transfer information out command complete */
  443. /* with FIFO */
  444. /* 92 Initiator transfer information in command complete */
  445. /* with FIFO */
  446. /* D2 Enable selection */
  447. /* 08 Reselection */
  448. /* 48 Disconnect command with FIFO */
  449. /* 88 Terminate command with FIFO */
  450. /* C8 Target command complete with FIFO */
  451. /* 18 SCAM Arbitration/ Selection */
  452. /* 5A Enable reselection */
  453. /* 98 Select without ATN with FIFO */
  454. /* B8 Select with ATN with FIFO */
  455. /* D8 Message Accepted */
  456. /* 58 NOP */
  457. /* */
  458. /************************************************************************/
  459. #define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
  460. #define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
  461. #define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
  462. #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
  463. #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */
  464. #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */
  465. #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */
  466. #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
  467. #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
  468. #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
  469. #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
  470. #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
  471. #define TCR0_OFFSET_MASK 0x001F /* Offset number */
  472. #define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
  473. #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
  474. #define NON_TAG_BUSY 0x0080 /* Non tag command active */
  475. #define ACTTAG_MASK 0x007F /* Active tags */
  476. /************************************************************************/
  477. /* */
  478. /* The DMA register offset for TRM_S1040 */
  479. /* */
  480. /************************************************************************/
  481. #define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
  482. #define DMACMD_SG 0x02 /* Enable HW S/G support */
  483. #define DMACMD_DIR 0x01 /* 1 = read from SCSI write to Host */
  484. #define XFERDATAIN_SG 0x0103 /* Transfer data in w/ SG */
  485. #define XFERDATAOUT_SG 0x0102 /* Transfer data out w/ SG */
  486. #define XFERDATAIN 0x0101 /* Transfer data in w/o SG */
  487. #define XFERDATAOUT 0x0100 /* Transfer data out w/o SG */
  488. #define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
  489. #define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */
  490. #define DMARESETMODULE 0x10 /* Reset PCI/DMA module */
  491. #define STOPDMAXFER 0x08 /* Stop DMA transfer */
  492. #define ABORTXFER 0x04 /* Abort DMA transfer */
  493. #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
  494. #define STARTDMAXFER 0x01 /* Start DMA transfer */
  495. #define TRM_S1040_DMA_FIFOSTAT 0xA2 /* DMA FIFO Status (R) */
  496. #define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
  497. #define XFERPENDING 0x80 /* Transfer pending */
  498. #define SCSIBUSY 0x40 /* SCSI busy */
  499. #define GLOBALINT 0x20 /* DMA_INTEN bit 0-4 set */
  500. #define FORCEDMACOMP 0x10 /* Force DMA transfer complete */
  501. #define DMAXFERERROR 0x08 /* DMA transfer error */
  502. #define DMAXFERABORT 0x04 /* DMA transfer abort */
  503. #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
  504. #define SCSICOMP 0x01 /* SCSI complete interrupt */
  505. #define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */
  506. #define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */
  507. #define EN_DMAXFERERROR 0x08 /* DMA transfer error */
  508. #define EN_DMAXFERABORT 0x04 /* DMA transfer abort */
  509. #define EN_DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
  510. #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
  511. #define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
  512. #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature (SG?) */
  513. #define DMA_PCI_DUAL_ADDR 0x4000 /* */
  514. #define DMA_CFG_RES 0x2000 /* Always 1 */
  515. #define DMA_AUTO_CLR_FIFO 0x1000 /* DISable DMA auto clear FIFO */
  516. #define DMA_MEM_MULTI_READ 0x0800 /* */
  517. #define DMA_MEM_WRITE_INVAL 0x0400 /* Memory write and invalidate */
  518. #define DMA_FIFO_CTRL 0x0300 /* Control FIFO operation with DMA */
  519. #define DMA_FIFO_HALF_HALF 0x0200 /* Keep half filled on both read/write */
  520. #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W), 24bits */
  521. #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
  522. #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
  523. #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */
  524. /************************************************************************/
  525. /* */
  526. /* The general register offset for TRM_S1040 */
  527. /* */
  528. /************************************************************************/
  529. #define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */
  530. #define CTRL_LED 0x80 /* Control onboard LED */
  531. #define EN_EEPROM 0x10 /* Enable EEPROM programming */
  532. #define DIS_TERM 0x08 /* Disable onboard termination */
  533. #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
  534. #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
  535. #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
  536. #define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */
  537. #define GTIMEOUT 0x80 /* Global timer reach 0 */
  538. #define EXT68HIGH 0x40 /* Higher 8 bit connected externally */
  539. #define INT68HIGH 0x20 /* Higher 8 bit connected internally */
  540. #define CON5068 0x10 /* External 50/68 pin connected (low) */
  541. #define CON68 0x08 /* Internal 68 pin connected (low) */
  542. #define CON50 0x04 /* Internal 50 pin connected (low!) */
  543. #define WIDESCSI 0x02 /* Wide SCSI card */
  544. #define STATUS_LOAD_DEFAULT 0x01 /* */
  545. #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
  546. #define NVR_BITOUT 0x08 /* Serial data out */
  547. #define NVR_BITIN 0x04 /* Serial data in */
  548. #define NVR_CLOCK 0x02 /* Serial clock */
  549. #define NVR_SELECT 0x01 /* Serial select */
  550. #define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */
  551. #define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */
  552. #define TRM_S1040_GEN_TIMER 0xDB /* Global timer */
  553. /************************************************************************/
  554. /* */
  555. /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */
  556. /* */
  557. /************************************************************************/
  558. #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
  559. #define NTC_DO_TAG_QUEUEING 0x10 /* Enable SCSI tag queuing */
  560. #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */
  561. #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
  562. #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
  563. #define NTC_DO_PARITY_CHK 0x01 /* (it sould define at NAC) */
  564. /* Parity check enable */
  565. /************************************************************************/
  566. /* */
  567. /* Nvram Initiater bits definition */
  568. /* */
  569. /************************************************************************/
  570. #if 0
  571. #define MORE2_DRV BIT0
  572. #define GREATER_1G BIT1
  573. #define RST_SCSI_BUS BIT2
  574. #define ACTIVE_NEGATION BIT3
  575. #define NO_SEEK BIT4
  576. #define LUN_CHECK BIT5
  577. #endif
  578. /************************************************************************/
  579. /* */
  580. /* Nvram Adapter Cfg bits definition */
  581. /* */
  582. /************************************************************************/
  583. #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */
  584. #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
  585. #define NAC_GREATER_1G 0x02 /* > 1G support enable */
  586. #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */
  587. /* #define NAC_DO_PARITY_CHK 0x08 */ /* Parity check enable */
  588. #endif