NCR53C9x.h 30 KB

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  1. /* NCR53C9x.c: Defines and structures for the NCR53C9x generic driver.
  2. *
  3. * Originaly esp.h: Defines and structures for the Sparc ESP
  4. * (Enhanced SCSI Processor) driver under Linux.
  5. *
  6. * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
  7. *
  8. * Generalization by Jesper Skov (jskov@cygnus.co.uk)
  9. *
  10. * More generalization (for i386 stuff) by Tymm Twillman (tymm@computer.org)
  11. */
  12. #ifndef NCR53C9X_H
  13. #define NCR53C9X_H
  14. #include <linux/interrupt.h>
  15. /* djweis for mac driver */
  16. #if defined(CONFIG_MAC)
  17. #define PAD_SIZE 15
  18. #else
  19. #define PAD_SIZE 3
  20. #endif
  21. /* Handle multiple hostadapters on Amiga
  22. * generally PAD_SIZE = 3
  23. * but there is one exception: Oktagon (PAD_SIZE = 1) */
  24. #if defined(CONFIG_OKTAGON_SCSI) || defined(CONFIG_OKTAGON_SCSI_MODULE)
  25. #undef PAD_SIZE
  26. #if defined(CONFIG_BLZ1230_SCSI) || defined(CONFIG_BLZ1230_SCSI_MODULE) || \
  27. defined(CONFIG_BLZ2060_SCSI) || defined(CONFIG_BLZ2060_SCSI_MODULE) || \
  28. defined(CONFIG_CYBERSTORM_SCSI) || defined(CONFIG_CYBERSTORM_SCSI_MODULE) || \
  29. defined(CONFIG_CYBERSTORMII_SCSI) || defined(CONFIG_CYBERSTORMII_SCSI_MODULE) || \
  30. defined(CONFIG_FASTLANE_SCSI) || defined(CONFIG_FASTLANE_SCSI_MODULE)
  31. #define MULTIPLE_PAD_SIZES
  32. #else
  33. #define PAD_SIZE 1
  34. #endif
  35. #endif
  36. /* Macros for debugging messages */
  37. #define DEBUG_ESP
  38. /* #define DEBUG_ESP_DATA */
  39. /* #define DEBUG_ESP_QUEUE */
  40. /* #define DEBUG_ESP_DISCONNECT */
  41. /* #define DEBUG_ESP_STATUS */
  42. /* #define DEBUG_ESP_PHASES */
  43. /* #define DEBUG_ESP_WORKBUS */
  44. /* #define DEBUG_STATE_MACHINE */
  45. /* #define DEBUG_ESP_CMDS */
  46. /* #define DEBUG_ESP_IRQS */
  47. /* #define DEBUG_SDTR */
  48. /* #define DEBUG_ESP_SG */
  49. /* Use the following to sprinkle debugging messages in a way which
  50. * suits you if combinations of the above become too verbose when
  51. * trying to track down a specific problem.
  52. */
  53. /* #define DEBUG_ESP_MISC */
  54. #if defined(DEBUG_ESP)
  55. #define ESPLOG(foo) printk foo
  56. #else
  57. #define ESPLOG(foo)
  58. #endif /* (DEBUG_ESP) */
  59. #if defined(DEBUG_ESP_DATA)
  60. #define ESPDATA(foo) printk foo
  61. #else
  62. #define ESPDATA(foo)
  63. #endif
  64. #if defined(DEBUG_ESP_QUEUE)
  65. #define ESPQUEUE(foo) printk foo
  66. #else
  67. #define ESPQUEUE(foo)
  68. #endif
  69. #if defined(DEBUG_ESP_DISCONNECT)
  70. #define ESPDISC(foo) printk foo
  71. #else
  72. #define ESPDISC(foo)
  73. #endif
  74. #if defined(DEBUG_ESP_STATUS)
  75. #define ESPSTAT(foo) printk foo
  76. #else
  77. #define ESPSTAT(foo)
  78. #endif
  79. #if defined(DEBUG_ESP_PHASES)
  80. #define ESPPHASE(foo) printk foo
  81. #else
  82. #define ESPPHASE(foo)
  83. #endif
  84. #if defined(DEBUG_ESP_WORKBUS)
  85. #define ESPBUS(foo) printk foo
  86. #else
  87. #define ESPBUS(foo)
  88. #endif
  89. #if defined(DEBUG_ESP_IRQS)
  90. #define ESPIRQ(foo) printk foo
  91. #else
  92. #define ESPIRQ(foo)
  93. #endif
  94. #if defined(DEBUG_SDTR)
  95. #define ESPSDTR(foo) printk foo
  96. #else
  97. #define ESPSDTR(foo)
  98. #endif
  99. #if defined(DEBUG_ESP_MISC)
  100. #define ESPMISC(foo) printk foo
  101. #else
  102. #define ESPMISC(foo)
  103. #endif
  104. /*
  105. * padding for register structure
  106. */
  107. #ifdef CONFIG_JAZZ_ESP
  108. #define EREGS_PAD(n)
  109. #else
  110. #ifndef MULTIPLE_PAD_SIZES
  111. #define EREGS_PAD(n) unchar n[PAD_SIZE];
  112. #endif
  113. #endif
  114. /* The ESP SCSI controllers have their register sets in three
  115. * "classes":
  116. *
  117. * 1) Registers which are both read and write.
  118. * 2) Registers which are read only.
  119. * 3) Registers which are write only.
  120. *
  121. * Yet, they all live within the same IO space.
  122. */
  123. #if !defined(__i386__) && !defined(__x86_64__)
  124. #ifndef MULTIPLE_PAD_SIZES
  125. #ifdef CONFIG_CPU_HAS_WB
  126. #include <asm/wbflush.h>
  127. #define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
  128. #else
  129. #define esp_write(__reg, __val) ((__reg) = (__val))
  130. #endif
  131. #define esp_read(__reg) (__reg)
  132. struct ESP_regs {
  133. /* Access Description Offset */
  134. volatile unchar esp_tclow; /* rw Low bits of the transfer count 0x00 */
  135. EREGS_PAD(tlpad1);
  136. volatile unchar esp_tcmed; /* rw Mid bits of the transfer count 0x04 */
  137. EREGS_PAD(fdpad);
  138. volatile unchar esp_fdata; /* rw FIFO data bits 0x08 */
  139. EREGS_PAD(cbpad);
  140. volatile unchar esp_cmnd; /* rw SCSI command bits 0x0c */
  141. EREGS_PAD(stpad);
  142. volatile unchar esp_status; /* ro ESP status register 0x10 */
  143. #define esp_busid esp_status /* wo Bus ID for select/reselect 0x10 */
  144. EREGS_PAD(irqpd);
  145. volatile unchar esp_intrpt; /* ro Kind of interrupt 0x14 */
  146. #define esp_timeo esp_intrpt /* wo Timeout value for select/resel 0x14 */
  147. EREGS_PAD(sspad);
  148. volatile unchar esp_sstep; /* ro Sequence step register 0x18 */
  149. #define esp_stp esp_sstep /* wo Transfer period per sync 0x18 */
  150. EREGS_PAD(ffpad);
  151. volatile unchar esp_fflags; /* ro Bits of current FIFO info 0x1c */
  152. #define esp_soff esp_fflags /* wo Sync offset 0x1c */
  153. EREGS_PAD(cf1pd);
  154. volatile unchar esp_cfg1; /* rw First configuration register 0x20 */
  155. EREGS_PAD(cfpad);
  156. volatile unchar esp_cfact; /* wo Clock conversion factor 0x24 */
  157. EREGS_PAD(ctpad);
  158. volatile unchar esp_ctest; /* wo Chip test register 0x28 */
  159. EREGS_PAD(cf2pd);
  160. volatile unchar esp_cfg2; /* rw Second configuration register 0x2c */
  161. EREGS_PAD(cf3pd);
  162. /* The following is only found on the 53C9X series SCSI chips */
  163. volatile unchar esp_cfg3; /* rw Third configuration register 0x30 */
  164. EREGS_PAD(cf4pd);
  165. volatile unchar esp_cfg4; /* rw Fourth configuration register 0x34 */
  166. EREGS_PAD(thpd);
  167. /* The following is found on all chips except the NCR53C90 (ESP100) */
  168. volatile unchar esp_tchi; /* rw High bits of transfer count 0x38 */
  169. #define esp_uid esp_tchi /* ro Unique ID code 0x38 */
  170. EREGS_PAD(fgpad);
  171. volatile unchar esp_fgrnd; /* rw Data base for fifo 0x3c */
  172. };
  173. #else /* MULTIPLE_PAD_SIZES */
  174. #define esp_write(__reg, __val) (*(__reg) = (__val))
  175. #define esp_read(__reg) (*(__reg))
  176. struct ESP_regs {
  177. unsigned char io_addr[64]; /* dummy */
  178. /* Access Description Offset */
  179. #define esp_tclow io_addr /* rw Low bits of the transfer count 0x00 */
  180. #define esp_tcmed io_addr + (1<<(esp->shift)) /* rw Mid bits of the transfer count 0x04 */
  181. #define esp_fdata io_addr + (2<<(esp->shift)) /* rw FIFO data bits 0x08 */
  182. #define esp_cmnd io_addr + (3<<(esp->shift)) /* rw SCSI command bits 0x0c */
  183. #define esp_status io_addr + (4<<(esp->shift)) /* ro ESP status register 0x10 */
  184. #define esp_busid esp_status /* wo Bus ID for select/reselect 0x10 */
  185. #define esp_intrpt io_addr + (5<<(esp->shift)) /* ro Kind of interrupt 0x14 */
  186. #define esp_timeo esp_intrpt /* wo Timeout value for select/resel 0x14 */
  187. #define esp_sstep io_addr + (6<<(esp->shift)) /* ro Sequence step register 0x18 */
  188. #define esp_stp esp_sstep /* wo Transfer period per sync 0x18 */
  189. #define esp_fflags io_addr + (7<<(esp->shift)) /* ro Bits of current FIFO info 0x1c */
  190. #define esp_soff esp_fflags /* wo Sync offset 0x1c */
  191. #define esp_cfg1 io_addr + (8<<(esp->shift)) /* rw First configuration register 0x20 */
  192. #define esp_cfact io_addr + (9<<(esp->shift)) /* wo Clock conversion factor 0x24 */
  193. #define esp_ctest io_addr + (10<<(esp->shift)) /* wo Chip test register 0x28 */
  194. #define esp_cfg2 io_addr + (11<<(esp->shift)) /* rw Second configuration register 0x2c */
  195. /* The following is only found on the 53C9X series SCSI chips */
  196. #define esp_cfg3 io_addr + (12<<(esp->shift)) /* rw Third configuration register 0x30 */
  197. #define esp_cfg4 io_addr + (13<<(esp->shift)) /* rw Fourth configuration register 0x34 */
  198. /* The following is found on all chips except the NCR53C90 (ESP100) */
  199. #define esp_tchi io_addr + (14<<(esp->shift)) /* rw High bits of transfer count 0x38 */
  200. #define esp_uid esp_tchi /* ro Unique ID code 0x38 */
  201. #define esp_fgrnd io_addr + (15<<(esp->shift)) /* rw Data base for fifo 0x3c */
  202. };
  203. #endif
  204. #else /* !defined(__i386__) && !defined(__x86_64__) */
  205. #define esp_write(__reg, __val) outb((__val), (__reg))
  206. #define esp_read(__reg) inb((__reg))
  207. struct ESP_regs {
  208. unsigned int io_addr;
  209. /* Access Description Offset */
  210. #define esp_tclow io_addr /* rw Low bits of the transfer count 0x00 */
  211. #define esp_tcmed io_addr + 1 /* rw Mid bits of the transfer count 0x04 */
  212. #define esp_fdata io_addr + 2 /* rw FIFO data bits 0x08 */
  213. #define esp_cmnd io_addr + 3 /* rw SCSI command bits 0x0c */
  214. #define esp_status io_addr + 4 /* ro ESP status register 0x10 */
  215. #define esp_busid esp_status /* wo Bus ID for select/reselect 0x10 */
  216. #define esp_intrpt io_addr + 5 /* ro Kind of interrupt 0x14 */
  217. #define esp_timeo esp_intrpt /* wo Timeout value for select/resel 0x14 */
  218. #define esp_sstep io_addr + 6 /* ro Sequence step register 0x18 */
  219. #define esp_stp esp_sstep /* wo Transfer period per sync 0x18 */
  220. #define esp_fflags io_addr + 7 /* ro Bits of current FIFO info 0x1c */
  221. #define esp_soff esp_fflags /* wo Sync offset 0x1c */
  222. #define esp_cfg1 io_addr + 8 /* rw First configuration register 0x20 */
  223. #define esp_cfact io_addr + 9 /* wo Clock conversion factor 0x24 */
  224. #define esp_ctest io_addr + 10 /* wo Chip test register 0x28 */
  225. #define esp_cfg2 io_addr + 11 /* rw Second configuration register 0x2c */
  226. /* The following is only found on the 53C9X series SCSI chips */
  227. #define esp_cfg3 io_addr + 12 /* rw Third configuration register 0x30 */
  228. #define esp_cfg4 io_addr + 13 /* rw Fourth configuration register 0x34 */
  229. /* The following is found on all chips except the NCR53C90 (ESP100) */
  230. #define esp_tchi io_addr + 14 /* rw High bits of transfer count 0x38 */
  231. #define esp_uid esp_tchi /* ro Unique ID code 0x38 */
  232. #define esp_fgrnd io_addr + 15 /* rw Data base for fifo 0x3c */
  233. };
  234. #endif /* !defined(__i386__) && !defined(__x86_64__) */
  235. /* Various revisions of the ESP board. */
  236. enum esp_rev {
  237. esp100 = 0x00, /* NCR53C90 - very broken */
  238. esp100a = 0x01, /* NCR53C90A */
  239. esp236 = 0x02,
  240. fas236 = 0x03,
  241. fas100a = 0x04,
  242. fast = 0x05,
  243. fas366 = 0x06,
  244. fas216 = 0x07,
  245. fsc = 0x08, /* SYM53C94-2 */
  246. espunknown = 0x09
  247. };
  248. /* We allocate one of these for each scsi device and attach it to
  249. * SDptr->hostdata for use in the driver
  250. */
  251. struct esp_device {
  252. unsigned char sync_min_period;
  253. unsigned char sync_max_offset;
  254. unsigned sync:1;
  255. unsigned wide:1;
  256. unsigned disconnect:1;
  257. };
  258. /* We get one of these for each ESP probed. */
  259. struct NCR_ESP {
  260. struct NCR_ESP *next; /* Next ESP on probed or NULL */
  261. struct ESP_regs *eregs; /* All esp registers */
  262. int dma; /* Who I do transfers with. */
  263. void *dregs; /* And his registers. */
  264. struct Scsi_Host *ehost; /* Backpointer to SCSI Host */
  265. void *edev; /* Pointer to controller base/SBus */
  266. int esp_id; /* Unique per-ESP ID number */
  267. /* ESP Configuration Registers */
  268. unsigned char config1; /* Copy of the 1st config register */
  269. unsigned char config2; /* Copy of the 2nd config register */
  270. unsigned char config3[16]; /* Copy of the 3rd config register */
  271. /* The current command we are sending to the ESP chip. This esp_command
  272. * ptr needs to be mapped in DVMA area so we can send commands and read
  273. * from the ESP fifo without burning precious CPU cycles. Programmed I/O
  274. * sucks when we have the DVMA to do it for us. The ESP is stupid and will
  275. * only send out 6, 10, and 12 byte SCSI commands, others we need to send
  276. * one byte at a time. esp_slowcmd being set says that we are doing one
  277. * of the command types ESP doesn't understand, esp_scmdp keeps track of
  278. * which byte we are sending, esp_scmdleft says how many bytes to go.
  279. */
  280. volatile unchar *esp_command; /* Location of command (CPU view) */
  281. __u32 esp_command_dvma; /* Location of command (DVMA view) */
  282. unsigned char esp_clen; /* Length of this command */
  283. unsigned char esp_slowcmd;
  284. unsigned char *esp_scmdp;
  285. unsigned char esp_scmdleft;
  286. /* The following are used to determine the cause of an IRQ. Upon every
  287. * IRQ entry we synchronize these with the hardware registers.
  288. */
  289. unchar ireg; /* Copy of ESP interrupt register */
  290. unchar sreg; /* Same for ESP status register */
  291. unchar seqreg; /* The ESP sequence register */
  292. /* The following is set when a premature interrupt condition is detected
  293. * in some FAS revisions.
  294. */
  295. unchar fas_premature_intr_workaround;
  296. /* To save register writes to the ESP, which can be expensive, we
  297. * keep track of the previous value that various registers had for
  298. * the last target we connected to. If they are the same for the
  299. * current target, we skip the register writes as they are not needed.
  300. */
  301. unchar prev_soff, prev_stp, prev_cfg3;
  302. /* For each target we keep track of save/restore data
  303. * pointer information. This needs to be updated majorly
  304. * when we add support for tagged queueing. -DaveM
  305. */
  306. struct esp_pointers {
  307. char *saved_ptr;
  308. struct scatterlist *saved_buffer;
  309. int saved_this_residual;
  310. int saved_buffers_residual;
  311. } data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;
  312. /* Clock periods, frequencies, synchronization, etc. */
  313. unsigned int cfreq; /* Clock frequency in HZ */
  314. unsigned int cfact; /* Clock conversion factor */
  315. unsigned int ccycle; /* One ESP clock cycle */
  316. unsigned int ctick; /* One ESP clock time */
  317. unsigned int radelay; /* FAST chip req/ack delay */
  318. unsigned int neg_defp; /* Default negotiation period */
  319. unsigned int sync_defp; /* Default sync transfer period */
  320. unsigned int max_period; /* longest our period can be */
  321. unsigned int min_period; /* shortest period we can withstand */
  322. /* For slow to medium speed input clock rates we shoot for 5mb/s,
  323. * but for high input clock rates we try to do 10mb/s although I
  324. * don't think a transfer can even run that fast with an ESP even
  325. * with DMA2 scatter gather pipelining.
  326. */
  327. #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
  328. #define SYNC_DEFP_FAST 0x19 /* 10mb/s */
  329. unsigned int snip; /* Sync. negotiation in progress */
  330. unsigned int wnip; /* WIDE negotiation in progress */
  331. unsigned int targets_present; /* targets spoken to before */
  332. int current_transfer_size; /* Set at beginning of data dma */
  333. unchar espcmdlog[32]; /* Log of current esp cmds sent. */
  334. unchar espcmdent; /* Current entry in esp cmd log. */
  335. /* Misc. info about this ESP */
  336. enum esp_rev erev; /* ESP revision */
  337. int irq; /* IRQ for this ESP */
  338. int scsi_id; /* Who am I as initiator? */
  339. int scsi_id_mask; /* Bitmask of 'me'. */
  340. int diff; /* Differential SCSI bus? */
  341. int slot; /* Slot the adapter occupies */
  342. /* Our command queues, only one cmd lives in the current_SC queue. */
  343. Scsi_Cmnd *issue_SC; /* Commands to be issued */
  344. Scsi_Cmnd *current_SC; /* Who is currently working the bus */
  345. Scsi_Cmnd *disconnected_SC; /* Commands disconnected from the bus */
  346. /* Message goo */
  347. unchar cur_msgout[16];
  348. unchar cur_msgin[16];
  349. unchar prevmsgout, prevmsgin;
  350. unchar msgout_len, msgin_len;
  351. unchar msgout_ctr, msgin_ctr;
  352. /* States that we cannot keep in the per cmd structure because they
  353. * cannot be assosciated with any specific command.
  354. */
  355. unchar resetting_bus;
  356. wait_queue_head_t reset_queue;
  357. unchar do_pio_cmds; /* Do command transfer with pio */
  358. /* How much bits do we have to shift the registers */
  359. unsigned char shift;
  360. /* Functions handling DMA
  361. */
  362. /* Required functions */
  363. int (*dma_bytes_sent)(struct NCR_ESP *, int);
  364. int (*dma_can_transfer)(struct NCR_ESP *, Scsi_Cmnd *);
  365. void (*dma_dump_state)(struct NCR_ESP *);
  366. void (*dma_init_read)(struct NCR_ESP *, __u32, int);
  367. void (*dma_init_write)(struct NCR_ESP *, __u32, int);
  368. void (*dma_ints_off)(struct NCR_ESP *);
  369. void (*dma_ints_on)(struct NCR_ESP *);
  370. int (*dma_irq_p)(struct NCR_ESP *);
  371. int (*dma_ports_p)(struct NCR_ESP *);
  372. void (*dma_setup)(struct NCR_ESP *, __u32, int, int);
  373. /* Optional functions (i.e. may be initialized to 0) */
  374. void (*dma_barrier)(struct NCR_ESP *);
  375. void (*dma_drain)(struct NCR_ESP *);
  376. void (*dma_invalidate)(struct NCR_ESP *);
  377. void (*dma_irq_entry)(struct NCR_ESP *);
  378. void (*dma_irq_exit)(struct NCR_ESP *);
  379. void (*dma_led_off)(struct NCR_ESP *);
  380. void (*dma_led_on)(struct NCR_ESP *);
  381. void (*dma_poll)(struct NCR_ESP *, unsigned char *);
  382. void (*dma_reset)(struct NCR_ESP *);
  383. /* Optional virtual DMA functions */
  384. void (*dma_mmu_get_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
  385. void (*dma_mmu_get_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
  386. void (*dma_mmu_release_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
  387. void (*dma_mmu_release_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
  388. void (*dma_advance_sg)(Scsi_Cmnd *);
  389. };
  390. /* Bitfield meanings for the above registers. */
  391. /* ESP config reg 1, read-write, found on all ESP chips */
  392. #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
  393. #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
  394. #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
  395. #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
  396. #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
  397. #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
  398. /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236+fsc chips */
  399. #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236,fsc) */
  400. #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236,fsc) */
  401. #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
  402. #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tmode only) */
  403. #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
  404. #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
  405. #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236,fsc) */
  406. #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,esp216,fsc) */
  407. #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (esp236) */
  408. #define ESP_CONFIG2_RFB 0x80 /* Reserve FIFO byte (fsc) */
  409. #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
  410. /* ESP config register 3 read-write, found only esp236+fas236+fas100a+fsc chips */
  411. #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/fas366) */
  412. #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236/fsc) */
  413. #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a) */
  414. #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236/fsc) */
  415. #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a) */
  416. #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236/fsc) */
  417. #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a) */
  418. #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236/fsc) */
  419. #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a) */
  420. #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236/fsc) */
  421. #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236/fsc) */
  422. #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236/fsc) */
  423. #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236/fsc) */
  424. /* ESP config register 4 read-write, found only on fsc chips */
  425. #define ESP_CONFIG4_BBTE 0x01 /* Back-to-Back transfer enable */
  426. #define ESP_CONFIG4_TEST 0x02 /* Transfer counter test mode */
  427. #define ESP_CONFIG4_EAN 0x04 /* Enable Active Negotiation */
  428. /* ESP command register read-write */
  429. /* Group 1 commands: These may be sent at any point in time to the ESP
  430. * chip. None of them can generate interrupts 'cept
  431. * the "SCSI bus reset" command if you have not disabled
  432. * SCSI reset interrupts in the config1 ESP register.
  433. */
  434. #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
  435. #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
  436. #define ESP_CMD_RC 0x02 /* Chip reset */
  437. #define ESP_CMD_RS 0x03 /* SCSI bus reset */
  438. /* Group 2 commands: ESP must be an initiator and connected to a target
  439. * for these commands to work.
  440. */
  441. #define ESP_CMD_TI 0x10 /* Transfer Information */
  442. #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
  443. #define ESP_CMD_MOK 0x12 /* Message okie-dokie */
  444. #define ESP_CMD_TPAD 0x18 /* Transfer Pad */
  445. #define ESP_CMD_SATN 0x1a /* Set ATN */
  446. #define ESP_CMD_RATN 0x1b /* De-assert ATN */
  447. /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
  448. * to a target as the initiator for these commands to work.
  449. */
  450. #define ESP_CMD_SMSG 0x20 /* Send message */
  451. #define ESP_CMD_SSTAT 0x21 /* Send status */
  452. #define ESP_CMD_SDATA 0x22 /* Send data */
  453. #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
  454. #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
  455. #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
  456. #define ESP_CMD_DCNCT 0x27 /* Disconnect */
  457. #define ESP_CMD_RMSG 0x28 /* Receive Message */
  458. #define ESP_CMD_RCMD 0x29 /* Receive Command */
  459. #define ESP_CMD_RDATA 0x2a /* Receive Data */
  460. #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
  461. /* Group 4 commands: The ESP must be in the disconnected state and must
  462. * not be connected to any targets as initiator for
  463. * these commands to work.
  464. */
  465. #define ESP_CMD_RSEL 0x40 /* Reselect */
  466. #define ESP_CMD_SEL 0x41 /* Select w/o ATN */
  467. #define ESP_CMD_SELA 0x42 /* Select w/ATN */
  468. #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
  469. #define ESP_CMD_ESEL 0x44 /* Enable selection */
  470. #define ESP_CMD_DSEL 0x45 /* Disable selections */
  471. #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
  472. #define ESP_CMD_RSEL3 0x47 /* Reselect3 */
  473. /* This bit enables the ESP's DMA */
  474. #define ESP_CMD_DMA 0x80 /* Do DMA? */
  475. /* ESP status register read-only */
  476. #define ESP_STAT_PIO 0x01 /* IO phase bit */
  477. #define ESP_STAT_PCD 0x02 /* CD phase bit */
  478. #define ESP_STAT_PMSG 0x04 /* MSG phase bit */
  479. #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
  480. #define ESP_STAT_TDONE 0x08 /* Transfer Completed */
  481. #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
  482. #define ESP_STAT_PERR 0x20 /* Parity error */
  483. #define ESP_STAT_SPAM 0x40 /* Real bad error */
  484. /* This indicates the 'interrupt pending' condition, it is a reserved
  485. * bit on old revs of the ESP (ESP100, ESP100A, FAS100A).
  486. */
  487. #define ESP_STAT_INTR 0x80 /* Interrupt */
  488. /* The status register can be masked with ESP_STAT_PMASK and compared
  489. * with the following values to determine the current phase the ESP
  490. * (at least thinks it) is in. For our purposes we also add our own
  491. * software 'done' bit for our phase management engine.
  492. */
  493. #define ESP_DOP (0) /* Data Out */
  494. #define ESP_DIP (ESP_STAT_PIO) /* Data In */
  495. #define ESP_CMDP (ESP_STAT_PCD) /* Command */
  496. #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
  497. #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
  498. #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
  499. /* ESP interrupt register read-only */
  500. #define ESP_INTR_S 0x01 /* Select w/o ATN */
  501. #define ESP_INTR_SATN 0x02 /* Select w/ATN */
  502. #define ESP_INTR_RSEL 0x04 /* Reselected */
  503. #define ESP_INTR_FDONE 0x08 /* Function done */
  504. #define ESP_INTR_BSERV 0x10 /* Bus service */
  505. #define ESP_INTR_DC 0x20 /* Disconnect */
  506. #define ESP_INTR_IC 0x40 /* Illegal command given */
  507. #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
  508. /* Interrupt status macros */
  509. #define ESP_SRESET_IRQ(esp) ((esp)->intreg & (ESP_INTR_SR))
  510. #define ESP_ILLCMD_IRQ(esp) ((esp)->intreg & (ESP_INTR_IC))
  511. #define ESP_SELECT_WITH_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_SATN))
  512. #define ESP_SELECT_WITHOUT_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_S))
  513. #define ESP_SELECTION_IRQ(esp) ((ESP_SELECT_WITH_ATN_IRQ(esp)) || \
  514. (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
  515. #define ESP_RESELECTION_IRQ(esp) ((esp)->intreg & (ESP_INTR_RSEL))
  516. /* ESP sequence step register read-only */
  517. #define ESP_STEP_VBITS 0x07 /* Valid bits */
  518. #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
  519. #define ESP_STEP_SID 0x01 /* One msg byte sent */
  520. #define ESP_STEP_NCMD 0x02 /* Was not in command phase */
  521. #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
  522. * bytes to be lost
  523. */
  524. #define ESP_STEP_FINI4 0x04 /* Command was sent ok */
  525. /* Ho hum, some ESP's set the step register to this as well... */
  526. #define ESP_STEP_FINI5 0x05
  527. #define ESP_STEP_FINI6 0x06
  528. #define ESP_STEP_FINI7 0x07
  529. #define ESP_STEP_SOM 0x08 /* Synchronous Offset Max */
  530. /* ESP chip-test register read-write */
  531. #define ESP_TEST_TARG 0x01 /* Target test mode */
  532. #define ESP_TEST_INI 0x02 /* Initiator test mode */
  533. #define ESP_TEST_TS 0x04 /* Tristate test mode */
  534. /* ESP unique ID register read-only, found on fas236+fas100a+fsc only */
  535. #define ESP_UID_F100A 0x00 /* FAS100A */
  536. #define ESP_UID_F236 0x02 /* FAS236 */
  537. #define ESP_UID_FSC 0xa2 /* NCR53CF9x-2 */
  538. #define ESP_UID_REV 0x07 /* ESP revision */
  539. #define ESP_UID_FAM 0xf8 /* ESP family */
  540. /* ESP fifo flags register read-only */
  541. /* Note that the following implies a 16 byte FIFO on the ESP. */
  542. #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
  543. #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100,fsc) */
  544. #define ESP_FF_SSTEP 0xe0 /* Sequence step */
  545. /* ESP clock conversion factor register write-only */
  546. #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
  547. #define ESP_CCF_NEVER 0x01 /* Set it to this and die */
  548. #define ESP_CCF_F2 0x02 /* 10MHz */
  549. #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
  550. #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
  551. #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
  552. #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
  553. #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
  554. #define ESP_BUS_TIMEOUT 275 /* In milli-seconds */
  555. #define ESP_TIMEO_CONST 8192
  556. #define FSC_TIMEO_CONST 7668
  557. #define ESP_NEG_DEFP(mhz, cfact) \
  558. ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
  559. #define FSC_NEG_DEFP(mhz, cfact) \
  560. ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (7668 * (cfact)))
  561. #define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000))
  562. #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
  563. /* UGLY, UGLY, UGLY! */
  564. extern int nesps, esps_in_use, esps_running;
  565. /* For our interrupt engine. */
  566. #define for_each_esp(esp) \
  567. for((esp) = espchain; (esp); (esp) = (esp)->next)
  568. /* External functions */
  569. extern void esp_bootup_reset(struct NCR_ESP *esp, struct ESP_regs *eregs);
  570. extern struct NCR_ESP *esp_allocate(struct scsi_host_template *, void *, int);
  571. extern void esp_deallocate(struct NCR_ESP *);
  572. extern void esp_release(void);
  573. extern void esp_initialize(struct NCR_ESP *);
  574. extern irqreturn_t esp_intr(int, void *);
  575. extern const char *esp_info(struct Scsi_Host *);
  576. extern int esp_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  577. extern int esp_abort(Scsi_Cmnd *);
  578. extern int esp_reset(Scsi_Cmnd *);
  579. extern int esp_proc_info(struct Scsi_Host *shost, char *buffer, char **start, off_t offset, int length,
  580. int inout);
  581. extern int esp_slave_alloc(struct scsi_device *);
  582. extern void esp_slave_destroy(struct scsi_device *);
  583. #endif /* !(NCR53C9X_H) */