o2micro.h 5.7 KB

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  1. /*
  2. * o2micro.h 1.13 1999/10/25 20:03:34
  3. *
  4. * The contents of this file are subject to the Mozilla Public License
  5. * Version 1.1 (the "License"); you may not use this file except in
  6. * compliance with the License. You may obtain a copy of the License
  7. * at http://www.mozilla.org/MPL/
  8. *
  9. * Software distributed under the License is distributed on an "AS IS"
  10. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11. * the License for the specific language governing rights and
  12. * limitations under the License.
  13. *
  14. * The initial developer of the original code is David A. Hinds
  15. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  16. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  17. *
  18. * Alternatively, the contents of this file may be used under the
  19. * terms of the GNU General Public License version 2 (the "GPL"), in which
  20. * case the provisions of the GPL are applicable instead of the
  21. * above. If you wish to allow the use of your version of this file
  22. * only under the terms of the GPL and not to allow others to use
  23. * your version of this file under the MPL, indicate your decision by
  24. * deleting the provisions above and replace them with the notice and
  25. * other provisions required by the GPL. If you do not delete the
  26. * provisions above, a recipient may use your version of this file
  27. * under either the MPL or the GPL.
  28. */
  29. #ifndef _LINUX_O2MICRO_H
  30. #define _LINUX_O2MICRO_H
  31. #ifndef PCI_VENDOR_ID_O2
  32. #define PCI_VENDOR_ID_O2 0x1217
  33. #endif
  34. #ifndef PCI_DEVICE_ID_O2_6729
  35. #define PCI_DEVICE_ID_O2_6729 0x6729
  36. #endif
  37. #ifndef PCI_DEVICE_ID_O2_6730
  38. #define PCI_DEVICE_ID_O2_6730 0x673a
  39. #endif
  40. #ifndef PCI_DEVICE_ID_O2_6832
  41. #define PCI_DEVICE_ID_O2_6832 0x6832
  42. #endif
  43. #ifndef PCI_DEVICE_ID_O2_6836
  44. #define PCI_DEVICE_ID_O2_6836 0x6836
  45. #endif
  46. #ifndef PCI_DEVICE_ID_O2_6812
  47. #define PCI_DEVICE_ID_O2_6812 0x6872
  48. #endif
  49. /* Additional PCI configuration registers */
  50. #define O2_MUX_CONTROL 0x90 /* 32 bit */
  51. #define O2_MUX_RING_OUT 0x0000000f
  52. #define O2_MUX_SKTB_ACTV 0x000000f0
  53. #define O2_MUX_SCTA_ACTV_ENA 0x00000100
  54. #define O2_MUX_SCTB_ACTV_ENA 0x00000200
  55. #define O2_MUX_SER_IRQ_ROUTE 0x0000e000
  56. #define O2_MUX_SER_PCI 0x00010000
  57. #define O2_MUX_SKTA_TURBO 0x000c0000 /* for 6833, 6860 */
  58. #define O2_MUX_SKTB_TURBO 0x00300000
  59. #define O2_MUX_AUX_VCC_3V 0x00400000
  60. #define O2_MUX_PCI_VCC_5V 0x00800000
  61. #define O2_MUX_PME_MUX 0x0f000000
  62. /* Additional ExCA registers */
  63. #define O2_MODE_A 0x38
  64. #define O2_MODE_A_2 0x26 /* for 6833B, 6860C */
  65. #define O2_MODE_A_CD_PULSE 0x04
  66. #define O2_MODE_A_SUSP_EDGE 0x08
  67. #define O2_MODE_A_HOST_SUSP 0x10
  68. #define O2_MODE_A_PWR_MASK 0x60
  69. #define O2_MODE_A_QUIET 0x80
  70. #define O2_MODE_B 0x39
  71. #define O2_MODE_B_2 0x2e /* for 6833B, 6860C */
  72. #define O2_MODE_B_IDENT 0x03
  73. #define O2_MODE_B_ID_BSTEP 0x00
  74. #define O2_MODE_B_ID_CSTEP 0x01
  75. #define O2_MODE_B_ID_O2 0x02
  76. #define O2_MODE_B_VS1 0x04
  77. #define O2_MODE_B_VS2 0x08
  78. #define O2_MODE_B_IRQ15_RI 0x80
  79. #define O2_MODE_C 0x3a
  80. #define O2_MODE_C_DREQ_MASK 0x03
  81. #define O2_MODE_C_DREQ_INPACK 0x01
  82. #define O2_MODE_C_DREQ_WP 0x02
  83. #define O2_MODE_C_DREQ_BVD2 0x03
  84. #define O2_MODE_C_ZVIDEO 0x08
  85. #define O2_MODE_C_IREQ_SEL 0x30
  86. #define O2_MODE_C_MGMT_SEL 0xc0
  87. #define O2_MODE_D 0x3b
  88. #define O2_MODE_D_IRQ_MODE 0x03
  89. #define O2_MODE_D_PCI_CLKRUN 0x04
  90. #define O2_MODE_D_CB_CLKRUN 0x08
  91. #define O2_MODE_D_SKT_ACTV 0x20
  92. #define O2_MODE_D_PCI_FIFO 0x40 /* for OZ6729, OZ6730 */
  93. #define O2_MODE_D_W97_IRQ 0x40
  94. #define O2_MODE_D_ISA_IRQ 0x80
  95. #define O2_MHPG_DMA 0x3c
  96. #define O2_MHPG_CHANNEL 0x07
  97. #define O2_MHPG_CINT_ENA 0x08
  98. #define O2_MHPG_CSC_ENA 0x10
  99. #define O2_FIFO_ENA 0x3d
  100. #define O2_FIFO_ZVIDEO_3 0x08
  101. #define O2_FIFO_PCI_FIFO 0x10
  102. #define O2_FIFO_POSTWR 0x40
  103. #define O2_FIFO_BUFFER 0x80
  104. #define O2_MODE_E 0x3e
  105. #define O2_MODE_E_MHPG_DMA 0x01
  106. #define O2_MODE_E_SPKR_OUT 0x02
  107. #define O2_MODE_E_LED_OUT 0x08
  108. #define O2_MODE_E_SKTA_ACTV 0x10
  109. #define O2_RESERVED1 0x94
  110. #define O2_RESERVED2 0xD4
  111. #define O2_RES_READ_PREFETCH 0x02
  112. #define O2_RES_WRITE_BURST 0x08
  113. static int o2micro_override(struct yenta_socket *socket)
  114. {
  115. /*
  116. * 'reserved' register at 0x94/D4. allows setting read prefetch and write
  117. * bursting. read prefetching for example makes the RME Hammerfall DSP
  118. * working. for some bridges it is at 0x94, for others at 0xD4. it's
  119. * ok to write to both registers on all O2 bridges.
  120. * from Eric Still, 02Micro.
  121. */
  122. u8 a, b;
  123. if (PCI_FUNC(socket->dev->devfn) == 0) {
  124. a = config_readb(socket, O2_RESERVED1);
  125. b = config_readb(socket, O2_RESERVED2);
  126. printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a, b);
  127. switch (socket->dev->device) {
  128. /*
  129. * older bridges have problems with both read prefetch and write
  130. * bursting depending on the combination of the chipset, bridge
  131. * and the cardbus card. so disable them to be on the safe side.
  132. */
  133. case PCI_DEVICE_ID_O2_6729:
  134. case PCI_DEVICE_ID_O2_6730:
  135. case PCI_DEVICE_ID_O2_6812:
  136. case PCI_DEVICE_ID_O2_6832:
  137. case PCI_DEVICE_ID_O2_6836:
  138. printk(KERN_INFO "Yenta O2: old bridge, disabling read prefetch/write burst\n");
  139. config_writeb(socket, O2_RESERVED1,
  140. a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
  141. config_writeb(socket, O2_RESERVED2,
  142. b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
  143. break;
  144. default:
  145. printk(KERN_INFO "Yenta O2: enabling read prefetch/write burst\n");
  146. config_writeb(socket, O2_RESERVED1,
  147. a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
  148. config_writeb(socket, O2_RESERVED2,
  149. b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
  150. }
  151. }
  152. return 0;
  153. }
  154. static void o2micro_restore_state(struct yenta_socket *socket)
  155. {
  156. /*
  157. * as long as read prefetch is the only thing in
  158. * o2micro_override, it's safe to call it from here
  159. */
  160. o2micro_override(socket);
  161. }
  162. #endif /* _LINUX_O2MICRO_H */