m8xx_pcmcia.c 33 KB

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  1. /*
  2. * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
  3. *
  4. * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
  5. * (C) 2001-2002 Montavista Software, Inc.
  6. * <mlocke@mvista.com>
  7. *
  8. * Support for two slots by Cyclades Corporation
  9. * <oliver.kurth@cyclades.de>
  10. * Further fixes, v2.6 kernel port
  11. * <marcelo.tosatti@cyclades.com>
  12. *
  13. * Some fixes, additions (C) 2005 Montavista Software, Inc.
  14. * <vbordug@ru.mvista.com>
  15. *
  16. * "The ExCA standard specifies that socket controllers should provide
  17. * two IO and five memory windows per socket, which can be independently
  18. * configured and positioned in the host address space and mapped to
  19. * arbitrary segments of card address space. " - David A Hinds. 1999
  20. *
  21. * This controller does _not_ meet the ExCA standard.
  22. *
  23. * m8xx pcmcia controller brief info:
  24. * + 8 windows (attrib, mem, i/o)
  25. * + up to two slots (SLOT_A and SLOT_B)
  26. * + inputpins, outputpins, event and mask registers.
  27. * - no offset register. sigh.
  28. *
  29. * Because of the lacking offset register we must map the whole card.
  30. * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
  31. * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
  32. * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
  33. * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
  34. * They are maximum 64KByte each...
  35. */
  36. #include <linux/module.h>
  37. #include <linux/init.h>
  38. #include <linux/types.h>
  39. #include <linux/fcntl.h>
  40. #include <linux/string.h>
  41. #include <asm/io.h>
  42. #include <asm/bitops.h>
  43. #include <asm/system.h>
  44. #include <linux/kernel.h>
  45. #include <linux/errno.h>
  46. #include <linux/slab.h>
  47. #include <linux/timer.h>
  48. #include <linux/ioport.h>
  49. #include <linux/delay.h>
  50. #include <linux/interrupt.h>
  51. #include <linux/platform_device.h>
  52. #include <asm/mpc8xx.h>
  53. #include <asm/8xx_immap.h>
  54. #include <asm/irq.h>
  55. #include <pcmcia/version.h>
  56. #include <pcmcia/cs_types.h>
  57. #include <pcmcia/cs.h>
  58. #include <pcmcia/ss.h>
  59. #ifdef PCMCIA_DEBUG
  60. static int pc_debug = PCMCIA_DEBUG;
  61. module_param(pc_debug, int, 0);
  62. #define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
  63. #else
  64. #define dprintk(args...)
  65. #endif
  66. #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
  67. #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
  68. static const char *version = "Version 0.06, Aug 2005";
  69. MODULE_LICENSE("Dual MPL/GPL");
  70. #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  71. /* The RPX series use SLOT_B */
  72. #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
  73. #define CONFIG_PCMCIA_SLOT_B
  74. #define CONFIG_BD_IS_MHZ
  75. #endif
  76. /* The ADS board use SLOT_A */
  77. #ifdef CONFIG_ADS
  78. #define CONFIG_PCMCIA_SLOT_A
  79. #define CONFIG_BD_IS_MHZ
  80. #endif
  81. /* The FADS series are a mess */
  82. #ifdef CONFIG_FADS
  83. #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
  84. #define CONFIG_PCMCIA_SLOT_A
  85. #else
  86. #define CONFIG_PCMCIA_SLOT_B
  87. #endif
  88. #endif
  89. #if defined(CONFIG_MPC885ADS)
  90. #define CONFIG_PCMCIA_SLOT_A
  91. #define PCMCIA_GLITCHY_CD
  92. #endif
  93. /* Cyclades ACS uses both slots */
  94. #ifdef CONFIG_PRxK
  95. #define CONFIG_PCMCIA_SLOT_A
  96. #define CONFIG_PCMCIA_SLOT_B
  97. #endif
  98. #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
  99. #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
  100. #define PCMCIA_SOCKETS_NO 2
  101. /* We have only 8 windows, dualsocket support will be limited. */
  102. #define PCMCIA_MEM_WIN_NO 2
  103. #define PCMCIA_IO_WIN_NO 2
  104. #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
  105. #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
  106. #define PCMCIA_SOCKETS_NO 1
  107. /* full support for one slot */
  108. #define PCMCIA_MEM_WIN_NO 5
  109. #define PCMCIA_IO_WIN_NO 2
  110. /* define _slot_ to be able to optimize macros */
  111. #ifdef CONFIG_PCMCIA_SLOT_A
  112. #define _slot_ 0
  113. #define PCMCIA_SLOT_MSG "SLOT_A"
  114. #else
  115. #define _slot_ 1
  116. #define PCMCIA_SLOT_MSG "SLOT_B"
  117. #endif
  118. #else
  119. #error m8xx_pcmcia: Bad configuration!
  120. #endif
  121. /* ------------------------------------------------------------------------- */
  122. #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
  123. #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
  124. #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
  125. #define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
  126. /* ------------------------------------------------------------------------- */
  127. /* 2.4.x and newer has this always in HZ */
  128. #define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
  129. static int pcmcia_schlvl = PCMCIA_SCHLVL;
  130. static DEFINE_SPINLOCK(events_lock);
  131. #define PCMCIA_SOCKET_KEY_5V 1
  132. #define PCMCIA_SOCKET_KEY_LV 2
  133. /* look up table for pgcrx registers */
  134. static u32 *m8xx_pgcrx[2] = {
  135. &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
  136. &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
  137. };
  138. /*
  139. * This structure is used to address each window in the PCMCIA controller.
  140. *
  141. * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
  142. * after pcmcia_win[n]...
  143. */
  144. struct pcmcia_win {
  145. u32 br;
  146. u32 or;
  147. };
  148. /*
  149. * For some reason the hardware guys decided to make both slots share
  150. * some registers.
  151. *
  152. * Could someone invent object oriented hardware ?
  153. *
  154. * The macros are used to get the right bit from the registers.
  155. * SLOT_A : slot = 0
  156. * SLOT_B : slot = 1
  157. */
  158. #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
  159. #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
  160. #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
  161. #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
  162. #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
  163. #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
  164. #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
  165. #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
  166. #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
  167. #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
  168. #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
  169. #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
  170. #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
  171. #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
  172. #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
  173. #define M8XX_PCMCIA_POR_VALID 0x00000001
  174. #define M8XX_PCMCIA_POR_WRPROT 0x00000002
  175. #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
  176. #define M8XX_PCMCIA_POR_IO 0x00000018
  177. #define M8XX_PCMCIA_POR_16BIT 0x00000040
  178. #define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
  179. #define M8XX_PGCRX_CXOE 0x00000080
  180. #define M8XX_PGCRX_CXRESET 0x00000040
  181. /* we keep one lookup table per socket to check flags */
  182. #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
  183. struct event_table {
  184. u32 regbit;
  185. u32 eventbit;
  186. };
  187. struct socket_info {
  188. void (*handler)(void *info, u32 events);
  189. void *info;
  190. u32 slot;
  191. socket_state_t state;
  192. struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
  193. struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
  194. struct event_table events[PCMCIA_EVENTS_MAX];
  195. struct pcmcia_socket socket;
  196. };
  197. static struct socket_info socket[PCMCIA_SOCKETS_NO];
  198. /*
  199. * Search this table to see if the windowsize is
  200. * supported...
  201. */
  202. #define M8XX_SIZES_NO 32
  203. static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
  204. {
  205. 0x00000001, 0x00000002, 0x00000008, 0x00000004,
  206. 0x00000080, 0x00000040, 0x00000010, 0x00000020,
  207. 0x00008000, 0x00004000, 0x00001000, 0x00002000,
  208. 0x00000100, 0x00000200, 0x00000800, 0x00000400,
  209. 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  210. 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
  211. 0x00010000, 0x00020000, 0x00080000, 0x00040000,
  212. 0x00800000, 0x00400000, 0x00100000, 0x00200000
  213. };
  214. /* ------------------------------------------------------------------------- */
  215. static irqreturn_t m8xx_interrupt(int irq, void *dev);
  216. #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
  217. /* ------------------------------------------------------------------------- */
  218. /* board specific stuff: */
  219. /* voltage_set(), hardware_enable() and hardware_disable() */
  220. /* ------------------------------------------------------------------------- */
  221. /* RPX Boards from Embedded Planet */
  222. #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
  223. /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
  224. * SYPCR is write once only, therefore must the slowest memory be faster
  225. * than the bus monitor or we will get a machine check due to the bus timeout.
  226. */
  227. #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
  228. #undef PCMCIA_BMT_LIMIT
  229. #define PCMCIA_BMT_LIMIT (6*8)
  230. static int voltage_set(int slot, int vcc, int vpp)
  231. {
  232. u32 reg = 0;
  233. switch(vcc) {
  234. case 0: break;
  235. case 33:
  236. reg |= BCSR1_PCVCTL4;
  237. break;
  238. case 50:
  239. reg |= BCSR1_PCVCTL5;
  240. break;
  241. default:
  242. return 1;
  243. }
  244. switch(vpp) {
  245. case 0: break;
  246. case 33:
  247. case 50:
  248. if(vcc == vpp)
  249. reg |= BCSR1_PCVCTL6;
  250. else
  251. return 1;
  252. break;
  253. case 120:
  254. reg |= BCSR1_PCVCTL7;
  255. default:
  256. return 1;
  257. }
  258. if(!((vcc == 50) || (vcc == 0)))
  259. return 1;
  260. /* first, turn off all power */
  261. out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
  262. /* enable new powersettings */
  263. out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
  264. return 0;
  265. }
  266. #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
  267. #define hardware_enable(_slot_) /* No hardware to enable */
  268. #define hardware_disable(_slot_) /* No hardware to disable */
  269. #endif /* CONFIG_RPXCLASSIC */
  270. /* FADS Boards from Motorola */
  271. #if defined(CONFIG_FADS)
  272. #define PCMCIA_BOARD_MSG "FADS"
  273. static int voltage_set(int slot, int vcc, int vpp)
  274. {
  275. u32 reg = 0;
  276. switch(vcc) {
  277. case 0:
  278. break;
  279. case 33:
  280. reg |= BCSR1_PCCVCC0;
  281. break;
  282. case 50:
  283. reg |= BCSR1_PCCVCC1;
  284. break;
  285. default:
  286. return 1;
  287. }
  288. switch(vpp) {
  289. case 0:
  290. break;
  291. case 33:
  292. case 50:
  293. if(vcc == vpp)
  294. reg |= BCSR1_PCCVPP1;
  295. else
  296. return 1;
  297. break;
  298. case 120:
  299. if ((vcc == 33) || (vcc == 50))
  300. reg |= BCSR1_PCCVPP0;
  301. else
  302. return 1;
  303. default:
  304. return 1;
  305. }
  306. /* first, turn off all power */
  307. out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
  308. /* enable new powersettings */
  309. out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | reg);
  310. return 0;
  311. }
  312. #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
  313. static void hardware_enable(int slot)
  314. {
  315. out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~BCSR1_PCCEN);
  316. }
  317. static void hardware_disable(int slot)
  318. {
  319. out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | BCSR1_PCCEN);
  320. }
  321. #endif
  322. /* MPC885ADS Boards */
  323. #if defined(CONFIG_MPC885ADS)
  324. #define PCMCIA_BOARD_MSG "MPC885ADS"
  325. static int voltage_set(int slot, int vcc, int vpp)
  326. {
  327. u32 reg = 0;
  328. unsigned *bcsr_io;
  329. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  330. switch(vcc) {
  331. case 0:
  332. break;
  333. case 33:
  334. reg |= BCSR1_PCCVCC0;
  335. break;
  336. case 50:
  337. reg |= BCSR1_PCCVCC1;
  338. break;
  339. default:
  340. goto out_unmap;
  341. }
  342. switch(vpp) {
  343. case 0:
  344. break;
  345. case 33:
  346. case 50:
  347. if(vcc == vpp)
  348. reg |= BCSR1_PCCVPP1;
  349. else
  350. goto out_unmap;
  351. break;
  352. case 120:
  353. if ((vcc == 33) || (vcc == 50))
  354. reg |= BCSR1_PCCVPP0;
  355. else
  356. goto out_unmap;
  357. default:
  358. goto out_unmap;
  359. }
  360. /* first, turn off all power */
  361. out_be32(bcsr_io, in_be32(bcsr_io) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
  362. /* enable new powersettings */
  363. out_be32(bcsr_io, in_be32(bcsr_io) | reg);
  364. iounmap(bcsr_io);
  365. return 0;
  366. out_unmap:
  367. iounmap(bcsr_io);
  368. return 1;
  369. }
  370. #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
  371. static void hardware_enable(int slot)
  372. {
  373. unsigned *bcsr_io;
  374. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  375. out_be32(bcsr_io, in_be32(bcsr_io) & ~BCSR1_PCCEN);
  376. iounmap(bcsr_io);
  377. }
  378. static void hardware_disable(int slot)
  379. {
  380. unsigned *bcsr_io;
  381. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  382. out_be32(bcsr_io, in_be32(bcsr_io) | BCSR1_PCCEN);
  383. iounmap(bcsr_io);
  384. }
  385. #endif
  386. /* ------------------------------------------------------------------------- */
  387. /* Motorola MBX860 */
  388. #if defined(CONFIG_MBX)
  389. #define PCMCIA_BOARD_MSG "MBX"
  390. static int voltage_set(int slot, int vcc, int vpp)
  391. {
  392. u8 reg = 0;
  393. switch(vcc) {
  394. case 0:
  395. break;
  396. case 33:
  397. reg |= CSR2_VCC_33;
  398. break;
  399. case 50:
  400. reg |= CSR2_VCC_50;
  401. break;
  402. default:
  403. return 1;
  404. }
  405. switch(vpp) {
  406. case 0:
  407. break;
  408. case 33:
  409. case 50:
  410. if(vcc == vpp)
  411. reg |= CSR2_VPP_VCC;
  412. else
  413. return 1;
  414. break;
  415. case 120:
  416. if ((vcc == 33) || (vcc == 50))
  417. reg |= CSR2_VPP_12;
  418. else
  419. return 1;
  420. default:
  421. return 1;
  422. }
  423. /* first, turn off all power */
  424. out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
  425. /* enable new powersettings */
  426. out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) | reg);
  427. return 0;
  428. }
  429. #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
  430. #define hardware_enable(_slot_) /* No hardware to enable */
  431. #define hardware_disable(_slot_) /* No hardware to disable */
  432. #endif /* CONFIG_MBX */
  433. #if defined(CONFIG_PRxK)
  434. #include <asm/cpld.h>
  435. extern volatile fpga_pc_regs *fpga_pc;
  436. #define PCMCIA_BOARD_MSG "MPC855T"
  437. static int voltage_set(int slot, int vcc, int vpp)
  438. {
  439. u8 reg = 0;
  440. u8 regread;
  441. cpld_regs *ccpld = get_cpld();
  442. switch(vcc) {
  443. case 0:
  444. break;
  445. case 33:
  446. reg |= PCMCIA_VCC_33;
  447. break;
  448. case 50:
  449. reg |= PCMCIA_VCC_50;
  450. break;
  451. default:
  452. return 1;
  453. }
  454. switch(vpp) {
  455. case 0:
  456. break;
  457. case 33:
  458. case 50:
  459. if(vcc == vpp)
  460. reg |= PCMCIA_VPP_VCC;
  461. else
  462. return 1;
  463. break;
  464. case 120:
  465. if ((vcc == 33) || (vcc == 50))
  466. reg |= PCMCIA_VPP_12;
  467. else
  468. return 1;
  469. default:
  470. return 1;
  471. }
  472. reg = reg >> (slot << 2);
  473. regread = in_8(&ccpld->fpga_pc_ctl);
  474. if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
  475. /* enable new powersettings */
  476. regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
  477. out_8(&ccpld->fpga_pc_ctl, reg | regread);
  478. msleep(100);
  479. }
  480. return 0;
  481. }
  482. #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
  483. #define hardware_enable(_slot_) /* No hardware to enable */
  484. #define hardware_disable(_slot_) /* No hardware to disable */
  485. #endif /* CONFIG_PRxK */
  486. static void m8xx_shutdown(void)
  487. {
  488. u32 m, i;
  489. struct pcmcia_win *w;
  490. for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
  491. w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
  492. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i));
  493. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i));
  494. /* turn off interrupt and disable CxOE */
  495. out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
  496. /* turn off memory windows */
  497. for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
  498. out_be32(&w->or, 0); /* set to not valid */
  499. w++;
  500. }
  501. /* turn off voltage */
  502. voltage_set(i, 0, 0);
  503. /* disable external hardware */
  504. hardware_disable(i);
  505. }
  506. free_irq(pcmcia_schlvl, NULL);
  507. }
  508. static struct device_driver m8xx_driver = {
  509. .name = "m8xx-pcmcia",
  510. .bus = &platform_bus_type,
  511. .suspend = pcmcia_socket_dev_suspend,
  512. .resume = pcmcia_socket_dev_resume,
  513. };
  514. static struct platform_device m8xx_device = {
  515. .name = "m8xx-pcmcia",
  516. .id = 0,
  517. };
  518. static u32 pending_events[PCMCIA_SOCKETS_NO];
  519. static DEFINE_SPINLOCK(pending_event_lock);
  520. static irqreturn_t m8xx_interrupt(int irq, void *dev)
  521. {
  522. struct socket_info *s;
  523. struct event_table *e;
  524. unsigned int i, events, pscr, pipr, per;
  525. dprintk("Interrupt!\n");
  526. /* get interrupt sources */
  527. pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr);
  528. pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
  529. per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per);
  530. for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
  531. s = &socket[i];
  532. e = &s->events[0];
  533. events = 0;
  534. while(e->regbit) {
  535. if(pscr & e->regbit)
  536. events |= e->eventbit;
  537. e++;
  538. }
  539. /*
  540. * report only if both card detect signals are the same
  541. * not too nice done,
  542. * we depend on that CD2 is the bit to the left of CD1...
  543. */
  544. if(events & SS_DETECT)
  545. if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
  546. (pipr & M8XX_PCMCIA_CD1(i)))
  547. {
  548. events &= ~SS_DETECT;
  549. }
  550. #ifdef PCMCIA_GLITCHY_CD
  551. /*
  552. * I've experienced CD problems with my ADS board.
  553. * We make an extra check to see if there was a
  554. * real change of Card detection.
  555. */
  556. if((events & SS_DETECT) &&
  557. ((pipr &
  558. (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
  559. (s->state.Vcc | s->state.Vpp)) {
  560. events &= ~SS_DETECT;
  561. /*printk( "CD glitch workaround - CD = 0x%08x!\n",
  562. (pipr & (M8XX_PCMCIA_CD2(i)
  563. | M8XX_PCMCIA_CD1(i))));*/
  564. }
  565. #endif
  566. /* call the handler */
  567. dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
  568. "pipr = 0x%08x\n",
  569. i, events, pscr, pipr);
  570. if(events) {
  571. spin_lock(&pending_event_lock);
  572. pending_events[i] |= events;
  573. spin_unlock(&pending_event_lock);
  574. /*
  575. * Turn off RDY_L bits in the PER mask on
  576. * CD interrupt receival.
  577. *
  578. * They can generate bad interrupts on the
  579. * ACS4,8,16,32. - marcelo
  580. */
  581. per &= ~M8XX_PCMCIA_RDY_L(0);
  582. per &= ~M8XX_PCMCIA_RDY_L(1);
  583. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per);
  584. if (events)
  585. pcmcia_parse_events(&socket[i].socket, events);
  586. }
  587. }
  588. /* clear the interrupt sources */
  589. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr);
  590. dprintk("Interrupt done.\n");
  591. return IRQ_HANDLED;
  592. }
  593. static u32 m8xx_get_graycode(u32 size)
  594. {
  595. u32 k;
  596. for(k = 0; k < M8XX_SIZES_NO; k++)
  597. if(m8xx_size_to_gray[k] == size)
  598. break;
  599. if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
  600. k = -1;
  601. return k;
  602. }
  603. static u32 m8xx_get_speed(u32 ns, u32 is_io)
  604. {
  605. u32 reg, clocks, psst, psl, psht;
  606. if(!ns) {
  607. /*
  608. * We get called with IO maps setup to 0ns
  609. * if not specified by the user.
  610. * They should be 255ns.
  611. */
  612. if(is_io)
  613. ns = 255;
  614. else
  615. ns = 100; /* fast memory if 0 */
  616. }
  617. /*
  618. * In PSST, PSL, PSHT fields we tell the controller
  619. * timing parameters in CLKOUT clock cycles.
  620. * CLKOUT is the same as GCLK2_50.
  621. */
  622. /* how we want to adjust the timing - in percent */
  623. #define ADJ 180 /* 80 % longer accesstime - to be sure */
  624. clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
  625. clocks = (clocks * ADJ) / (100*1000);
  626. if(clocks >= PCMCIA_BMT_LIMIT) {
  627. printk( "Max access time limit reached\n");
  628. clocks = PCMCIA_BMT_LIMIT-1;
  629. }
  630. psst = clocks / 7; /* setup time */
  631. psht = clocks / 7; /* hold time */
  632. psl = (clocks * 5) / 7; /* strobe length */
  633. psst += clocks - (psst + psht + psl);
  634. reg = psst << 12;
  635. reg |= psl << 7;
  636. reg |= psht << 16;
  637. return reg;
  638. }
  639. static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
  640. {
  641. int lsock = container_of(sock, struct socket_info, socket)->slot;
  642. struct socket_info *s = &socket[lsock];
  643. unsigned int pipr, reg;
  644. pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
  645. *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
  646. | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
  647. *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
  648. if (s->state.flags & SS_IOCARD)
  649. *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
  650. else {
  651. *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
  652. *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
  653. *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
  654. }
  655. if (s->state.Vcc | s->state.Vpp)
  656. *value |= SS_POWERON;
  657. /*
  658. * Voltage detection:
  659. * This driver only supports 16-Bit pc-cards.
  660. * Cardbus is not handled here.
  661. *
  662. * To determine what voltage to use we must read the VS1 and VS2 pin.
  663. * Depending on what socket type is present,
  664. * different combinations mean different things.
  665. *
  666. * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
  667. *
  668. * 5V 5V, LV* NC NC 5V only 5V (if available)
  669. *
  670. * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
  671. *
  672. * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
  673. *
  674. * LV* 5V - - shall not fit into socket
  675. *
  676. * LV* LV* GND NC 3.3V only 3.3V
  677. *
  678. * LV* LV* NC GND x.xV x.xV (if avail.)
  679. *
  680. * LV* LV* GND GND 3.3 or x.xV as low as possible
  681. *
  682. * *LV means Low Voltage
  683. *
  684. *
  685. * That gives us the following table:
  686. *
  687. * Socket VS1 VS2 Voltage
  688. *
  689. * 5V NC NC 5V
  690. * 5V NC GND none (should not be possible)
  691. * 5V GND NC >= 3.3V
  692. * 5V GND GND >= x.xV
  693. *
  694. * LV NC NC 5V (if available)
  695. * LV NC GND x.xV (if available)
  696. * LV GND NC 3.3V
  697. * LV GND GND >= x.xV
  698. *
  699. * So, how do I determine if I have a 5V or a LV
  700. * socket on my board? Look at the socket!
  701. *
  702. *
  703. * Socket with 5V key:
  704. * ++--------------------------------------------+
  705. * || |
  706. * || ||
  707. * || ||
  708. * | |
  709. * +---------------------------------------------+
  710. *
  711. * Socket with LV key:
  712. * ++--------------------------------------------+
  713. * || |
  714. * | ||
  715. * | ||
  716. * | |
  717. * +---------------------------------------------+
  718. *
  719. *
  720. * With other words - LV only cards does not fit
  721. * into the 5V socket!
  722. */
  723. /* read out VS1 and VS2 */
  724. reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
  725. >> M8XX_PCMCIA_VS_SHIFT(lsock);
  726. if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
  727. switch(reg) {
  728. case 1:
  729. *value |= SS_3VCARD;
  730. break; /* GND, NC - 3.3V only */
  731. case 2:
  732. *value |= SS_XVCARD;
  733. break; /* NC. GND - x.xV only */
  734. };
  735. }
  736. dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
  737. return 0;
  738. }
  739. static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
  740. {
  741. int lsock = container_of(sock, struct socket_info, socket)->slot;
  742. struct socket_info *s = &socket[lsock];
  743. struct event_table *e;
  744. unsigned int reg;
  745. unsigned long flags;
  746. dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
  747. "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
  748. state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
  749. /* First, set voltage - bail out if invalid */
  750. if(voltage_set(lsock, state->Vcc, state->Vpp))
  751. return -EINVAL;
  752. /* Take care of reset... */
  753. if(state->flags & SS_RESET)
  754. out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
  755. else
  756. out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
  757. /* ... and output enable. */
  758. /* The CxOE signal is connected to a 74541 on the ADS.
  759. I guess most other boards used the ADS as a reference.
  760. I tried to control the CxOE signal with SS_OUTPUT_ENA,
  761. but the reset signal seems connected via the 541.
  762. If the CxOE is left high are some signals tristated and
  763. no pullups are present -> the cards act wierd.
  764. So right now the buffers are enabled if the power is on. */
  765. if(state->Vcc || state->Vpp)
  766. out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
  767. else
  768. out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
  769. /*
  770. * We'd better turn off interrupts before
  771. * we mess with the events-table..
  772. */
  773. spin_lock_irqsave(&events_lock, flags);
  774. /*
  775. * Play around with the interrupt mask to be able to
  776. * give the events the generic pcmcia driver wants us to.
  777. */
  778. e = &s->events[0];
  779. reg = 0;
  780. if(state->csc_mask & SS_DETECT) {
  781. e->eventbit = SS_DETECT;
  782. reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
  783. | M8XX_PCMCIA_CD1(lsock));
  784. e++;
  785. }
  786. if(state->flags & SS_IOCARD) {
  787. /*
  788. * I/O card
  789. */
  790. if(state->csc_mask & SS_STSCHG) {
  791. e->eventbit = SS_STSCHG;
  792. reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
  793. e++;
  794. }
  795. /*
  796. * If io_irq is non-zero we should enable irq.
  797. */
  798. if(state->io_irq) {
  799. out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24);
  800. /*
  801. * Strange thing here:
  802. * The manual does not tell us which interrupt
  803. * the sources generate.
  804. * Anyhow, I found out that RDY_L generates IREQLVL.
  805. *
  806. * We use level triggerd interrupts, and they don't
  807. * have to be cleared in PSCR in the interrupt handler.
  808. */
  809. reg |= M8XX_PCMCIA_RDY_L(lsock);
  810. }
  811. else
  812. out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
  813. }
  814. else {
  815. /*
  816. * Memory card
  817. */
  818. if(state->csc_mask & SS_BATDEAD) {
  819. e->eventbit = SS_BATDEAD;
  820. reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
  821. e++;
  822. }
  823. if(state->csc_mask & SS_BATWARN) {
  824. e->eventbit = SS_BATWARN;
  825. reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
  826. e++;
  827. }
  828. /* What should I trigger on - low/high,raise,fall? */
  829. if(state->csc_mask & SS_READY) {
  830. e->eventbit = SS_READY;
  831. reg |= e->regbit = 0; //??
  832. e++;
  833. }
  834. }
  835. e->regbit = 0; /* terminate list */
  836. /*
  837. * Clear the status changed .
  838. * Port A and Port B share the same port.
  839. * Writing ones will clear the bits.
  840. */
  841. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg);
  842. /*
  843. * Write the mask.
  844. * Port A and Port B share the same port.
  845. * Need for read-modify-write.
  846. * Ones will enable the interrupt.
  847. */
  848. /*
  849. reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
  850. & M8XX_PCMCIA_MASK(lsock);
  851. */
  852. reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
  853. (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
  854. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg);
  855. spin_unlock_irqrestore(&events_lock, flags);
  856. /* copy the struct and modify the copy */
  857. s->state = *state;
  858. return 0;
  859. }
  860. static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
  861. {
  862. int lsock = container_of(sock, struct socket_info, socket)->slot;
  863. struct socket_info *s = &socket[lsock];
  864. struct pcmcia_win *w;
  865. unsigned int reg, winnr;
  866. #define M8XX_SIZE (io->stop - io->start + 1)
  867. #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
  868. dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
  869. "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
  870. io->speed, io->start, io->stop);
  871. if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
  872. || (io->stop > 0xffff) || (io->stop < io->start))
  873. return -EINVAL;
  874. if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
  875. return -EINVAL;
  876. if(io->flags & MAP_ACTIVE) {
  877. dprintk( "io->flags & MAP_ACTIVE\n");
  878. winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
  879. + (lsock * PCMCIA_IO_WIN_NO) + io->map;
  880. /* setup registers */
  881. w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
  882. w += winnr;
  883. out_be32(&w->or, 0); /* turn off window first */
  884. out_be32(&w->br, M8XX_BASE);
  885. reg <<= 27;
  886. reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
  887. reg |= m8xx_get_speed(io->speed, 1);
  888. if(io->flags & MAP_WRPROT)
  889. reg |= M8XX_PCMCIA_POR_WRPROT;
  890. if(io->flags & (MAP_16BIT | MAP_AUTOSZ))
  891. reg |= M8XX_PCMCIA_POR_16BIT;
  892. if(io->flags & MAP_ACTIVE)
  893. reg |= M8XX_PCMCIA_POR_VALID;
  894. out_be32(&w->or, reg);
  895. dprintk("Socket %u: Mapped io window %u at %#8.8x, "
  896. "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
  897. } else {
  898. /* shutdown IO window */
  899. winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
  900. + (lsock * PCMCIA_IO_WIN_NO) + io->map;
  901. /* setup registers */
  902. w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
  903. w += winnr;
  904. out_be32(&w->or, 0); /* turn off window */
  905. out_be32(&w->br, 0); /* turn off base address */
  906. dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
  907. "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
  908. }
  909. /* copy the struct and modify the copy */
  910. s->io_win[io->map] = *io;
  911. s->io_win[io->map].flags &= (MAP_WRPROT
  912. | MAP_16BIT
  913. | MAP_ACTIVE);
  914. dprintk("SetIOMap exit\n");
  915. return 0;
  916. }
  917. static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
  918. {
  919. int lsock = container_of(sock, struct socket_info, socket)->slot;
  920. struct socket_info *s = &socket[lsock];
  921. struct pcmcia_win *w;
  922. struct pccard_mem_map *old;
  923. unsigned int reg, winnr;
  924. dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
  925. "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
  926. mem->speed, mem->static_start, mem->card_start);
  927. if ((mem->map >= PCMCIA_MEM_WIN_NO)
  928. // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
  929. || (mem->card_start >= 0x04000000)
  930. || (mem->static_start & 0xfff) /* 4KByte resolution */
  931. || (mem->card_start & 0xfff))
  932. return -EINVAL;
  933. if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
  934. printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
  935. return -EINVAL;
  936. }
  937. reg <<= 27;
  938. winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
  939. /* Setup the window in the pcmcia controller */
  940. w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
  941. w += winnr;
  942. reg |= lsock << 2;
  943. reg |= m8xx_get_speed(mem->speed, 0);
  944. if(mem->flags & MAP_ATTRIB)
  945. reg |= M8XX_PCMCIA_POR_ATTRMEM;
  946. if(mem->flags & MAP_WRPROT)
  947. reg |= M8XX_PCMCIA_POR_WRPROT;
  948. if(mem->flags & MAP_16BIT)
  949. reg |= M8XX_PCMCIA_POR_16BIT;
  950. if(mem->flags & MAP_ACTIVE)
  951. reg |= M8XX_PCMCIA_POR_VALID;
  952. out_be32(&w->or, reg);
  953. dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
  954. "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
  955. if(mem->flags & MAP_ACTIVE) {
  956. /* get the new base address */
  957. mem->static_start = PCMCIA_MEM_WIN_BASE +
  958. (PCMCIA_MEM_WIN_SIZE * winnr)
  959. + mem->card_start;
  960. }
  961. dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
  962. "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
  963. mem->speed, mem->static_start, mem->card_start);
  964. /* copy the struct and modify the copy */
  965. old = &s->mem_win[mem->map];
  966. *old = *mem;
  967. old->flags &= (MAP_ATTRIB
  968. | MAP_WRPROT
  969. | MAP_16BIT
  970. | MAP_ACTIVE);
  971. return 0;
  972. }
  973. static int m8xx_sock_init(struct pcmcia_socket *sock)
  974. {
  975. int i;
  976. pccard_io_map io = { 0, 0, 0, 0, 1 };
  977. pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
  978. dprintk( "sock_init(%d)\n", s);
  979. m8xx_set_socket(sock, &dead_socket);
  980. for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
  981. io.map = i;
  982. m8xx_set_io_map(sock, &io);
  983. }
  984. for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
  985. mem.map = i;
  986. m8xx_set_mem_map(sock, &mem);
  987. }
  988. return 0;
  989. }
  990. static int m8xx_suspend(struct pcmcia_socket *sock)
  991. {
  992. return m8xx_set_socket(sock, &dead_socket);
  993. }
  994. static struct pccard_operations m8xx_services = {
  995. .init = m8xx_sock_init,
  996. .suspend = m8xx_suspend,
  997. .get_status = m8xx_get_status,
  998. .set_socket = m8xx_set_socket,
  999. .set_io_map = m8xx_set_io_map,
  1000. .set_mem_map = m8xx_set_mem_map,
  1001. };
  1002. static int __init m8xx_init(void)
  1003. {
  1004. struct pcmcia_win *w;
  1005. unsigned int i,m;
  1006. pcmcia_info("%s\n", version);
  1007. if (driver_register(&m8xx_driver))
  1008. return -1;
  1009. pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
  1010. " with IRQ %u.\n", pcmcia_schlvl);
  1011. /* Configure Status change interrupt */
  1012. if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0,
  1013. "m8xx_pcmcia", NULL)) {
  1014. pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
  1015. pcmcia_schlvl);
  1016. return -1;
  1017. }
  1018. w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
  1019. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr,
  1020. M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
  1021. out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per,
  1022. in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
  1023. ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)));
  1024. /* connect interrupt and disable CxOE */
  1025. out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
  1026. out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
  1027. /* intialize the fixed memory windows */
  1028. for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
  1029. for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
  1030. out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
  1031. (PCMCIA_MEM_WIN_SIZE
  1032. * (m + i * PCMCIA_MEM_WIN_NO)));
  1033. out_be32(&w->or, 0); /* set to not valid */
  1034. w++;
  1035. }
  1036. }
  1037. /* turn off voltage */
  1038. voltage_set(0, 0, 0);
  1039. voltage_set(1, 0, 0);
  1040. /* Enable external hardware */
  1041. hardware_enable(0);
  1042. hardware_enable(1);
  1043. platform_device_register(&m8xx_device);
  1044. for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
  1045. socket[i].slot = i;
  1046. socket[i].socket.owner = THIS_MODULE;
  1047. socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
  1048. socket[i].socket.irq_mask = 0x000;
  1049. socket[i].socket.map_size = 0x1000;
  1050. socket[i].socket.io_offset = 0;
  1051. socket[i].socket.pci_irq = i ? 7 : 9;
  1052. socket[i].socket.ops = &m8xx_services;
  1053. socket[i].socket.resource_ops = &pccard_iodyn_ops;
  1054. socket[i].socket.cb_dev = NULL;
  1055. socket[i].socket.dev.parent = &m8xx_device.dev;
  1056. }
  1057. for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
  1058. pcmcia_register_socket(&socket[i].socket);
  1059. return 0;
  1060. }
  1061. static void __exit m8xx_exit(void)
  1062. {
  1063. int i;
  1064. for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
  1065. pcmcia_unregister_socket(&socket[i].socket);
  1066. m8xx_shutdown();
  1067. platform_device_unregister(&m8xx_device);
  1068. driver_unregister(&m8xx_driver);
  1069. }
  1070. module_init(m8xx_init);
  1071. module_exit(m8xx_exit);