m32r_cfc.c 21 KB

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  1. /*
  2. * drivers/pcmcia/m32r_cfc.c
  3. *
  4. * Device driver for the CFC functionality of M32R.
  5. *
  6. * Copyright (c) 2001, 2002, 2003, 2004
  7. * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/types.h>
  13. #include <linux/fcntl.h>
  14. #include <linux/string.h>
  15. #include <linux/kernel.h>
  16. #include <linux/errno.h>
  17. #include <linux/timer.h>
  18. #include <linux/slab.h>
  19. #include <linux/ioport.h>
  20. #include <linux/delay.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/bitops.h>
  25. #include <asm/irq.h>
  26. #include <asm/io.h>
  27. #include <asm/system.h>
  28. #include <pcmcia/cs_types.h>
  29. #include <pcmcia/ss.h>
  30. #include <pcmcia/cs.h>
  31. #undef MAX_IO_WIN /* FIXME */
  32. #define MAX_IO_WIN 1
  33. #undef MAX_WIN /* FIXME */
  34. #define MAX_WIN 1
  35. #include "m32r_cfc.h"
  36. #ifdef DEBUG
  37. static int m32r_cfc_debug;
  38. module_param(m32r_cfc_debug, int, 0644);
  39. #define debug(lvl, fmt, arg...) do { \
  40. if (m32r_cfc_debug > (lvl)) \
  41. printk(KERN_DEBUG "m32r_cfc: " fmt , ## arg); \
  42. } while (0)
  43. #else
  44. #define debug(n, args...) do { } while (0)
  45. #endif
  46. /* Poll status interval -- 0 means default to interrupt */
  47. static int poll_interval = 0;
  48. typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
  49. typedef struct pcc_socket {
  50. u_short type, flags;
  51. struct pcmcia_socket socket;
  52. unsigned int number;
  53. kio_addr_t ioaddr;
  54. u_long mapaddr;
  55. u_long base; /* PCC register base */
  56. u_char cs_irq1, cs_irq2, intr;
  57. pccard_io_map io_map[MAX_IO_WIN];
  58. pccard_mem_map mem_map[MAX_WIN];
  59. u_char io_win;
  60. u_char mem_win;
  61. pcc_as_t current_space;
  62. u_char last_iodbex;
  63. #ifdef CONFIG_PROC_FS
  64. struct proc_dir_entry *proc;
  65. #endif
  66. } pcc_socket_t;
  67. static int pcc_sockets = 0;
  68. static pcc_socket_t socket[M32R_MAX_PCC] = {
  69. { 0, }, /* ... */
  70. };
  71. /*====================================================================*/
  72. static unsigned int pcc_get(u_short, unsigned int);
  73. static void pcc_set(u_short, unsigned int , unsigned int );
  74. static DEFINE_SPINLOCK(pcc_lock);
  75. #if !defined(CONFIG_PLAT_USRV)
  76. static inline u_long pcc_port2addr(unsigned long port, int size) {
  77. u_long addr = 0;
  78. u_long odd;
  79. if (size == 1) { /* byte access */
  80. odd = (port&1) << 11;
  81. port -= port & 1;
  82. addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
  83. } else if (size == 2)
  84. addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
  85. return addr;
  86. }
  87. #else /* CONFIG_PLAT_USRV */
  88. static inline u_long pcc_port2addr(unsigned long port, int size) {
  89. u_long odd;
  90. u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
  91. if (size == 1) { /* byte access */
  92. odd = port & 1;
  93. port -= odd;
  94. odd <<= 11;
  95. addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
  96. } else if (size == 2) /* word access */
  97. addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
  98. return addr;
  99. }
  100. #endif /* CONFIG_PLAT_USRV */
  101. void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
  102. size_t nmemb, int flag)
  103. {
  104. u_long addr;
  105. unsigned char *bp = (unsigned char *)buf;
  106. unsigned long flags;
  107. debug(3, "m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
  108. "size=%u, nmemb=%d, flag=%d\n",
  109. sock, port, buf, size, nmemb, flag);
  110. addr = pcc_port2addr(port, 1);
  111. if (!addr) {
  112. printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
  113. return;
  114. }
  115. debug(3, "m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
  116. spin_lock_irqsave(&pcc_lock, flags);
  117. /* read Byte */
  118. while (nmemb--)
  119. *bp++ = readb(addr);
  120. spin_unlock_irqrestore(&pcc_lock, flags);
  121. }
  122. void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
  123. size_t nmemb, int flag)
  124. {
  125. u_long addr;
  126. unsigned short *bp = (unsigned short *)buf;
  127. unsigned long flags;
  128. debug(3, "m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
  129. "buf=%p, size=%u, nmemb=%d, flag=%d\n",
  130. sock, port, buf, size, nmemb, flag);
  131. if (size != 2)
  132. printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
  133. port);
  134. if (size == 9)
  135. printk("m32r_cfc: ioread_word :insw \n");
  136. addr = pcc_port2addr(port, 2);
  137. if (!addr) {
  138. printk("m32r_cfc:ioread_word null port :%#lx\n",port);
  139. return;
  140. }
  141. debug(3, "m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
  142. spin_lock_irqsave(&pcc_lock, flags);
  143. /* read Word */
  144. while (nmemb--)
  145. *bp++ = readw(addr);
  146. spin_unlock_irqrestore(&pcc_lock, flags);
  147. }
  148. void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
  149. size_t nmemb, int flag)
  150. {
  151. u_long addr;
  152. unsigned char *bp = (unsigned char *)buf;
  153. unsigned long flags;
  154. debug(3, "m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
  155. "buf=%p, size=%u, nmemb=%d, flag=%d\n",
  156. sock, port, buf, size, nmemb, flag);
  157. /* write Byte */
  158. addr = pcc_port2addr(port, 1);
  159. if (!addr) {
  160. printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
  161. return;
  162. }
  163. debug(3, "m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
  164. spin_lock_irqsave(&pcc_lock, flags);
  165. while (nmemb--)
  166. writeb(*bp++, addr);
  167. spin_unlock_irqrestore(&pcc_lock, flags);
  168. }
  169. void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
  170. size_t nmemb, int flag)
  171. {
  172. u_long addr;
  173. unsigned short *bp = (unsigned short *)buf;
  174. unsigned long flags;
  175. debug(3, "m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
  176. "buf=%p, size=%u, nmemb=%d, flag=%d\n",
  177. sock, port, buf, size, nmemb, flag);
  178. if(size != 2)
  179. printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
  180. size, port);
  181. if(size == 9)
  182. printk("m32r_cfc: iowrite_word :outsw \n");
  183. addr = pcc_port2addr(port, 2);
  184. if (!addr) {
  185. printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
  186. return;
  187. }
  188. #if 1
  189. if (addr & 1) {
  190. printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
  191. addr);
  192. return;
  193. }
  194. #endif
  195. debug(3, "m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
  196. spin_lock_irqsave(&pcc_lock, flags);
  197. while (nmemb--)
  198. writew(*bp++, addr);
  199. spin_unlock_irqrestore(&pcc_lock, flags);
  200. }
  201. /*====================================================================*/
  202. #define IS_REGISTERED 0x2000
  203. #define IS_ALIVE 0x8000
  204. typedef struct pcc_t {
  205. char *name;
  206. u_short flags;
  207. } pcc_t;
  208. static pcc_t pcc[] = {
  209. #if !defined(CONFIG_PLAT_USRV)
  210. { "m32r_cfc", 0 }, { "", 0 },
  211. #else /* CONFIG_PLAT_USRV */
  212. { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
  213. { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
  214. #endif /* CONFIG_PLAT_USRV */
  215. };
  216. static irqreturn_t pcc_interrupt(int, void *);
  217. /*====================================================================*/
  218. static struct timer_list poll_timer;
  219. static unsigned int pcc_get(u_short sock, unsigned int reg)
  220. {
  221. unsigned int val = inw(reg);
  222. debug(3, "m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
  223. return val;
  224. }
  225. static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
  226. {
  227. outw(data, reg);
  228. debug(3, "m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
  229. }
  230. /*======================================================================
  231. See if a card is present, powered up, in IO mode, and already
  232. bound to a (non PC Card) Linux driver. We leave these alone.
  233. We make an exception for cards that seem to be serial devices.
  234. ======================================================================*/
  235. static int __init is_alive(u_short sock)
  236. {
  237. unsigned int stat;
  238. debug(3, "m32r_cfc: is_alive:\n");
  239. printk("CF: ");
  240. stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
  241. if (!stat)
  242. printk("No ");
  243. printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
  244. debug(3, "m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
  245. return 0;
  246. }
  247. static void add_pcc_socket(ulong base, int irq, ulong mapaddr, kio_addr_t ioaddr)
  248. {
  249. pcc_socket_t *t = &socket[pcc_sockets];
  250. debug(3, "m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
  251. "mapaddr=%#lx, ioaddr=%08x\n",
  252. base, irq, mapaddr, ioaddr);
  253. /* add sockets */
  254. t->ioaddr = ioaddr;
  255. t->mapaddr = mapaddr;
  256. #if !defined(CONFIG_PLAT_USRV)
  257. t->base = 0;
  258. t->flags = 0;
  259. t->cs_irq1 = irq; // insert irq
  260. t->cs_irq2 = irq + 1; // eject irq
  261. #else /* CONFIG_PLAT_USRV */
  262. t->base = base;
  263. t->flags = 0;
  264. t->cs_irq1 = 0; // insert irq
  265. t->cs_irq2 = 0; // eject irq
  266. #endif /* CONFIG_PLAT_USRV */
  267. if (is_alive(pcc_sockets))
  268. t->flags |= IS_ALIVE;
  269. /* add pcc */
  270. #if !defined(CONFIG_PLAT_USRV)
  271. request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
  272. #else /* CONFIG_PLAT_USRV */
  273. {
  274. unsigned int reg_base;
  275. reg_base = (unsigned int)PLD_CFRSTCR;
  276. reg_base |= pcc_sockets << 8;
  277. request_region(reg_base, 0x20, "m32r_cfc");
  278. }
  279. #endif /* CONFIG_PLAT_USRV */
  280. printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
  281. printk("pcc at 0x%08lx\n", t->base);
  282. /* Update socket interrupt information, capabilities */
  283. t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
  284. t->socket.map_size = M32R_PCC_MAPSIZE;
  285. t->socket.io_offset = ioaddr; /* use for io access offset */
  286. t->socket.irq_mask = 0;
  287. #if !defined(CONFIG_PLAT_USRV)
  288. t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */
  289. #else /* CONFIG_PLAT_USRV */
  290. t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
  291. #endif /* CONFIG_PLAT_USRV */
  292. #ifndef CONFIG_PLAT_USRV
  293. /* insert interrupt */
  294. request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
  295. #ifndef CONFIG_PLAT_MAPPI3
  296. /* eject interrupt */
  297. request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
  298. #endif
  299. debug(3, "m32r_cfc: enable CFMSK, RDYSEL\n");
  300. pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
  301. #endif /* CONFIG_PLAT_USRV */
  302. #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
  303. pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
  304. #endif
  305. pcc_sockets++;
  306. return;
  307. }
  308. /*====================================================================*/
  309. static irqreturn_t pcc_interrupt(int irq, void *dev)
  310. {
  311. int i;
  312. u_int events = 0;
  313. int handled = 0;
  314. debug(3, "m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev);
  315. for (i = 0; i < pcc_sockets; i++) {
  316. if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
  317. continue;
  318. handled = 1;
  319. debug(3, "m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
  320. i, irq);
  321. events |= SS_DETECT; /* insert or eject */
  322. if (events)
  323. pcmcia_parse_events(&socket[i].socket, events);
  324. }
  325. debug(3, "m32r_cfc: pcc_interrupt: done\n");
  326. return IRQ_RETVAL(handled);
  327. } /* pcc_interrupt */
  328. static void pcc_interrupt_wrapper(u_long data)
  329. {
  330. debug(3, "m32r_cfc: pcc_interrupt_wrapper:\n");
  331. pcc_interrupt(0, NULL);
  332. init_timer(&poll_timer);
  333. poll_timer.expires = jiffies + poll_interval;
  334. add_timer(&poll_timer);
  335. }
  336. /*====================================================================*/
  337. static int _pcc_get_status(u_short sock, u_int *value)
  338. {
  339. u_int status;
  340. debug(3, "m32r_cfc: _pcc_get_status:\n");
  341. status = pcc_get(sock, (unsigned int)PLD_CFSTS);
  342. *value = (status) ? SS_DETECT : 0;
  343. debug(3, "m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
  344. #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
  345. if ( status ) {
  346. /* enable CF power */
  347. status = inw((unsigned int)PLD_CPCR);
  348. if (!(status & PLD_CPCR_CF)) {
  349. debug(3, "m32r_cfc: _pcc_get_status: "
  350. "power on (CPCR=0x%08x)\n", status);
  351. status |= PLD_CPCR_CF;
  352. outw(status, (unsigned int)PLD_CPCR);
  353. udelay(100);
  354. }
  355. *value |= SS_POWERON;
  356. pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
  357. udelay(100);
  358. *value |= SS_READY; /* always ready */
  359. *value |= SS_3VCARD;
  360. } else {
  361. /* disable CF power */
  362. status = inw((unsigned int)PLD_CPCR);
  363. status &= ~PLD_CPCR_CF;
  364. outw(status, (unsigned int)PLD_CPCR);
  365. udelay(100);
  366. debug(3, "m32r_cfc: _pcc_get_status: "
  367. "power off (CPCR=0x%08x)\n", status);
  368. }
  369. #elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
  370. if ( status ) {
  371. status = pcc_get(sock, (unsigned int)PLD_CPCR);
  372. if (status == 0) { /* power off */
  373. pcc_set(sock, (unsigned int)PLD_CPCR, 1);
  374. pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
  375. udelay(50);
  376. }
  377. *value |= SS_POWERON;
  378. pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
  379. udelay(50);
  380. pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
  381. udelay(25); /* for IDE reset */
  382. pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
  383. mdelay(2); /* for IDE reset */
  384. *value |= SS_READY;
  385. *value |= SS_3VCARD;
  386. } else {
  387. /* disable CF power */
  388. pcc_set(sock, (unsigned int)PLD_CPCR, 0);
  389. udelay(100);
  390. debug(3, "m32r_cfc: _pcc_get_status: "
  391. "power off (CPCR=0x%08x)\n", status);
  392. }
  393. #else
  394. #error no platform configuration
  395. #endif
  396. debug(3, "m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
  397. sock, *value);
  398. return 0;
  399. } /* _get_status */
  400. /*====================================================================*/
  401. static int _pcc_set_socket(u_short sock, socket_state_t *state)
  402. {
  403. debug(3, "m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
  404. "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
  405. state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
  406. #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
  407. if (state->Vcc) {
  408. if ((state->Vcc != 50) && (state->Vcc != 33))
  409. return -EINVAL;
  410. /* accept 5V and 3.3V */
  411. }
  412. #endif
  413. if (state->flags & SS_RESET) {
  414. debug(3, ":RESET\n");
  415. pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
  416. }else{
  417. pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
  418. }
  419. if (state->flags & SS_OUTPUT_ENA){
  420. debug(3, ":OUTPUT_ENA\n");
  421. /* bit clear */
  422. pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
  423. } else {
  424. pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
  425. }
  426. #ifdef DEBUG
  427. if(state->flags & SS_IOCARD){
  428. debug(3, ":IOCARD");
  429. }
  430. if (state->flags & SS_PWR_AUTO) {
  431. debug(3, ":PWR_AUTO");
  432. }
  433. if (state->csc_mask & SS_DETECT)
  434. debug(3, ":csc-SS_DETECT");
  435. if (state->flags & SS_IOCARD) {
  436. if (state->csc_mask & SS_STSCHG)
  437. debug(3, ":STSCHG");
  438. } else {
  439. if (state->csc_mask & SS_BATDEAD)
  440. debug(3, ":BATDEAD");
  441. if (state->csc_mask & SS_BATWARN)
  442. debug(3, ":BATWARN");
  443. if (state->csc_mask & SS_READY)
  444. debug(3, ":READY");
  445. }
  446. debug(3, "\n");
  447. #endif
  448. return 0;
  449. } /* _set_socket */
  450. /*====================================================================*/
  451. static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
  452. {
  453. u_char map;
  454. debug(3, "m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
  455. "%#lx-%#lx)\n", sock, io->map, io->flags,
  456. io->speed, io->start, io->stop);
  457. map = io->map;
  458. return 0;
  459. } /* _set_io_map */
  460. /*====================================================================*/
  461. static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
  462. {
  463. u_char map = mem->map;
  464. u_long addr;
  465. pcc_socket_t *t = &socket[sock];
  466. debug(3, "m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
  467. "%#lx, %#x)\n", sock, map, mem->flags,
  468. mem->speed, mem->static_start, mem->card_start);
  469. /*
  470. * sanity check
  471. */
  472. if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
  473. return -EINVAL;
  474. }
  475. /*
  476. * de-activate
  477. */
  478. if ((mem->flags & MAP_ACTIVE) == 0) {
  479. t->current_space = as_none;
  480. return 0;
  481. }
  482. /*
  483. * Set mode
  484. */
  485. if (mem->flags & MAP_ATTRIB) {
  486. t->current_space = as_attr;
  487. } else {
  488. t->current_space = as_comm;
  489. }
  490. /*
  491. * Set address
  492. */
  493. addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
  494. mem->static_start = addr + mem->card_start;
  495. return 0;
  496. } /* _set_mem_map */
  497. #if 0 /* driver model ordering issue */
  498. /*======================================================================
  499. Routines for accessing socket information and register dumps via
  500. /proc/bus/pccard/...
  501. ======================================================================*/
  502. static ssize_t show_info(struct class_device *class_dev, char *buf)
  503. {
  504. pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
  505. socket.dev);
  506. return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
  507. pcc[s->type].name, s->base);
  508. }
  509. static ssize_t show_exca(struct class_device *class_dev, char *buf)
  510. {
  511. /* FIXME */
  512. return 0;
  513. }
  514. static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
  515. static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
  516. #endif
  517. /*====================================================================*/
  518. /* this is horribly ugly... proper locking needs to be done here at
  519. * some time... */
  520. #define LOCKED(x) do { \
  521. int retval; \
  522. unsigned long flags; \
  523. spin_lock_irqsave(&pcc_lock, flags); \
  524. retval = x; \
  525. spin_unlock_irqrestore(&pcc_lock, flags); \
  526. return retval; \
  527. } while (0)
  528. static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
  529. {
  530. unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
  531. if (socket[sock].flags & IS_ALIVE) {
  532. debug(3, "m32r_cfc: pcc_get_status: sock(%d) -EINVAL\n", sock);
  533. *value = 0;
  534. return -EINVAL;
  535. }
  536. debug(3, "m32r_cfc: pcc_get_status: sock(%d)\n", sock);
  537. LOCKED(_pcc_get_status(sock, value));
  538. }
  539. static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
  540. {
  541. unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
  542. if (socket[sock].flags & IS_ALIVE) {
  543. debug(3, "m32r_cfc: pcc_set_socket: sock(%d) -EINVAL\n", sock);
  544. return -EINVAL;
  545. }
  546. debug(3, "m32r_cfc: pcc_set_socket: sock(%d)\n", sock);
  547. LOCKED(_pcc_set_socket(sock, state));
  548. }
  549. static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
  550. {
  551. unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
  552. if (socket[sock].flags & IS_ALIVE) {
  553. debug(3, "m32r_cfc: pcc_set_io_map: sock(%d) -EINVAL\n", sock);
  554. return -EINVAL;
  555. }
  556. debug(3, "m32r_cfc: pcc_set_io_map: sock(%d)\n", sock);
  557. LOCKED(_pcc_set_io_map(sock, io));
  558. }
  559. static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
  560. {
  561. unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
  562. if (socket[sock].flags & IS_ALIVE) {
  563. debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
  564. return -EINVAL;
  565. }
  566. debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d)\n", sock);
  567. LOCKED(_pcc_set_mem_map(sock, mem));
  568. }
  569. static int pcc_init(struct pcmcia_socket *s)
  570. {
  571. debug(3, "m32r_cfc: pcc_init()\n");
  572. return 0;
  573. }
  574. static struct pccard_operations pcc_operations = {
  575. .init = pcc_init,
  576. .get_status = pcc_get_status,
  577. .set_socket = pcc_set_socket,
  578. .set_io_map = pcc_set_io_map,
  579. .set_mem_map = pcc_set_mem_map,
  580. };
  581. /*====================================================================*/
  582. static struct device_driver pcc_driver = {
  583. .name = "cfc",
  584. .bus = &platform_bus_type,
  585. .suspend = pcmcia_socket_dev_suspend,
  586. .resume = pcmcia_socket_dev_resume,
  587. };
  588. static struct platform_device pcc_device = {
  589. .name = "cfc",
  590. .id = 0,
  591. };
  592. /*====================================================================*/
  593. static int __init init_m32r_pcc(void)
  594. {
  595. int i, ret;
  596. ret = driver_register(&pcc_driver);
  597. if (ret)
  598. return ret;
  599. ret = platform_device_register(&pcc_device);
  600. if (ret){
  601. driver_unregister(&pcc_driver);
  602. return ret;
  603. }
  604. #if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
  605. pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
  606. pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
  607. #endif
  608. pcc_sockets = 0;
  609. #if !defined(CONFIG_PLAT_USRV)
  610. add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
  611. CFC_IOPORT_BASE);
  612. #else /* CONFIG_PLAT_USRV */
  613. {
  614. ulong base, mapaddr;
  615. kio_addr_t ioaddr;
  616. for (i = 0 ; i < M32R_MAX_PCC ; i++) {
  617. base = (ulong)PLD_CFRSTCR;
  618. base = base | (i << 8);
  619. ioaddr = (i + 1) << 12;
  620. mapaddr = CFC_ATTR_MAPBASE | (i << 20);
  621. add_pcc_socket(base, 0, mapaddr, ioaddr);
  622. }
  623. }
  624. #endif /* CONFIG_PLAT_USRV */
  625. if (pcc_sockets == 0) {
  626. printk("socket is not found.\n");
  627. platform_device_unregister(&pcc_device);
  628. driver_unregister(&pcc_driver);
  629. return -ENODEV;
  630. }
  631. /* Set up interrupt handler(s) */
  632. for (i = 0 ; i < pcc_sockets ; i++) {
  633. socket[i].socket.dev.parent = &pcc_device.dev;
  634. socket[i].socket.ops = &pcc_operations;
  635. socket[i].socket.resource_ops = &pccard_nonstatic_ops;
  636. socket[i].socket.owner = THIS_MODULE;
  637. socket[i].number = i;
  638. ret = pcmcia_register_socket(&socket[i].socket);
  639. if (!ret)
  640. socket[i].flags |= IS_REGISTERED;
  641. #if 0 /* driver model ordering issue */
  642. class_device_create_file(&socket[i].socket.dev,
  643. &class_device_attr_info);
  644. class_device_create_file(&socket[i].socket.dev,
  645. &class_device_attr_exca);
  646. #endif
  647. }
  648. /* Finally, schedule a polling interrupt */
  649. if (poll_interval != 0) {
  650. poll_timer.function = pcc_interrupt_wrapper;
  651. poll_timer.data = 0;
  652. init_timer(&poll_timer);
  653. poll_timer.expires = jiffies + poll_interval;
  654. add_timer(&poll_timer);
  655. }
  656. return 0;
  657. } /* init_m32r_pcc */
  658. static void __exit exit_m32r_pcc(void)
  659. {
  660. int i;
  661. for (i = 0; i < pcc_sockets; i++)
  662. if (socket[i].flags & IS_REGISTERED)
  663. pcmcia_unregister_socket(&socket[i].socket);
  664. platform_device_unregister(&pcc_device);
  665. if (poll_interval != 0)
  666. del_timer_sync(&poll_timer);
  667. driver_unregister(&pcc_driver);
  668. } /* exit_m32r_pcc */
  669. module_init(init_m32r_pcc);
  670. module_exit(exit_m32r_pcc);
  671. MODULE_LICENSE("Dual MPL/GPL");
  672. /*====================================================================*/