au1000_pb1x00.c 9.1 KB

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  1. /*
  2. *
  3. * Alchemy Semi Pb1x00 boards specific pcmcia routines.
  4. *
  5. * Copyright 2002 MontaVista Software Inc.
  6. * Author: MontaVista Software, Inc.
  7. * ppopov@mvista.com or source@mvista.com
  8. *
  9. * ########################################################################
  10. *
  11. * This program is free software; you can distribute it and/or modify it
  12. * under the terms of the GNU General Public License (Version 2) as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope it will be useful, but WITHOUT
  16. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  18. * for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, write to the Free Software Foundation, Inc.,
  22. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  23. */
  24. #include <linux/module.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/kernel.h>
  29. #include <linux/tqueue.h>
  30. #include <linux/timer.h>
  31. #include <linux/mm.h>
  32. #include <linux/proc_fs.h>
  33. #include <linux/types.h>
  34. #include <pcmcia/cs_types.h>
  35. #include <pcmcia/cs.h>
  36. #include <pcmcia/ss.h>
  37. #include <pcmcia/bulkmem.h>
  38. #include <pcmcia/cistpl.h>
  39. #include <pcmcia/bus_ops.h>
  40. #include "cs_internal.h"
  41. #include <asm/io.h>
  42. #include <asm/irq.h>
  43. #include <asm/system.h>
  44. #include <asm/au1000.h>
  45. #include <asm/au1000_pcmcia.h>
  46. #define debug(fmt, arg...) do { } while (0)
  47. #ifdef CONFIG_MIPS_PB1000
  48. #include <asm/pb1000.h>
  49. #define PCMCIA_IRQ AU1000_GPIO_15
  50. #elif defined (CONFIG_MIPS_PB1500)
  51. #include <asm/pb1500.h>
  52. #define PCMCIA_IRQ AU1500_GPIO_203
  53. #elif defined (CONFIG_MIPS_PB1100)
  54. #include <asm/pb1100.h>
  55. #define PCMCIA_IRQ AU1000_GPIO_11
  56. #endif
  57. static int pb1x00_pcmcia_init(struct pcmcia_init *init)
  58. {
  59. #ifdef CONFIG_MIPS_PB1000
  60. u16 pcr;
  61. pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
  62. au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */
  63. au_sync_delay(100);
  64. au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */
  65. au_sync();
  66. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
  67. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
  68. au_writel(pcr, PB1000_PCR);
  69. au_sync_delay(20);
  70. return PCMCIA_NUM_SOCKS;
  71. #else /* fixme -- take care of the Pb1500 at some point */
  72. u16 pcr;
  73. pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf; /* turn off power */
  74. pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
  75. au_writew(pcr, PCMCIA_BOARD_REG);
  76. au_sync_delay(500);
  77. return PCMCIA_NUM_SOCKS;
  78. #endif
  79. }
  80. static int pb1x00_pcmcia_shutdown(void)
  81. {
  82. #ifdef CONFIG_MIPS_PB1000
  83. u16 pcr;
  84. pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
  85. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
  86. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
  87. au_writel(pcr, PB1000_PCR);
  88. au_sync_delay(20);
  89. return 0;
  90. #else
  91. u16 pcr;
  92. pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf; /* turn off power */
  93. pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
  94. au_writew(pcr, PCMCIA_BOARD_REG);
  95. au_sync_delay(2);
  96. return 0;
  97. #endif
  98. }
  99. static int
  100. pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
  101. {
  102. u32 inserted0, inserted1;
  103. u16 vs0, vs1;
  104. #ifdef CONFIG_MIPS_PB1000
  105. vs0 = vs1 = (u16)au_readl(PB1000_ACR1);
  106. inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2));
  107. inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2));
  108. vs0 = (vs0 >> 4) & 0x3;
  109. vs1 = (vs1 >> 12) & 0x3;
  110. #else
  111. vs0 = (au_readw(BOARD_STATUS_REG) >> 4) & 0x3;
  112. #ifdef CONFIG_MIPS_PB1500
  113. inserted0 = !((au_readl(GPIO2_PINSTATE) >> 1) & 0x1); /* gpio 201 */
  114. #else /* Pb1100 */
  115. inserted0 = !((au_readl(SYS_PINSTATERD) >> 9) & 0x1); /* gpio 9 */
  116. #endif
  117. inserted1 = 0;
  118. #endif
  119. state->ready = 0;
  120. state->vs_Xv = 0;
  121. state->vs_3v = 0;
  122. state->detect = 0;
  123. if (sock == 0) {
  124. if (inserted0) {
  125. switch (vs0) {
  126. case 0:
  127. case 2:
  128. state->vs_3v=1;
  129. break;
  130. case 3: /* 5V */
  131. break;
  132. default:
  133. /* return without setting 'detect' */
  134. printk(KERN_ERR "pb1x00 bad VS (%d)\n",
  135. vs0);
  136. return 0;
  137. }
  138. state->detect = 1;
  139. }
  140. }
  141. else {
  142. if (inserted1) {
  143. switch (vs1) {
  144. case 0:
  145. case 2:
  146. state->vs_3v=1;
  147. break;
  148. case 3: /* 5V */
  149. break;
  150. default:
  151. /* return without setting 'detect' */
  152. printk(KERN_ERR "pb1x00 bad VS (%d)\n",
  153. vs1);
  154. return 0;
  155. }
  156. state->detect = 1;
  157. }
  158. }
  159. if (state->detect) {
  160. state->ready = 1;
  161. }
  162. state->bvd1=1;
  163. state->bvd2=1;
  164. state->wrprot=0;
  165. return 1;
  166. }
  167. static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
  168. {
  169. if(info->sock > PCMCIA_MAX_SOCK) return -1;
  170. /*
  171. * Even in the case of the Pb1000, both sockets are connected
  172. * to the same irq line.
  173. */
  174. info->irq = PCMCIA_IRQ;
  175. return 0;
  176. }
  177. static int
  178. pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure)
  179. {
  180. u16 pcr;
  181. if(configure->sock > PCMCIA_MAX_SOCK) return -1;
  182. #ifdef CONFIG_MIPS_PB1000
  183. pcr = au_readl(PB1000_PCR);
  184. if (configure->sock == 0) {
  185. pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 |
  186. PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1);
  187. }
  188. else {
  189. pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 |
  190. PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1);
  191. }
  192. pcr &= ~PCR_SLOT_0_RST;
  193. debug("Vcc %dV Vpp %dV, pcr %x\n",
  194. configure->vcc, configure->vpp, pcr);
  195. switch(configure->vcc){
  196. case 0: /* Vcc 0 */
  197. switch(configure->vpp) {
  198. case 0:
  199. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND,
  200. configure->sock);
  201. break;
  202. case 12:
  203. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V,
  204. configure->sock);
  205. break;
  206. case 50:
  207. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V,
  208. configure->sock);
  209. break;
  210. case 33:
  211. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V,
  212. configure->sock);
  213. break;
  214. default:
  215. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
  216. configure->sock);
  217. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  218. __FUNCTION__,
  219. configure->vcc,
  220. configure->vpp);
  221. break;
  222. }
  223. break;
  224. case 50: /* Vcc 5V */
  225. switch(configure->vpp) {
  226. case 0:
  227. pcr |= SET_VCC_VPP(VCC_5V,VPP_GND,
  228. configure->sock);
  229. break;
  230. case 50:
  231. pcr |= SET_VCC_VPP(VCC_5V,VPP_5V,
  232. configure->sock);
  233. break;
  234. case 12:
  235. pcr |= SET_VCC_VPP(VCC_5V,VPP_12V,
  236. configure->sock);
  237. break;
  238. case 33:
  239. pcr |= SET_VCC_VPP(VCC_5V,VPP_3V,
  240. configure->sock);
  241. break;
  242. default:
  243. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
  244. configure->sock);
  245. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  246. __FUNCTION__,
  247. configure->vcc,
  248. configure->vpp);
  249. break;
  250. }
  251. break;
  252. case 33: /* Vcc 3.3V */
  253. switch(configure->vpp) {
  254. case 0:
  255. pcr |= SET_VCC_VPP(VCC_3V,VPP_GND,
  256. configure->sock);
  257. break;
  258. case 50:
  259. pcr |= SET_VCC_VPP(VCC_3V,VPP_5V,
  260. configure->sock);
  261. break;
  262. case 12:
  263. pcr |= SET_VCC_VPP(VCC_3V,VPP_12V,
  264. configure->sock);
  265. break;
  266. case 33:
  267. pcr |= SET_VCC_VPP(VCC_3V,VPP_3V,
  268. configure->sock);
  269. break;
  270. default:
  271. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
  272. configure->sock);
  273. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  274. __FUNCTION__,
  275. configure->vcc,
  276. configure->vpp);
  277. break;
  278. }
  279. break;
  280. default: /* what's this ? */
  281. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock);
  282. printk(KERN_ERR "%s: bad Vcc %d\n",
  283. __FUNCTION__, configure->vcc);
  284. break;
  285. }
  286. if (configure->sock == 0) {
  287. pcr &= ~(PCR_SLOT_0_RST);
  288. if (configure->reset)
  289. pcr |= PCR_SLOT_0_RST;
  290. }
  291. else {
  292. pcr &= ~(PCR_SLOT_1_RST);
  293. if (configure->reset)
  294. pcr |= PCR_SLOT_1_RST;
  295. }
  296. au_writel(pcr, PB1000_PCR);
  297. au_sync_delay(300);
  298. #else
  299. pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf;
  300. debug("Vcc %dV Vpp %dV, pcr %x, reset %d\n",
  301. configure->vcc, configure->vpp, pcr, configure->reset);
  302. switch(configure->vcc){
  303. case 0: /* Vcc 0 */
  304. pcr |= SET_VCC_VPP(0,0);
  305. break;
  306. case 50: /* Vcc 5V */
  307. switch(configure->vpp) {
  308. case 0:
  309. pcr |= SET_VCC_VPP(2,0);
  310. break;
  311. case 50:
  312. pcr |= SET_VCC_VPP(2,1);
  313. break;
  314. case 12:
  315. pcr |= SET_VCC_VPP(2,2);
  316. break;
  317. case 33:
  318. default:
  319. pcr |= SET_VCC_VPP(0,0);
  320. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  321. __FUNCTION__,
  322. configure->vcc,
  323. configure->vpp);
  324. break;
  325. }
  326. break;
  327. case 33: /* Vcc 3.3V */
  328. switch(configure->vpp) {
  329. case 0:
  330. pcr |= SET_VCC_VPP(1,0);
  331. break;
  332. case 12:
  333. pcr |= SET_VCC_VPP(1,2);
  334. break;
  335. case 33:
  336. pcr |= SET_VCC_VPP(1,1);
  337. break;
  338. case 50:
  339. default:
  340. pcr |= SET_VCC_VPP(0,0);
  341. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  342. __FUNCTION__,
  343. configure->vcc,
  344. configure->vpp);
  345. break;
  346. }
  347. break;
  348. default: /* what's this ? */
  349. pcr |= SET_VCC_VPP(0,0);
  350. printk(KERN_ERR "%s: bad Vcc %d\n",
  351. __FUNCTION__, configure->vcc);
  352. break;
  353. }
  354. au_writew(pcr, PCMCIA_BOARD_REG);
  355. au_sync_delay(300);
  356. if (!configure->reset) {
  357. pcr |= PC_DRV_EN;
  358. au_writew(pcr, PCMCIA_BOARD_REG);
  359. au_sync_delay(100);
  360. pcr |= PC_DEASSERT_RST;
  361. au_writew(pcr, PCMCIA_BOARD_REG);
  362. au_sync_delay(100);
  363. }
  364. else {
  365. pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
  366. au_writew(pcr, PCMCIA_BOARD_REG);
  367. au_sync_delay(100);
  368. }
  369. #endif
  370. return 0;
  371. }
  372. struct pcmcia_low_level pb1x00_pcmcia_ops = {
  373. pb1x00_pcmcia_init,
  374. pb1x00_pcmcia_shutdown,
  375. pb1x00_pcmcia_socket_state,
  376. pb1x00_pcmcia_get_irq_info,
  377. pb1x00_pcmcia_configure_socket
  378. };