pci.c 36 KB

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  1. /*
  2. * $Id: pci.c,v 1.1.1.1 2007/06/12 07:27:09 eyryu Exp $
  3. *
  4. * PCI Bus Services, see include/linux/pci.h for further explanation.
  5. *
  6. * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
  7. * David Mosberger-Tang
  8. *
  9. * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/delay.h>
  13. #include <linux/init.h>
  14. #include <linux/pci.h>
  15. #include <linux/module.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/string.h>
  18. #include <asm/dma.h> /* isa_dma_bridge_buggy */
  19. #include "pci.h"
  20. unsigned int pci_pm_d3_delay = 10;
  21. #define DEFAULT_CARDBUS_IO_SIZE (256)
  22. #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
  23. /* pci=cbmemsize=nnM,cbiosize=nn can override this */
  24. unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
  25. unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
  26. /**
  27. * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  28. * @bus: pointer to PCI bus structure to search
  29. *
  30. * Given a PCI bus, returns the highest PCI bus number present in the set
  31. * including the given PCI bus and its list of child PCI buses.
  32. */
  33. unsigned char __devinit
  34. pci_bus_max_busnr(struct pci_bus* bus)
  35. {
  36. struct list_head *tmp;
  37. unsigned char max, n;
  38. max = bus->subordinate;
  39. list_for_each(tmp, &bus->children) {
  40. n = pci_bus_max_busnr(pci_bus_b(tmp));
  41. if(n > max)
  42. max = n;
  43. }
  44. return max;
  45. }
  46. EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
  47. #if 0
  48. /**
  49. * pci_max_busnr - returns maximum PCI bus number
  50. *
  51. * Returns the highest PCI bus number present in the system global list of
  52. * PCI buses.
  53. */
  54. unsigned char __devinit
  55. pci_max_busnr(void)
  56. {
  57. struct pci_bus *bus = NULL;
  58. unsigned char max, n;
  59. max = 0;
  60. while ((bus = pci_find_next_bus(bus)) != NULL) {
  61. n = pci_bus_max_busnr(bus);
  62. if(n > max)
  63. max = n;
  64. }
  65. return max;
  66. }
  67. #endif /* 0 */
  68. #define PCI_FIND_CAP_TTL 48
  69. static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
  70. u8 pos, int cap, int *ttl)
  71. {
  72. u8 id;
  73. while ((*ttl)--) {
  74. pci_bus_read_config_byte(bus, devfn, pos, &pos);
  75. if (pos < 0x40)
  76. break;
  77. pos &= ~3;
  78. pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
  79. &id);
  80. if (id == 0xff)
  81. break;
  82. if (id == cap)
  83. return pos;
  84. pos += PCI_CAP_LIST_NEXT;
  85. }
  86. return 0;
  87. }
  88. static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
  89. u8 pos, int cap)
  90. {
  91. int ttl = PCI_FIND_CAP_TTL;
  92. return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
  93. }
  94. int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
  95. {
  96. return __pci_find_next_cap(dev->bus, dev->devfn,
  97. pos + PCI_CAP_LIST_NEXT, cap);
  98. }
  99. EXPORT_SYMBOL_GPL(pci_find_next_capability);
  100. static int __pci_bus_find_cap_start(struct pci_bus *bus,
  101. unsigned int devfn, u8 hdr_type)
  102. {
  103. u16 status;
  104. pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
  105. if (!(status & PCI_STATUS_CAP_LIST))
  106. return 0;
  107. switch (hdr_type) {
  108. case PCI_HEADER_TYPE_NORMAL:
  109. case PCI_HEADER_TYPE_BRIDGE:
  110. return PCI_CAPABILITY_LIST;
  111. case PCI_HEADER_TYPE_CARDBUS:
  112. return PCI_CB_CAPABILITY_LIST;
  113. default:
  114. return 0;
  115. }
  116. return 0;
  117. }
  118. /**
  119. * pci_find_capability - query for devices' capabilities
  120. * @dev: PCI device to query
  121. * @cap: capability code
  122. *
  123. * Tell if a device supports a given PCI capability.
  124. * Returns the address of the requested capability structure within the
  125. * device's PCI configuration space or 0 in case the device does not
  126. * support it. Possible values for @cap:
  127. *
  128. * %PCI_CAP_ID_PM Power Management
  129. * %PCI_CAP_ID_AGP Accelerated Graphics Port
  130. * %PCI_CAP_ID_VPD Vital Product Data
  131. * %PCI_CAP_ID_SLOTID Slot Identification
  132. * %PCI_CAP_ID_MSI Message Signalled Interrupts
  133. * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
  134. * %PCI_CAP_ID_PCIX PCI-X
  135. * %PCI_CAP_ID_EXP PCI Express
  136. */
  137. int pci_find_capability(struct pci_dev *dev, int cap)
  138. {
  139. int pos;
  140. pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
  141. if (pos)
  142. pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
  143. return pos;
  144. }
  145. /**
  146. * pci_bus_find_capability - query for devices' capabilities
  147. * @bus: the PCI bus to query
  148. * @devfn: PCI device to query
  149. * @cap: capability code
  150. *
  151. * Like pci_find_capability() but works for pci devices that do not have a
  152. * pci_dev structure set up yet.
  153. *
  154. * Returns the address of the requested capability structure within the
  155. * device's PCI configuration space or 0 in case the device does not
  156. * support it.
  157. */
  158. int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
  159. {
  160. int pos;
  161. u8 hdr_type;
  162. pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
  163. pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
  164. if (pos)
  165. pos = __pci_find_next_cap(bus, devfn, pos, cap);
  166. return pos;
  167. }
  168. /**
  169. * pci_find_ext_capability - Find an extended capability
  170. * @dev: PCI device to query
  171. * @cap: capability code
  172. *
  173. * Returns the address of the requested extended capability structure
  174. * within the device's PCI configuration space or 0 if the device does
  175. * not support it. Possible values for @cap:
  176. *
  177. * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
  178. * %PCI_EXT_CAP_ID_VC Virtual Channel
  179. * %PCI_EXT_CAP_ID_DSN Device Serial Number
  180. * %PCI_EXT_CAP_ID_PWR Power Budgeting
  181. */
  182. int pci_find_ext_capability(struct pci_dev *dev, int cap)
  183. {
  184. u32 header;
  185. int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
  186. int pos = 0x100;
  187. if (dev->cfg_size <= 256)
  188. return 0;
  189. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  190. return 0;
  191. /*
  192. * If we have no capabilities, this is indicated by cap ID,
  193. * cap version and next pointer all being 0.
  194. */
  195. if (header == 0)
  196. return 0;
  197. while (ttl-- > 0) {
  198. if (PCI_EXT_CAP_ID(header) == cap)
  199. return pos;
  200. pos = PCI_EXT_CAP_NEXT(header);
  201. if (pos < 0x100)
  202. break;
  203. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  204. break;
  205. }
  206. return 0;
  207. }
  208. EXPORT_SYMBOL_GPL(pci_find_ext_capability);
  209. static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
  210. {
  211. int rc, ttl = PCI_FIND_CAP_TTL;
  212. u8 cap, mask;
  213. if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
  214. mask = HT_3BIT_CAP_MASK;
  215. else
  216. mask = HT_5BIT_CAP_MASK;
  217. pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
  218. PCI_CAP_ID_HT, &ttl);
  219. while (pos) {
  220. rc = pci_read_config_byte(dev, pos + 3, &cap);
  221. if (rc != PCIBIOS_SUCCESSFUL)
  222. return 0;
  223. if ((cap & mask) == ht_cap)
  224. return pos;
  225. pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
  226. pos + PCI_CAP_LIST_NEXT,
  227. PCI_CAP_ID_HT, &ttl);
  228. }
  229. return 0;
  230. }
  231. /**
  232. * pci_find_next_ht_capability - query a device's Hypertransport capabilities
  233. * @dev: PCI device to query
  234. * @pos: Position from which to continue searching
  235. * @ht_cap: Hypertransport capability code
  236. *
  237. * To be used in conjunction with pci_find_ht_capability() to search for
  238. * all capabilities matching @ht_cap. @pos should always be a value returned
  239. * from pci_find_ht_capability().
  240. *
  241. * NB. To be 100% safe against broken PCI devices, the caller should take
  242. * steps to avoid an infinite loop.
  243. */
  244. int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
  245. {
  246. return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
  247. }
  248. EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
  249. /**
  250. * pci_find_ht_capability - query a device's Hypertransport capabilities
  251. * @dev: PCI device to query
  252. * @ht_cap: Hypertransport capability code
  253. *
  254. * Tell if a device supports a given Hypertransport capability.
  255. * Returns an address within the device's PCI configuration space
  256. * or 0 in case the device does not support the request capability.
  257. * The address points to the PCI capability, of type PCI_CAP_ID_HT,
  258. * which has a Hypertransport capability matching @ht_cap.
  259. */
  260. int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
  261. {
  262. int pos;
  263. pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
  264. if (pos)
  265. pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
  266. return pos;
  267. }
  268. EXPORT_SYMBOL_GPL(pci_find_ht_capability);
  269. /**
  270. * pci_find_parent_resource - return resource region of parent bus of given region
  271. * @dev: PCI device structure contains resources to be searched
  272. * @res: child resource record for which parent is sought
  273. *
  274. * For given resource region of given device, return the resource
  275. * region of parent bus the given region is contained in or where
  276. * it should be allocated from.
  277. */
  278. struct resource *
  279. pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
  280. {
  281. const struct pci_bus *bus = dev->bus;
  282. int i;
  283. struct resource *best = NULL;
  284. for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
  285. struct resource *r = bus->resource[i];
  286. if (!r)
  287. continue;
  288. if (res->start && !(res->start >= r->start && res->end <= r->end))
  289. continue; /* Not contained */
  290. if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
  291. continue; /* Wrong type */
  292. if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
  293. return r; /* Exact match */
  294. if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
  295. best = r; /* Approximating prefetchable by non-prefetchable */
  296. }
  297. return best;
  298. }
  299. /**
  300. * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
  301. * @dev: PCI device to have its BARs restored
  302. *
  303. * Restore the BAR values for a given device, so as to make it
  304. * accessible by its driver.
  305. */
  306. void
  307. pci_restore_bars(struct pci_dev *dev)
  308. {
  309. int i, numres;
  310. switch (dev->hdr_type) {
  311. case PCI_HEADER_TYPE_NORMAL:
  312. numres = 6;
  313. break;
  314. case PCI_HEADER_TYPE_BRIDGE:
  315. numres = 2;
  316. break;
  317. case PCI_HEADER_TYPE_CARDBUS:
  318. numres = 1;
  319. break;
  320. default:
  321. /* Should never get here, but just in case... */
  322. return;
  323. }
  324. for (i = 0; i < numres; i ++)
  325. pci_update_resource(dev, &dev->resource[i], i);
  326. }
  327. int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
  328. /**
  329. * pci_set_power_state - Set the power state of a PCI device
  330. * @dev: PCI device to be suspended
  331. * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
  332. *
  333. * Transition a device to a new power state, using the Power Management
  334. * Capabilities in the device's config space.
  335. *
  336. * RETURN VALUE:
  337. * -EINVAL if trying to enter a lower state than we're already in.
  338. * 0 if we're already in the requested state.
  339. * -EIO if device does not support PCI PM.
  340. * 0 if we can successfully change the power state.
  341. */
  342. int
  343. pci_set_power_state(struct pci_dev *dev, pci_power_t state)
  344. {
  345. int pm, need_restore = 0;
  346. u16 pmcsr, pmc;
  347. /* bound the state we're entering */
  348. if (state > PCI_D3hot)
  349. state = PCI_D3hot;
  350. /*
  351. * If the device or the parent bridge can't support PCI PM, ignore
  352. * the request if we're doing anything besides putting it into D0
  353. * (which would only happen on boot).
  354. */
  355. if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
  356. return 0;
  357. /* Validate current state:
  358. * Can enter D0 from any state, but if we can only go deeper
  359. * to sleep if we're already in a low power state
  360. */
  361. if (state != PCI_D0 && dev->current_state > state) {
  362. printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
  363. __FUNCTION__, pci_name(dev), state, dev->current_state);
  364. return -EINVAL;
  365. } else if (dev->current_state == state)
  366. return 0; /* we're already there */
  367. /* find PCI PM capability in list */
  368. pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  369. /* abort if the device doesn't support PM capabilities */
  370. if (!pm)
  371. return -EIO;
  372. pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
  373. if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
  374. printk(KERN_DEBUG
  375. "PCI: %s has unsupported PM cap regs version (%u)\n",
  376. pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
  377. return -EIO;
  378. }
  379. /* check if this device supports the desired state */
  380. if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
  381. return -EIO;
  382. else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
  383. return -EIO;
  384. pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
  385. /* If we're (effectively) in D3, force entire word to 0.
  386. * This doesn't affect PME_Status, disables PME_En, and
  387. * sets PowerState to 0.
  388. */
  389. switch (dev->current_state) {
  390. case PCI_D0:
  391. case PCI_D1:
  392. case PCI_D2:
  393. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  394. pmcsr |= state;
  395. break;
  396. case PCI_UNKNOWN: /* Boot-up */
  397. if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
  398. && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
  399. need_restore = 1;
  400. /* Fall-through: force to D0 */
  401. default:
  402. pmcsr = 0;
  403. break;
  404. }
  405. /* enter specified state */
  406. pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
  407. /* Mandatory power management transition delays */
  408. /* see PCI PM 1.1 5.6.1 table 18 */
  409. if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
  410. msleep(pci_pm_d3_delay);
  411. else if (state == PCI_D2 || dev->current_state == PCI_D2)
  412. udelay(200);
  413. /*
  414. * Give firmware a chance to be called, such as ACPI _PRx, _PSx
  415. * Firmware method after native method ?
  416. */
  417. if (platform_pci_set_power_state)
  418. platform_pci_set_power_state(dev, state);
  419. dev->current_state = state;
  420. /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
  421. * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
  422. * from D3hot to D0 _may_ perform an internal reset, thereby
  423. * going to "D0 Uninitialized" rather than "D0 Initialized".
  424. * For example, at least some versions of the 3c905B and the
  425. * 3c556B exhibit this behaviour.
  426. *
  427. * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
  428. * devices in a D3hot state at boot. Consequently, we need to
  429. * restore at least the BARs so that the device will be
  430. * accessible to its driver.
  431. */
  432. if (need_restore)
  433. pci_restore_bars(dev);
  434. return 0;
  435. }
  436. int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
  437. /**
  438. * pci_choose_state - Choose the power state of a PCI device
  439. * @dev: PCI device to be suspended
  440. * @state: target sleep state for the whole system. This is the value
  441. * that is passed to suspend() function.
  442. *
  443. * Returns PCI power state suitable for given device and given system
  444. * message.
  445. */
  446. pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
  447. {
  448. int ret;
  449. if (!pci_find_capability(dev, PCI_CAP_ID_PM))
  450. return PCI_D0;
  451. if (platform_pci_choose_state) {
  452. ret = platform_pci_choose_state(dev, state);
  453. if (ret >= 0)
  454. state.event = ret;
  455. }
  456. switch (state.event) {
  457. case PM_EVENT_ON:
  458. return PCI_D0;
  459. case PM_EVENT_FREEZE:
  460. case PM_EVENT_PRETHAW:
  461. /* REVISIT both freeze and pre-thaw "should" use D0 */
  462. case PM_EVENT_SUSPEND:
  463. return PCI_D3hot;
  464. default:
  465. printk("Unrecognized suspend event %d\n", state.event);
  466. BUG();
  467. }
  468. return PCI_D0;
  469. }
  470. EXPORT_SYMBOL(pci_choose_state);
  471. static int pci_save_pcie_state(struct pci_dev *dev)
  472. {
  473. int pos, i = 0;
  474. struct pci_cap_saved_state *save_state;
  475. u16 *cap;
  476. pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
  477. if (pos <= 0)
  478. return 0;
  479. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
  480. if (!save_state)
  481. save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
  482. if (!save_state) {
  483. dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
  484. return -ENOMEM;
  485. }
  486. cap = (u16 *)&save_state->data[0];
  487. pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
  488. pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
  489. pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
  490. pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
  491. pci_add_saved_cap(dev, save_state);
  492. return 0;
  493. }
  494. static void pci_restore_pcie_state(struct pci_dev *dev)
  495. {
  496. int i = 0, pos;
  497. struct pci_cap_saved_state *save_state;
  498. u16 *cap;
  499. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
  500. pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
  501. if (!save_state || pos <= 0)
  502. return;
  503. cap = (u16 *)&save_state->data[0];
  504. pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
  505. pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
  506. pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
  507. pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
  508. }
  509. static int pci_save_pcix_state(struct pci_dev *dev)
  510. {
  511. int pos, i = 0;
  512. struct pci_cap_saved_state *save_state;
  513. u16 *cap;
  514. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  515. if (pos <= 0)
  516. return 0;
  517. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
  518. if (!save_state)
  519. save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
  520. if (!save_state) {
  521. dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
  522. return -ENOMEM;
  523. }
  524. cap = (u16 *)&save_state->data[0];
  525. pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
  526. pci_add_saved_cap(dev, save_state);
  527. return 0;
  528. }
  529. static void pci_restore_pcix_state(struct pci_dev *dev)
  530. {
  531. int i = 0, pos;
  532. struct pci_cap_saved_state *save_state;
  533. u16 *cap;
  534. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
  535. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  536. if (!save_state || pos <= 0)
  537. return;
  538. cap = (u16 *)&save_state->data[0];
  539. pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
  540. }
  541. /**
  542. * pci_save_state - save the PCI configuration space of a device before suspending
  543. * @dev: - PCI device that we're dealing with
  544. */
  545. int
  546. pci_save_state(struct pci_dev *dev)
  547. {
  548. int i;
  549. /* XXX: 100% dword access ok here? */
  550. for (i = 0; i < 16; i++)
  551. pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
  552. if ((i = pci_save_pcie_state(dev)) != 0)
  553. return i;
  554. if ((i = pci_save_pcix_state(dev)) != 0)
  555. return i;
  556. return 0;
  557. }
  558. /**
  559. * pci_restore_state - Restore the saved state of a PCI device
  560. * @dev: - PCI device that we're dealing with
  561. */
  562. int
  563. pci_restore_state(struct pci_dev *dev)
  564. {
  565. int i;
  566. int val;
  567. /* PCI Express register must be restored first */
  568. pci_restore_pcie_state(dev);
  569. /*
  570. * The Base Address register should be programmed before the command
  571. * register(s)
  572. */
  573. for (i = 15; i >= 0; i--) {
  574. pci_read_config_dword(dev, i * 4, &val);
  575. if (val != dev->saved_config_space[i]) {
  576. printk(KERN_DEBUG "PM: Writing back config space on "
  577. "device %s at offset %x (was %x, writing %x)\n",
  578. pci_name(dev), i,
  579. val, (int)dev->saved_config_space[i]);
  580. pci_write_config_dword(dev,i * 4,
  581. dev->saved_config_space[i]);
  582. }
  583. }
  584. pci_restore_pcix_state(dev);
  585. pci_restore_msi_state(dev);
  586. return 0;
  587. }
  588. static int do_pci_enable_device(struct pci_dev *dev, int bars)
  589. {
  590. int err;
  591. err = pci_set_power_state(dev, PCI_D0);
  592. if (err < 0 && err != -EIO)
  593. return err;
  594. err = pcibios_enable_device(dev, bars);
  595. if (err < 0)
  596. return err;
  597. pci_fixup_device(pci_fixup_enable, dev);
  598. return 0;
  599. }
  600. /**
  601. * __pci_reenable_device - Resume abandoned device
  602. * @dev: PCI device to be resumed
  603. *
  604. * Note this function is a backend of pci_default_resume and is not supposed
  605. * to be called by normal code, write proper resume handler and use it instead.
  606. */
  607. int
  608. __pci_reenable_device(struct pci_dev *dev)
  609. {
  610. if (atomic_read(&dev->enable_cnt))
  611. return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
  612. return 0;
  613. }
  614. /**
  615. * pci_enable_device_bars - Initialize some of a device for use
  616. * @dev: PCI device to be initialized
  617. * @bars: bitmask of BAR's that must be configured
  618. *
  619. * Initialize device before it's used by a driver. Ask low-level code
  620. * to enable selected I/O and memory resources. Wake up the device if it
  621. * was suspended. Beware, this function can fail.
  622. */
  623. int
  624. pci_enable_device_bars(struct pci_dev *dev, int bars)
  625. {
  626. int err;
  627. if (atomic_add_return(1, &dev->enable_cnt) > 1)
  628. return 0; /* already enabled */
  629. err = do_pci_enable_device(dev, bars);
  630. if (err < 0)
  631. atomic_dec(&dev->enable_cnt);
  632. return err;
  633. }
  634. /**
  635. * pci_enable_device - Initialize device before it's used by a driver.
  636. * @dev: PCI device to be initialized
  637. *
  638. * Initialize device before it's used by a driver. Ask low-level code
  639. * to enable I/O and memory. Wake up the device if it was suspended.
  640. * Beware, this function can fail.
  641. *
  642. * Note we don't actually enable the device many times if we call
  643. * this function repeatedly (we just increment the count).
  644. */
  645. int pci_enable_device(struct pci_dev *dev)
  646. {
  647. return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
  648. }
  649. /*
  650. * Managed PCI resources. This manages device on/off, intx/msi/msix
  651. * on/off and BAR regions. pci_dev itself records msi/msix status, so
  652. * there's no need to track it separately. pci_devres is initialized
  653. * when a device is enabled using managed PCI device enable interface.
  654. */
  655. struct pci_devres {
  656. unsigned int enabled:1;
  657. unsigned int pinned:1;
  658. unsigned int orig_intx:1;
  659. unsigned int restore_intx:1;
  660. u32 region_mask;
  661. };
  662. static void pcim_release(struct device *gendev, void *res)
  663. {
  664. struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
  665. struct pci_devres *this = res;
  666. int i;
  667. if (dev->msi_enabled)
  668. pci_disable_msi(dev);
  669. if (dev->msix_enabled)
  670. pci_disable_msix(dev);
  671. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  672. if (this->region_mask & (1 << i))
  673. pci_release_region(dev, i);
  674. if (this->restore_intx)
  675. pci_intx(dev, this->orig_intx);
  676. if (this->enabled && !this->pinned)
  677. pci_disable_device(dev);
  678. }
  679. static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
  680. {
  681. struct pci_devres *dr, *new_dr;
  682. dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
  683. if (dr)
  684. return dr;
  685. new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
  686. if (!new_dr)
  687. return NULL;
  688. return devres_get(&pdev->dev, new_dr, NULL, NULL);
  689. }
  690. static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
  691. {
  692. if (pci_is_managed(pdev))
  693. return devres_find(&pdev->dev, pcim_release, NULL, NULL);
  694. return NULL;
  695. }
  696. /**
  697. * pcim_enable_device - Managed pci_enable_device()
  698. * @pdev: PCI device to be initialized
  699. *
  700. * Managed pci_enable_device().
  701. */
  702. int pcim_enable_device(struct pci_dev *pdev)
  703. {
  704. struct pci_devres *dr;
  705. int rc;
  706. dr = get_pci_dr(pdev);
  707. if (unlikely(!dr))
  708. return -ENOMEM;
  709. WARN_ON(!!dr->enabled);
  710. rc = pci_enable_device(pdev);
  711. if (!rc) {
  712. pdev->is_managed = 1;
  713. dr->enabled = 1;
  714. }
  715. return rc;
  716. }
  717. /**
  718. * pcim_pin_device - Pin managed PCI device
  719. * @pdev: PCI device to pin
  720. *
  721. * Pin managed PCI device @pdev. Pinned device won't be disabled on
  722. * driver detach. @pdev must have been enabled with
  723. * pcim_enable_device().
  724. */
  725. void pcim_pin_device(struct pci_dev *pdev)
  726. {
  727. struct pci_devres *dr;
  728. dr = find_pci_dr(pdev);
  729. WARN_ON(!dr || !dr->enabled);
  730. if (dr)
  731. dr->pinned = 1;
  732. }
  733. /**
  734. * pcibios_disable_device - disable arch specific PCI resources for device dev
  735. * @dev: the PCI device to disable
  736. *
  737. * Disables architecture specific PCI resources for the device. This
  738. * is the default implementation. Architecture implementations can
  739. * override this.
  740. */
  741. void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
  742. /**
  743. * pci_disable_device - Disable PCI device after use
  744. * @dev: PCI device to be disabled
  745. *
  746. * Signal to the system that the PCI device is not in use by the system
  747. * anymore. This only involves disabling PCI bus-mastering, if active.
  748. *
  749. * Note we don't actually disable the device until all callers of
  750. * pci_device_enable() have called pci_device_disable().
  751. */
  752. void
  753. pci_disable_device(struct pci_dev *dev)
  754. {
  755. struct pci_devres *dr;
  756. u16 pci_command;
  757. dr = find_pci_dr(dev);
  758. if (dr)
  759. dr->enabled = 0;
  760. if (atomic_sub_return(1, &dev->enable_cnt) != 0)
  761. return;
  762. pci_read_config_word(dev, PCI_COMMAND, &pci_command);
  763. if (pci_command & PCI_COMMAND_MASTER) {
  764. pci_command &= ~PCI_COMMAND_MASTER;
  765. pci_write_config_word(dev, PCI_COMMAND, pci_command);
  766. }
  767. dev->is_busmaster = 0;
  768. pcibios_disable_device(dev);
  769. }
  770. /**
  771. * pci_enable_wake - enable device to generate PME# when suspended
  772. * @dev: - PCI device to operate on
  773. * @state: - Current state of device.
  774. * @enable: - Flag to enable or disable generation
  775. *
  776. * Set the bits in the device's PM Capabilities to generate PME# when
  777. * the system is suspended.
  778. *
  779. * -EIO is returned if device doesn't have PM Capabilities.
  780. * -EINVAL is returned if device supports it, but can't generate wake events.
  781. * 0 if operation is successful.
  782. *
  783. */
  784. int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
  785. {
  786. int pm;
  787. u16 value;
  788. /* find PCI PM capability in list */
  789. pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  790. /* If device doesn't support PM Capabilities, but request is to disable
  791. * wake events, it's a nop; otherwise fail */
  792. if (!pm)
  793. return enable ? -EIO : 0;
  794. /* Check device's ability to generate PME# */
  795. pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
  796. value &= PCI_PM_CAP_PME_MASK;
  797. value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
  798. /* Check if it can generate PME# from requested state. */
  799. if (!value || !(value & (1 << state)))
  800. return enable ? -EINVAL : 0;
  801. pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
  802. /* Clear PME_Status by writing 1 to it and enable PME# */
  803. value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
  804. if (!enable)
  805. value &= ~PCI_PM_CTRL_PME_ENABLE;
  806. pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
  807. return 0;
  808. }
  809. int
  810. pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
  811. {
  812. u8 pin;
  813. pin = dev->pin;
  814. if (!pin)
  815. return -1;
  816. pin--;
  817. while (dev->bus->self) {
  818. pin = (pin + PCI_SLOT(dev->devfn)) % 4;
  819. dev = dev->bus->self;
  820. }
  821. *bridge = dev;
  822. return pin;
  823. }
  824. /**
  825. * pci_release_region - Release a PCI bar
  826. * @pdev: PCI device whose resources were previously reserved by pci_request_region
  827. * @bar: BAR to release
  828. *
  829. * Releases the PCI I/O and memory resources previously reserved by a
  830. * successful call to pci_request_region. Call this function only
  831. * after all use of the PCI regions has ceased.
  832. */
  833. void pci_release_region(struct pci_dev *pdev, int bar)
  834. {
  835. struct pci_devres *dr;
  836. if (pci_resource_len(pdev, bar) == 0)
  837. return;
  838. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
  839. release_region(pci_resource_start(pdev, bar),
  840. pci_resource_len(pdev, bar));
  841. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
  842. release_mem_region(pci_resource_start(pdev, bar),
  843. pci_resource_len(pdev, bar));
  844. dr = find_pci_dr(pdev);
  845. if (dr)
  846. dr->region_mask &= ~(1 << bar);
  847. }
  848. /**
  849. * pci_request_region - Reserved PCI I/O and memory resource
  850. * @pdev: PCI device whose resources are to be reserved
  851. * @bar: BAR to be reserved
  852. * @res_name: Name to be associated with resource.
  853. *
  854. * Mark the PCI region associated with PCI device @pdev BR @bar as
  855. * being reserved by owner @res_name. Do not access any
  856. * address inside the PCI regions unless this call returns
  857. * successfully.
  858. *
  859. * Returns 0 on success, or %EBUSY on error. A warning
  860. * message is also printed on failure.
  861. */
  862. int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
  863. {
  864. struct pci_devres *dr;
  865. if (pci_resource_len(pdev, bar) == 0)
  866. return 0;
  867. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
  868. if (!request_region(pci_resource_start(pdev, bar),
  869. pci_resource_len(pdev, bar), res_name))
  870. goto err_out;
  871. }
  872. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
  873. if (!request_mem_region(pci_resource_start(pdev, bar),
  874. pci_resource_len(pdev, bar), res_name))
  875. goto err_out;
  876. }
  877. dr = find_pci_dr(pdev);
  878. if (dr)
  879. dr->region_mask |= 1 << bar;
  880. return 0;
  881. err_out:
  882. printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
  883. "for device %s\n",
  884. pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
  885. bar + 1, /* PCI BAR # */
  886. (unsigned long long)pci_resource_len(pdev, bar),
  887. (unsigned long long)pci_resource_start(pdev, bar),
  888. pci_name(pdev));
  889. return -EBUSY;
  890. }
  891. /**
  892. * pci_release_selected_regions - Release selected PCI I/O and memory resources
  893. * @pdev: PCI device whose resources were previously reserved
  894. * @bars: Bitmask of BARs to be released
  895. *
  896. * Release selected PCI I/O and memory resources previously reserved.
  897. * Call this function only after all use of the PCI regions has ceased.
  898. */
  899. void pci_release_selected_regions(struct pci_dev *pdev, int bars)
  900. {
  901. int i;
  902. for (i = 0; i < 6; i++)
  903. if (bars & (1 << i))
  904. pci_release_region(pdev, i);
  905. }
  906. /**
  907. * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
  908. * @pdev: PCI device whose resources are to be reserved
  909. * @bars: Bitmask of BARs to be requested
  910. * @res_name: Name to be associated with resource
  911. */
  912. int pci_request_selected_regions(struct pci_dev *pdev, int bars,
  913. const char *res_name)
  914. {
  915. int i;
  916. for (i = 0; i < 6; i++)
  917. if (bars & (1 << i))
  918. if(pci_request_region(pdev, i, res_name))
  919. goto err_out;
  920. return 0;
  921. err_out:
  922. while(--i >= 0)
  923. if (bars & (1 << i))
  924. pci_release_region(pdev, i);
  925. return -EBUSY;
  926. }
  927. /**
  928. * pci_release_regions - Release reserved PCI I/O and memory resources
  929. * @pdev: PCI device whose resources were previously reserved by pci_request_regions
  930. *
  931. * Releases all PCI I/O and memory resources previously reserved by a
  932. * successful call to pci_request_regions. Call this function only
  933. * after all use of the PCI regions has ceased.
  934. */
  935. void pci_release_regions(struct pci_dev *pdev)
  936. {
  937. pci_release_selected_regions(pdev, (1 << 6) - 1);
  938. }
  939. /**
  940. * pci_request_regions - Reserved PCI I/O and memory resources
  941. * @pdev: PCI device whose resources are to be reserved
  942. * @res_name: Name to be associated with resource.
  943. *
  944. * Mark all PCI regions associated with PCI device @pdev as
  945. * being reserved by owner @res_name. Do not access any
  946. * address inside the PCI regions unless this call returns
  947. * successfully.
  948. *
  949. * Returns 0 on success, or %EBUSY on error. A warning
  950. * message is also printed on failure.
  951. */
  952. int pci_request_regions(struct pci_dev *pdev, const char *res_name)
  953. {
  954. return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
  955. }
  956. /**
  957. * pci_set_master - enables bus-mastering for device dev
  958. * @dev: the PCI device to enable
  959. *
  960. * Enables bus-mastering on the device and calls pcibios_set_master()
  961. * to do the needed arch specific settings.
  962. */
  963. void
  964. pci_set_master(struct pci_dev *dev)
  965. {
  966. u16 cmd;
  967. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  968. if (! (cmd & PCI_COMMAND_MASTER)) {
  969. pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
  970. cmd |= PCI_COMMAND_MASTER;
  971. pci_write_config_word(dev, PCI_COMMAND, cmd);
  972. }
  973. dev->is_busmaster = 1;
  974. pcibios_set_master(dev);
  975. }
  976. #ifdef PCI_DISABLE_MWI
  977. int pci_set_mwi(struct pci_dev *dev)
  978. {
  979. return 0;
  980. }
  981. void pci_clear_mwi(struct pci_dev *dev)
  982. {
  983. }
  984. #else
  985. #ifndef PCI_CACHE_LINE_BYTES
  986. #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
  987. #endif
  988. /* This can be overridden by arch code. */
  989. /* Don't forget this is measured in 32-bit words, not bytes */
  990. u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
  991. /**
  992. * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
  993. * @dev: the PCI device for which MWI is to be enabled
  994. *
  995. * Helper function for pci_set_mwi.
  996. * Originally copied from drivers/net/acenic.c.
  997. * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
  998. *
  999. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  1000. */
  1001. static int
  1002. pci_set_cacheline_size(struct pci_dev *dev)
  1003. {
  1004. u8 cacheline_size;
  1005. if (!pci_cache_line_size)
  1006. return -EINVAL; /* The system doesn't support MWI. */
  1007. /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
  1008. equal to or multiple of the right value. */
  1009. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  1010. if (cacheline_size >= pci_cache_line_size &&
  1011. (cacheline_size % pci_cache_line_size) == 0)
  1012. return 0;
  1013. /* Write the correct value. */
  1014. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
  1015. /* Read it back. */
  1016. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  1017. if (cacheline_size == pci_cache_line_size)
  1018. return 0;
  1019. printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
  1020. "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
  1021. return -EINVAL;
  1022. }
  1023. /**
  1024. * pci_set_mwi - enables memory-write-invalidate PCI transaction
  1025. * @dev: the PCI device for which MWI is enabled
  1026. *
  1027. * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
  1028. * and then calls @pcibios_set_mwi to do the needed arch specific
  1029. * operations or a generic mwi-prep function.
  1030. *
  1031. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  1032. */
  1033. int
  1034. pci_set_mwi(struct pci_dev *dev)
  1035. {
  1036. int rc;
  1037. u16 cmd;
  1038. rc = pci_set_cacheline_size(dev);
  1039. if (rc)
  1040. return rc;
  1041. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1042. if (! (cmd & PCI_COMMAND_INVALIDATE)) {
  1043. pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
  1044. cmd |= PCI_COMMAND_INVALIDATE;
  1045. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1046. }
  1047. return 0;
  1048. }
  1049. /**
  1050. * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
  1051. * @dev: the PCI device to disable
  1052. *
  1053. * Disables PCI Memory-Write-Invalidate transaction on the device
  1054. */
  1055. void
  1056. pci_clear_mwi(struct pci_dev *dev)
  1057. {
  1058. u16 cmd;
  1059. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1060. if (cmd & PCI_COMMAND_INVALIDATE) {
  1061. cmd &= ~PCI_COMMAND_INVALIDATE;
  1062. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1063. }
  1064. }
  1065. #endif /* ! PCI_DISABLE_MWI */
  1066. /**
  1067. * pci_intx - enables/disables PCI INTx for device dev
  1068. * @pdev: the PCI device to operate on
  1069. * @enable: boolean: whether to enable or disable PCI INTx
  1070. *
  1071. * Enables/disables PCI INTx for device dev
  1072. */
  1073. void
  1074. pci_intx(struct pci_dev *pdev, int enable)
  1075. {
  1076. u16 pci_command, new;
  1077. pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
  1078. if (enable) {
  1079. new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
  1080. } else {
  1081. new = pci_command | PCI_COMMAND_INTX_DISABLE;
  1082. }
  1083. if (new != pci_command) {
  1084. struct pci_devres *dr;
  1085. pci_write_config_word(pdev, PCI_COMMAND, new);
  1086. dr = find_pci_dr(pdev);
  1087. if (dr && !dr->restore_intx) {
  1088. dr->restore_intx = 1;
  1089. dr->orig_intx = !enable;
  1090. }
  1091. }
  1092. }
  1093. /**
  1094. * pci_msi_off - disables any msi or msix capabilities
  1095. * @pdev: the PCI device to operate on
  1096. *
  1097. * If you want to use msi see pci_enable_msi and friends.
  1098. * This is a lower level primitive that allows us to disable
  1099. * msi operation at the device level.
  1100. */
  1101. void pci_msi_off(struct pci_dev *dev)
  1102. {
  1103. int pos;
  1104. u16 control;
  1105. pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
  1106. if (pos) {
  1107. pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
  1108. control &= ~PCI_MSI_FLAGS_ENABLE;
  1109. pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
  1110. }
  1111. pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  1112. if (pos) {
  1113. pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
  1114. control &= ~PCI_MSIX_FLAGS_ENABLE;
  1115. pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
  1116. }
  1117. }
  1118. #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
  1119. /*
  1120. * These can be overridden by arch-specific implementations
  1121. */
  1122. int
  1123. pci_set_dma_mask(struct pci_dev *dev, u64 mask)
  1124. {
  1125. if (!pci_dma_supported(dev, mask))
  1126. return -EIO;
  1127. dev->dma_mask = mask;
  1128. return 0;
  1129. }
  1130. int
  1131. pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
  1132. {
  1133. if (!pci_dma_supported(dev, mask))
  1134. return -EIO;
  1135. dev->dev.coherent_dma_mask = mask;
  1136. return 0;
  1137. }
  1138. #endif
  1139. /**
  1140. * pci_select_bars - Make BAR mask from the type of resource
  1141. * @dev: the PCI device for which BAR mask is made
  1142. * @flags: resource type mask to be selected
  1143. *
  1144. * This helper routine makes bar mask from the type of resource.
  1145. */
  1146. int pci_select_bars(struct pci_dev *dev, unsigned long flags)
  1147. {
  1148. int i, bars = 0;
  1149. for (i = 0; i < PCI_NUM_RESOURCES; i++)
  1150. if (pci_resource_flags(dev, i) & flags)
  1151. bars |= (1 << i);
  1152. return bars;
  1153. }
  1154. static int __devinit pci_init(void)
  1155. {
  1156. struct pci_dev *dev = NULL;
  1157. while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
  1158. pci_fixup_device(pci_fixup_final, dev);
  1159. }
  1160. return 0;
  1161. }
  1162. static int __devinit pci_setup(char *str)
  1163. {
  1164. while (str) {
  1165. char *k = strchr(str, ',');
  1166. if (k)
  1167. *k++ = 0;
  1168. if (*str && (str = pcibios_setup(str)) && *str) {
  1169. if (!strcmp(str, "nomsi")) {
  1170. pci_no_msi();
  1171. } else if (!strncmp(str, "cbiosize=", 9)) {
  1172. pci_cardbus_io_size = memparse(str + 9, &str);
  1173. } else if (!strncmp(str, "cbmemsize=", 10)) {
  1174. pci_cardbus_mem_size = memparse(str + 10, &str);
  1175. } else {
  1176. printk(KERN_ERR "PCI: Unknown option `%s'\n",
  1177. str);
  1178. }
  1179. }
  1180. str = k;
  1181. }
  1182. return 0;
  1183. }
  1184. early_param("pci", pci_setup);
  1185. device_initcall(pci_init);
  1186. EXPORT_SYMBOL_GPL(pci_restore_bars);
  1187. EXPORT_SYMBOL(pci_enable_device_bars);
  1188. EXPORT_SYMBOL(pci_enable_device);
  1189. EXPORT_SYMBOL(pcim_enable_device);
  1190. EXPORT_SYMBOL(pcim_pin_device);
  1191. EXPORT_SYMBOL(pci_disable_device);
  1192. EXPORT_SYMBOL(pci_find_capability);
  1193. EXPORT_SYMBOL(pci_bus_find_capability);
  1194. EXPORT_SYMBOL(pci_release_regions);
  1195. EXPORT_SYMBOL(pci_request_regions);
  1196. EXPORT_SYMBOL(pci_release_region);
  1197. EXPORT_SYMBOL(pci_request_region);
  1198. EXPORT_SYMBOL(pci_release_selected_regions);
  1199. EXPORT_SYMBOL(pci_request_selected_regions);
  1200. EXPORT_SYMBOL(pci_set_master);
  1201. EXPORT_SYMBOL(pci_set_mwi);
  1202. EXPORT_SYMBOL(pci_clear_mwi);
  1203. EXPORT_SYMBOL_GPL(pci_intx);
  1204. EXPORT_SYMBOL(pci_set_dma_mask);
  1205. EXPORT_SYMBOL(pci_set_consistent_dma_mask);
  1206. EXPORT_SYMBOL(pci_assign_resource);
  1207. EXPORT_SYMBOL(pci_find_parent_resource);
  1208. EXPORT_SYMBOL(pci_select_bars);
  1209. EXPORT_SYMBOL(pci_set_power_state);
  1210. EXPORT_SYMBOL(pci_save_state);
  1211. EXPORT_SYMBOL(pci_restore_state);
  1212. EXPORT_SYMBOL(pci_enable_wake);