parport_pc.c 92 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427
  1. /* Low-level parallel-port routines for 8255-based PC-style hardware.
  2. *
  3. * Authors: Phil Blundell <philb@gnu.org>
  4. * Tim Waugh <tim@cyberelk.demon.co.uk>
  5. * Jose Renau <renau@acm.org>
  6. * David Campbell
  7. * Andrea Arcangeli
  8. *
  9. * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
  10. *
  11. * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
  12. * DMA support - Bert De Jonghe <bert@sophis.be>
  13. * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
  14. * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
  15. * Various hacks, Fred Barnes, 04/2001
  16. * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
  17. */
  18. /* This driver should work with any hardware that is broadly compatible
  19. * with that in the IBM PC. This applies to the majority of integrated
  20. * I/O chipsets that are commonly available. The expected register
  21. * layout is:
  22. *
  23. * base+0 data
  24. * base+1 status
  25. * base+2 control
  26. *
  27. * In addition, there are some optional registers:
  28. *
  29. * base+3 EPP address
  30. * base+4 EPP data
  31. * base+0x400 ECP config A
  32. * base+0x401 ECP config B
  33. * base+0x402 ECP control
  34. *
  35. * All registers are 8 bits wide and read/write. If your hardware differs
  36. * only in register addresses (eg because your registers are on 32-bit
  37. * word boundaries) then you can alter the constants in parport_pc.h to
  38. * accommodate this.
  39. *
  40. * Note that the ECP registers may not start at offset 0x400 for PCI cards,
  41. * but rather will start at port->base_hi.
  42. */
  43. #include <linux/module.h>
  44. #include <linux/init.h>
  45. #include <linux/sched.h>
  46. #include <linux/delay.h>
  47. #include <linux/errno.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/ioport.h>
  50. #include <linux/kernel.h>
  51. #include <linux/slab.h>
  52. #include <linux/pci.h>
  53. #include <linux/pnp.h>
  54. #include <linux/sysctl.h>
  55. #include <asm/io.h>
  56. #include <asm/dma.h>
  57. #include <asm/uaccess.h>
  58. #include <linux/parport.h>
  59. #include <linux/parport_pc.h>
  60. #include <linux/via.h>
  61. #include <asm/parport.h>
  62. #define PARPORT_PC_MAX_PORTS PARPORT_MAX
  63. #ifdef CONFIG_ISA_DMA_API
  64. #define HAS_DMA
  65. #endif
  66. /* ECR modes */
  67. #define ECR_SPP 00
  68. #define ECR_PS2 01
  69. #define ECR_PPF 02
  70. #define ECR_ECP 03
  71. #define ECR_EPP 04
  72. #define ECR_VND 05
  73. #define ECR_TST 06
  74. #define ECR_CNF 07
  75. #define ECR_MODE_MASK 0xe0
  76. #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
  77. #undef DEBUG
  78. #ifdef DEBUG
  79. #define DPRINTK printk
  80. #else
  81. #define DPRINTK(stuff...)
  82. #endif
  83. #define NR_SUPERIOS 3
  84. static struct superio_struct { /* For Super-IO chips autodetection */
  85. int io;
  86. int irq;
  87. int dma;
  88. } superios[NR_SUPERIOS] = { {0,},};
  89. static int user_specified;
  90. #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
  91. (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
  92. static int verbose_probing;
  93. #endif
  94. static int pci_registered_parport;
  95. static int pnp_registered_parport;
  96. /* frob_control, but for ECR */
  97. static void frob_econtrol (struct parport *pb, unsigned char m,
  98. unsigned char v)
  99. {
  100. unsigned char ectr = 0;
  101. if (m != 0xff)
  102. ectr = inb (ECONTROL (pb));
  103. DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
  104. m, v, ectr, (ectr & ~m) ^ v);
  105. outb ((ectr & ~m) ^ v, ECONTROL (pb));
  106. }
  107. static __inline__ void frob_set_mode (struct parport *p, int mode)
  108. {
  109. frob_econtrol (p, ECR_MODE_MASK, mode << 5);
  110. }
  111. #ifdef CONFIG_PARPORT_PC_FIFO
  112. /* Safely change the mode bits in the ECR
  113. Returns:
  114. 0 : Success
  115. -EBUSY: Could not drain FIFO in some finite amount of time,
  116. mode not changed!
  117. */
  118. static int change_mode(struct parport *p, int m)
  119. {
  120. const struct parport_pc_private *priv = p->physport->private_data;
  121. unsigned char oecr;
  122. int mode;
  123. DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
  124. if (!priv->ecr) {
  125. printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
  126. return 0;
  127. }
  128. /* Bits <7:5> contain the mode. */
  129. oecr = inb (ECONTROL (p));
  130. mode = (oecr >> 5) & 0x7;
  131. if (mode == m) return 0;
  132. if (mode >= 2 && !(priv->ctr & 0x20)) {
  133. /* This mode resets the FIFO, so we may
  134. * have to wait for it to drain first. */
  135. unsigned long expire = jiffies + p->physport->cad->timeout;
  136. int counter;
  137. switch (mode) {
  138. case ECR_PPF: /* Parallel Port FIFO mode */
  139. case ECR_ECP: /* ECP Parallel Port mode */
  140. /* Busy wait for 200us */
  141. for (counter = 0; counter < 40; counter++) {
  142. if (inb (ECONTROL (p)) & 0x01)
  143. break;
  144. if (signal_pending (current)) break;
  145. udelay (5);
  146. }
  147. /* Poll slowly. */
  148. while (!(inb (ECONTROL (p)) & 0x01)) {
  149. if (time_after_eq (jiffies, expire))
  150. /* The FIFO is stuck. */
  151. return -EBUSY;
  152. schedule_timeout_interruptible(msecs_to_jiffies(10));
  153. if (signal_pending (current))
  154. break;
  155. }
  156. }
  157. }
  158. if (mode >= 2 && m >= 2) {
  159. /* We have to go through mode 001 */
  160. oecr &= ~(7 << 5);
  161. oecr |= ECR_PS2 << 5;
  162. ECR_WRITE (p, oecr);
  163. }
  164. /* Set the mode. */
  165. oecr &= ~(7 << 5);
  166. oecr |= m << 5;
  167. ECR_WRITE (p, oecr);
  168. return 0;
  169. }
  170. #ifdef CONFIG_PARPORT_1284
  171. /* Find FIFO lossage; FIFO is reset */
  172. #if 0
  173. static int get_fifo_residue (struct parport *p)
  174. {
  175. int residue;
  176. int cnfga;
  177. const struct parport_pc_private *priv = p->physport->private_data;
  178. /* Adjust for the contents of the FIFO. */
  179. for (residue = priv->fifo_depth; ; residue--) {
  180. if (inb (ECONTROL (p)) & 0x2)
  181. /* Full up. */
  182. break;
  183. outb (0, FIFO (p));
  184. }
  185. printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
  186. residue);
  187. /* Reset the FIFO. */
  188. frob_set_mode (p, ECR_PS2);
  189. /* Now change to config mode and clean up. FIXME */
  190. frob_set_mode (p, ECR_CNF);
  191. cnfga = inb (CONFIGA (p));
  192. printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
  193. if (!(cnfga & (1<<2))) {
  194. printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
  195. residue++;
  196. }
  197. /* Don't care about partial PWords until support is added for
  198. * PWord != 1 byte. */
  199. /* Back to PS2 mode. */
  200. frob_set_mode (p, ECR_PS2);
  201. DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
  202. return residue;
  203. }
  204. #endif /* 0 */
  205. #endif /* IEEE 1284 support */
  206. #endif /* FIFO support */
  207. /*
  208. * Clear TIMEOUT BIT in EPP MODE
  209. *
  210. * This is also used in SPP detection.
  211. */
  212. static int clear_epp_timeout(struct parport *pb)
  213. {
  214. unsigned char r;
  215. if (!(parport_pc_read_status(pb) & 0x01))
  216. return 1;
  217. /* To clear timeout some chips require double read */
  218. parport_pc_read_status(pb);
  219. r = parport_pc_read_status(pb);
  220. outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
  221. outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
  222. r = parport_pc_read_status(pb);
  223. return !(r & 0x01);
  224. }
  225. /*
  226. * Access functions.
  227. *
  228. * Most of these aren't static because they may be used by the
  229. * parport_xxx_yyy macros. extern __inline__ versions of several
  230. * of these are in parport_pc.h.
  231. */
  232. static irqreturn_t parport_pc_interrupt(int irq, void *dev_id)
  233. {
  234. parport_generic_irq(irq, (struct parport *) dev_id);
  235. /* FIXME! Was it really ours? */
  236. return IRQ_HANDLED;
  237. }
  238. static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
  239. {
  240. s->u.pc.ctr = 0xc;
  241. if (dev->irq_func &&
  242. dev->port->irq != PARPORT_IRQ_NONE)
  243. /* Set ackIntEn */
  244. s->u.pc.ctr |= 0x10;
  245. s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
  246. * D.Gruszka VScom */
  247. }
  248. static void parport_pc_save_state(struct parport *p, struct parport_state *s)
  249. {
  250. const struct parport_pc_private *priv = p->physport->private_data;
  251. s->u.pc.ctr = priv->ctr;
  252. if (priv->ecr)
  253. s->u.pc.ecr = inb (ECONTROL (p));
  254. }
  255. static void parport_pc_restore_state(struct parport *p, struct parport_state *s)
  256. {
  257. struct parport_pc_private *priv = p->physport->private_data;
  258. register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
  259. outb (c, CONTROL (p));
  260. priv->ctr = c;
  261. if (priv->ecr)
  262. ECR_WRITE (p, s->u.pc.ecr);
  263. }
  264. #ifdef CONFIG_PARPORT_1284
  265. static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
  266. size_t length, int flags)
  267. {
  268. size_t got = 0;
  269. if (flags & PARPORT_W91284PIC) {
  270. unsigned char status;
  271. size_t left = length;
  272. /* use knowledge about data lines..:
  273. * nFault is 0 if there is at least 1 byte in the Warp's FIFO
  274. * pError is 1 if there are 16 bytes in the Warp's FIFO
  275. */
  276. status = inb (STATUS (port));
  277. while (!(status & 0x08) && (got < length)) {
  278. if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
  279. /* can grab 16 bytes from warp fifo */
  280. if (!((long)buf & 0x03)) {
  281. insl (EPPDATA (port), buf, 4);
  282. } else {
  283. insb (EPPDATA (port), buf, 16);
  284. }
  285. buf += 16;
  286. got += 16;
  287. left -= 16;
  288. } else {
  289. /* grab single byte from the warp fifo */
  290. *((char *)buf) = inb (EPPDATA (port));
  291. buf++;
  292. got++;
  293. left--;
  294. }
  295. status = inb (STATUS (port));
  296. if (status & 0x01) {
  297. /* EPP timeout should never occur... */
  298. printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
  299. "w91284pic (should not have done)\n", port->name);
  300. clear_epp_timeout (port);
  301. }
  302. }
  303. return got;
  304. }
  305. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  306. if (!(((long)buf | length) & 0x03)) {
  307. insl (EPPDATA (port), buf, (length >> 2));
  308. } else {
  309. insb (EPPDATA (port), buf, length);
  310. }
  311. if (inb (STATUS (port)) & 0x01) {
  312. clear_epp_timeout (port);
  313. return -EIO;
  314. }
  315. return length;
  316. }
  317. for (; got < length; got++) {
  318. *((char*)buf) = inb (EPPDATA(port));
  319. buf++;
  320. if (inb (STATUS (port)) & 0x01) {
  321. /* EPP timeout */
  322. clear_epp_timeout (port);
  323. break;
  324. }
  325. }
  326. return got;
  327. }
  328. static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
  329. size_t length, int flags)
  330. {
  331. size_t written = 0;
  332. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  333. if (!(((long)buf | length) & 0x03)) {
  334. outsl (EPPDATA (port), buf, (length >> 2));
  335. } else {
  336. outsb (EPPDATA (port), buf, length);
  337. }
  338. if (inb (STATUS (port)) & 0x01) {
  339. clear_epp_timeout (port);
  340. return -EIO;
  341. }
  342. return length;
  343. }
  344. for (; written < length; written++) {
  345. outb (*((char*)buf), EPPDATA(port));
  346. buf++;
  347. if (inb (STATUS(port)) & 0x01) {
  348. clear_epp_timeout (port);
  349. break;
  350. }
  351. }
  352. return written;
  353. }
  354. static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
  355. size_t length, int flags)
  356. {
  357. size_t got = 0;
  358. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  359. insb (EPPADDR (port), buf, length);
  360. if (inb (STATUS (port)) & 0x01) {
  361. clear_epp_timeout (port);
  362. return -EIO;
  363. }
  364. return length;
  365. }
  366. for (; got < length; got++) {
  367. *((char*)buf) = inb (EPPADDR (port));
  368. buf++;
  369. if (inb (STATUS (port)) & 0x01) {
  370. clear_epp_timeout (port);
  371. break;
  372. }
  373. }
  374. return got;
  375. }
  376. static size_t parport_pc_epp_write_addr (struct parport *port,
  377. const void *buf, size_t length,
  378. int flags)
  379. {
  380. size_t written = 0;
  381. if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
  382. outsb (EPPADDR (port), buf, length);
  383. if (inb (STATUS (port)) & 0x01) {
  384. clear_epp_timeout (port);
  385. return -EIO;
  386. }
  387. return length;
  388. }
  389. for (; written < length; written++) {
  390. outb (*((char*)buf), EPPADDR (port));
  391. buf++;
  392. if (inb (STATUS (port)) & 0x01) {
  393. clear_epp_timeout (port);
  394. break;
  395. }
  396. }
  397. return written;
  398. }
  399. static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
  400. size_t length, int flags)
  401. {
  402. size_t got;
  403. frob_set_mode (port, ECR_EPP);
  404. parport_pc_data_reverse (port);
  405. parport_pc_write_control (port, 0x4);
  406. got = parport_pc_epp_read_data (port, buf, length, flags);
  407. frob_set_mode (port, ECR_PS2);
  408. return got;
  409. }
  410. static size_t parport_pc_ecpepp_write_data (struct parport *port,
  411. const void *buf, size_t length,
  412. int flags)
  413. {
  414. size_t written;
  415. frob_set_mode (port, ECR_EPP);
  416. parport_pc_write_control (port, 0x4);
  417. parport_pc_data_forward (port);
  418. written = parport_pc_epp_write_data (port, buf, length, flags);
  419. frob_set_mode (port, ECR_PS2);
  420. return written;
  421. }
  422. static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
  423. size_t length, int flags)
  424. {
  425. size_t got;
  426. frob_set_mode (port, ECR_EPP);
  427. parport_pc_data_reverse (port);
  428. parport_pc_write_control (port, 0x4);
  429. got = parport_pc_epp_read_addr (port, buf, length, flags);
  430. frob_set_mode (port, ECR_PS2);
  431. return got;
  432. }
  433. static size_t parport_pc_ecpepp_write_addr (struct parport *port,
  434. const void *buf, size_t length,
  435. int flags)
  436. {
  437. size_t written;
  438. frob_set_mode (port, ECR_EPP);
  439. parport_pc_write_control (port, 0x4);
  440. parport_pc_data_forward (port);
  441. written = parport_pc_epp_write_addr (port, buf, length, flags);
  442. frob_set_mode (port, ECR_PS2);
  443. return written;
  444. }
  445. #endif /* IEEE 1284 support */
  446. #ifdef CONFIG_PARPORT_PC_FIFO
  447. static size_t parport_pc_fifo_write_block_pio (struct parport *port,
  448. const void *buf, size_t length)
  449. {
  450. int ret = 0;
  451. const unsigned char *bufp = buf;
  452. size_t left = length;
  453. unsigned long expire = jiffies + port->physport->cad->timeout;
  454. const int fifo = FIFO (port);
  455. int poll_for = 8; /* 80 usecs */
  456. const struct parport_pc_private *priv = port->physport->private_data;
  457. const int fifo_depth = priv->fifo_depth;
  458. port = port->physport;
  459. /* We don't want to be interrupted every character. */
  460. parport_pc_disable_irq (port);
  461. /* set nErrIntrEn and serviceIntr */
  462. frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
  463. /* Forward mode. */
  464. parport_pc_data_forward (port); /* Must be in PS2 mode */
  465. while (left) {
  466. unsigned char byte;
  467. unsigned char ecrval = inb (ECONTROL (port));
  468. int i = 0;
  469. if (need_resched() && time_before (jiffies, expire))
  470. /* Can't yield the port. */
  471. schedule ();
  472. /* Anyone else waiting for the port? */
  473. if (port->waithead) {
  474. printk (KERN_DEBUG "Somebody wants the port\n");
  475. break;
  476. }
  477. if (ecrval & 0x02) {
  478. /* FIFO is full. Wait for interrupt. */
  479. /* Clear serviceIntr */
  480. ECR_WRITE (port, ecrval & ~(1<<2));
  481. false_alarm:
  482. ret = parport_wait_event (port, HZ);
  483. if (ret < 0) break;
  484. ret = 0;
  485. if (!time_before (jiffies, expire)) {
  486. /* Timed out. */
  487. printk (KERN_DEBUG "FIFO write timed out\n");
  488. break;
  489. }
  490. ecrval = inb (ECONTROL (port));
  491. if (!(ecrval & (1<<2))) {
  492. if (need_resched() &&
  493. time_before (jiffies, expire))
  494. schedule ();
  495. goto false_alarm;
  496. }
  497. continue;
  498. }
  499. /* Can't fail now. */
  500. expire = jiffies + port->cad->timeout;
  501. poll:
  502. if (signal_pending (current))
  503. break;
  504. if (ecrval & 0x01) {
  505. /* FIFO is empty. Blast it full. */
  506. const int n = left < fifo_depth ? left : fifo_depth;
  507. outsb (fifo, bufp, n);
  508. bufp += n;
  509. left -= n;
  510. /* Adjust the poll time. */
  511. if (i < (poll_for - 2)) poll_for--;
  512. continue;
  513. } else if (i++ < poll_for) {
  514. udelay (10);
  515. ecrval = inb (ECONTROL (port));
  516. goto poll;
  517. }
  518. /* Half-full (call me an optimist) */
  519. byte = *bufp++;
  520. outb (byte, fifo);
  521. left--;
  522. }
  523. dump_parport_state ("leave fifo_write_block_pio", port);
  524. return length - left;
  525. }
  526. #ifdef HAS_DMA
  527. static size_t parport_pc_fifo_write_block_dma (struct parport *port,
  528. const void *buf, size_t length)
  529. {
  530. int ret = 0;
  531. unsigned long dmaflag;
  532. size_t left = length;
  533. const struct parport_pc_private *priv = port->physport->private_data;
  534. dma_addr_t dma_addr, dma_handle;
  535. size_t maxlen = 0x10000; /* max 64k per DMA transfer */
  536. unsigned long start = (unsigned long) buf;
  537. unsigned long end = (unsigned long) buf + length - 1;
  538. dump_parport_state ("enter fifo_write_block_dma", port);
  539. if (end < MAX_DMA_ADDRESS) {
  540. /* If it would cross a 64k boundary, cap it at the end. */
  541. if ((start ^ end) & ~0xffffUL)
  542. maxlen = 0x10000 - (start & 0xffff);
  543. dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
  544. PCI_DMA_TODEVICE);
  545. } else {
  546. /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
  547. maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
  548. dma_addr = priv->dma_handle;
  549. dma_handle = 0;
  550. }
  551. port = port->physport;
  552. /* We don't want to be interrupted every character. */
  553. parport_pc_disable_irq (port);
  554. /* set nErrIntrEn and serviceIntr */
  555. frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
  556. /* Forward mode. */
  557. parport_pc_data_forward (port); /* Must be in PS2 mode */
  558. while (left) {
  559. unsigned long expire = jiffies + port->physport->cad->timeout;
  560. size_t count = left;
  561. if (count > maxlen)
  562. count = maxlen;
  563. if (!dma_handle) /* bounce buffer ! */
  564. memcpy(priv->dma_buf, buf, count);
  565. dmaflag = claim_dma_lock();
  566. disable_dma(port->dma);
  567. clear_dma_ff(port->dma);
  568. set_dma_mode(port->dma, DMA_MODE_WRITE);
  569. set_dma_addr(port->dma, dma_addr);
  570. set_dma_count(port->dma, count);
  571. /* Set DMA mode */
  572. frob_econtrol (port, 1<<3, 1<<3);
  573. /* Clear serviceIntr */
  574. frob_econtrol (port, 1<<2, 0);
  575. enable_dma(port->dma);
  576. release_dma_lock(dmaflag);
  577. /* assume DMA will be successful */
  578. left -= count;
  579. buf += count;
  580. if (dma_handle) dma_addr += count;
  581. /* Wait for interrupt. */
  582. false_alarm:
  583. ret = parport_wait_event (port, HZ);
  584. if (ret < 0) break;
  585. ret = 0;
  586. if (!time_before (jiffies, expire)) {
  587. /* Timed out. */
  588. printk (KERN_DEBUG "DMA write timed out\n");
  589. break;
  590. }
  591. /* Is serviceIntr set? */
  592. if (!(inb (ECONTROL (port)) & (1<<2))) {
  593. cond_resched();
  594. goto false_alarm;
  595. }
  596. dmaflag = claim_dma_lock();
  597. disable_dma(port->dma);
  598. clear_dma_ff(port->dma);
  599. count = get_dma_residue(port->dma);
  600. release_dma_lock(dmaflag);
  601. cond_resched(); /* Can't yield the port. */
  602. /* Anyone else waiting for the port? */
  603. if (port->waithead) {
  604. printk (KERN_DEBUG "Somebody wants the port\n");
  605. break;
  606. }
  607. /* update for possible DMA residue ! */
  608. buf -= count;
  609. left += count;
  610. if (dma_handle) dma_addr -= count;
  611. }
  612. /* Maybe got here through break, so adjust for DMA residue! */
  613. dmaflag = claim_dma_lock();
  614. disable_dma(port->dma);
  615. clear_dma_ff(port->dma);
  616. left += get_dma_residue(port->dma);
  617. release_dma_lock(dmaflag);
  618. /* Turn off DMA mode */
  619. frob_econtrol (port, 1<<3, 0);
  620. if (dma_handle)
  621. pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
  622. dump_parport_state ("leave fifo_write_block_dma", port);
  623. return length - left;
  624. }
  625. #endif
  626. static inline size_t parport_pc_fifo_write_block(struct parport *port,
  627. const void *buf, size_t length)
  628. {
  629. #ifdef HAS_DMA
  630. if (port->dma != PARPORT_DMA_NONE)
  631. return parport_pc_fifo_write_block_dma (port, buf, length);
  632. #endif
  633. return parport_pc_fifo_write_block_pio (port, buf, length);
  634. }
  635. /* Parallel Port FIFO mode (ECP chipsets) */
  636. static size_t parport_pc_compat_write_block_pio (struct parport *port,
  637. const void *buf, size_t length,
  638. int flags)
  639. {
  640. size_t written;
  641. int r;
  642. unsigned long expire;
  643. const struct parport_pc_private *priv = port->physport->private_data;
  644. /* Special case: a timeout of zero means we cannot call schedule().
  645. * Also if O_NONBLOCK is set then use the default implementation. */
  646. if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
  647. return parport_ieee1284_write_compat (port, buf,
  648. length, flags);
  649. /* Set up parallel port FIFO mode.*/
  650. parport_pc_data_forward (port); /* Must be in PS2 mode */
  651. parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
  652. r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
  653. if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
  654. port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
  655. /* Write the data to the FIFO. */
  656. written = parport_pc_fifo_write_block(port, buf, length);
  657. /* Finish up. */
  658. /* For some hardware we don't want to touch the mode until
  659. * the FIFO is empty, so allow 4 seconds for each position
  660. * in the fifo.
  661. */
  662. expire = jiffies + (priv->fifo_depth * HZ * 4);
  663. do {
  664. /* Wait for the FIFO to empty */
  665. r = change_mode (port, ECR_PS2);
  666. if (r != -EBUSY) {
  667. break;
  668. }
  669. } while (time_before (jiffies, expire));
  670. if (r == -EBUSY) {
  671. printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
  672. /* Prevent further data transfer. */
  673. frob_set_mode (port, ECR_TST);
  674. /* Adjust for the contents of the FIFO. */
  675. for (written -= priv->fifo_depth; ; written++) {
  676. if (inb (ECONTROL (port)) & 0x2) {
  677. /* Full up. */
  678. break;
  679. }
  680. outb (0, FIFO (port));
  681. }
  682. /* Reset the FIFO and return to PS2 mode. */
  683. frob_set_mode (port, ECR_PS2);
  684. }
  685. r = parport_wait_peripheral (port,
  686. PARPORT_STATUS_BUSY,
  687. PARPORT_STATUS_BUSY);
  688. if (r)
  689. printk (KERN_DEBUG
  690. "%s: BUSY timeout (%d) in compat_write_block_pio\n",
  691. port->name, r);
  692. port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
  693. return written;
  694. }
  695. /* ECP */
  696. #ifdef CONFIG_PARPORT_1284
  697. static size_t parport_pc_ecp_write_block_pio (struct parport *port,
  698. const void *buf, size_t length,
  699. int flags)
  700. {
  701. size_t written;
  702. int r;
  703. unsigned long expire;
  704. const struct parport_pc_private *priv = port->physport->private_data;
  705. /* Special case: a timeout of zero means we cannot call schedule().
  706. * Also if O_NONBLOCK is set then use the default implementation. */
  707. if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
  708. return parport_ieee1284_ecp_write_data (port, buf,
  709. length, flags);
  710. /* Switch to forward mode if necessary. */
  711. if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
  712. /* Event 47: Set nInit high. */
  713. parport_frob_control (port,
  714. PARPORT_CONTROL_INIT
  715. | PARPORT_CONTROL_AUTOFD,
  716. PARPORT_CONTROL_INIT
  717. | PARPORT_CONTROL_AUTOFD);
  718. /* Event 49: PError goes high. */
  719. r = parport_wait_peripheral (port,
  720. PARPORT_STATUS_PAPEROUT,
  721. PARPORT_STATUS_PAPEROUT);
  722. if (r) {
  723. printk (KERN_DEBUG "%s: PError timeout (%d) "
  724. "in ecp_write_block_pio\n", port->name, r);
  725. }
  726. }
  727. /* Set up ECP parallel port mode.*/
  728. parport_pc_data_forward (port); /* Must be in PS2 mode */
  729. parport_pc_frob_control (port,
  730. PARPORT_CONTROL_STROBE |
  731. PARPORT_CONTROL_AUTOFD,
  732. 0);
  733. r = change_mode (port, ECR_ECP); /* ECP FIFO */
  734. if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
  735. port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
  736. /* Write the data to the FIFO. */
  737. written = parport_pc_fifo_write_block(port, buf, length);
  738. /* Finish up. */
  739. /* For some hardware we don't want to touch the mode until
  740. * the FIFO is empty, so allow 4 seconds for each position
  741. * in the fifo.
  742. */
  743. expire = jiffies + (priv->fifo_depth * (HZ * 4));
  744. do {
  745. /* Wait for the FIFO to empty */
  746. r = change_mode (port, ECR_PS2);
  747. if (r != -EBUSY) {
  748. break;
  749. }
  750. } while (time_before (jiffies, expire));
  751. if (r == -EBUSY) {
  752. printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
  753. /* Prevent further data transfer. */
  754. frob_set_mode (port, ECR_TST);
  755. /* Adjust for the contents of the FIFO. */
  756. for (written -= priv->fifo_depth; ; written++) {
  757. if (inb (ECONTROL (port)) & 0x2) {
  758. /* Full up. */
  759. break;
  760. }
  761. outb (0, FIFO (port));
  762. }
  763. /* Reset the FIFO and return to PS2 mode. */
  764. frob_set_mode (port, ECR_PS2);
  765. /* Host transfer recovery. */
  766. parport_pc_data_reverse (port); /* Must be in PS2 mode */
  767. udelay (5);
  768. parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
  769. r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
  770. if (r)
  771. printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
  772. "in ecp_write_block_pio\n", port->name, r);
  773. parport_frob_control (port,
  774. PARPORT_CONTROL_INIT,
  775. PARPORT_CONTROL_INIT);
  776. r = parport_wait_peripheral (port,
  777. PARPORT_STATUS_PAPEROUT,
  778. PARPORT_STATUS_PAPEROUT);
  779. if (r)
  780. printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
  781. "in ecp_write_block_pio\n", port->name, r);
  782. }
  783. r = parport_wait_peripheral (port,
  784. PARPORT_STATUS_BUSY,
  785. PARPORT_STATUS_BUSY);
  786. if(r)
  787. printk (KERN_DEBUG
  788. "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
  789. port->name, r);
  790. port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
  791. return written;
  792. }
  793. #if 0
  794. static size_t parport_pc_ecp_read_block_pio (struct parport *port,
  795. void *buf, size_t length,
  796. int flags)
  797. {
  798. size_t left = length;
  799. size_t fifofull;
  800. int r;
  801. const int fifo = FIFO(port);
  802. const struct parport_pc_private *priv = port->physport->private_data;
  803. const int fifo_depth = priv->fifo_depth;
  804. char *bufp = buf;
  805. port = port->physport;
  806. DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
  807. dump_parport_state ("enter fcn", port);
  808. /* Special case: a timeout of zero means we cannot call schedule().
  809. * Also if O_NONBLOCK is set then use the default implementation. */
  810. if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
  811. return parport_ieee1284_ecp_read_data (port, buf,
  812. length, flags);
  813. if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
  814. /* If the peripheral is allowed to send RLE compressed
  815. * data, it is possible for a byte to expand to 128
  816. * bytes in the FIFO. */
  817. fifofull = 128;
  818. } else {
  819. fifofull = fifo_depth;
  820. }
  821. /* If the caller wants less than a full FIFO's worth of data,
  822. * go through software emulation. Otherwise we may have to throw
  823. * away data. */
  824. if (length < fifofull)
  825. return parport_ieee1284_ecp_read_data (port, buf,
  826. length, flags);
  827. if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
  828. /* change to reverse-idle phase (must be in forward-idle) */
  829. /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
  830. parport_frob_control (port,
  831. PARPORT_CONTROL_AUTOFD
  832. | PARPORT_CONTROL_STROBE,
  833. PARPORT_CONTROL_AUTOFD);
  834. parport_pc_data_reverse (port); /* Must be in PS2 mode */
  835. udelay (5);
  836. /* Event 39: Set nInit low to initiate bus reversal */
  837. parport_frob_control (port,
  838. PARPORT_CONTROL_INIT,
  839. 0);
  840. /* Event 40: Wait for nAckReverse (PError) to go low */
  841. r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
  842. if (r) {
  843. printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
  844. "in ecp_read_block_pio\n", port->name, r);
  845. return 0;
  846. }
  847. }
  848. /* Set up ECP FIFO mode.*/
  849. /* parport_pc_frob_control (port,
  850. PARPORT_CONTROL_STROBE |
  851. PARPORT_CONTROL_AUTOFD,
  852. PARPORT_CONTROL_AUTOFD); */
  853. r = change_mode (port, ECR_ECP); /* ECP FIFO */
  854. if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
  855. port->ieee1284.phase = IEEE1284_PH_REV_DATA;
  856. /* the first byte must be collected manually */
  857. dump_parport_state ("pre 43", port);
  858. /* Event 43: Wait for nAck to go low */
  859. r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
  860. if (r) {
  861. /* timed out while reading -- no data */
  862. printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
  863. goto out_no_data;
  864. }
  865. /* read byte */
  866. *bufp++ = inb (DATA (port));
  867. left--;
  868. dump_parport_state ("43-44", port);
  869. /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
  870. parport_pc_frob_control (port,
  871. PARPORT_CONTROL_AUTOFD,
  872. 0);
  873. dump_parport_state ("pre 45", port);
  874. /* Event 45: Wait for nAck to go high */
  875. /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
  876. dump_parport_state ("post 45", port);
  877. r = 0;
  878. if (r) {
  879. /* timed out while waiting for peripheral to respond to ack */
  880. printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
  881. /* keep hold of the byte we've got already */
  882. goto out_no_data;
  883. }
  884. /* Event 46: nAutoFd (HostAck) goes low to accept more data */
  885. parport_pc_frob_control (port,
  886. PARPORT_CONTROL_AUTOFD,
  887. PARPORT_CONTROL_AUTOFD);
  888. dump_parport_state ("rev idle", port);
  889. /* Do the transfer. */
  890. while (left > fifofull) {
  891. int ret;
  892. unsigned long expire = jiffies + port->cad->timeout;
  893. unsigned char ecrval = inb (ECONTROL (port));
  894. if (need_resched() && time_before (jiffies, expire))
  895. /* Can't yield the port. */
  896. schedule ();
  897. /* At this point, the FIFO may already be full. In
  898. * that case ECP is already holding back the
  899. * peripheral (assuming proper design) with a delayed
  900. * handshake. Work fast to avoid a peripheral
  901. * timeout. */
  902. if (ecrval & 0x01) {
  903. /* FIFO is empty. Wait for interrupt. */
  904. dump_parport_state ("FIFO empty", port);
  905. /* Anyone else waiting for the port? */
  906. if (port->waithead) {
  907. printk (KERN_DEBUG "Somebody wants the port\n");
  908. break;
  909. }
  910. /* Clear serviceIntr */
  911. ECR_WRITE (port, ecrval & ~(1<<2));
  912. false_alarm:
  913. dump_parport_state ("waiting", port);
  914. ret = parport_wait_event (port, HZ);
  915. DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
  916. if (ret < 0)
  917. break;
  918. ret = 0;
  919. if (!time_before (jiffies, expire)) {
  920. /* Timed out. */
  921. dump_parport_state ("timeout", port);
  922. printk (KERN_DEBUG "PIO read timed out\n");
  923. break;
  924. }
  925. ecrval = inb (ECONTROL (port));
  926. if (!(ecrval & (1<<2))) {
  927. if (need_resched() &&
  928. time_before (jiffies, expire)) {
  929. schedule ();
  930. }
  931. goto false_alarm;
  932. }
  933. /* Depending on how the FIFO threshold was
  934. * set, how long interrupt service took, and
  935. * how fast the peripheral is, we might be
  936. * lucky and have a just filled FIFO. */
  937. continue;
  938. }
  939. if (ecrval & 0x02) {
  940. /* FIFO is full. */
  941. dump_parport_state ("FIFO full", port);
  942. insb (fifo, bufp, fifo_depth);
  943. bufp += fifo_depth;
  944. left -= fifo_depth;
  945. continue;
  946. }
  947. DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
  948. /* FIFO not filled. We will cycle this loop for a while
  949. * and either the peripheral will fill it faster,
  950. * tripping a fast empty with insb, or we empty it. */
  951. *bufp++ = inb (fifo);
  952. left--;
  953. }
  954. /* scoop up anything left in the FIFO */
  955. while (left && !(inb (ECONTROL (port) & 0x01))) {
  956. *bufp++ = inb (fifo);
  957. left--;
  958. }
  959. port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
  960. dump_parport_state ("rev idle2", port);
  961. out_no_data:
  962. /* Go to forward idle mode to shut the peripheral up (event 47). */
  963. parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
  964. /* event 49: PError goes high */
  965. r = parport_wait_peripheral (port,
  966. PARPORT_STATUS_PAPEROUT,
  967. PARPORT_STATUS_PAPEROUT);
  968. if (r) {
  969. printk (KERN_DEBUG
  970. "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
  971. port->name, r);
  972. }
  973. port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
  974. /* Finish up. */
  975. {
  976. int lost = get_fifo_residue (port);
  977. if (lost)
  978. /* Shouldn't happen with compliant peripherals. */
  979. printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
  980. port->name, lost);
  981. }
  982. dump_parport_state ("fwd idle", port);
  983. return length - left;
  984. }
  985. #endif /* 0 */
  986. #endif /* IEEE 1284 support */
  987. #endif /* Allowed to use FIFO/DMA */
  988. /*
  989. * ******************************************
  990. * INITIALISATION AND MODULE STUFF BELOW HERE
  991. * ******************************************
  992. */
  993. /* GCC is not inlining extern inline function later overwriten to non-inline,
  994. so we use outlined_ variants here. */
  995. static const struct parport_operations parport_pc_ops =
  996. {
  997. .write_data = parport_pc_write_data,
  998. .read_data = parport_pc_read_data,
  999. .write_control = parport_pc_write_control,
  1000. .read_control = parport_pc_read_control,
  1001. .frob_control = parport_pc_frob_control,
  1002. .read_status = parport_pc_read_status,
  1003. .enable_irq = parport_pc_enable_irq,
  1004. .disable_irq = parport_pc_disable_irq,
  1005. .data_forward = parport_pc_data_forward,
  1006. .data_reverse = parport_pc_data_reverse,
  1007. .init_state = parport_pc_init_state,
  1008. .save_state = parport_pc_save_state,
  1009. .restore_state = parport_pc_restore_state,
  1010. .epp_write_data = parport_ieee1284_epp_write_data,
  1011. .epp_read_data = parport_ieee1284_epp_read_data,
  1012. .epp_write_addr = parport_ieee1284_epp_write_addr,
  1013. .epp_read_addr = parport_ieee1284_epp_read_addr,
  1014. .ecp_write_data = parport_ieee1284_ecp_write_data,
  1015. .ecp_read_data = parport_ieee1284_ecp_read_data,
  1016. .ecp_write_addr = parport_ieee1284_ecp_write_addr,
  1017. .compat_write_data = parport_ieee1284_write_compat,
  1018. .nibble_read_data = parport_ieee1284_read_nibble,
  1019. .byte_read_data = parport_ieee1284_read_byte,
  1020. .owner = THIS_MODULE,
  1021. };
  1022. #ifdef CONFIG_PARPORT_PC_SUPERIO
  1023. /* Super-IO chipset detection, Winbond, SMSC */
  1024. static void __devinit show_parconfig_smsc37c669(int io, int key)
  1025. {
  1026. int cr1,cr4,cra,cr23,cr26,cr27,i=0;
  1027. static const char *const modes[]={
  1028. "SPP and Bidirectional (PS/2)",
  1029. "EPP and SPP",
  1030. "ECP",
  1031. "ECP and EPP" };
  1032. outb(key,io);
  1033. outb(key,io);
  1034. outb(1,io);
  1035. cr1=inb(io+1);
  1036. outb(4,io);
  1037. cr4=inb(io+1);
  1038. outb(0x0a,io);
  1039. cra=inb(io+1);
  1040. outb(0x23,io);
  1041. cr23=inb(io+1);
  1042. outb(0x26,io);
  1043. cr26=inb(io+1);
  1044. outb(0x27,io);
  1045. cr27=inb(io+1);
  1046. outb(0xaa,io);
  1047. if (verbose_probing) {
  1048. printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
  1049. "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
  1050. cr1,cr4,cra,cr23,cr26,cr27);
  1051. /* The documentation calls DMA and IRQ-Lines by letters, so
  1052. the board maker can/will wire them
  1053. appropriately/randomly... G=reserved H=IDE-irq, */
  1054. printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
  1055. "fifo threshold=%d\n", cr23*4,
  1056. (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
  1057. (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
  1058. printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
  1059. (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
  1060. printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
  1061. (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
  1062. (cr4 & 0x40) ? "1.7" : "1.9");
  1063. }
  1064. /* Heuristics ! BIOS setup for this mainboard device limits
  1065. the choices to standard settings, i.e. io-address and IRQ
  1066. are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
  1067. DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
  1068. if(cr23*4 >=0x100) { /* if active */
  1069. while((superios[i].io!= 0) && (i<NR_SUPERIOS))
  1070. i++;
  1071. if(i==NR_SUPERIOS)
  1072. printk(KERN_INFO "Super-IO: too many chips!\n");
  1073. else {
  1074. int d;
  1075. switch (cr23*4) {
  1076. case 0x3bc:
  1077. superios[i].io = 0x3bc;
  1078. superios[i].irq = 7;
  1079. break;
  1080. case 0x378:
  1081. superios[i].io = 0x378;
  1082. superios[i].irq = 7;
  1083. break;
  1084. case 0x278:
  1085. superios[i].io = 0x278;
  1086. superios[i].irq = 5;
  1087. }
  1088. d=(cr26 &0x0f);
  1089. if((d==1) || (d==3))
  1090. superios[i].dma= d;
  1091. else
  1092. superios[i].dma= PARPORT_DMA_NONE;
  1093. }
  1094. }
  1095. }
  1096. static void __devinit show_parconfig_winbond(int io, int key)
  1097. {
  1098. int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
  1099. static const char *const modes[] = {
  1100. "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
  1101. "EPP-1.9 and SPP",
  1102. "ECP",
  1103. "ECP and EPP-1.9",
  1104. "Standard (SPP)",
  1105. "EPP-1.7 and SPP", /* 5 */
  1106. "undefined!",
  1107. "ECP and EPP-1.7" };
  1108. static char *const irqtypes[] = {
  1109. "pulsed low, high-Z",
  1110. "follows nACK" };
  1111. /* The registers are called compatible-PnP because the
  1112. register layout is modelled after ISA-PnP, the access
  1113. method is just another ... */
  1114. outb(key,io);
  1115. outb(key,io);
  1116. outb(0x07,io); /* Register 7: Select Logical Device */
  1117. outb(0x01,io+1); /* LD1 is Parallel Port */
  1118. outb(0x30,io);
  1119. cr30=inb(io+1);
  1120. outb(0x60,io);
  1121. cr60=inb(io+1);
  1122. outb(0x61,io);
  1123. cr61=inb(io+1);
  1124. outb(0x70,io);
  1125. cr70=inb(io+1);
  1126. outb(0x74,io);
  1127. cr74=inb(io+1);
  1128. outb(0xf0,io);
  1129. crf0=inb(io+1);
  1130. outb(0xaa,io);
  1131. if (verbose_probing) {
  1132. printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
  1133. "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
  1134. printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
  1135. (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
  1136. if ((cr74 & 0x07) > 3)
  1137. printk("dma=none\n");
  1138. else
  1139. printk("dma=%d\n",cr74 & 0x07);
  1140. printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
  1141. irqtypes[crf0>>7], (crf0>>3)&0x0f);
  1142. printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
  1143. }
  1144. if(cr30 & 0x01) { /* the settings can be interrogated later ... */
  1145. while((superios[i].io!= 0) && (i<NR_SUPERIOS))
  1146. i++;
  1147. if(i==NR_SUPERIOS)
  1148. printk(KERN_INFO "Super-IO: too many chips!\n");
  1149. else {
  1150. superios[i].io = (cr60<<8)|cr61;
  1151. superios[i].irq = cr70&0x0f;
  1152. superios[i].dma = (((cr74 & 0x07) > 3) ?
  1153. PARPORT_DMA_NONE : (cr74 & 0x07));
  1154. }
  1155. }
  1156. }
  1157. static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
  1158. {
  1159. const char *type = "unknown";
  1160. int id,progif=2;
  1161. if (devid == devrev)
  1162. /* simple heuristics, we happened to read some
  1163. non-winbond register */
  1164. return;
  1165. id=(devid<<8) | devrev;
  1166. /* Values are from public data sheets pdf files, I can just
  1167. confirm 83977TF is correct :-) */
  1168. if (id == 0x9771) type="83977F/AF";
  1169. else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
  1170. else if (id == 0x9774) type="83977ATF";
  1171. else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
  1172. else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
  1173. else if ((id & ~0x0f) == 0x5210) type="83627";
  1174. else if ((id & ~0x0f) == 0x6010) type="83697HF";
  1175. else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
  1176. else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
  1177. else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
  1178. else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
  1179. else progif=0;
  1180. if (verbose_probing)
  1181. printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
  1182. "devid=%02x devrev=%02x oldid=%02x type=%s\n",
  1183. efer, key, devid, devrev, oldid, type);
  1184. if (progif == 2)
  1185. show_parconfig_winbond(efer,key);
  1186. }
  1187. static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
  1188. {
  1189. const char *type = "unknown";
  1190. void (*func)(int io, int key);
  1191. int id;
  1192. if (devid == devrev)
  1193. /* simple heuristics, we happened to read some
  1194. non-smsc register */
  1195. return;
  1196. func=NULL;
  1197. id=(devid<<8) | devrev;
  1198. if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
  1199. else if (id==0x6582) type="37c665IR";
  1200. else if (devid==0x65) type="37c665GT";
  1201. else if (devid==0x66) type="37c666GT";
  1202. if (verbose_probing)
  1203. printk(KERN_INFO "SMSC chip at EFER=0x%x "
  1204. "key=0x%02x devid=%02x devrev=%02x type=%s\n",
  1205. efer, key, devid, devrev, type);
  1206. if (func)
  1207. func(efer,key);
  1208. }
  1209. static void __devinit winbond_check(int io, int key)
  1210. {
  1211. int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
  1212. if (!request_region(io, 3, __FUNCTION__))
  1213. return;
  1214. /* First probe without key */
  1215. outb(0x20,io);
  1216. x_devid=inb(io+1);
  1217. outb(0x21,io);
  1218. x_devrev=inb(io+1);
  1219. outb(0x09,io);
  1220. x_oldid=inb(io+1);
  1221. outb(key,io);
  1222. outb(key,io); /* Write Magic Sequence to EFER, extended
  1223. funtion enable register */
  1224. outb(0x20,io); /* Write EFIR, extended function index register */
  1225. devid=inb(io+1); /* Read EFDR, extended function data register */
  1226. outb(0x21,io);
  1227. devrev=inb(io+1);
  1228. outb(0x09,io);
  1229. oldid=inb(io+1);
  1230. outb(0xaa,io); /* Magic Seal */
  1231. if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
  1232. goto out; /* protection against false positives */
  1233. decode_winbond(io,key,devid,devrev,oldid);
  1234. out:
  1235. release_region(io, 3);
  1236. }
  1237. static void __devinit winbond_check2(int io,int key)
  1238. {
  1239. int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
  1240. if (!request_region(io, 3, __FUNCTION__))
  1241. return;
  1242. /* First probe without the key */
  1243. outb(0x20,io+2);
  1244. x_devid=inb(io+2);
  1245. outb(0x21,io+1);
  1246. x_devrev=inb(io+2);
  1247. outb(0x09,io+1);
  1248. x_oldid=inb(io+2);
  1249. outb(key,io); /* Write Magic Byte to EFER, extended
  1250. funtion enable register */
  1251. outb(0x20,io+2); /* Write EFIR, extended function index register */
  1252. devid=inb(io+2); /* Read EFDR, extended function data register */
  1253. outb(0x21,io+1);
  1254. devrev=inb(io+2);
  1255. outb(0x09,io+1);
  1256. oldid=inb(io+2);
  1257. outb(0xaa,io); /* Magic Seal */
  1258. if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
  1259. goto out; /* protection against false positives */
  1260. decode_winbond(io,key,devid,devrev,oldid);
  1261. out:
  1262. release_region(io, 3);
  1263. }
  1264. static void __devinit smsc_check(int io, int key)
  1265. {
  1266. int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
  1267. if (!request_region(io, 3, __FUNCTION__))
  1268. return;
  1269. /* First probe without the key */
  1270. outb(0x0d,io);
  1271. x_oldid=inb(io+1);
  1272. outb(0x0e,io);
  1273. x_oldrev=inb(io+1);
  1274. outb(0x20,io);
  1275. x_id=inb(io+1);
  1276. outb(0x21,io);
  1277. x_rev=inb(io+1);
  1278. outb(key,io);
  1279. outb(key,io); /* Write Magic Sequence to EFER, extended
  1280. funtion enable register */
  1281. outb(0x0d,io); /* Write EFIR, extended function index register */
  1282. oldid=inb(io+1); /* Read EFDR, extended function data register */
  1283. outb(0x0e,io);
  1284. oldrev=inb(io+1);
  1285. outb(0x20,io);
  1286. id=inb(io+1);
  1287. outb(0x21,io);
  1288. rev=inb(io+1);
  1289. outb(0xaa,io); /* Magic Seal */
  1290. if ((x_id == id) && (x_oldrev == oldrev) &&
  1291. (x_oldid == oldid) && (x_rev == rev))
  1292. goto out; /* protection against false positives */
  1293. decode_smsc(io,key,oldid,oldrev);
  1294. out:
  1295. release_region(io, 3);
  1296. }
  1297. static void __devinit detect_and_report_winbond (void)
  1298. {
  1299. if (verbose_probing)
  1300. printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
  1301. winbond_check(0x3f0,0x87);
  1302. winbond_check(0x370,0x87);
  1303. winbond_check(0x2e ,0x87);
  1304. winbond_check(0x4e ,0x87);
  1305. winbond_check(0x3f0,0x86);
  1306. winbond_check2(0x250,0x88);
  1307. winbond_check2(0x250,0x89);
  1308. }
  1309. static void __devinit detect_and_report_smsc (void)
  1310. {
  1311. if (verbose_probing)
  1312. printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
  1313. smsc_check(0x3f0,0x55);
  1314. smsc_check(0x370,0x55);
  1315. smsc_check(0x3f0,0x44);
  1316. smsc_check(0x370,0x44);
  1317. }
  1318. #endif /* CONFIG_PARPORT_PC_SUPERIO */
  1319. static int get_superio_dma (struct parport *p)
  1320. {
  1321. int i=0;
  1322. while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
  1323. i++;
  1324. if (i!=NR_SUPERIOS)
  1325. return superios[i].dma;
  1326. return PARPORT_DMA_NONE;
  1327. }
  1328. static int get_superio_irq (struct parport *p)
  1329. {
  1330. int i=0;
  1331. while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
  1332. i++;
  1333. if (i!=NR_SUPERIOS)
  1334. return superios[i].irq;
  1335. return PARPORT_IRQ_NONE;
  1336. }
  1337. /* --- Mode detection ------------------------------------- */
  1338. /*
  1339. * Checks for port existence, all ports support SPP MODE
  1340. * Returns:
  1341. * 0 : No parallel port at this address
  1342. * PARPORT_MODE_PCSPP : SPP port detected
  1343. * (if the user specified an ioport himself,
  1344. * this shall always be the case!)
  1345. *
  1346. */
  1347. static int parport_SPP_supported(struct parport *pb)
  1348. {
  1349. unsigned char r, w;
  1350. /*
  1351. * first clear an eventually pending EPP timeout
  1352. * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
  1353. * that does not even respond to SPP cycles if an EPP
  1354. * timeout is pending
  1355. */
  1356. clear_epp_timeout(pb);
  1357. /* Do a simple read-write test to make sure the port exists. */
  1358. w = 0xc;
  1359. outb (w, CONTROL (pb));
  1360. /* Is there a control register that we can read from? Some
  1361. * ports don't allow reads, so read_control just returns a
  1362. * software copy. Some ports _do_ allow reads, so bypass the
  1363. * software copy here. In addition, some bits aren't
  1364. * writable. */
  1365. r = inb (CONTROL (pb));
  1366. if ((r & 0xf) == w) {
  1367. w = 0xe;
  1368. outb (w, CONTROL (pb));
  1369. r = inb (CONTROL (pb));
  1370. outb (0xc, CONTROL (pb));
  1371. if ((r & 0xf) == w)
  1372. return PARPORT_MODE_PCSPP;
  1373. }
  1374. if (user_specified)
  1375. /* That didn't work, but the user thinks there's a
  1376. * port here. */
  1377. printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
  1378. "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
  1379. /* Try the data register. The data lines aren't tri-stated at
  1380. * this stage, so we expect back what we wrote. */
  1381. w = 0xaa;
  1382. parport_pc_write_data (pb, w);
  1383. r = parport_pc_read_data (pb);
  1384. if (r == w) {
  1385. w = 0x55;
  1386. parport_pc_write_data (pb, w);
  1387. r = parport_pc_read_data (pb);
  1388. if (r == w)
  1389. return PARPORT_MODE_PCSPP;
  1390. }
  1391. if (user_specified) {
  1392. /* Didn't work, but the user is convinced this is the
  1393. * place. */
  1394. printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
  1395. "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
  1396. printk (KERN_INFO "parport 0x%lx: You gave this address, "
  1397. "but there is probably no parallel port there!\n",
  1398. pb->base);
  1399. }
  1400. /* It's possible that we can't read the control register or
  1401. * the data register. In that case just believe the user. */
  1402. if (user_specified)
  1403. return PARPORT_MODE_PCSPP;
  1404. return 0;
  1405. }
  1406. /* Check for ECR
  1407. *
  1408. * Old style XT ports alias io ports every 0x400, hence accessing ECR
  1409. * on these cards actually accesses the CTR.
  1410. *
  1411. * Modern cards don't do this but reading from ECR will return 0xff
  1412. * regardless of what is written here if the card does NOT support
  1413. * ECP.
  1414. *
  1415. * We first check to see if ECR is the same as CTR. If not, the low
  1416. * two bits of ECR aren't writable, so we check by writing ECR and
  1417. * reading it back to see if it's what we expect.
  1418. */
  1419. static int parport_ECR_present(struct parport *pb)
  1420. {
  1421. struct parport_pc_private *priv = pb->private_data;
  1422. unsigned char r = 0xc;
  1423. outb (r, CONTROL (pb));
  1424. if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
  1425. outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
  1426. r = inb (CONTROL (pb));
  1427. if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
  1428. goto no_reg; /* Sure that no ECR register exists */
  1429. }
  1430. if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
  1431. goto no_reg;
  1432. ECR_WRITE (pb, 0x34);
  1433. if (inb (ECONTROL (pb)) != 0x35)
  1434. goto no_reg;
  1435. priv->ecr = 1;
  1436. outb (0xc, CONTROL (pb));
  1437. /* Go to mode 000 */
  1438. frob_set_mode (pb, ECR_SPP);
  1439. return 1;
  1440. no_reg:
  1441. outb (0xc, CONTROL (pb));
  1442. return 0;
  1443. }
  1444. #ifdef CONFIG_PARPORT_1284
  1445. /* Detect PS/2 support.
  1446. *
  1447. * Bit 5 (0x20) sets the PS/2 data direction; setting this high
  1448. * allows us to read data from the data lines. In theory we would get back
  1449. * 0xff but any peripheral attached to the port may drag some or all of the
  1450. * lines down to zero. So if we get back anything that isn't the contents
  1451. * of the data register we deem PS/2 support to be present.
  1452. *
  1453. * Some SPP ports have "half PS/2" ability - you can't turn off the line
  1454. * drivers, but an external peripheral with sufficiently beefy drivers of
  1455. * its own can overpower them and assert its own levels onto the bus, from
  1456. * where they can then be read back as normal. Ports with this property
  1457. * and the right type of device attached are likely to fail the SPP test,
  1458. * (as they will appear to have stuck bits) and so the fact that they might
  1459. * be misdetected here is rather academic.
  1460. */
  1461. static int parport_PS2_supported(struct parport *pb)
  1462. {
  1463. int ok = 0;
  1464. clear_epp_timeout(pb);
  1465. /* try to tri-state the buffer */
  1466. parport_pc_data_reverse (pb);
  1467. parport_pc_write_data(pb, 0x55);
  1468. if (parport_pc_read_data(pb) != 0x55) ok++;
  1469. parport_pc_write_data(pb, 0xaa);
  1470. if (parport_pc_read_data(pb) != 0xaa) ok++;
  1471. /* cancel input mode */
  1472. parport_pc_data_forward (pb);
  1473. if (ok) {
  1474. pb->modes |= PARPORT_MODE_TRISTATE;
  1475. } else {
  1476. struct parport_pc_private *priv = pb->private_data;
  1477. priv->ctr_writable &= ~0x20;
  1478. }
  1479. return ok;
  1480. }
  1481. #ifdef CONFIG_PARPORT_PC_FIFO
  1482. static int __devinit parport_ECP_supported(struct parport *pb)
  1483. {
  1484. int i;
  1485. int config, configb;
  1486. int pword;
  1487. struct parport_pc_private *priv = pb->private_data;
  1488. /* Translate ECP intrLine to ISA irq value */
  1489. static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
  1490. /* If there is no ECR, we have no hope of supporting ECP. */
  1491. if (!priv->ecr)
  1492. return 0;
  1493. /* Find out FIFO depth */
  1494. ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
  1495. ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
  1496. for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
  1497. outb (0xaa, FIFO (pb));
  1498. /*
  1499. * Using LGS chipset it uses ECR register, but
  1500. * it doesn't support ECP or FIFO MODE
  1501. */
  1502. if (i == 1024) {
  1503. ECR_WRITE (pb, ECR_SPP << 5);
  1504. return 0;
  1505. }
  1506. priv->fifo_depth = i;
  1507. if (verbose_probing)
  1508. printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
  1509. /* Find out writeIntrThreshold */
  1510. frob_econtrol (pb, 1<<2, 1<<2);
  1511. frob_econtrol (pb, 1<<2, 0);
  1512. for (i = 1; i <= priv->fifo_depth; i++) {
  1513. inb (FIFO (pb));
  1514. udelay (50);
  1515. if (inb (ECONTROL (pb)) & (1<<2))
  1516. break;
  1517. }
  1518. if (i <= priv->fifo_depth) {
  1519. if (verbose_probing)
  1520. printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
  1521. pb->base, i);
  1522. } else
  1523. /* Number of bytes we know we can write if we get an
  1524. interrupt. */
  1525. i = 0;
  1526. priv->writeIntrThreshold = i;
  1527. /* Find out readIntrThreshold */
  1528. frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
  1529. parport_pc_data_reverse (pb); /* Must be in PS2 mode */
  1530. frob_set_mode (pb, ECR_TST); /* Test FIFO */
  1531. frob_econtrol (pb, 1<<2, 1<<2);
  1532. frob_econtrol (pb, 1<<2, 0);
  1533. for (i = 1; i <= priv->fifo_depth; i++) {
  1534. outb (0xaa, FIFO (pb));
  1535. if (inb (ECONTROL (pb)) & (1<<2))
  1536. break;
  1537. }
  1538. if (i <= priv->fifo_depth) {
  1539. if (verbose_probing)
  1540. printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
  1541. pb->base, i);
  1542. } else
  1543. /* Number of bytes we can read if we get an interrupt. */
  1544. i = 0;
  1545. priv->readIntrThreshold = i;
  1546. ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
  1547. ECR_WRITE (pb, 0xf4); /* Configuration mode */
  1548. config = inb (CONFIGA (pb));
  1549. pword = (config >> 4) & 0x7;
  1550. switch (pword) {
  1551. case 0:
  1552. pword = 2;
  1553. printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
  1554. pb->base);
  1555. break;
  1556. case 2:
  1557. pword = 4;
  1558. printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
  1559. pb->base);
  1560. break;
  1561. default:
  1562. printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
  1563. pb->base);
  1564. /* Assume 1 */
  1565. case 1:
  1566. pword = 1;
  1567. }
  1568. priv->pword = pword;
  1569. if (verbose_probing) {
  1570. printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
  1571. printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
  1572. config & 0x80 ? "Level" : "Pulses");
  1573. configb = inb (CONFIGB (pb));
  1574. printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
  1575. pb->base, config, configb);
  1576. printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
  1577. if ((configb >>3) & 0x07)
  1578. printk("%d",intrline[(configb >>3) & 0x07]);
  1579. else
  1580. printk("<none or set by other means>");
  1581. printk (" dma=");
  1582. if( (configb & 0x03 ) == 0x00)
  1583. printk("<none or set by other means>\n");
  1584. else
  1585. printk("%d\n",configb & 0x07);
  1586. }
  1587. /* Go back to mode 000 */
  1588. frob_set_mode (pb, ECR_SPP);
  1589. return 1;
  1590. }
  1591. #endif
  1592. static int parport_ECPPS2_supported(struct parport *pb)
  1593. {
  1594. const struct parport_pc_private *priv = pb->private_data;
  1595. int result;
  1596. unsigned char oecr;
  1597. if (!priv->ecr)
  1598. return 0;
  1599. oecr = inb (ECONTROL (pb));
  1600. ECR_WRITE (pb, ECR_PS2 << 5);
  1601. result = parport_PS2_supported(pb);
  1602. ECR_WRITE (pb, oecr);
  1603. return result;
  1604. }
  1605. /* EPP mode detection */
  1606. static int parport_EPP_supported(struct parport *pb)
  1607. {
  1608. const struct parport_pc_private *priv = pb->private_data;
  1609. /*
  1610. * Theory:
  1611. * Bit 0 of STR is the EPP timeout bit, this bit is 0
  1612. * when EPP is possible and is set high when an EPP timeout
  1613. * occurs (EPP uses the HALT line to stop the CPU while it does
  1614. * the byte transfer, an EPP timeout occurs if the attached
  1615. * device fails to respond after 10 micro seconds).
  1616. *
  1617. * This bit is cleared by either reading it (National Semi)
  1618. * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
  1619. * This bit is always high in non EPP modes.
  1620. */
  1621. /* If EPP timeout bit clear then EPP available */
  1622. if (!clear_epp_timeout(pb)) {
  1623. return 0; /* No way to clear timeout */
  1624. }
  1625. /* Check for Intel bug. */
  1626. if (priv->ecr) {
  1627. unsigned char i;
  1628. for (i = 0x00; i < 0x80; i += 0x20) {
  1629. ECR_WRITE (pb, i);
  1630. if (clear_epp_timeout (pb)) {
  1631. /* Phony EPP in ECP. */
  1632. return 0;
  1633. }
  1634. }
  1635. }
  1636. pb->modes |= PARPORT_MODE_EPP;
  1637. /* Set up access functions to use EPP hardware. */
  1638. pb->ops->epp_read_data = parport_pc_epp_read_data;
  1639. pb->ops->epp_write_data = parport_pc_epp_write_data;
  1640. pb->ops->epp_read_addr = parport_pc_epp_read_addr;
  1641. pb->ops->epp_write_addr = parport_pc_epp_write_addr;
  1642. return 1;
  1643. }
  1644. static int parport_ECPEPP_supported(struct parport *pb)
  1645. {
  1646. struct parport_pc_private *priv = pb->private_data;
  1647. int result;
  1648. unsigned char oecr;
  1649. if (!priv->ecr) {
  1650. return 0;
  1651. }
  1652. oecr = inb (ECONTROL (pb));
  1653. /* Search for SMC style EPP+ECP mode */
  1654. ECR_WRITE (pb, 0x80);
  1655. outb (0x04, CONTROL (pb));
  1656. result = parport_EPP_supported(pb);
  1657. ECR_WRITE (pb, oecr);
  1658. if (result) {
  1659. /* Set up access functions to use ECP+EPP hardware. */
  1660. pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
  1661. pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
  1662. pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
  1663. pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
  1664. }
  1665. return result;
  1666. }
  1667. #else /* No IEEE 1284 support */
  1668. /* Don't bother probing for modes we know we won't use. */
  1669. static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
  1670. #ifdef CONFIG_PARPORT_PC_FIFO
  1671. static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
  1672. #endif
  1673. static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
  1674. static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
  1675. static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
  1676. #endif /* No IEEE 1284 support */
  1677. /* --- IRQ detection -------------------------------------- */
  1678. /* Only if supports ECP mode */
  1679. static int programmable_irq_support(struct parport *pb)
  1680. {
  1681. int irq, intrLine;
  1682. unsigned char oecr = inb (ECONTROL (pb));
  1683. static const int lookup[8] = {
  1684. PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
  1685. };
  1686. ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
  1687. intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
  1688. irq = lookup[intrLine];
  1689. ECR_WRITE (pb, oecr);
  1690. return irq;
  1691. }
  1692. static int irq_probe_ECP(struct parport *pb)
  1693. {
  1694. int i;
  1695. unsigned long irqs;
  1696. irqs = probe_irq_on();
  1697. ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
  1698. ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
  1699. ECR_WRITE (pb, ECR_TST << 5);
  1700. /* If Full FIFO sure that writeIntrThreshold is generated */
  1701. for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
  1702. outb (0xaa, FIFO (pb));
  1703. pb->irq = probe_irq_off(irqs);
  1704. ECR_WRITE (pb, ECR_SPP << 5);
  1705. if (pb->irq <= 0)
  1706. pb->irq = PARPORT_IRQ_NONE;
  1707. return pb->irq;
  1708. }
  1709. /*
  1710. * This detection seems that only works in National Semiconductors
  1711. * This doesn't work in SMC, LGS, and Winbond
  1712. */
  1713. static int irq_probe_EPP(struct parport *pb)
  1714. {
  1715. #ifndef ADVANCED_DETECT
  1716. return PARPORT_IRQ_NONE;
  1717. #else
  1718. int irqs;
  1719. unsigned char oecr;
  1720. if (pb->modes & PARPORT_MODE_PCECR)
  1721. oecr = inb (ECONTROL (pb));
  1722. irqs = probe_irq_on();
  1723. if (pb->modes & PARPORT_MODE_PCECR)
  1724. frob_econtrol (pb, 0x10, 0x10);
  1725. clear_epp_timeout(pb);
  1726. parport_pc_frob_control (pb, 0x20, 0x20);
  1727. parport_pc_frob_control (pb, 0x10, 0x10);
  1728. clear_epp_timeout(pb);
  1729. /* Device isn't expecting an EPP read
  1730. * and generates an IRQ.
  1731. */
  1732. parport_pc_read_epp(pb);
  1733. udelay(20);
  1734. pb->irq = probe_irq_off (irqs);
  1735. if (pb->modes & PARPORT_MODE_PCECR)
  1736. ECR_WRITE (pb, oecr);
  1737. parport_pc_write_control(pb, 0xc);
  1738. if (pb->irq <= 0)
  1739. pb->irq = PARPORT_IRQ_NONE;
  1740. return pb->irq;
  1741. #endif /* Advanced detection */
  1742. }
  1743. static int irq_probe_SPP(struct parport *pb)
  1744. {
  1745. /* Don't even try to do this. */
  1746. return PARPORT_IRQ_NONE;
  1747. }
  1748. /* We will attempt to share interrupt requests since other devices
  1749. * such as sound cards and network cards seem to like using the
  1750. * printer IRQs.
  1751. *
  1752. * When ECP is available we can autoprobe for IRQs.
  1753. * NOTE: If we can autoprobe it, we can register the IRQ.
  1754. */
  1755. static int parport_irq_probe(struct parport *pb)
  1756. {
  1757. struct parport_pc_private *priv = pb->private_data;
  1758. if (priv->ecr) {
  1759. pb->irq = programmable_irq_support(pb);
  1760. if (pb->irq == PARPORT_IRQ_NONE)
  1761. pb->irq = irq_probe_ECP(pb);
  1762. }
  1763. if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
  1764. (pb->modes & PARPORT_MODE_EPP))
  1765. pb->irq = irq_probe_EPP(pb);
  1766. clear_epp_timeout(pb);
  1767. if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
  1768. pb->irq = irq_probe_EPP(pb);
  1769. clear_epp_timeout(pb);
  1770. if (pb->irq == PARPORT_IRQ_NONE)
  1771. pb->irq = irq_probe_SPP(pb);
  1772. if (pb->irq == PARPORT_IRQ_NONE)
  1773. pb->irq = get_superio_irq(pb);
  1774. return pb->irq;
  1775. }
  1776. /* --- DMA detection -------------------------------------- */
  1777. /* Only if chipset conforms to ECP ISA Interface Standard */
  1778. static int programmable_dma_support (struct parport *p)
  1779. {
  1780. unsigned char oecr = inb (ECONTROL (p));
  1781. int dma;
  1782. frob_set_mode (p, ECR_CNF);
  1783. dma = inb (CONFIGB(p)) & 0x07;
  1784. /* 000: Indicates jumpered 8-bit DMA if read-only.
  1785. 100: Indicates jumpered 16-bit DMA if read-only. */
  1786. if ((dma & 0x03) == 0)
  1787. dma = PARPORT_DMA_NONE;
  1788. ECR_WRITE (p, oecr);
  1789. return dma;
  1790. }
  1791. static int parport_dma_probe (struct parport *p)
  1792. {
  1793. const struct parport_pc_private *priv = p->private_data;
  1794. if (priv->ecr)
  1795. p->dma = programmable_dma_support(p); /* ask ECP chipset first */
  1796. if (p->dma == PARPORT_DMA_NONE) {
  1797. /* ask known Super-IO chips proper, although these
  1798. claim ECP compatible, some don't report their DMA
  1799. conforming to ECP standards */
  1800. p->dma = get_superio_dma(p);
  1801. }
  1802. return p->dma;
  1803. }
  1804. /* --- Initialisation code -------------------------------- */
  1805. static LIST_HEAD(ports_list);
  1806. static DEFINE_SPINLOCK(ports_lock);
  1807. struct parport *parport_pc_probe_port (unsigned long int base,
  1808. unsigned long int base_hi,
  1809. int irq, int dma,
  1810. struct pci_dev *dev)
  1811. {
  1812. struct parport_pc_private *priv;
  1813. struct parport_operations *ops;
  1814. struct parport *p;
  1815. int probedirq = PARPORT_IRQ_NONE;
  1816. struct resource *base_res;
  1817. struct resource *ECR_res = NULL;
  1818. struct resource *EPP_res = NULL;
  1819. ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL);
  1820. if (!ops)
  1821. goto out1;
  1822. priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
  1823. if (!priv)
  1824. goto out2;
  1825. /* a misnomer, actually - it's allocate and reserve parport number */
  1826. p = parport_register_port(base, irq, dma, ops);
  1827. if (!p)
  1828. goto out3;
  1829. base_res = request_region(base, 3, p->name);
  1830. if (!base_res)
  1831. goto out4;
  1832. memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
  1833. priv->ctr = 0xc;
  1834. priv->ctr_writable = ~0x10;
  1835. priv->ecr = 0;
  1836. priv->fifo_depth = 0;
  1837. priv->dma_buf = NULL;
  1838. priv->dma_handle = 0;
  1839. priv->dev = dev;
  1840. INIT_LIST_HEAD(&priv->list);
  1841. priv->port = p;
  1842. p->base_hi = base_hi;
  1843. p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
  1844. p->private_data = priv;
  1845. if (base_hi) {
  1846. ECR_res = request_region(base_hi, 3, p->name);
  1847. if (ECR_res)
  1848. parport_ECR_present(p);
  1849. }
  1850. if (base != 0x3bc) {
  1851. EPP_res = request_region(base+0x3, 5, p->name);
  1852. if (EPP_res)
  1853. if (!parport_EPP_supported(p))
  1854. parport_ECPEPP_supported(p);
  1855. }
  1856. if (!parport_SPP_supported (p))
  1857. /* No port. */
  1858. goto out5;
  1859. if (priv->ecr)
  1860. parport_ECPPS2_supported(p);
  1861. else
  1862. parport_PS2_supported(p);
  1863. p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
  1864. printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
  1865. if (p->base_hi && priv->ecr)
  1866. printk(" (0x%lx)", p->base_hi);
  1867. if (p->irq == PARPORT_IRQ_AUTO) {
  1868. p->irq = PARPORT_IRQ_NONE;
  1869. parport_irq_probe(p);
  1870. } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
  1871. p->irq = PARPORT_IRQ_NONE;
  1872. parport_irq_probe(p);
  1873. probedirq = p->irq;
  1874. p->irq = PARPORT_IRQ_NONE;
  1875. }
  1876. if (p->irq != PARPORT_IRQ_NONE) {
  1877. printk(", irq %d", p->irq);
  1878. priv->ctr_writable |= 0x10;
  1879. if (p->dma == PARPORT_DMA_AUTO) {
  1880. p->dma = PARPORT_DMA_NONE;
  1881. parport_dma_probe(p);
  1882. }
  1883. }
  1884. if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
  1885. is mandatory (see above) */
  1886. p->dma = PARPORT_DMA_NONE;
  1887. #ifdef CONFIG_PARPORT_PC_FIFO
  1888. if (parport_ECP_supported(p) &&
  1889. p->dma != PARPORT_DMA_NOFIFO &&
  1890. priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
  1891. p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
  1892. p->ops->compat_write_data = parport_pc_compat_write_block_pio;
  1893. #ifdef CONFIG_PARPORT_1284
  1894. p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
  1895. /* currently broken, but working on it.. (FB) */
  1896. /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
  1897. #endif /* IEEE 1284 support */
  1898. if (p->dma != PARPORT_DMA_NONE) {
  1899. printk(", dma %d", p->dma);
  1900. p->modes |= PARPORT_MODE_DMA;
  1901. }
  1902. else printk(", using FIFO");
  1903. }
  1904. else
  1905. /* We can't use the DMA channel after all. */
  1906. p->dma = PARPORT_DMA_NONE;
  1907. #endif /* Allowed to use FIFO/DMA */
  1908. printk(" [");
  1909. #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
  1910. {
  1911. int f = 0;
  1912. printmode(PCSPP);
  1913. printmode(TRISTATE);
  1914. printmode(COMPAT)
  1915. printmode(EPP);
  1916. printmode(ECP);
  1917. printmode(DMA);
  1918. }
  1919. #undef printmode
  1920. #ifndef CONFIG_PARPORT_1284
  1921. printk ("(,...)");
  1922. #endif /* CONFIG_PARPORT_1284 */
  1923. printk("]\n");
  1924. if (probedirq != PARPORT_IRQ_NONE)
  1925. printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
  1926. /* If No ECP release the ports grabbed above. */
  1927. if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
  1928. release_region(base_hi, 3);
  1929. ECR_res = NULL;
  1930. }
  1931. /* Likewise for EEP ports */
  1932. if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
  1933. release_region(base+3, 5);
  1934. EPP_res = NULL;
  1935. }
  1936. if (p->irq != PARPORT_IRQ_NONE) {
  1937. if (request_irq (p->irq, parport_pc_interrupt,
  1938. 0, p->name, p)) {
  1939. printk (KERN_WARNING "%s: irq %d in use, "
  1940. "resorting to polled operation\n",
  1941. p->name, p->irq);
  1942. p->irq = PARPORT_IRQ_NONE;
  1943. p->dma = PARPORT_DMA_NONE;
  1944. }
  1945. #ifdef CONFIG_PARPORT_PC_FIFO
  1946. #ifdef HAS_DMA
  1947. if (p->dma != PARPORT_DMA_NONE) {
  1948. if (request_dma (p->dma, p->name)) {
  1949. printk (KERN_WARNING "%s: dma %d in use, "
  1950. "resorting to PIO operation\n",
  1951. p->name, p->dma);
  1952. p->dma = PARPORT_DMA_NONE;
  1953. } else {
  1954. priv->dma_buf =
  1955. pci_alloc_consistent(priv->dev,
  1956. PAGE_SIZE,
  1957. &priv->dma_handle);
  1958. if (! priv->dma_buf) {
  1959. printk (KERN_WARNING "%s: "
  1960. "cannot get buffer for DMA, "
  1961. "resorting to PIO operation\n",
  1962. p->name);
  1963. free_dma(p->dma);
  1964. p->dma = PARPORT_DMA_NONE;
  1965. }
  1966. }
  1967. }
  1968. #endif
  1969. #endif
  1970. }
  1971. /* Done probing. Now put the port into a sensible start-up state. */
  1972. if (priv->ecr)
  1973. /*
  1974. * Put the ECP detected port in PS2 mode.
  1975. * Do this also for ports that have ECR but don't do ECP.
  1976. */
  1977. ECR_WRITE (p, 0x34);
  1978. parport_pc_write_data(p, 0);
  1979. parport_pc_data_forward (p);
  1980. /* Now that we've told the sharing engine about the port, and
  1981. found out its characteristics, let the high-level drivers
  1982. know about it. */
  1983. spin_lock(&ports_lock);
  1984. list_add(&priv->list, &ports_list);
  1985. spin_unlock(&ports_lock);
  1986. parport_announce_port (p);
  1987. return p;
  1988. out5:
  1989. if (ECR_res)
  1990. release_region(base_hi, 3);
  1991. if (EPP_res)
  1992. release_region(base+0x3, 5);
  1993. release_region(base, 3);
  1994. out4:
  1995. parport_put_port(p);
  1996. out3:
  1997. kfree (priv);
  1998. out2:
  1999. kfree (ops);
  2000. out1:
  2001. return NULL;
  2002. }
  2003. EXPORT_SYMBOL (parport_pc_probe_port);
  2004. void parport_pc_unregister_port (struct parport *p)
  2005. {
  2006. struct parport_pc_private *priv = p->private_data;
  2007. struct parport_operations *ops = p->ops;
  2008. parport_remove_port(p);
  2009. spin_lock(&ports_lock);
  2010. list_del_init(&priv->list);
  2011. spin_unlock(&ports_lock);
  2012. #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
  2013. if (p->dma != PARPORT_DMA_NONE)
  2014. free_dma(p->dma);
  2015. #endif
  2016. if (p->irq != PARPORT_IRQ_NONE)
  2017. free_irq(p->irq, p);
  2018. release_region(p->base, 3);
  2019. if (p->size > 3)
  2020. release_region(p->base + 3, p->size - 3);
  2021. if (p->modes & PARPORT_MODE_ECP)
  2022. release_region(p->base_hi, 3);
  2023. #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
  2024. if (priv->dma_buf)
  2025. pci_free_consistent(priv->dev, PAGE_SIZE,
  2026. priv->dma_buf,
  2027. priv->dma_handle);
  2028. #endif
  2029. kfree (p->private_data);
  2030. parport_put_port(p);
  2031. kfree (ops); /* hope no-one cached it */
  2032. }
  2033. EXPORT_SYMBOL (parport_pc_unregister_port);
  2034. #ifdef CONFIG_PCI
  2035. /* ITE support maintained by Rich Liu <richliu@poorman.org> */
  2036. static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
  2037. int autodma,
  2038. const struct parport_pc_via_data *via)
  2039. {
  2040. short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
  2041. struct resource *base_res;
  2042. u32 ite8872set;
  2043. u32 ite8872_lpt, ite8872_lpthi;
  2044. u8 ite8872_irq, type;
  2045. char *fake_name = "parport probe";
  2046. int irq;
  2047. int i;
  2048. DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
  2049. // make sure which one chip
  2050. for(i = 0; i < 5; i++) {
  2051. base_res = request_region(inta_addr[i], 0x8, fake_name);
  2052. if (base_res) {
  2053. int test;
  2054. pci_write_config_dword (pdev, 0x60,
  2055. 0xe7000000 | inta_addr[i]);
  2056. pci_write_config_dword (pdev, 0x78,
  2057. 0x00000000 | inta_addr[i]);
  2058. test = inb (inta_addr[i]);
  2059. if (test != 0xff) break;
  2060. release_region(inta_addr[i], 0x8);
  2061. }
  2062. }
  2063. if(i >= 5) {
  2064. printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
  2065. return 0;
  2066. }
  2067. type = inb (inta_addr[i] + 0x18);
  2068. type &= 0x0f;
  2069. switch (type) {
  2070. case 0x2:
  2071. printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
  2072. ite8872set = 0x64200000;
  2073. break;
  2074. case 0xa:
  2075. printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
  2076. ite8872set = 0x64200000;
  2077. break;
  2078. case 0xe:
  2079. printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
  2080. ite8872set = 0x64e00000;
  2081. break;
  2082. case 0x6:
  2083. printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
  2084. return 0;
  2085. case 0x8:
  2086. DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
  2087. return 0;
  2088. default:
  2089. printk (KERN_INFO "parport_pc: unknown ITE887x\n");
  2090. printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
  2091. "output to Rich.Liu@ite.com.tw\n");
  2092. return 0;
  2093. }
  2094. pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
  2095. pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
  2096. ite8872_lpt &= 0x0000ff00;
  2097. pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
  2098. ite8872_lpthi &= 0x0000ff00;
  2099. pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
  2100. pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
  2101. pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
  2102. // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
  2103. // SET Parallel IRQ
  2104. pci_write_config_dword (pdev, 0x9c,
  2105. ite8872set | (ite8872_irq * 0x11111));
  2106. DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
  2107. DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
  2108. ite8872_lpt);
  2109. DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
  2110. ite8872_lpthi);
  2111. /* Let the user (or defaults) steer us away from interrupts */
  2112. irq = ite8872_irq;
  2113. if (autoirq != PARPORT_IRQ_AUTO)
  2114. irq = PARPORT_IRQ_NONE;
  2115. /*
  2116. * Release the resource so that parport_pc_probe_port can get it.
  2117. */
  2118. release_resource(base_res);
  2119. if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
  2120. irq, PARPORT_DMA_NONE, NULL)) {
  2121. printk (KERN_INFO
  2122. "parport_pc: ITE 8872 parallel port: io=0x%X",
  2123. ite8872_lpt);
  2124. if (irq != PARPORT_IRQ_NONE)
  2125. printk (", irq=%d", irq);
  2126. printk ("\n");
  2127. return 1;
  2128. }
  2129. return 0;
  2130. }
  2131. /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
  2132. based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
  2133. static int __devinitdata parport_init_mode = 0;
  2134. /* Data for two known VIA chips */
  2135. static struct parport_pc_via_data via_686a_data __devinitdata = {
  2136. 0x51,
  2137. 0x50,
  2138. 0x85,
  2139. 0x02,
  2140. 0xE2,
  2141. 0xF0,
  2142. 0xE6
  2143. };
  2144. static struct parport_pc_via_data via_8231_data __devinitdata = {
  2145. 0x45,
  2146. 0x44,
  2147. 0x50,
  2148. 0x04,
  2149. 0xF2,
  2150. 0xFA,
  2151. 0xF6
  2152. };
  2153. static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq,
  2154. int autodma,
  2155. const struct parport_pc_via_data *via)
  2156. {
  2157. u8 tmp, tmp2, siofunc;
  2158. u8 ppcontrol = 0;
  2159. int dma, irq;
  2160. unsigned port1, port2;
  2161. unsigned have_epp = 0;
  2162. printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
  2163. switch(parport_init_mode)
  2164. {
  2165. case 1:
  2166. printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
  2167. siofunc = VIA_FUNCTION_PARPORT_SPP;
  2168. break;
  2169. case 2:
  2170. printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
  2171. siofunc = VIA_FUNCTION_PARPORT_SPP;
  2172. ppcontrol = VIA_PARPORT_BIDIR;
  2173. break;
  2174. case 3:
  2175. printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
  2176. siofunc = VIA_FUNCTION_PARPORT_EPP;
  2177. ppcontrol = VIA_PARPORT_BIDIR;
  2178. have_epp = 1;
  2179. break;
  2180. case 4:
  2181. printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
  2182. siofunc = VIA_FUNCTION_PARPORT_ECP;
  2183. ppcontrol = VIA_PARPORT_BIDIR;
  2184. break;
  2185. case 5:
  2186. printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
  2187. siofunc = VIA_FUNCTION_PARPORT_ECP;
  2188. ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
  2189. have_epp = 1;
  2190. break;
  2191. default:
  2192. printk(KERN_DEBUG "parport_pc: probing current configuration\n");
  2193. siofunc = VIA_FUNCTION_PROBE;
  2194. break;
  2195. }
  2196. /*
  2197. * unlock super i/o configuration
  2198. */
  2199. pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
  2200. tmp |= via->via_pci_superio_config_data;
  2201. pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
  2202. /* Bits 1-0: Parallel Port Mode / Enable */
  2203. outb(via->viacfg_function, VIA_CONFIG_INDEX);
  2204. tmp = inb (VIA_CONFIG_DATA);
  2205. /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
  2206. outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
  2207. tmp2 = inb (VIA_CONFIG_DATA);
  2208. if (siofunc == VIA_FUNCTION_PROBE)
  2209. {
  2210. siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
  2211. ppcontrol = tmp2;
  2212. }
  2213. else
  2214. {
  2215. tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
  2216. tmp |= siofunc;
  2217. outb(via->viacfg_function, VIA_CONFIG_INDEX);
  2218. outb(tmp, VIA_CONFIG_DATA);
  2219. tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
  2220. tmp2 |= ppcontrol;
  2221. outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
  2222. outb(tmp2, VIA_CONFIG_DATA);
  2223. }
  2224. /* Parallel Port I/O Base Address, bits 9-2 */
  2225. outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
  2226. port1 = inb(VIA_CONFIG_DATA) << 2;
  2227. printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1);
  2228. if ((port1 == 0x3BC) && have_epp)
  2229. {
  2230. outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
  2231. outb((0x378 >> 2), VIA_CONFIG_DATA);
  2232. printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
  2233. port1 = 0x378;
  2234. }
  2235. /*
  2236. * lock super i/o configuration
  2237. */
  2238. pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
  2239. tmp &= ~via->via_pci_superio_config_data;
  2240. pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
  2241. if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
  2242. printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
  2243. return 0;
  2244. }
  2245. /* Bits 7-4: PnP Routing for Parallel Port IRQ */
  2246. pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
  2247. irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
  2248. if (siofunc == VIA_FUNCTION_PARPORT_ECP)
  2249. {
  2250. /* Bits 3-2: PnP Routing for Parallel Port DMA */
  2251. pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
  2252. dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
  2253. }
  2254. else
  2255. /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
  2256. dma = PARPORT_DMA_NONE;
  2257. /* Let the user (or defaults) steer us away from interrupts and DMA */
  2258. if (autoirq == PARPORT_IRQ_NONE) {
  2259. irq = PARPORT_IRQ_NONE;
  2260. dma = PARPORT_DMA_NONE;
  2261. }
  2262. if (autodma == PARPORT_DMA_NONE)
  2263. dma = PARPORT_DMA_NONE;
  2264. switch (port1) {
  2265. case 0x3bc: port2 = 0x7bc; break;
  2266. case 0x378: port2 = 0x778; break;
  2267. case 0x278: port2 = 0x678; break;
  2268. default:
  2269. printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
  2270. port1);
  2271. return 0;
  2272. }
  2273. /* filter bogus IRQs */
  2274. switch (irq) {
  2275. case 0:
  2276. case 2:
  2277. case 8:
  2278. case 13:
  2279. irq = PARPORT_IRQ_NONE;
  2280. break;
  2281. default: /* do nothing */
  2282. break;
  2283. }
  2284. /* finally, do the probe with values obtained */
  2285. if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
  2286. printk (KERN_INFO
  2287. "parport_pc: VIA parallel port: io=0x%X", port1);
  2288. if (irq != PARPORT_IRQ_NONE)
  2289. printk (", irq=%d", irq);
  2290. if (dma != PARPORT_DMA_NONE)
  2291. printk (", dma=%d", dma);
  2292. printk ("\n");
  2293. return 1;
  2294. }
  2295. printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
  2296. port1, irq, dma);
  2297. return 0;
  2298. }
  2299. enum parport_pc_sio_types {
  2300. sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
  2301. sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
  2302. sio_ite_8872,
  2303. last_sio
  2304. };
  2305. /* each element directly indexed from enum list, above */
  2306. static struct parport_pc_superio {
  2307. int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
  2308. const struct parport_pc_via_data *via);
  2309. const struct parport_pc_via_data *via;
  2310. } parport_pc_superio_info[] __devinitdata = {
  2311. { sio_via_probe, &via_686a_data, },
  2312. { sio_via_probe, &via_8231_data, },
  2313. { sio_ite_8872_probe, NULL, },
  2314. };
  2315. enum parport_pc_pci_cards {
  2316. siig_1p_10x = last_sio,
  2317. siig_2p_10x,
  2318. siig_1p_20x,
  2319. siig_2p_20x,
  2320. lava_parallel,
  2321. lava_parallel_dual_a,
  2322. lava_parallel_dual_b,
  2323. boca_ioppar,
  2324. plx_9050,
  2325. timedia_4078a,
  2326. timedia_4079h,
  2327. timedia_4085h,
  2328. timedia_4088a,
  2329. timedia_4089a,
  2330. timedia_4095a,
  2331. timedia_4096a,
  2332. timedia_4078u,
  2333. timedia_4079a,
  2334. timedia_4085u,
  2335. timedia_4079r,
  2336. timedia_4079s,
  2337. timedia_4079d,
  2338. timedia_4079e,
  2339. timedia_4079f,
  2340. timedia_9079a,
  2341. timedia_9079b,
  2342. timedia_9079c,
  2343. timedia_4006a,
  2344. timedia_4014,
  2345. timedia_4008a,
  2346. timedia_4018,
  2347. timedia_9018a,
  2348. syba_2p_epp,
  2349. syba_1p_ecp,
  2350. titan_010l,
  2351. titan_1284p1,
  2352. titan_1284p2,
  2353. avlab_1p,
  2354. avlab_2p,
  2355. oxsemi_952,
  2356. oxsemi_954,
  2357. oxsemi_840,
  2358. aks_0100,
  2359. mobility_pp,
  2360. netmos_9705,
  2361. netmos_9715,
  2362. netmos_9755,
  2363. netmos_9805,
  2364. netmos_9815,
  2365. };
  2366. /* each element directly indexed from enum list, above
  2367. * (but offset by last_sio) */
  2368. static struct parport_pc_pci {
  2369. int numports;
  2370. struct { /* BAR (base address registers) numbers in the config
  2371. space header */
  2372. int lo;
  2373. int hi; /* -1 if not there, >6 for offset-method (max
  2374. BAR is 6) */
  2375. } addr[4];
  2376. /* If set, this is called immediately after pci_enable_device.
  2377. * If it returns non-zero, no probing will take place and the
  2378. * ports will not be used. */
  2379. int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
  2380. /* If set, this is called after probing for ports. If 'failed'
  2381. * is non-zero we couldn't use any of the ports. */
  2382. void (*postinit_hook) (struct pci_dev *pdev, int failed);
  2383. } cards[] = {
  2384. /* siig_1p_10x */ { 1, { { 2, 3 }, } },
  2385. /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
  2386. /* siig_1p_20x */ { 1, { { 0, 1 }, } },
  2387. /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2388. /* lava_parallel */ { 1, { { 0, -1 }, } },
  2389. /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
  2390. /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
  2391. /* boca_ioppar */ { 1, { { 0, -1 }, } },
  2392. /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
  2393. /* timedia_4078a */ { 1, { { 2, -1 }, } },
  2394. /* timedia_4079h */ { 1, { { 2, 3 }, } },
  2395. /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
  2396. /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  2397. /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  2398. /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  2399. /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  2400. /* timedia_4078u */ { 1, { { 2, -1 }, } },
  2401. /* timedia_4079a */ { 1, { { 2, 3 }, } },
  2402. /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
  2403. /* timedia_4079r */ { 1, { { 2, 3 }, } },
  2404. /* timedia_4079s */ { 1, { { 2, 3 }, } },
  2405. /* timedia_4079d */ { 1, { { 2, 3 }, } },
  2406. /* timedia_4079e */ { 1, { { 2, 3 }, } },
  2407. /* timedia_4079f */ { 1, { { 2, 3 }, } },
  2408. /* timedia_9079a */ { 1, { { 2, 3 }, } },
  2409. /* timedia_9079b */ { 1, { { 2, 3 }, } },
  2410. /* timedia_9079c */ { 1, { { 2, 3 }, } },
  2411. /* timedia_4006a */ { 1, { { 0, -1 }, } },
  2412. /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
  2413. /* timedia_4008a */ { 1, { { 0, 1 }, } },
  2414. /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2415. /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2416. /* SYBA uses fixed offsets in
  2417. a 1K io window */
  2418. /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
  2419. /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
  2420. /* titan_010l */ { 1, { { 3, -1 }, } },
  2421. /* titan_1284p1 */ { 1, { { 0, 1 }, } },
  2422. /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
  2423. /* avlab_1p */ { 1, { { 0, 1}, } },
  2424. /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
  2425. /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
  2426. * and 840 locks up if you write 1 to bit 2! */
  2427. /* oxsemi_952 */ { 1, { { 0, 1 }, } },
  2428. /* oxsemi_954 */ { 1, { { 0, -1 }, } },
  2429. /* oxsemi_840 */ { 1, { { 0, -1 }, } },
  2430. /* aks_0100 */ { 1, { { 0, -1 }, } },
  2431. /* mobility_pp */ { 1, { { 0, 1 }, } },
  2432. /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
  2433. /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
  2434. /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
  2435. /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */
  2436. /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
  2437. };
  2438. static const struct pci_device_id parport_pc_pci_tbl[] = {
  2439. /* Super-IO onboard chips */
  2440. { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
  2441. { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
  2442. { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
  2443. PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
  2444. /* PCI cards */
  2445. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
  2446. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
  2447. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
  2448. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
  2449. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
  2450. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
  2451. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
  2452. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
  2453. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
  2454. PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
  2455. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
  2456. PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
  2457. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
  2458. PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
  2459. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
  2460. PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
  2461. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  2462. PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
  2463. /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
  2464. { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
  2465. { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
  2466. { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
  2467. { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
  2468. { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
  2469. { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
  2470. { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
  2471. { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
  2472. { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
  2473. { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
  2474. { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
  2475. { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
  2476. { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
  2477. { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
  2478. { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
  2479. { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
  2480. { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
  2481. { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
  2482. { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
  2483. { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
  2484. { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
  2485. { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
  2486. { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
  2487. { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
  2488. { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
  2489. PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
  2490. { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
  2491. PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
  2492. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
  2493. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
  2494. { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
  2495. { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
  2496. /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
  2497. { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
  2498. { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
  2499. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
  2500. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
  2501. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
  2502. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
  2503. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
  2504. PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
  2505. { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
  2506. PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
  2507. /* NetMos communication controllers */
  2508. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
  2509. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
  2510. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
  2511. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
  2512. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
  2513. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
  2514. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
  2515. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
  2516. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
  2517. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
  2518. { 0, } /* terminate list */
  2519. };
  2520. MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
  2521. struct pci_parport_data {
  2522. int num;
  2523. struct parport *ports[2];
  2524. };
  2525. static int parport_pc_pci_probe (struct pci_dev *dev,
  2526. const struct pci_device_id *id)
  2527. {
  2528. int err, count, n, i = id->driver_data;
  2529. struct pci_parport_data *data;
  2530. if (i < last_sio)
  2531. /* This is an onboard Super-IO and has already been probed */
  2532. return 0;
  2533. /* This is a PCI card */
  2534. i -= last_sio;
  2535. count = 0;
  2536. if ((err = pci_enable_device (dev)) != 0)
  2537. return err;
  2538. data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
  2539. if (!data)
  2540. return -ENOMEM;
  2541. if (cards[i].preinit_hook &&
  2542. cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
  2543. kfree(data);
  2544. return -ENODEV;
  2545. }
  2546. for (n = 0; n < cards[i].numports; n++) {
  2547. int lo = cards[i].addr[n].lo;
  2548. int hi = cards[i].addr[n].hi;
  2549. unsigned long io_lo, io_hi;
  2550. io_lo = pci_resource_start (dev, lo);
  2551. io_hi = 0;
  2552. if ((hi >= 0) && (hi <= 6))
  2553. io_hi = pci_resource_start (dev, hi);
  2554. else if (hi > 6)
  2555. io_lo += hi; /* Reinterpret the meaning of
  2556. "hi" as an offset (see SYBA
  2557. def.) */
  2558. /* TODO: test if sharing interrupts works */
  2559. printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
  2560. "I/O at %#lx(%#lx)\n",
  2561. parport_pc_pci_tbl[i + last_sio].vendor,
  2562. parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
  2563. data->ports[count] =
  2564. parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
  2565. PARPORT_DMA_NONE, dev);
  2566. if (data->ports[count])
  2567. count++;
  2568. }
  2569. data->num = count;
  2570. if (cards[i].postinit_hook)
  2571. cards[i].postinit_hook (dev, count == 0);
  2572. if (count) {
  2573. pci_set_drvdata(dev, data);
  2574. return 0;
  2575. }
  2576. kfree(data);
  2577. return -ENODEV;
  2578. }
  2579. static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
  2580. {
  2581. struct pci_parport_data *data = pci_get_drvdata(dev);
  2582. int i;
  2583. pci_set_drvdata(dev, NULL);
  2584. if (data) {
  2585. for (i = data->num - 1; i >= 0; i--)
  2586. parport_pc_unregister_port(data->ports[i]);
  2587. kfree(data);
  2588. }
  2589. }
  2590. static struct pci_driver parport_pc_pci_driver = {
  2591. .name = "parport_pc",
  2592. .id_table = parport_pc_pci_tbl,
  2593. .probe = parport_pc_pci_probe,
  2594. .remove = __devexit_p(parport_pc_pci_remove),
  2595. };
  2596. static int __init parport_pc_init_superio (int autoirq, int autodma)
  2597. {
  2598. const struct pci_device_id *id;
  2599. struct pci_dev *pdev = NULL;
  2600. int ret = 0;
  2601. for_each_pci_dev(pdev) {
  2602. id = pci_match_id(parport_pc_pci_tbl, pdev);
  2603. if (id == NULL || id->driver_data >= last_sio)
  2604. continue;
  2605. if (parport_pc_superio_info[id->driver_data].probe
  2606. (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) {
  2607. ret++;
  2608. }
  2609. }
  2610. return ret; /* number of devices found */
  2611. }
  2612. #else
  2613. static struct pci_driver parport_pc_pci_driver;
  2614. static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
  2615. #endif /* CONFIG_PCI */
  2616. static const struct pnp_device_id parport_pc_pnp_tbl[] = {
  2617. /* Standard LPT Printer Port */
  2618. {.id = "PNP0400", .driver_data = 0},
  2619. /* ECP Printer Port */
  2620. {.id = "PNP0401", .driver_data = 0},
  2621. { }
  2622. };
  2623. MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl);
  2624. static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
  2625. {
  2626. struct parport *pdata;
  2627. unsigned long io_lo, io_hi;
  2628. int dma, irq;
  2629. if (pnp_port_valid(dev,0) &&
  2630. !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) {
  2631. io_lo = pnp_port_start(dev,0);
  2632. } else
  2633. return -EINVAL;
  2634. if (pnp_port_valid(dev,1) &&
  2635. !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) {
  2636. io_hi = pnp_port_start(dev,1);
  2637. } else
  2638. io_hi = 0;
  2639. if (pnp_irq_valid(dev,0) &&
  2640. !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) {
  2641. irq = pnp_irq(dev,0);
  2642. } else
  2643. irq = PARPORT_IRQ_NONE;
  2644. if (pnp_dma_valid(dev,0) &&
  2645. !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) {
  2646. dma = pnp_dma(dev,0);
  2647. } else
  2648. dma = PARPORT_DMA_NONE;
  2649. printk(KERN_INFO "parport: PnPBIOS parport detected.\n");
  2650. if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL)))
  2651. return -ENODEV;
  2652. pnp_set_drvdata(dev,pdata);
  2653. return 0;
  2654. }
  2655. static void parport_pc_pnp_remove(struct pnp_dev *dev)
  2656. {
  2657. struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
  2658. if (!pdata)
  2659. return;
  2660. parport_pc_unregister_port(pdata);
  2661. }
  2662. /* we only need the pnp layer to activate the device, at least for now */
  2663. static struct pnp_driver parport_pc_pnp_driver = {
  2664. .name = "parport_pc",
  2665. .id_table = parport_pc_pnp_tbl,
  2666. .probe = parport_pc_pnp_probe,
  2667. .remove = parport_pc_pnp_remove,
  2668. };
  2669. /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
  2670. static int __devinit __attribute__((unused))
  2671. parport_pc_find_isa_ports (int autoirq, int autodma)
  2672. {
  2673. int count = 0;
  2674. if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
  2675. count++;
  2676. if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
  2677. count++;
  2678. if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
  2679. count++;
  2680. return count;
  2681. }
  2682. /* This function is called by parport_pc_init if the user didn't
  2683. * specify any ports to probe. Its job is to find some ports. Order
  2684. * is important here -- we want ISA ports to be registered first,
  2685. * followed by PCI cards (for least surprise), but before that we want
  2686. * to do chipset-specific tests for some onboard ports that we know
  2687. * about.
  2688. *
  2689. * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
  2690. * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
  2691. */
  2692. static void __init parport_pc_find_ports (int autoirq, int autodma)
  2693. {
  2694. int count = 0, err;
  2695. #ifdef CONFIG_PARPORT_PC_SUPERIO
  2696. detect_and_report_winbond ();
  2697. detect_and_report_smsc ();
  2698. #endif
  2699. /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
  2700. count += parport_pc_init_superio (autoirq, autodma);
  2701. /* PnP ports, skip detection if SuperIO already found them */
  2702. if (!count) {
  2703. err = pnp_register_driver (&parport_pc_pnp_driver);
  2704. if (!err)
  2705. pnp_registered_parport = 1;
  2706. }
  2707. /* ISA ports and whatever (see asm/parport.h). */
  2708. parport_pc_find_nonpci_ports (autoirq, autodma);
  2709. err = pci_register_driver (&parport_pc_pci_driver);
  2710. if (!err)
  2711. pci_registered_parport = 1;
  2712. }
  2713. /*
  2714. * Piles of crap below pretend to be a parser for module and kernel
  2715. * parameters. Say "thank you" to whoever had come up with that
  2716. * syntax and keep in mind that code below is a cleaned up version.
  2717. */
  2718. static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
  2719. static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] =
  2720. { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
  2721. static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
  2722. static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
  2723. static int __init parport_parse_param(const char *s, int *val,
  2724. int automatic, int none, int nofifo)
  2725. {
  2726. if (!s)
  2727. return 0;
  2728. if (!strncmp(s, "auto", 4))
  2729. *val = automatic;
  2730. else if (!strncmp(s, "none", 4))
  2731. *val = none;
  2732. else if (nofifo && !strncmp(s, "nofifo", 4))
  2733. *val = nofifo;
  2734. else {
  2735. char *ep;
  2736. unsigned long r = simple_strtoul(s, &ep, 0);
  2737. if (ep != s)
  2738. *val = r;
  2739. else {
  2740. printk(KERN_ERR "parport: bad specifier `%s'\n", s);
  2741. return -1;
  2742. }
  2743. }
  2744. return 0;
  2745. }
  2746. static int __init parport_parse_irq(const char *irqstr, int *val)
  2747. {
  2748. return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
  2749. PARPORT_IRQ_NONE, 0);
  2750. }
  2751. static int __init parport_parse_dma(const char *dmastr, int *val)
  2752. {
  2753. return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
  2754. PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
  2755. }
  2756. #ifdef CONFIG_PCI
  2757. static int __init parport_init_mode_setup(char *str)
  2758. {
  2759. printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
  2760. if (!strcmp (str, "spp"))
  2761. parport_init_mode=1;
  2762. if (!strcmp (str, "ps2"))
  2763. parport_init_mode=2;
  2764. if (!strcmp (str, "epp"))
  2765. parport_init_mode=3;
  2766. if (!strcmp (str, "ecp"))
  2767. parport_init_mode=4;
  2768. if (!strcmp (str, "ecpepp"))
  2769. parport_init_mode=5;
  2770. return 1;
  2771. }
  2772. #endif
  2773. #ifdef MODULE
  2774. static const char *irq[PARPORT_PC_MAX_PORTS];
  2775. static const char *dma[PARPORT_PC_MAX_PORTS];
  2776. MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
  2777. module_param_array(io, int, NULL, 0);
  2778. MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
  2779. module_param_array(io_hi, int, NULL, 0);
  2780. MODULE_PARM_DESC(irq, "IRQ line");
  2781. module_param_array(irq, charp, NULL, 0);
  2782. MODULE_PARM_DESC(dma, "DMA channel");
  2783. module_param_array(dma, charp, NULL, 0);
  2784. #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
  2785. (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
  2786. MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
  2787. module_param(verbose_probing, int, 0644);
  2788. #endif
  2789. #ifdef CONFIG_PCI
  2790. static char *init_mode;
  2791. MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
  2792. module_param(init_mode, charp, 0);
  2793. #endif
  2794. static int __init parse_parport_params(void)
  2795. {
  2796. unsigned int i;
  2797. int val;
  2798. #ifdef CONFIG_PCI
  2799. if (init_mode)
  2800. parport_init_mode_setup(init_mode);
  2801. #endif
  2802. for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
  2803. if (parport_parse_irq(irq[i], &val))
  2804. return 1;
  2805. irqval[i] = val;
  2806. if (parport_parse_dma(dma[i], &val))
  2807. return 1;
  2808. dmaval[i] = val;
  2809. }
  2810. if (!io[0]) {
  2811. /* The user can make us use any IRQs or DMAs we find. */
  2812. if (irq[0] && !parport_parse_irq(irq[0], &val))
  2813. switch (val) {
  2814. case PARPORT_IRQ_NONE:
  2815. case PARPORT_IRQ_AUTO:
  2816. irqval[0] = val;
  2817. break;
  2818. default:
  2819. printk (KERN_WARNING
  2820. "parport_pc: irq specified "
  2821. "without base address. Use 'io=' "
  2822. "to specify one\n");
  2823. }
  2824. if (dma[0] && !parport_parse_dma(dma[0], &val))
  2825. switch (val) {
  2826. case PARPORT_DMA_NONE:
  2827. case PARPORT_DMA_AUTO:
  2828. dmaval[0] = val;
  2829. break;
  2830. default:
  2831. printk (KERN_WARNING
  2832. "parport_pc: dma specified "
  2833. "without base address. Use 'io=' "
  2834. "to specify one\n");
  2835. }
  2836. }
  2837. return 0;
  2838. }
  2839. #else
  2840. static int parport_setup_ptr __initdata = 0;
  2841. /*
  2842. * Acceptable parameters:
  2843. *
  2844. * parport=0
  2845. * parport=auto
  2846. * parport=0xBASE[,IRQ[,DMA]]
  2847. *
  2848. * IRQ/DMA may be numeric or 'auto' or 'none'
  2849. */
  2850. static int __init parport_setup (char *str)
  2851. {
  2852. char *endptr;
  2853. char *sep;
  2854. int val;
  2855. if (!str || !*str || (*str == '0' && !*(str+1))) {
  2856. /* Disable parport if "parport=0" in cmdline */
  2857. io[0] = PARPORT_DISABLE;
  2858. return 1;
  2859. }
  2860. if (!strncmp (str, "auto", 4)) {
  2861. irqval[0] = PARPORT_IRQ_AUTO;
  2862. dmaval[0] = PARPORT_DMA_AUTO;
  2863. return 1;
  2864. }
  2865. val = simple_strtoul (str, &endptr, 0);
  2866. if (endptr == str) {
  2867. printk (KERN_WARNING "parport=%s not understood\n", str);
  2868. return 1;
  2869. }
  2870. if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
  2871. printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
  2872. return 1;
  2873. }
  2874. io[parport_setup_ptr] = val;
  2875. irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
  2876. dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
  2877. sep = strchr(str, ',');
  2878. if (sep++) {
  2879. if (parport_parse_irq(sep, &val))
  2880. return 1;
  2881. irqval[parport_setup_ptr] = val;
  2882. sep = strchr(sep, ',');
  2883. if (sep++) {
  2884. if (parport_parse_dma(sep, &val))
  2885. return 1;
  2886. dmaval[parport_setup_ptr] = val;
  2887. }
  2888. }
  2889. parport_setup_ptr++;
  2890. return 1;
  2891. }
  2892. static int __init parse_parport_params(void)
  2893. {
  2894. return io[0] == PARPORT_DISABLE;
  2895. }
  2896. __setup ("parport=", parport_setup);
  2897. /*
  2898. * Acceptable parameters:
  2899. *
  2900. * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
  2901. */
  2902. #ifdef CONFIG_PCI
  2903. __setup("parport_init_mode=",parport_init_mode_setup);
  2904. #endif
  2905. #endif
  2906. /* "Parser" ends here */
  2907. static int __init parport_pc_init(void)
  2908. {
  2909. if (parse_parport_params())
  2910. return -EINVAL;
  2911. if (io[0]) {
  2912. int i;
  2913. /* Only probe the ports we were given. */
  2914. user_specified = 1;
  2915. for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
  2916. if (!io[i])
  2917. break;
  2918. if ((io_hi[i]) == PARPORT_IOHI_AUTO)
  2919. io_hi[i] = 0x400 + io[i];
  2920. parport_pc_probe_port(io[i], io_hi[i],
  2921. irqval[i], dmaval[i], NULL);
  2922. }
  2923. } else
  2924. parport_pc_find_ports (irqval[0], dmaval[0]);
  2925. return 0;
  2926. }
  2927. static void __exit parport_pc_exit(void)
  2928. {
  2929. if (pci_registered_parport)
  2930. pci_unregister_driver (&parport_pc_pci_driver);
  2931. if (pnp_registered_parport)
  2932. pnp_unregister_driver (&parport_pc_pnp_driver);
  2933. spin_lock(&ports_lock);
  2934. while (!list_empty(&ports_list)) {
  2935. struct parport_pc_private *priv;
  2936. struct parport *port;
  2937. priv = list_entry(ports_list.next,
  2938. struct parport_pc_private, list);
  2939. port = priv->port;
  2940. spin_unlock(&ports_lock);
  2941. parport_pc_unregister_port(port);
  2942. spin_lock(&ports_lock);
  2943. }
  2944. spin_unlock(&ports_lock);
  2945. }
  2946. MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
  2947. MODULE_DESCRIPTION("PC-style parallel port driver");
  2948. MODULE_LICENSE("GPL");
  2949. module_init(parport_pc_init)
  2950. module_exit(parport_pc_exit)