via-velocity.h 48 KB

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  1. /*
  2. * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
  3. * All rights reserved.
  4. *
  5. * This software may be redistributed and/or modified under
  6. * the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 2 of the License, or
  8. * any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * File: via-velocity.h
  16. *
  17. * Purpose: Header file to define driver's private structures.
  18. *
  19. * Author: Chuang Liang-Shing, AJ Jiang
  20. *
  21. * Date: Jan 24, 2003
  22. */
  23. #ifndef VELOCITY_H
  24. #define VELOCITY_H
  25. #define VELOCITY_TX_CSUM_SUPPORT
  26. #define VELOCITY_NAME "via-velocity"
  27. #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
  28. #define VELOCITY_VERSION "1.14"
  29. #define VELOCITY_IO_SIZE 256
  30. #define PKT_BUF_SZ 1540
  31. #define MAX_UNITS 8
  32. #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
  33. #define REV_ID_VT6110 (0)
  34. #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
  35. #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
  36. #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
  37. #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
  38. #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
  39. #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
  40. #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
  41. #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
  42. #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
  43. #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
  44. #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
  45. #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
  46. #define VAR_USED(p) do {(p)=(p);} while (0)
  47. /*
  48. * Purpose: Structures for MAX RX/TX descriptors.
  49. */
  50. #define B_OWNED_BY_CHIP 1
  51. #define B_OWNED_BY_HOST 0
  52. /*
  53. * Bits in the RSR0 register
  54. */
  55. #define RSR_DETAG 0x0080
  56. #define RSR_SNTAG 0x0040
  57. #define RSR_RXER 0x0020
  58. #define RSR_RL 0x0010
  59. #define RSR_CE 0x0008
  60. #define RSR_FAE 0x0004
  61. #define RSR_CRC 0x0002
  62. #define RSR_VIDM 0x0001
  63. /*
  64. * Bits in the RSR1 register
  65. */
  66. #define RSR_RXOK 0x8000 // rx OK
  67. #define RSR_PFT 0x4000 // Perfect filtering address match
  68. #define RSR_MAR 0x2000 // MAC accept multicast address packet
  69. #define RSR_BAR 0x1000 // MAC accept broadcast address packet
  70. #define RSR_PHY 0x0800 // MAC accept physical address packet
  71. #define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
  72. #define RSR_STP 0x0200 // start of packet
  73. #define RSR_EDP 0x0100 // end of packet
  74. /*
  75. * Bits in the RSR1 register
  76. */
  77. #define RSR1_RXOK 0x80 // rx OK
  78. #define RSR1_PFT 0x40 // Perfect filtering address match
  79. #define RSR1_MAR 0x20 // MAC accept multicast address packet
  80. #define RSR1_BAR 0x10 // MAC accept broadcast address packet
  81. #define RSR1_PHY 0x08 // MAC accept physical address packet
  82. #define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
  83. #define RSR1_STP 0x02 // start of packet
  84. #define RSR1_EDP 0x01 // end of packet
  85. /*
  86. * Bits in the CSM register
  87. */
  88. #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok
  89. #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok
  90. #define CSM_FRAG 0x10 //Fragment IP datagram
  91. #define CSM_IPKT 0x04 //Received an IP packet
  92. #define CSM_TCPKT 0x02 //Received a TCP packet
  93. #define CSM_UDPKT 0x01 //Received a UDP packet
  94. /*
  95. * Bits in the TSR0 register
  96. */
  97. #define TSR0_ABT 0x0080 // Tx abort because of excessive collision
  98. #define TSR0_OWT 0x0040 // Jumbo frame Tx abort
  99. #define TSR0_OWC 0x0020 // Out of window collision
  100. #define TSR0_COLS 0x0010 // experience collision in this transmit event
  101. #define TSR0_NCR3 0x0008 // collision retry counter[3]
  102. #define TSR0_NCR2 0x0004 // collision retry counter[2]
  103. #define TSR0_NCR1 0x0002 // collision retry counter[1]
  104. #define TSR0_NCR0 0x0001 // collision retry counter[0]
  105. #define TSR0_TERR 0x8000 //
  106. #define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
  107. #define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
  108. #define TSR0_LNKFL 0x1000 // packet serviced during link down
  109. #define TSR0_SHDN 0x0400 // shutdown case
  110. #define TSR0_CRS 0x0200 // carrier sense lost
  111. #define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
  112. /*
  113. * Bits in the TSR1 register
  114. */
  115. #define TSR1_TERR 0x80 //
  116. #define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
  117. #define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
  118. #define TSR1_LNKFL 0x10 // packet serviced during link down
  119. #define TSR1_SHDN 0x04 // shutdown case
  120. #define TSR1_CRS 0x02 // carrier sense lost
  121. #define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
  122. //
  123. // Bits in the TCR0 register
  124. //
  125. #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
  126. #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
  127. #define TCR0_VETAG 0x20 // enable VLAN tag
  128. #define TCR0_IPCK 0x10 // request IP checksum calculation.
  129. #define TCR0_UDPCK 0x08 // request UDP checksum calculation.
  130. #define TCR0_TCPCK 0x04 // request TCP checksum calculation.
  131. #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
  132. #define TCR0_CRC 0x01 // disable CRC generation
  133. #define TCPLS_NORMAL 3
  134. #define TCPLS_START 2
  135. #define TCPLS_END 1
  136. #define TCPLS_MED 0
  137. // max transmit or receive buffer size
  138. #define CB_RX_BUF_SIZE 2048UL // max buffer size
  139. // NOTE: must be multiple of 4
  140. #define CB_MAX_RD_NUM 512 // MAX # of RD
  141. #define CB_MAX_TD_NUM 256 // MAX # of TD
  142. #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
  143. #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
  144. #define CB_INIT_RD_NUM 128 // init # of RD, for setup default
  145. #define CB_INIT_TD_NUM 64 // init # of TD, for setup default
  146. // for 3119
  147. #define CB_TD_RING_NUM 4 // # of TD rings.
  148. #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
  149. /*
  150. * If collisions excess 15 times , tx will abort, and
  151. * if tx fifo underflow, tx will fail
  152. * we should try to resend it
  153. */
  154. #define CB_MAX_TX_ABORT_RETRY 3
  155. /*
  156. * Receive descriptor
  157. */
  158. struct rdesc0 {
  159. u16 RSR; /* Receive status */
  160. u16 len:14; /* Received packet length */
  161. u16 reserved:1;
  162. u16 owner:1; /* Who owns this buffer ? */
  163. };
  164. struct rdesc1 {
  165. u16 PQTAG;
  166. u8 CSM;
  167. u8 IPKT;
  168. };
  169. struct rx_desc {
  170. struct rdesc0 rdesc0;
  171. struct rdesc1 rdesc1;
  172. u32 pa_low; /* Low 32 bit PCI address */
  173. u16 pa_high; /* Next 16 bit PCI address (48 total) */
  174. u16 len:15; /* Frame size */
  175. u16 inten:1; /* Enable interrupt */
  176. } __attribute__ ((__packed__));
  177. /*
  178. * Transmit descriptor
  179. */
  180. struct tdesc0 {
  181. u16 TSR; /* Transmit status register */
  182. u16 pktsize:14; /* Size of frame */
  183. u16 reserved:1;
  184. u16 owner:1; /* Who owns the buffer */
  185. };
  186. struct pqinf { /* Priority queue info */
  187. u16 VID:12;
  188. u16 CFI:1;
  189. u16 priority:3;
  190. } __attribute__ ((__packed__));
  191. struct tdesc1 {
  192. struct pqinf pqinf;
  193. u8 TCR;
  194. u8 TCPLS:2;
  195. u8 reserved:2;
  196. u8 CMDZ:4;
  197. } __attribute__ ((__packed__));
  198. struct td_buf {
  199. u32 pa_low;
  200. u16 pa_high;
  201. u16 bufsize:14;
  202. u16 reserved:1;
  203. u16 queue:1;
  204. } __attribute__ ((__packed__));
  205. struct tx_desc {
  206. struct tdesc0 tdesc0;
  207. struct tdesc1 tdesc1;
  208. struct td_buf td_buf[7];
  209. };
  210. struct velocity_rd_info {
  211. struct sk_buff *skb;
  212. dma_addr_t skb_dma;
  213. };
  214. /*
  215. * Used to track transmit side buffers.
  216. */
  217. struct velocity_td_info {
  218. struct sk_buff *skb;
  219. u8 *buf;
  220. int nskb_dma;
  221. dma_addr_t skb_dma[7];
  222. dma_addr_t buf_dma;
  223. };
  224. enum velocity_owner {
  225. OWNED_BY_HOST = 0,
  226. OWNED_BY_NIC = 1
  227. };
  228. /*
  229. * MAC registers and macros.
  230. */
  231. #define MCAM_SIZE 64
  232. #define VCAM_SIZE 64
  233. #define TX_QUEUE_NO 4
  234. #define MAX_HW_MIB_COUNTER 32
  235. #define VELOCITY_MIN_MTU (64)
  236. #define VELOCITY_MAX_MTU (9000)
  237. /*
  238. * Registers in the MAC
  239. */
  240. #define MAC_REG_PAR 0x00 // physical address
  241. #define MAC_REG_RCR 0x06
  242. #define MAC_REG_TCR 0x07
  243. #define MAC_REG_CR0_SET 0x08
  244. #define MAC_REG_CR1_SET 0x09
  245. #define MAC_REG_CR2_SET 0x0A
  246. #define MAC_REG_CR3_SET 0x0B
  247. #define MAC_REG_CR0_CLR 0x0C
  248. #define MAC_REG_CR1_CLR 0x0D
  249. #define MAC_REG_CR2_CLR 0x0E
  250. #define MAC_REG_CR3_CLR 0x0F
  251. #define MAC_REG_MAR 0x10
  252. #define MAC_REG_CAM 0x10
  253. #define MAC_REG_DEC_BASE_HI 0x18
  254. #define MAC_REG_DBF_BASE_HI 0x1C
  255. #define MAC_REG_ISR_CTL 0x20
  256. #define MAC_REG_ISR_HOTMR 0x20
  257. #define MAC_REG_ISR_TSUPTHR 0x20
  258. #define MAC_REG_ISR_RSUPTHR 0x20
  259. #define MAC_REG_ISR_CTL1 0x21
  260. #define MAC_REG_TXE_SR 0x22
  261. #define MAC_REG_RXE_SR 0x23
  262. #define MAC_REG_ISR 0x24
  263. #define MAC_REG_ISR0 0x24
  264. #define MAC_REG_ISR1 0x25
  265. #define MAC_REG_ISR2 0x26
  266. #define MAC_REG_ISR3 0x27
  267. #define MAC_REG_IMR 0x28
  268. #define MAC_REG_IMR0 0x28
  269. #define MAC_REG_IMR1 0x29
  270. #define MAC_REG_IMR2 0x2A
  271. #define MAC_REG_IMR3 0x2B
  272. #define MAC_REG_TDCSR_SET 0x30
  273. #define MAC_REG_RDCSR_SET 0x32
  274. #define MAC_REG_TDCSR_CLR 0x34
  275. #define MAC_REG_RDCSR_CLR 0x36
  276. #define MAC_REG_RDBASE_LO 0x38
  277. #define MAC_REG_RDINDX 0x3C
  278. #define MAC_REG_TDBASE_LO 0x40
  279. #define MAC_REG_RDCSIZE 0x50
  280. #define MAC_REG_TDCSIZE 0x52
  281. #define MAC_REG_TDINDX 0x54
  282. #define MAC_REG_TDIDX0 0x54
  283. #define MAC_REG_TDIDX1 0x56
  284. #define MAC_REG_TDIDX2 0x58
  285. #define MAC_REG_TDIDX3 0x5A
  286. #define MAC_REG_PAUSE_TIMER 0x5C
  287. #define MAC_REG_RBRDU 0x5E
  288. #define MAC_REG_FIFO_TEST0 0x60
  289. #define MAC_REG_FIFO_TEST1 0x64
  290. #define MAC_REG_CAMADDR 0x68
  291. #define MAC_REG_CAMCR 0x69
  292. #define MAC_REG_GFTEST 0x6A
  293. #define MAC_REG_FTSTCMD 0x6B
  294. #define MAC_REG_MIICFG 0x6C
  295. #define MAC_REG_MIISR 0x6D
  296. #define MAC_REG_PHYSR0 0x6E
  297. #define MAC_REG_PHYSR1 0x6F
  298. #define MAC_REG_MIICR 0x70
  299. #define MAC_REG_MIIADR 0x71
  300. #define MAC_REG_MIIDATA 0x72
  301. #define MAC_REG_SOFT_TIMER0 0x74
  302. #define MAC_REG_SOFT_TIMER1 0x76
  303. #define MAC_REG_CFGA 0x78
  304. #define MAC_REG_CFGB 0x79
  305. #define MAC_REG_CFGC 0x7A
  306. #define MAC_REG_CFGD 0x7B
  307. #define MAC_REG_DCFG0 0x7C
  308. #define MAC_REG_DCFG1 0x7D
  309. #define MAC_REG_MCFG0 0x7E
  310. #define MAC_REG_MCFG1 0x7F
  311. #define MAC_REG_TBIST 0x80
  312. #define MAC_REG_RBIST 0x81
  313. #define MAC_REG_PMCC 0x82
  314. #define MAC_REG_STICKHW 0x83
  315. #define MAC_REG_MIBCR 0x84
  316. #define MAC_REG_EERSV 0x85
  317. #define MAC_REG_REVID 0x86
  318. #define MAC_REG_MIBREAD 0x88
  319. #define MAC_REG_BPMA 0x8C
  320. #define MAC_REG_EEWR_DATA 0x8C
  321. #define MAC_REG_BPMD_WR 0x8F
  322. #define MAC_REG_BPCMD 0x90
  323. #define MAC_REG_BPMD_RD 0x91
  324. #define MAC_REG_EECHKSUM 0x92
  325. #define MAC_REG_EECSR 0x93
  326. #define MAC_REG_EERD_DATA 0x94
  327. #define MAC_REG_EADDR 0x96
  328. #define MAC_REG_EMBCMD 0x97
  329. #define MAC_REG_JMPSR0 0x98
  330. #define MAC_REG_JMPSR1 0x99
  331. #define MAC_REG_JMPSR2 0x9A
  332. #define MAC_REG_JMPSR3 0x9B
  333. #define MAC_REG_CHIPGSR 0x9C
  334. #define MAC_REG_TESTCFG 0x9D
  335. #define MAC_REG_DEBUG 0x9E
  336. #define MAC_REG_CHIPGCR 0x9F
  337. #define MAC_REG_WOLCR0_SET 0xA0
  338. #define MAC_REG_WOLCR1_SET 0xA1
  339. #define MAC_REG_PWCFG_SET 0xA2
  340. #define MAC_REG_WOLCFG_SET 0xA3
  341. #define MAC_REG_WOLCR0_CLR 0xA4
  342. #define MAC_REG_WOLCR1_CLR 0xA5
  343. #define MAC_REG_PWCFG_CLR 0xA6
  344. #define MAC_REG_WOLCFG_CLR 0xA7
  345. #define MAC_REG_WOLSR0_SET 0xA8
  346. #define MAC_REG_WOLSR1_SET 0xA9
  347. #define MAC_REG_WOLSR0_CLR 0xAC
  348. #define MAC_REG_WOLSR1_CLR 0xAD
  349. #define MAC_REG_PATRN_CRC0 0xB0
  350. #define MAC_REG_PATRN_CRC1 0xB2
  351. #define MAC_REG_PATRN_CRC2 0xB4
  352. #define MAC_REG_PATRN_CRC3 0xB6
  353. #define MAC_REG_PATRN_CRC4 0xB8
  354. #define MAC_REG_PATRN_CRC5 0xBA
  355. #define MAC_REG_PATRN_CRC6 0xBC
  356. #define MAC_REG_PATRN_CRC7 0xBE
  357. #define MAC_REG_BYTEMSK0_0 0xC0
  358. #define MAC_REG_BYTEMSK0_1 0xC4
  359. #define MAC_REG_BYTEMSK0_2 0xC8
  360. #define MAC_REG_BYTEMSK0_3 0xCC
  361. #define MAC_REG_BYTEMSK1_0 0xD0
  362. #define MAC_REG_BYTEMSK1_1 0xD4
  363. #define MAC_REG_BYTEMSK1_2 0xD8
  364. #define MAC_REG_BYTEMSK1_3 0xDC
  365. #define MAC_REG_BYTEMSK2_0 0xE0
  366. #define MAC_REG_BYTEMSK2_1 0xE4
  367. #define MAC_REG_BYTEMSK2_2 0xE8
  368. #define MAC_REG_BYTEMSK2_3 0xEC
  369. #define MAC_REG_BYTEMSK3_0 0xF0
  370. #define MAC_REG_BYTEMSK3_1 0xF4
  371. #define MAC_REG_BYTEMSK3_2 0xF8
  372. #define MAC_REG_BYTEMSK3_3 0xFC
  373. /*
  374. * Bits in the RCR register
  375. */
  376. #define RCR_AS 0x80
  377. #define RCR_AP 0x40
  378. #define RCR_AL 0x20
  379. #define RCR_PROM 0x10
  380. #define RCR_AB 0x08
  381. #define RCR_AM 0x04
  382. #define RCR_AR 0x02
  383. #define RCR_SEP 0x01
  384. /*
  385. * Bits in the TCR register
  386. */
  387. #define TCR_TB2BDIS 0x80
  388. #define TCR_COLTMC1 0x08
  389. #define TCR_COLTMC0 0x04
  390. #define TCR_LB1 0x02 /* loopback[1] */
  391. #define TCR_LB0 0x01 /* loopback[0] */
  392. /*
  393. * Bits in the CR0 register
  394. */
  395. #define CR0_TXON 0x00000008UL
  396. #define CR0_RXON 0x00000004UL
  397. #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
  398. #define CR0_STRT 0x00000001UL /* start MAC */
  399. #define CR0_SFRST 0x00008000UL /* software reset */
  400. #define CR0_TM1EN 0x00004000UL
  401. #define CR0_TM0EN 0x00002000UL
  402. #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
  403. #define CR0_DISAU 0x00000100UL
  404. #define CR0_XONEN 0x00800000UL
  405. #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
  406. #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
  407. #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
  408. #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
  409. #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
  410. #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
  411. #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
  412. #define CR0_GSPRST 0x80000000UL
  413. #define CR0_FORSRST 0x40000000UL
  414. #define CR0_FPHYRST 0x20000000UL
  415. #define CR0_DIAG 0x10000000UL
  416. #define CR0_INTPCTL 0x04000000UL
  417. #define CR0_GINTMSK1 0x02000000UL
  418. #define CR0_GINTMSK0 0x01000000UL
  419. /*
  420. * Bits in the CR1 register
  421. */
  422. #define CR1_SFRST 0x80 /* software reset */
  423. #define CR1_TM1EN 0x40
  424. #define CR1_TM0EN 0x20
  425. #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
  426. #define CR1_DISAU 0x01
  427. /*
  428. * Bits in the CR2 register
  429. */
  430. #define CR2_XONEN 0x80
  431. #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
  432. #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
  433. #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
  434. #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
  435. #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
  436. #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
  437. #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
  438. /*
  439. * Bits in the CR3 register
  440. */
  441. #define CR3_GSPRST 0x80
  442. #define CR3_FORSRST 0x40
  443. #define CR3_FPHYRST 0x20
  444. #define CR3_DIAG 0x10
  445. #define CR3_INTPCTL 0x04
  446. #define CR3_GINTMSK1 0x02
  447. #define CR3_GINTMSK0 0x01
  448. #define ISRCTL_UDPINT 0x8000
  449. #define ISRCTL_TSUPDIS 0x4000
  450. #define ISRCTL_RSUPDIS 0x2000
  451. #define ISRCTL_PMSK1 0x1000
  452. #define ISRCTL_PMSK0 0x0800
  453. #define ISRCTL_INTPD 0x0400
  454. #define ISRCTL_HCRLD 0x0200
  455. #define ISRCTL_SCRLD 0x0100
  456. /*
  457. * Bits in the ISR_CTL1 register
  458. */
  459. #define ISRCTL1_UDPINT 0x80
  460. #define ISRCTL1_TSUPDIS 0x40
  461. #define ISRCTL1_RSUPDIS 0x20
  462. #define ISRCTL1_PMSK1 0x10
  463. #define ISRCTL1_PMSK0 0x08
  464. #define ISRCTL1_INTPD 0x04
  465. #define ISRCTL1_HCRLD 0x02
  466. #define ISRCTL1_SCRLD 0x01
  467. /*
  468. * Bits in the TXE_SR register
  469. */
  470. #define TXESR_TFDBS 0x08
  471. #define TXESR_TDWBS 0x04
  472. #define TXESR_TDRBS 0x02
  473. #define TXESR_TDSTR 0x01
  474. /*
  475. * Bits in the RXE_SR register
  476. */
  477. #define RXESR_RFDBS 0x08
  478. #define RXESR_RDWBS 0x04
  479. #define RXESR_RDRBS 0x02
  480. #define RXESR_RDSTR 0x01
  481. /*
  482. * Bits in the ISR register
  483. */
  484. #define ISR_ISR3 0x80000000UL
  485. #define ISR_ISR2 0x40000000UL
  486. #define ISR_ISR1 0x20000000UL
  487. #define ISR_ISR0 0x10000000UL
  488. #define ISR_TXSTLI 0x02000000UL
  489. #define ISR_RXSTLI 0x01000000UL
  490. #define ISR_HFLD 0x00800000UL
  491. #define ISR_UDPI 0x00400000UL
  492. #define ISR_MIBFI 0x00200000UL
  493. #define ISR_SHDNI 0x00100000UL
  494. #define ISR_PHYI 0x00080000UL
  495. #define ISR_PWEI 0x00040000UL
  496. #define ISR_TMR1I 0x00020000UL
  497. #define ISR_TMR0I 0x00010000UL
  498. #define ISR_SRCI 0x00008000UL
  499. #define ISR_LSTPEI 0x00004000UL
  500. #define ISR_LSTEI 0x00002000UL
  501. #define ISR_OVFI 0x00001000UL
  502. #define ISR_FLONI 0x00000800UL
  503. #define ISR_RACEI 0x00000400UL
  504. #define ISR_TXWB1I 0x00000200UL
  505. #define ISR_TXWB0I 0x00000100UL
  506. #define ISR_PTX3I 0x00000080UL
  507. #define ISR_PTX2I 0x00000040UL
  508. #define ISR_PTX1I 0x00000020UL
  509. #define ISR_PTX0I 0x00000010UL
  510. #define ISR_PTXI 0x00000008UL
  511. #define ISR_PRXI 0x00000004UL
  512. #define ISR_PPTXI 0x00000002UL
  513. #define ISR_PPRXI 0x00000001UL
  514. /*
  515. * Bits in the IMR register
  516. */
  517. #define IMR_TXSTLM 0x02000000UL
  518. #define IMR_UDPIM 0x00400000UL
  519. #define IMR_MIBFIM 0x00200000UL
  520. #define IMR_SHDNIM 0x00100000UL
  521. #define IMR_PHYIM 0x00080000UL
  522. #define IMR_PWEIM 0x00040000UL
  523. #define IMR_TMR1IM 0x00020000UL
  524. #define IMR_TMR0IM 0x00010000UL
  525. #define IMR_SRCIM 0x00008000UL
  526. #define IMR_LSTPEIM 0x00004000UL
  527. #define IMR_LSTEIM 0x00002000UL
  528. #define IMR_OVFIM 0x00001000UL
  529. #define IMR_FLONIM 0x00000800UL
  530. #define IMR_RACEIM 0x00000400UL
  531. #define IMR_TXWB1IM 0x00000200UL
  532. #define IMR_TXWB0IM 0x00000100UL
  533. #define IMR_PTX3IM 0x00000080UL
  534. #define IMR_PTX2IM 0x00000040UL
  535. #define IMR_PTX1IM 0x00000020UL
  536. #define IMR_PTX0IM 0x00000010UL
  537. #define IMR_PTXIM 0x00000008UL
  538. #define IMR_PRXIM 0x00000004UL
  539. #define IMR_PPTXIM 0x00000002UL
  540. #define IMR_PPRXIM 0x00000001UL
  541. /* 0x0013FB0FUL = initial value of IMR */
  542. #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
  543. IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
  544. IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
  545. IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
  546. /*
  547. * Bits in the TDCSR0/1, RDCSR0 register
  548. */
  549. #define TRDCSR_DEAD 0x0008
  550. #define TRDCSR_WAK 0x0004
  551. #define TRDCSR_ACT 0x0002
  552. #define TRDCSR_RUN 0x0001
  553. /*
  554. * Bits in the CAMADDR register
  555. */
  556. #define CAMADDR_CAMEN 0x80
  557. #define CAMADDR_VCAMSL 0x40
  558. /*
  559. * Bits in the CAMCR register
  560. */
  561. #define CAMCR_PS1 0x80
  562. #define CAMCR_PS0 0x40
  563. #define CAMCR_AITRPKT 0x20
  564. #define CAMCR_AITR16 0x10
  565. #define CAMCR_CAMRD 0x08
  566. #define CAMCR_CAMWR 0x04
  567. #define CAMCR_PS_CAM_MASK 0x40
  568. #define CAMCR_PS_CAM_DATA 0x80
  569. #define CAMCR_PS_MAR 0x00
  570. /*
  571. * Bits in the MIICFG register
  572. */
  573. #define MIICFG_MPO1 0x80
  574. #define MIICFG_MPO0 0x40
  575. #define MIICFG_MFDC 0x20
  576. /*
  577. * Bits in the MIISR register
  578. */
  579. #define MIISR_MIDLE 0x80
  580. /*
  581. * Bits in the PHYSR0 register
  582. */
  583. #define PHYSR0_PHYRST 0x80
  584. #define PHYSR0_LINKGD 0x40
  585. #define PHYSR0_FDPX 0x10
  586. #define PHYSR0_SPDG 0x08
  587. #define PHYSR0_SPD10 0x04
  588. #define PHYSR0_RXFLC 0x02
  589. #define PHYSR0_TXFLC 0x01
  590. /*
  591. * Bits in the PHYSR1 register
  592. */
  593. #define PHYSR1_PHYTBI 0x01
  594. /*
  595. * Bits in the MIICR register
  596. */
  597. #define MIICR_MAUTO 0x80
  598. #define MIICR_RCMD 0x40
  599. #define MIICR_WCMD 0x20
  600. #define MIICR_MDPM 0x10
  601. #define MIICR_MOUT 0x08
  602. #define MIICR_MDO 0x04
  603. #define MIICR_MDI 0x02
  604. #define MIICR_MDC 0x01
  605. /*
  606. * Bits in the MIIADR register
  607. */
  608. #define MIIADR_SWMPL 0x80
  609. /*
  610. * Bits in the CFGA register
  611. */
  612. #define CFGA_PMHCTG 0x08
  613. #define CFGA_GPIO1PD 0x04
  614. #define CFGA_ABSHDN 0x02
  615. #define CFGA_PACPI 0x01
  616. /*
  617. * Bits in the CFGB register
  618. */
  619. #define CFGB_GTCKOPT 0x80
  620. #define CFGB_MIIOPT 0x40
  621. #define CFGB_CRSEOPT 0x20
  622. #define CFGB_OFSET 0x10
  623. #define CFGB_CRANDOM 0x08
  624. #define CFGB_CAP 0x04
  625. #define CFGB_MBA 0x02
  626. #define CFGB_BAKOPT 0x01
  627. /*
  628. * Bits in the CFGC register
  629. */
  630. #define CFGC_EELOAD 0x80
  631. #define CFGC_BROPT 0x40
  632. #define CFGC_DLYEN 0x20
  633. #define CFGC_DTSEL 0x10
  634. #define CFGC_BTSEL 0x08
  635. #define CFGC_BPS2 0x04 /* bootrom select[2] */
  636. #define CFGC_BPS1 0x02 /* bootrom select[1] */
  637. #define CFGC_BPS0 0x01 /* bootrom select[0] */
  638. /*
  639. * Bits in the CFGD register
  640. */
  641. #define CFGD_IODIS 0x80
  642. #define CFGD_MSLVDACEN 0x40
  643. #define CFGD_CFGDACEN 0x20
  644. #define CFGD_PCI64EN 0x10
  645. #define CFGD_HTMRL4 0x08
  646. /*
  647. * Bits in the DCFG1 register
  648. */
  649. #define DCFG_XMWI 0x8000
  650. #define DCFG_XMRM 0x4000
  651. #define DCFG_XMRL 0x2000
  652. #define DCFG_PERDIS 0x1000
  653. #define DCFG_MRWAIT 0x0400
  654. #define DCFG_MWWAIT 0x0200
  655. #define DCFG_LATMEN 0x0100
  656. /*
  657. * Bits in the MCFG0 register
  658. */
  659. #define MCFG_RXARB 0x0080
  660. #define MCFG_RFT1 0x0020
  661. #define MCFG_RFT0 0x0010
  662. #define MCFG_LOWTHOPT 0x0008
  663. #define MCFG_PQEN 0x0004
  664. #define MCFG_RTGOPT 0x0002
  665. #define MCFG_VIDFR 0x0001
  666. /*
  667. * Bits in the MCFG1 register
  668. */
  669. #define MCFG_TXARB 0x8000
  670. #define MCFG_TXQBK1 0x0800
  671. #define MCFG_TXQBK0 0x0400
  672. #define MCFG_TXQNOBK 0x0200
  673. #define MCFG_SNAPOPT 0x0100
  674. /*
  675. * Bits in the PMCC register
  676. */
  677. #define PMCC_DSI 0x80
  678. #define PMCC_D2_DIS 0x40
  679. #define PMCC_D1_DIS 0x20
  680. #define PMCC_D3C_EN 0x10
  681. #define PMCC_D3H_EN 0x08
  682. #define PMCC_D2_EN 0x04
  683. #define PMCC_D1_EN 0x02
  684. #define PMCC_D0_EN 0x01
  685. /*
  686. * Bits in STICKHW
  687. */
  688. #define STICKHW_SWPTAG 0x10
  689. #define STICKHW_WOLSR 0x08
  690. #define STICKHW_WOLEN 0x04
  691. #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
  692. #define STICKHW_DS0 0x01 /* suspend well DS write port */
  693. /*
  694. * Bits in the MIBCR register
  695. */
  696. #define MIBCR_MIBISTOK 0x80
  697. #define MIBCR_MIBISTGO 0x40
  698. #define MIBCR_MIBINC 0x20
  699. #define MIBCR_MIBHI 0x10
  700. #define MIBCR_MIBFRZ 0x08
  701. #define MIBCR_MIBFLSH 0x04
  702. #define MIBCR_MPTRINI 0x02
  703. #define MIBCR_MIBCLR 0x01
  704. /*
  705. * Bits in the EERSV register
  706. */
  707. #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
  708. #define EERSV_BOOT_MASK ((u8) 0x06)
  709. #define EERSV_BOOT_INT19 ((u8) 0x00)
  710. #define EERSV_BOOT_INT18 ((u8) 0x02)
  711. #define EERSV_BOOT_LOCAL ((u8) 0x04)
  712. #define EERSV_BOOT_BEV ((u8) 0x06)
  713. /*
  714. * Bits in BPCMD
  715. */
  716. #define BPCMD_BPDNE 0x80
  717. #define BPCMD_EBPWR 0x02
  718. #define BPCMD_EBPRD 0x01
  719. /*
  720. * Bits in the EECSR register
  721. */
  722. #define EECSR_EMBP 0x40 /* eeprom embeded programming */
  723. #define EECSR_RELOAD 0x20 /* eeprom content reload */
  724. #define EECSR_DPM 0x10 /* eeprom direct programming */
  725. #define EECSR_ECS 0x08 /* eeprom CS pin */
  726. #define EECSR_ECK 0x04 /* eeprom CK pin */
  727. #define EECSR_EDI 0x02 /* eeprom DI pin */
  728. #define EECSR_EDO 0x01 /* eeprom DO pin */
  729. /*
  730. * Bits in the EMBCMD register
  731. */
  732. #define EMBCMD_EDONE 0x80
  733. #define EMBCMD_EWDIS 0x08
  734. #define EMBCMD_EWEN 0x04
  735. #define EMBCMD_EWR 0x02
  736. #define EMBCMD_ERD 0x01
  737. /*
  738. * Bits in TESTCFG register
  739. */
  740. #define TESTCFG_HBDIS 0x80
  741. /*
  742. * Bits in CHIPGCR register
  743. */
  744. #define CHIPGCR_FCGMII 0x80
  745. #define CHIPGCR_FCFDX 0x40
  746. #define CHIPGCR_FCRESV 0x20
  747. #define CHIPGCR_FCMODE 0x10
  748. #define CHIPGCR_LPSOPT 0x08
  749. #define CHIPGCR_TM1US 0x04
  750. #define CHIPGCR_TM0US 0x02
  751. #define CHIPGCR_PHYINTEN 0x01
  752. /*
  753. * Bits in WOLCR0
  754. */
  755. #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
  756. #define WOLCR_MSWOLEN6 0x0040
  757. #define WOLCR_MSWOLEN5 0x0020
  758. #define WOLCR_MSWOLEN4 0x0010
  759. #define WOLCR_MSWOLEN3 0x0008
  760. #define WOLCR_MSWOLEN2 0x0004
  761. #define WOLCR_MSWOLEN1 0x0002
  762. #define WOLCR_MSWOLEN0 0x0001
  763. #define WOLCR_ARP_EN 0x0001
  764. /*
  765. * Bits in WOLCR1
  766. */
  767. #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
  768. #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
  769. #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
  770. #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
  771. /*
  772. * Bits in PWCFG
  773. */
  774. #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
  775. #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
  776. #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
  777. #define PWCFG_LEGCY_WOL 0x10
  778. #define PWCFG_PMCSR_PME_SR 0x08
  779. #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
  780. #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
  781. #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
  782. /*
  783. * Bits in WOLCFG
  784. */
  785. #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
  786. #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
  787. #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
  788. #define WOLCFG_SMIIACC 0x08 /* ?? */
  789. #define WOLCFG_SGENWH 0x02
  790. #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
  791. to report status change */
  792. /*
  793. * Bits in WOLSR1
  794. */
  795. #define WOLSR_LINKOFF_INT 0x0800
  796. #define WOLSR_LINKON_INT 0x0400
  797. #define WOLSR_MAGIC_INT 0x0200
  798. #define WOLSR_UNICAST_INT 0x0100
  799. /*
  800. * Ethernet address filter type
  801. */
  802. #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
  803. #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
  804. #define PKT_TYPE_MULTICAST 0x0002
  805. #define PKT_TYPE_ALL_MULTICAST 0x0004
  806. #define PKT_TYPE_BROADCAST 0x0008
  807. #define PKT_TYPE_PROMISCUOUS 0x0020
  808. #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
  809. #define PKT_TYPE_RUNT 0x4000
  810. #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
  811. /*
  812. * Loopback mode
  813. */
  814. #define MAC_LB_NONE 0x00
  815. #define MAC_LB_INTERNAL 0x01
  816. #define MAC_LB_EXTERNAL 0x02
  817. /*
  818. * Enabled mask value of irq
  819. */
  820. #if defined(_SIM)
  821. #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
  822. set IMR0 to 0x0F according to spec */
  823. #else
  824. #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
  825. ignore MIBFI,RACEI to
  826. reduce intr. frequency
  827. NOTE.... do not enable NoBuf int mask at driver driver
  828. when (1) NoBuf -> RxThreshold = SF
  829. (2) OK -> RxThreshold = original value
  830. */
  831. #endif
  832. /*
  833. * Revision id
  834. */
  835. #define REV_ID_VT3119_A0 0x00
  836. #define REV_ID_VT3119_A1 0x01
  837. #define REV_ID_VT3216_A0 0x10
  838. /*
  839. * Max time out delay time
  840. */
  841. #define W_MAX_TIMEOUT 0x0FFFU
  842. /*
  843. * MAC registers as a structure. Cannot be directly accessed this
  844. * way but generates offsets for readl/writel() calls
  845. */
  846. struct mac_regs {
  847. volatile u8 PAR[6]; /* 0x00 */
  848. volatile u8 RCR;
  849. volatile u8 TCR;
  850. volatile u32 CR0Set; /* 0x08 */
  851. volatile u32 CR0Clr; /* 0x0C */
  852. volatile u8 MARCAM[8]; /* 0x10 */
  853. volatile u32 DecBaseHi; /* 0x18 */
  854. volatile u16 DbfBaseHi; /* 0x1C */
  855. volatile u16 reserved_1E;
  856. volatile u16 ISRCTL; /* 0x20 */
  857. volatile u8 TXESR;
  858. volatile u8 RXESR;
  859. volatile u32 ISR; /* 0x24 */
  860. volatile u32 IMR;
  861. volatile u32 TDStatusPort; /* 0x2C */
  862. volatile u16 TDCSRSet; /* 0x30 */
  863. volatile u8 RDCSRSet;
  864. volatile u8 reserved_33;
  865. volatile u16 TDCSRClr;
  866. volatile u8 RDCSRClr;
  867. volatile u8 reserved_37;
  868. volatile u32 RDBaseLo; /* 0x38 */
  869. volatile u16 RDIdx; /* 0x3C */
  870. volatile u16 reserved_3E;
  871. volatile u32 TDBaseLo[4]; /* 0x40 */
  872. volatile u16 RDCSize; /* 0x50 */
  873. volatile u16 TDCSize; /* 0x52 */
  874. volatile u16 TDIdx[4]; /* 0x54 */
  875. volatile u16 tx_pause_timer; /* 0x5C */
  876. volatile u16 RBRDU; /* 0x5E */
  877. volatile u32 FIFOTest0; /* 0x60 */
  878. volatile u32 FIFOTest1; /* 0x64 */
  879. volatile u8 CAMADDR; /* 0x68 */
  880. volatile u8 CAMCR; /* 0x69 */
  881. volatile u8 GFTEST; /* 0x6A */
  882. volatile u8 FTSTCMD; /* 0x6B */
  883. volatile u8 MIICFG; /* 0x6C */
  884. volatile u8 MIISR;
  885. volatile u8 PHYSR0;
  886. volatile u8 PHYSR1;
  887. volatile u8 MIICR;
  888. volatile u8 MIIADR;
  889. volatile u16 MIIDATA;
  890. volatile u16 SoftTimer0; /* 0x74 */
  891. volatile u16 SoftTimer1;
  892. volatile u8 CFGA; /* 0x78 */
  893. volatile u8 CFGB;
  894. volatile u8 CFGC;
  895. volatile u8 CFGD;
  896. volatile u16 DCFG; /* 0x7C */
  897. volatile u16 MCFG;
  898. volatile u8 TBIST; /* 0x80 */
  899. volatile u8 RBIST;
  900. volatile u8 PMCPORT;
  901. volatile u8 STICKHW;
  902. volatile u8 MIBCR; /* 0x84 */
  903. volatile u8 reserved_85;
  904. volatile u8 rev_id;
  905. volatile u8 PORSTS;
  906. volatile u32 MIBData; /* 0x88 */
  907. volatile u16 EEWrData;
  908. volatile u8 reserved_8E;
  909. volatile u8 BPMDWr;
  910. volatile u8 BPCMD;
  911. volatile u8 BPMDRd;
  912. volatile u8 EECHKSUM; /* 0x92 */
  913. volatile u8 EECSR;
  914. volatile u16 EERdData; /* 0x94 */
  915. volatile u8 EADDR;
  916. volatile u8 EMBCMD;
  917. volatile u8 JMPSR0; /* 0x98 */
  918. volatile u8 JMPSR1;
  919. volatile u8 JMPSR2;
  920. volatile u8 JMPSR3;
  921. volatile u8 CHIPGSR; /* 0x9C */
  922. volatile u8 TESTCFG;
  923. volatile u8 DEBUG;
  924. volatile u8 CHIPGCR;
  925. volatile u16 WOLCRSet; /* 0xA0 */
  926. volatile u8 PWCFGSet;
  927. volatile u8 WOLCFGSet;
  928. volatile u16 WOLCRClr; /* 0xA4 */
  929. volatile u8 PWCFGCLR;
  930. volatile u8 WOLCFGClr;
  931. volatile u16 WOLSRSet; /* 0xA8 */
  932. volatile u16 reserved_AA;
  933. volatile u16 WOLSRClr; /* 0xAC */
  934. volatile u16 reserved_AE;
  935. volatile u16 PatternCRC[8]; /* 0xB0 */
  936. volatile u32 ByteMask[4][4]; /* 0xC0 */
  937. } __attribute__ ((__packed__));
  938. enum hw_mib {
  939. HW_MIB_ifRxAllPkts = 0,
  940. HW_MIB_ifRxOkPkts,
  941. HW_MIB_ifTxOkPkts,
  942. HW_MIB_ifRxErrorPkts,
  943. HW_MIB_ifRxRuntOkPkt,
  944. HW_MIB_ifRxRuntErrPkt,
  945. HW_MIB_ifRx64Pkts,
  946. HW_MIB_ifTx64Pkts,
  947. HW_MIB_ifRx65To127Pkts,
  948. HW_MIB_ifTx65To127Pkts,
  949. HW_MIB_ifRx128To255Pkts,
  950. HW_MIB_ifTx128To255Pkts,
  951. HW_MIB_ifRx256To511Pkts,
  952. HW_MIB_ifTx256To511Pkts,
  953. HW_MIB_ifRx512To1023Pkts,
  954. HW_MIB_ifTx512To1023Pkts,
  955. HW_MIB_ifRx1024To1518Pkts,
  956. HW_MIB_ifTx1024To1518Pkts,
  957. HW_MIB_ifTxEtherCollisions,
  958. HW_MIB_ifRxPktCRCE,
  959. HW_MIB_ifRxJumboPkts,
  960. HW_MIB_ifTxJumboPkts,
  961. HW_MIB_ifRxMacControlFrames,
  962. HW_MIB_ifTxMacControlFrames,
  963. HW_MIB_ifRxPktFAE,
  964. HW_MIB_ifRxLongOkPkt,
  965. HW_MIB_ifRxLongPktErrPkt,
  966. HW_MIB_ifTXSQEErrors,
  967. HW_MIB_ifRxNobuf,
  968. HW_MIB_ifRxSymbolErrors,
  969. HW_MIB_ifInRangeLengthErrors,
  970. HW_MIB_ifLateCollisions,
  971. HW_MIB_SIZE
  972. };
  973. enum chip_type {
  974. CHIP_TYPE_VT6110 = 1,
  975. };
  976. struct velocity_info_tbl {
  977. enum chip_type chip_id;
  978. char *name;
  979. int txqueue;
  980. u32 flags;
  981. };
  982. #define mac_hw_mibs_init(regs) {\
  983. BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
  984. BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
  985. do {}\
  986. while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
  987. BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
  988. }
  989. #define mac_read_isr(regs) readl(&((regs)->ISR))
  990. #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
  991. #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
  992. #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
  993. #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
  994. #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
  995. #define mac_hw_mibs_read(regs, MIBs) {\
  996. int i;\
  997. BYTE_REG_BITS_ON(MIBCR_MPTRINI,&((regs)->MIBCR));\
  998. for (i=0;i<HW_MIB_SIZE;i++) {\
  999. (MIBs)[i]=readl(&((regs)->MIBData));\
  1000. }\
  1001. }
  1002. #define mac_set_dma_length(regs, n) {\
  1003. BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
  1004. }
  1005. #define mac_set_rx_thresh(regs, n) {\
  1006. BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
  1007. }
  1008. #define mac_rx_queue_run(regs) {\
  1009. writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
  1010. }
  1011. #define mac_rx_queue_wake(regs) {\
  1012. writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
  1013. }
  1014. #define mac_tx_queue_run(regs, n) {\
  1015. writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
  1016. }
  1017. #define mac_tx_queue_wake(regs, n) {\
  1018. writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
  1019. }
  1020. #define mac_eeprom_reload(regs) {\
  1021. int i=0;\
  1022. BYTE_REG_BITS_ON(EECSR_RELOAD,&((regs)->EECSR));\
  1023. do {\
  1024. udelay(10);\
  1025. if (i++>0x1000) {\
  1026. break;\
  1027. }\
  1028. }while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&((regs)->EECSR)));\
  1029. }
  1030. enum velocity_cam_type {
  1031. VELOCITY_VLAN_ID_CAM = 0,
  1032. VELOCITY_MULTICAST_CAM
  1033. };
  1034. /**
  1035. * mac_get_cam_mask - Read a CAM mask
  1036. * @regs: register block for this velocity
  1037. * @mask: buffer to store mask
  1038. * @cam_type: CAM to fetch
  1039. *
  1040. * Fetch the mask bits of the selected CAM and store them into the
  1041. * provided mask buffer.
  1042. */
  1043. static inline void mac_get_cam_mask(struct mac_regs __iomem * regs, u8 * mask, enum velocity_cam_type cam_type)
  1044. {
  1045. int i;
  1046. /* Select CAM mask */
  1047. BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1048. if (cam_type == VELOCITY_VLAN_ID_CAM)
  1049. writeb(CAMADDR_VCAMSL, &regs->CAMADDR);
  1050. else
  1051. writeb(0, &regs->CAMADDR);
  1052. /* read mask */
  1053. for (i = 0; i < 8; i++)
  1054. *mask++ = readb(&(regs->MARCAM[i]));
  1055. /* disable CAMEN */
  1056. writeb(0, &regs->CAMADDR);
  1057. /* Select mar */
  1058. BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1059. }
  1060. /**
  1061. * mac_set_cam_mask - Set a CAM mask
  1062. * @regs: register block for this velocity
  1063. * @mask: CAM mask to load
  1064. * @cam_type: CAM to store
  1065. *
  1066. * Store a new mask into a CAM
  1067. */
  1068. static inline void mac_set_cam_mask(struct mac_regs __iomem * regs, u8 * mask, enum velocity_cam_type cam_type)
  1069. {
  1070. int i;
  1071. /* Select CAM mask */
  1072. BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1073. if (cam_type == VELOCITY_VLAN_ID_CAM)
  1074. writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
  1075. else
  1076. writeb(CAMADDR_CAMEN, &regs->CAMADDR);
  1077. for (i = 0; i < 8; i++) {
  1078. writeb(*mask++, &(regs->MARCAM[i]));
  1079. }
  1080. /* disable CAMEN */
  1081. writeb(0, &regs->CAMADDR);
  1082. /* Select mar */
  1083. BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1084. }
  1085. /**
  1086. * mac_set_cam - set CAM data
  1087. * @regs: register block of this velocity
  1088. * @idx: Cam index
  1089. * @addr: 2 or 6 bytes of CAM data
  1090. * @cam_type: CAM to load
  1091. *
  1092. * Load an address or vlan tag into a CAM
  1093. */
  1094. static inline void mac_set_cam(struct mac_regs __iomem * regs, int idx, u8 *addr, enum velocity_cam_type cam_type)
  1095. {
  1096. int i;
  1097. /* Select CAM mask */
  1098. BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1099. idx &= (64 - 1);
  1100. if (cam_type == VELOCITY_VLAN_ID_CAM)
  1101. writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
  1102. else
  1103. writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
  1104. if (cam_type == VELOCITY_VLAN_ID_CAM)
  1105. writew(*((u16 *) addr), &regs->MARCAM[0]);
  1106. else {
  1107. for (i = 0; i < 6; i++) {
  1108. writeb(*addr++, &(regs->MARCAM[i]));
  1109. }
  1110. }
  1111. BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
  1112. udelay(10);
  1113. writeb(0, &regs->CAMADDR);
  1114. /* Select mar */
  1115. BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1116. }
  1117. /**
  1118. * mac_get_cam - fetch CAM data
  1119. * @regs: register block of this velocity
  1120. * @idx: Cam index
  1121. * @addr: buffer to hold up to 6 bytes of CAM data
  1122. * @cam_type: CAM to load
  1123. *
  1124. * Load an address or vlan tag from a CAM into the buffer provided by
  1125. * the caller. VLAN tags are 2 bytes the address cam entries are 6.
  1126. */
  1127. static inline void mac_get_cam(struct mac_regs __iomem * regs, int idx, u8 *addr, enum velocity_cam_type cam_type)
  1128. {
  1129. int i;
  1130. /* Select CAM mask */
  1131. BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1132. idx &= (64 - 1);
  1133. if (cam_type == VELOCITY_VLAN_ID_CAM)
  1134. writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
  1135. else
  1136. writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
  1137. BYTE_REG_BITS_ON(CAMCR_CAMRD, &regs->CAMCR);
  1138. udelay(10);
  1139. if (cam_type == VELOCITY_VLAN_ID_CAM)
  1140. *((u16 *) addr) = readw(&(regs->MARCAM[0]));
  1141. else
  1142. for (i = 0; i < 6; i++, addr++)
  1143. *((u8 *) addr) = readb(&(regs->MARCAM[i]));
  1144. writeb(0, &regs->CAMADDR);
  1145. /* Select mar */
  1146. BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
  1147. }
  1148. /**
  1149. * mac_wol_reset - reset WOL after exiting low power
  1150. * @regs: register block of this velocity
  1151. *
  1152. * Called after we drop out of wake on lan mode in order to
  1153. * reset the Wake on lan features. This function doesn't restore
  1154. * the rest of the logic from the result of sleep/wakeup
  1155. */
  1156. static inline void mac_wol_reset(struct mac_regs __iomem * regs)
  1157. {
  1158. /* Turn off SWPTAG right after leaving power mode */
  1159. BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
  1160. /* clear sticky bits */
  1161. BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
  1162. BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
  1163. BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
  1164. /* disable force PME-enable */
  1165. writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
  1166. /* disable power-event config bit */
  1167. writew(0xFFFF, &regs->WOLCRClr);
  1168. /* clear power status */
  1169. writew(0xFFFF, &regs->WOLSRClr);
  1170. }
  1171. /*
  1172. * Header for WOL definitions. Used to compute hashes
  1173. */
  1174. typedef u8 MCAM_ADDR[ETH_ALEN];
  1175. struct arp_packet {
  1176. u8 dest_mac[ETH_ALEN];
  1177. u8 src_mac[ETH_ALEN];
  1178. u16 type;
  1179. u16 ar_hrd;
  1180. u16 ar_pro;
  1181. u8 ar_hln;
  1182. u8 ar_pln;
  1183. u16 ar_op;
  1184. u8 ar_sha[ETH_ALEN];
  1185. u8 ar_sip[4];
  1186. u8 ar_tha[ETH_ALEN];
  1187. u8 ar_tip[4];
  1188. } __attribute__ ((__packed__));
  1189. struct _magic_packet {
  1190. u8 dest_mac[6];
  1191. u8 src_mac[6];
  1192. u16 type;
  1193. u8 MAC[16][6];
  1194. u8 password[6];
  1195. } __attribute__ ((__packed__));
  1196. /*
  1197. * Store for chip context when saving and restoring status. Not
  1198. * all fields are saved/restored currently.
  1199. */
  1200. struct velocity_context {
  1201. u8 mac_reg[256];
  1202. MCAM_ADDR cam_addr[MCAM_SIZE];
  1203. u16 vcam[VCAM_SIZE];
  1204. u32 cammask[2];
  1205. u32 patcrc[2];
  1206. u32 pattern[8];
  1207. };
  1208. /*
  1209. * MII registers.
  1210. */
  1211. /*
  1212. * Registers in the MII (offset unit is WORD)
  1213. */
  1214. #define MII_REG_BMCR 0x00 // physical address
  1215. #define MII_REG_BMSR 0x01 //
  1216. #define MII_REG_PHYID1 0x02 // OUI
  1217. #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
  1218. #define MII_REG_ANAR 0x04 //
  1219. #define MII_REG_ANLPAR 0x05 //
  1220. #define MII_REG_G1000CR 0x09 //
  1221. #define MII_REG_G1000SR 0x0A //
  1222. #define MII_REG_MODCFG 0x10 //
  1223. #define MII_REG_TCSR 0x16 //
  1224. #define MII_REG_PLED 0x1B //
  1225. // NS, MYSON only
  1226. #define MII_REG_PCR 0x17 //
  1227. // ESI only
  1228. #define MII_REG_PCSR 0x17 //
  1229. #define MII_REG_AUXCR 0x1C //
  1230. // Marvell 88E1000/88E1000S
  1231. #define MII_REG_PSCR 0x10 // PHY specific control register
  1232. //
  1233. // Bits in the BMCR register
  1234. //
  1235. #define BMCR_RESET 0x8000 //
  1236. #define BMCR_LBK 0x4000 //
  1237. #define BMCR_SPEED100 0x2000 //
  1238. #define BMCR_AUTO 0x1000 //
  1239. #define BMCR_PD 0x0800 //
  1240. #define BMCR_ISO 0x0400 //
  1241. #define BMCR_REAUTO 0x0200 //
  1242. #define BMCR_FDX 0x0100 //
  1243. #define BMCR_SPEED1G 0x0040 //
  1244. //
  1245. // Bits in the BMSR register
  1246. //
  1247. #define BMSR_AUTOCM 0x0020 //
  1248. #define BMSR_LNK 0x0004 //
  1249. //
  1250. // Bits in the ANAR register
  1251. //
  1252. #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
  1253. #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
  1254. #define ANAR_T4 0x0200 //
  1255. #define ANAR_TXFD 0x0100 //
  1256. #define ANAR_TX 0x0080 //
  1257. #define ANAR_10FD 0x0040 //
  1258. #define ANAR_10 0x0020 //
  1259. //
  1260. // Bits in the ANLPAR register
  1261. //
  1262. #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
  1263. #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
  1264. #define ANLPAR_T4 0x0200 //
  1265. #define ANLPAR_TXFD 0x0100 //
  1266. #define ANLPAR_TX 0x0080 //
  1267. #define ANLPAR_10FD 0x0040 //
  1268. #define ANLPAR_10 0x0020 //
  1269. //
  1270. // Bits in the G1000CR register
  1271. //
  1272. #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
  1273. #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
  1274. //
  1275. // Bits in the G1000SR register
  1276. //
  1277. #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
  1278. #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
  1279. #define TCSR_ECHODIS 0x2000 //
  1280. #define AUXCR_MDPPS 0x0004 //
  1281. // Bits in the PLED register
  1282. #define PLED_LALBE 0x0004 //
  1283. // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
  1284. #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
  1285. #define PHYID_CICADA_CS8201 0x000FC410UL
  1286. #define PHYID_VT3216_32BIT 0x000FC610UL
  1287. #define PHYID_VT3216_64BIT 0x000FC600UL
  1288. #define PHYID_MARVELL_1000 0x01410C50UL
  1289. #define PHYID_MARVELL_1000S 0x01410C40UL
  1290. #define PHYID_REV_ID_MASK 0x0000000FUL
  1291. #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
  1292. #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
  1293. #define MII_REG_BITS_ON(x,i,p) do {\
  1294. u16 w;\
  1295. velocity_mii_read((p),(i),&(w));\
  1296. (w)|=(x);\
  1297. velocity_mii_write((p),(i),(w));\
  1298. } while (0)
  1299. #define MII_REG_BITS_OFF(x,i,p) do {\
  1300. u16 w;\
  1301. velocity_mii_read((p),(i),&(w));\
  1302. (w)&=(~(x));\
  1303. velocity_mii_write((p),(i),(w));\
  1304. } while (0)
  1305. #define MII_REG_BITS_IS_ON(x,i,p) ({\
  1306. u16 w;\
  1307. velocity_mii_read((p),(i),&(w));\
  1308. ((int) ((w) & (x)));})
  1309. #define MII_GET_PHY_ID(p) ({\
  1310. u32 id;\
  1311. velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\
  1312. velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\
  1313. (id);})
  1314. /*
  1315. * Inline debug routine
  1316. */
  1317. enum velocity_msg_level {
  1318. MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
  1319. MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
  1320. MSG_LEVEL_INFO = 2, //Normal message.
  1321. MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
  1322. MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
  1323. };
  1324. #ifdef VELOCITY_DEBUG
  1325. #define ASSERT(x) { \
  1326. if (!(x)) { \
  1327. printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
  1328. __FUNCTION__, __LINE__);\
  1329. BUG(); \
  1330. }\
  1331. }
  1332. #define VELOCITY_DBG(p,args...) printk(p, ##args)
  1333. #else
  1334. #define ASSERT(x)
  1335. #define VELOCITY_DBG(x)
  1336. #endif
  1337. #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0)
  1338. #define VELOCITY_PRT_CAMMASK(p,t) {\
  1339. int i;\
  1340. if ((t)==VELOCITY_MULTICAST_CAM) {\
  1341. for (i=0;i<(MCAM_SIZE/8);i++)\
  1342. printk("%02X",(p)->mCAMmask[i]);\
  1343. }\
  1344. else {\
  1345. for (i=0;i<(VCAM_SIZE/8);i++)\
  1346. printk("%02X",(p)->vCAMmask[i]);\
  1347. }\
  1348. printk("\n");\
  1349. }
  1350. #define VELOCITY_WOL_MAGIC 0x00000000UL
  1351. #define VELOCITY_WOL_PHY 0x00000001UL
  1352. #define VELOCITY_WOL_ARP 0x00000002UL
  1353. #define VELOCITY_WOL_UCAST 0x00000004UL
  1354. #define VELOCITY_WOL_BCAST 0x00000010UL
  1355. #define VELOCITY_WOL_MCAST 0x00000020UL
  1356. #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
  1357. /*
  1358. * Flags for options
  1359. */
  1360. #define VELOCITY_FLAGS_TAGGING 0x00000001UL
  1361. #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL
  1362. #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
  1363. #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
  1364. #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
  1365. #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
  1366. /*
  1367. * Flags for driver status
  1368. */
  1369. #define VELOCITY_FLAGS_OPENED 0x00010000UL
  1370. #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
  1371. #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
  1372. #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
  1373. /*
  1374. * Flags for MII status
  1375. */
  1376. #define VELOCITY_LINK_FAIL 0x00000001UL
  1377. #define VELOCITY_SPEED_10 0x00000002UL
  1378. #define VELOCITY_SPEED_100 0x00000004UL
  1379. #define VELOCITY_SPEED_1000 0x00000008UL
  1380. #define VELOCITY_DUPLEX_FULL 0x00000010UL
  1381. #define VELOCITY_AUTONEG_ENABLE 0x00000020UL
  1382. #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
  1383. /*
  1384. * For velocity_set_media_duplex
  1385. */
  1386. #define VELOCITY_LINK_CHANGE 0x00000001UL
  1387. enum speed_opt {
  1388. SPD_DPX_AUTO = 0,
  1389. SPD_DPX_100_HALF = 1,
  1390. SPD_DPX_100_FULL = 2,
  1391. SPD_DPX_10_HALF = 3,
  1392. SPD_DPX_10_FULL = 4
  1393. };
  1394. enum velocity_init_type {
  1395. VELOCITY_INIT_COLD = 0,
  1396. VELOCITY_INIT_RESET,
  1397. VELOCITY_INIT_WOL
  1398. };
  1399. enum velocity_flow_cntl_type {
  1400. FLOW_CNTL_DEFAULT = 1,
  1401. FLOW_CNTL_TX,
  1402. FLOW_CNTL_RX,
  1403. FLOW_CNTL_TX_RX,
  1404. FLOW_CNTL_DISABLE,
  1405. };
  1406. struct velocity_opt {
  1407. int numrx; /* Number of RX descriptors */
  1408. int numtx; /* Number of TX descriptors */
  1409. enum speed_opt spd_dpx; /* Media link mode */
  1410. int vid; /* vlan id */
  1411. int DMA_length; /* DMA length */
  1412. int rx_thresh; /* RX_THRESH */
  1413. int flow_cntl;
  1414. int wol_opts; /* Wake on lan options */
  1415. int td_int_count;
  1416. int int_works;
  1417. int rx_bandwidth_hi;
  1418. int rx_bandwidth_lo;
  1419. int rx_bandwidth_en;
  1420. u32 flags;
  1421. };
  1422. struct velocity_info {
  1423. struct list_head list;
  1424. struct pci_dev *pdev;
  1425. struct net_device *dev;
  1426. struct net_device_stats stats;
  1427. dma_addr_t rd_pool_dma;
  1428. dma_addr_t td_pool_dma[TX_QUEUE_NO];
  1429. dma_addr_t tx_bufs_dma;
  1430. u8 *tx_bufs;
  1431. u8 ip_addr[4];
  1432. enum chip_type chip_id;
  1433. struct mac_regs __iomem * mac_regs;
  1434. unsigned long memaddr;
  1435. unsigned long ioaddr;
  1436. u8 rev_id;
  1437. #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)]))
  1438. int num_txq;
  1439. volatile int td_used[TX_QUEUE_NO];
  1440. int td_curr[TX_QUEUE_NO];
  1441. int td_tail[TX_QUEUE_NO];
  1442. struct tx_desc *td_rings[TX_QUEUE_NO];
  1443. struct velocity_td_info *td_infos[TX_QUEUE_NO];
  1444. int rd_curr;
  1445. int rd_dirty;
  1446. u32 rd_filled;
  1447. struct rx_desc *rd_ring;
  1448. struct velocity_rd_info *rd_info; /* It's an array */
  1449. #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
  1450. u32 mib_counter[MAX_HW_MIB_COUNTER];
  1451. struct velocity_opt options;
  1452. u32 int_mask;
  1453. u32 flags;
  1454. int rx_buf_sz;
  1455. u32 mii_status;
  1456. u32 phy_id;
  1457. int multicast_limit;
  1458. u8 vCAMmask[(VCAM_SIZE / 8)];
  1459. u8 mCAMmask[(MCAM_SIZE / 8)];
  1460. spinlock_t lock;
  1461. int wol_opts;
  1462. u8 wol_passwd[6];
  1463. struct velocity_context context;
  1464. u32 ticks;
  1465. u32 rx_bytes;
  1466. };
  1467. /**
  1468. * velocity_get_ip - find an IP address for the device
  1469. * @vptr: Velocity to query
  1470. *
  1471. * Dig out an IP address for this interface so that we can
  1472. * configure wakeup with WOL for ARP. If there are multiple IP
  1473. * addresses on this chain then we use the first - multi-IP WOL is not
  1474. * supported.
  1475. *
  1476. * CHECK ME: locking
  1477. */
  1478. static inline int velocity_get_ip(struct velocity_info *vptr)
  1479. {
  1480. struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
  1481. struct in_ifaddr *ifa;
  1482. if (in_dev != NULL) {
  1483. ifa = (struct in_ifaddr *) in_dev->ifa_list;
  1484. if (ifa != NULL) {
  1485. memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
  1486. return 0;
  1487. }
  1488. }
  1489. return -ENOENT;
  1490. }
  1491. /**
  1492. * velocity_update_hw_mibs - fetch MIB counters from chip
  1493. * @vptr: velocity to update
  1494. *
  1495. * The velocity hardware keeps certain counters in the hardware
  1496. * side. We need to read these when the user asks for statistics
  1497. * or when they overflow (causing an interrupt). The read of the
  1498. * statistic clears it, so we keep running master counters in user
  1499. * space.
  1500. */
  1501. static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
  1502. {
  1503. u32 tmp;
  1504. int i;
  1505. BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
  1506. while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
  1507. BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
  1508. for (i = 0; i < HW_MIB_SIZE; i++) {
  1509. tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
  1510. vptr->mib_counter[i] += tmp;
  1511. }
  1512. }
  1513. /**
  1514. * init_flow_control_register - set up flow control
  1515. * @vptr: velocity to configure
  1516. *
  1517. * Configure the flow control registers for this velocity device.
  1518. */
  1519. static inline void init_flow_control_register(struct velocity_info *vptr)
  1520. {
  1521. struct mac_regs __iomem * regs = vptr->mac_regs;
  1522. /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
  1523. depend on RD=64, and Turn on XNOEN in FlowCR1 */
  1524. writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), &regs->CR0Set);
  1525. writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), &regs->CR0Clr);
  1526. /* Set TxPauseTimer to 0xFFFF */
  1527. writew(0xFFFF, &regs->tx_pause_timer);
  1528. /* Initialize RBRDU to Rx buffer count. */
  1529. writew(vptr->options.numrx, &regs->RBRDU);
  1530. }
  1531. #endif