ucc_geth_phy.h 6.9 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Author: Shlomi Gridish <gridish@freescale.com>
  5. *
  6. * Description:
  7. * UCC GETH Driver -- PHY handling
  8. *
  9. * Changelog:
  10. * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11. * - Rearrange code and style fixes
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. *
  18. */
  19. #ifndef __UCC_GETH_PHY_H__
  20. #define __UCC_GETH_PHY_H__
  21. #define MII_end ((u32)-2)
  22. #define MII_read ((u32)-1)
  23. #define MIIMIND_BUSY 0x00000001
  24. #define MIIMIND_NOTVALID 0x00000004
  25. #define UGETH_AN_TIMEOUT 2000
  26. /* 1000BT control (Marvell & BCM54xx at least) */
  27. #define MII_1000BASETCONTROL 0x09
  28. #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
  29. #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
  30. /* Cicada Extended Control Register 1 */
  31. #define MII_CIS8201_EXT_CON1 0x17
  32. #define MII_CIS8201_EXTCON1_INIT 0x0000
  33. /* Cicada Interrupt Mask Register */
  34. #define MII_CIS8201_IMASK 0x19
  35. #define MII_CIS8201_IMASK_IEN 0x8000
  36. #define MII_CIS8201_IMASK_SPEED 0x4000
  37. #define MII_CIS8201_IMASK_LINK 0x2000
  38. #define MII_CIS8201_IMASK_DUPLEX 0x1000
  39. #define MII_CIS8201_IMASK_MASK 0xf000
  40. /* Cicada Interrupt Status Register */
  41. #define MII_CIS8201_ISTAT 0x1a
  42. #define MII_CIS8201_ISTAT_STATUS 0x8000
  43. #define MII_CIS8201_ISTAT_SPEED 0x4000
  44. #define MII_CIS8201_ISTAT_LINK 0x2000
  45. #define MII_CIS8201_ISTAT_DUPLEX 0x1000
  46. /* Cicada Auxiliary Control/Status Register */
  47. #define MII_CIS8201_AUX_CONSTAT 0x1c
  48. #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
  49. #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
  50. #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
  51. #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
  52. #define MII_CIS8201_AUXCONSTAT_100 0x0008
  53. /* 88E1011 PHY Status Register */
  54. #define MII_M1011_PHY_SPEC_STATUS 0x11
  55. #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
  56. #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
  57. #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
  58. #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
  59. #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
  60. #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
  61. #define MII_M1011_IEVENT 0x13
  62. #define MII_M1011_IEVENT_CLEAR 0x0000
  63. #define MII_M1011_IMASK 0x12
  64. #define MII_M1011_IMASK_INIT 0x6400
  65. #define MII_M1011_IMASK_CLEAR 0x0000
  66. #define MII_DM9161_SCR 0x10
  67. #define MII_DM9161_SCR_INIT 0x0610
  68. /* DM9161 Specified Configuration and Status Register */
  69. #define MII_DM9161_SCSR 0x11
  70. #define MII_DM9161_SCSR_100F 0x8000
  71. #define MII_DM9161_SCSR_100H 0x4000
  72. #define MII_DM9161_SCSR_10F 0x2000
  73. #define MII_DM9161_SCSR_10H 0x1000
  74. /* DM9161 Interrupt Register */
  75. #define MII_DM9161_INTR 0x15
  76. #define MII_DM9161_INTR_PEND 0x8000
  77. #define MII_DM9161_INTR_DPLX_MASK 0x0800
  78. #define MII_DM9161_INTR_SPD_MASK 0x0400
  79. #define MII_DM9161_INTR_LINK_MASK 0x0200
  80. #define MII_DM9161_INTR_MASK 0x0100
  81. #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
  82. #define MII_DM9161_INTR_SPD_CHANGE 0x0008
  83. #define MII_DM9161_INTR_LINK_CHANGE 0x0004
  84. #define MII_DM9161_INTR_INIT 0x0000
  85. #define MII_DM9161_INTR_STOP \
  86. (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
  87. | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
  88. /* DM9161 10BT Configuration/Status */
  89. #define MII_DM9161_10BTCSR 0x12
  90. #define MII_DM9161_10BTCSR_INIT 0x7800
  91. #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
  92. SUPPORTED_10baseT_Full | \
  93. SUPPORTED_100baseT_Half | \
  94. SUPPORTED_100baseT_Full | \
  95. SUPPORTED_Autoneg | \
  96. SUPPORTED_TP | \
  97. SUPPORTED_MII)
  98. #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
  99. SUPPORTED_1000baseT_Half | \
  100. SUPPORTED_1000baseT_Full)
  101. #define MII_READ_COMMAND 0x00000001
  102. #define MII_INTERRUPT_DISABLED 0x0
  103. #define MII_INTERRUPT_ENABLED 0x1
  104. /* Taken from mii_if_info and sungem_phy.h */
  105. struct ugeth_mii_info {
  106. /* Information about the PHY type */
  107. /* And management functions */
  108. struct phy_info *phyinfo;
  109. struct ucc_mii_mng *mii_regs;
  110. /* forced speed & duplex (no autoneg)
  111. * partner speed & duplex & pause (autoneg)
  112. */
  113. int speed;
  114. int duplex;
  115. int pause;
  116. /* The most recently read link state */
  117. int link;
  118. /* Enabled Interrupts */
  119. u32 interrupts;
  120. u32 advertising;
  121. int autoneg;
  122. int mii_id;
  123. /* private data pointer */
  124. /* For use by PHYs to maintain extra state */
  125. void *priv;
  126. /* Provided by host chip */
  127. struct net_device *dev;
  128. /* A lock to ensure that only one thing can read/write
  129. * the MDIO bus at a time */
  130. spinlock_t mdio_lock;
  131. /* Provided by ethernet driver */
  132. int (*mdio_read) (struct net_device * dev, int mii_id, int reg);
  133. void (*mdio_write) (struct net_device * dev, int mii_id, int reg,
  134. int val);
  135. };
  136. /* struct phy_info: a structure which defines attributes for a PHY
  137. *
  138. * id will contain a number which represents the PHY. During
  139. * startup, the driver will poll the PHY to find out what its
  140. * UID--as defined by registers 2 and 3--is. The 32-bit result
  141. * gotten from the PHY will be ANDed with phy_id_mask to
  142. * discard any bits which may change based on revision numbers
  143. * unimportant to functionality
  144. *
  145. * There are 6 commands which take a ugeth_mii_info structure.
  146. * Each PHY must declare config_aneg, and read_status.
  147. */
  148. struct phy_info {
  149. u32 phy_id;
  150. char *name;
  151. unsigned int phy_id_mask;
  152. u32 features;
  153. /* Called to initialize the PHY */
  154. int (*init) (struct ugeth_mii_info * mii_info);
  155. /* Called to suspend the PHY for power */
  156. int (*suspend) (struct ugeth_mii_info * mii_info);
  157. /* Reconfigures autonegotiation (or disables it) */
  158. int (*config_aneg) (struct ugeth_mii_info * mii_info);
  159. /* Determines the negotiated speed and duplex */
  160. int (*read_status) (struct ugeth_mii_info * mii_info);
  161. /* Clears any pending interrupts */
  162. int (*ack_interrupt) (struct ugeth_mii_info * mii_info);
  163. /* Enables or disables interrupts */
  164. int (*config_intr) (struct ugeth_mii_info * mii_info);
  165. /* Clears up any memory if needed */
  166. void (*close) (struct ugeth_mii_info * mii_info);
  167. };
  168. struct phy_info *get_phy_info(struct ugeth_mii_info *mii_info);
  169. void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value);
  170. int read_phy_reg(struct net_device *dev, int mii_id, int regnum);
  171. void mii_clear_phy_interrupt(struct ugeth_mii_info *mii_info);
  172. void mii_configure_phy_interrupt(struct ugeth_mii_info *mii_info,
  173. u32 interrupts);
  174. struct dm9161_private {
  175. struct timer_list timer;
  176. int resetdone;
  177. };
  178. #endif /* __UCC_GETH_PHY_H__ */