ucc_geth_phy.c 20 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Author: Shlomi Gridish <gridish@freescale.com>
  5. *
  6. * Description:
  7. * UCC GETH Driver -- PHY handling
  8. *
  9. * Changelog:
  10. * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11. * - Rearrange code and style fixes
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. *
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/string.h>
  21. #include <linux/errno.h>
  22. #include <linux/slab.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/init.h>
  25. #include <linux/delay.h>
  26. #include <linux/netdevice.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/skbuff.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/mm.h>
  31. #include <linux/module.h>
  32. #include <linux/version.h>
  33. #include <linux/crc32.h>
  34. #include <linux/mii.h>
  35. #include <linux/ethtool.h>
  36. #include <asm/io.h>
  37. #include <asm/irq.h>
  38. #include <asm/uaccess.h>
  39. #include "ucc_geth.h"
  40. #include "ucc_geth_phy.h"
  41. #define ugphy_printk(level, format, arg...) \
  42. printk(level format "\n", ## arg)
  43. #define ugphy_dbg(format, arg...) \
  44. ugphy_printk(KERN_DEBUG, format , ## arg)
  45. #define ugphy_err(format, arg...) \
  46. ugphy_printk(KERN_ERR, format , ## arg)
  47. #define ugphy_info(format, arg...) \
  48. ugphy_printk(KERN_INFO, format , ## arg)
  49. #define ugphy_warn(format, arg...) \
  50. ugphy_printk(KERN_WARNING, format , ## arg)
  51. #ifdef UGETH_VERBOSE_DEBUG
  52. #define ugphy_vdbg ugphy_dbg
  53. #else
  54. #define ugphy_vdbg(fmt, args...) do { } while (0)
  55. #endif /* UGETH_VERBOSE_DEBUG */
  56. static void config_genmii_advert(struct ugeth_mii_info *mii_info);
  57. static void genmii_setup_forced(struct ugeth_mii_info *mii_info);
  58. static void genmii_restart_aneg(struct ugeth_mii_info *mii_info);
  59. static int gbit_config_aneg(struct ugeth_mii_info *mii_info);
  60. static int genmii_config_aneg(struct ugeth_mii_info *mii_info);
  61. static int genmii_update_link(struct ugeth_mii_info *mii_info);
  62. static int genmii_read_status(struct ugeth_mii_info *mii_info);
  63. static u16 ucc_geth_phy_read(struct ugeth_mii_info *mii_info, u16 regnum)
  64. {
  65. u16 retval;
  66. unsigned long flags;
  67. ugphy_vdbg("%s: IN", __FUNCTION__);
  68. spin_lock_irqsave(&mii_info->mdio_lock, flags);
  69. retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
  70. spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
  71. return retval;
  72. }
  73. static void ucc_geth_phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val)
  74. {
  75. unsigned long flags;
  76. ugphy_vdbg("%s: IN", __FUNCTION__);
  77. spin_lock_irqsave(&mii_info->mdio_lock, flags);
  78. mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
  79. spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
  80. }
  81. /* Write value to the PHY for this device to the register at regnum, */
  82. /* waiting until the write is done before it returns. All PHY */
  83. /* configuration has to be done through the TSEC1 MIIM regs */
  84. void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value)
  85. {
  86. struct ucc_geth_private *ugeth = netdev_priv(dev);
  87. struct ucc_mii_mng *mii_regs;
  88. enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
  89. u32 tmp_reg;
  90. ugphy_vdbg("%s: IN", __FUNCTION__);
  91. spin_lock_irq(&ugeth->lock);
  92. mii_regs = ugeth->mii_info->mii_regs;
  93. /* Set this UCC to be the master of the MII managment */
  94. ucc_set_qe_mux_mii_mng(ugeth->ug_info->uf_info.ucc_num);
  95. /* Stop the MII management read cycle */
  96. out_be32(&mii_regs->miimcom, 0);
  97. /* Setting up the MII Mangement Address Register */
  98. tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
  99. out_be32(&mii_regs->miimadd, tmp_reg);
  100. /* Setting up the MII Mangement Control Register with the value */
  101. out_be32(&mii_regs->miimcon, (u32) value);
  102. /* Wait till MII management write is complete */
  103. while ((in_be32(&mii_regs->miimind)) & MIIMIND_BUSY)
  104. cpu_relax();
  105. spin_unlock_irq(&ugeth->lock);
  106. udelay(10000);
  107. }
  108. /* Reads from register regnum in the PHY for device dev, */
  109. /* returning the value. Clears miimcom first. All PHY */
  110. /* configuration has to be done through the TSEC1 MIIM regs */
  111. int read_phy_reg(struct net_device *dev, int mii_id, int regnum)
  112. {
  113. struct ucc_geth_private *ugeth = netdev_priv(dev);
  114. struct ucc_mii_mng *mii_regs;
  115. enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
  116. u32 tmp_reg;
  117. u16 value;
  118. ugphy_vdbg("%s: IN", __FUNCTION__);
  119. spin_lock_irq(&ugeth->lock);
  120. mii_regs = ugeth->mii_info->mii_regs;
  121. /* Setting up the MII Mangement Address Register */
  122. tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
  123. out_be32(&mii_regs->miimadd, tmp_reg);
  124. /* Perform an MII management read cycle */
  125. out_be32(&mii_regs->miimcom, MIIMCOM_READ_CYCLE);
  126. /* Wait till MII management write is complete */
  127. while ((in_be32(&mii_regs->miimind)) & MIIMIND_BUSY)
  128. cpu_relax();
  129. udelay(10000);
  130. /* Read MII management status */
  131. value = (u16) in_be32(&mii_regs->miimstat);
  132. out_be32(&mii_regs->miimcom, 0);
  133. if (value == 0xffff)
  134. ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
  135. mii_id, mii_reg, (u32) & (mii_regs->miimcfg));
  136. spin_unlock_irq(&ugeth->lock);
  137. return (value);
  138. }
  139. void mii_clear_phy_interrupt(struct ugeth_mii_info *mii_info)
  140. {
  141. ugphy_vdbg("%s: IN", __FUNCTION__);
  142. if (mii_info->phyinfo->ack_interrupt)
  143. mii_info->phyinfo->ack_interrupt(mii_info);
  144. }
  145. void mii_configure_phy_interrupt(struct ugeth_mii_info *mii_info,
  146. u32 interrupts)
  147. {
  148. ugphy_vdbg("%s: IN", __FUNCTION__);
  149. mii_info->interrupts = interrupts;
  150. if (mii_info->phyinfo->config_intr)
  151. mii_info->phyinfo->config_intr(mii_info);
  152. }
  153. /* Writes MII_ADVERTISE with the appropriate values, after
  154. * sanitizing advertise to make sure only supported features
  155. * are advertised
  156. */
  157. static void config_genmii_advert(struct ugeth_mii_info *mii_info)
  158. {
  159. u32 advertise;
  160. u16 adv;
  161. ugphy_vdbg("%s: IN", __FUNCTION__);
  162. /* Only allow advertising what this PHY supports */
  163. mii_info->advertising &= mii_info->phyinfo->features;
  164. advertise = mii_info->advertising;
  165. /* Setup standard advertisement */
  166. adv = ucc_geth_phy_read(mii_info, MII_ADVERTISE);
  167. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  168. if (advertise & ADVERTISED_10baseT_Half)
  169. adv |= ADVERTISE_10HALF;
  170. if (advertise & ADVERTISED_10baseT_Full)
  171. adv |= ADVERTISE_10FULL;
  172. if (advertise & ADVERTISED_100baseT_Half)
  173. adv |= ADVERTISE_100HALF;
  174. if (advertise & ADVERTISED_100baseT_Full)
  175. adv |= ADVERTISE_100FULL;
  176. ucc_geth_phy_write(mii_info, MII_ADVERTISE, adv);
  177. }
  178. static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
  179. {
  180. u16 ctrl;
  181. u32 features = mii_info->phyinfo->features;
  182. ugphy_vdbg("%s: IN", __FUNCTION__);
  183. ctrl = ucc_geth_phy_read(mii_info, MII_BMCR);
  184. ctrl &=
  185. ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
  186. ctrl |= BMCR_RESET;
  187. switch (mii_info->speed) {
  188. case SPEED_1000:
  189. if (features & (SUPPORTED_1000baseT_Half
  190. | SUPPORTED_1000baseT_Full)) {
  191. ctrl |= BMCR_SPEED1000;
  192. break;
  193. }
  194. mii_info->speed = SPEED_100;
  195. case SPEED_100:
  196. if (features & (SUPPORTED_100baseT_Half
  197. | SUPPORTED_100baseT_Full)) {
  198. ctrl |= BMCR_SPEED100;
  199. break;
  200. }
  201. mii_info->speed = SPEED_10;
  202. case SPEED_10:
  203. if (features & (SUPPORTED_10baseT_Half
  204. | SUPPORTED_10baseT_Full))
  205. break;
  206. default: /* Unsupported speed! */
  207. ugphy_err("%s: Bad speed!", mii_info->dev->name);
  208. break;
  209. }
  210. ucc_geth_phy_write(mii_info, MII_BMCR, ctrl);
  211. }
  212. /* Enable and Restart Autonegotiation */
  213. static void genmii_restart_aneg(struct ugeth_mii_info *mii_info)
  214. {
  215. u16 ctl;
  216. ugphy_vdbg("%s: IN", __FUNCTION__);
  217. ctl = ucc_geth_phy_read(mii_info, MII_BMCR);
  218. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  219. ucc_geth_phy_write(mii_info, MII_BMCR, ctl);
  220. }
  221. static int gbit_config_aneg(struct ugeth_mii_info *mii_info)
  222. {
  223. u16 adv;
  224. u32 advertise;
  225. ugphy_vdbg("%s: IN", __FUNCTION__);
  226. if (mii_info->autoneg) {
  227. /* Configure the ADVERTISE register */
  228. config_genmii_advert(mii_info);
  229. advertise = mii_info->advertising;
  230. adv = ucc_geth_phy_read(mii_info, MII_1000BASETCONTROL);
  231. adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
  232. MII_1000BASETCONTROL_HALFDUPLEXCAP);
  233. if (advertise & SUPPORTED_1000baseT_Half)
  234. adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
  235. if (advertise & SUPPORTED_1000baseT_Full)
  236. adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
  237. ucc_geth_phy_write(mii_info, MII_1000BASETCONTROL, adv);
  238. /* Start/Restart aneg */
  239. genmii_restart_aneg(mii_info);
  240. } else
  241. genmii_setup_forced(mii_info);
  242. return 0;
  243. }
  244. static int genmii_config_aneg(struct ugeth_mii_info *mii_info)
  245. {
  246. ugphy_vdbg("%s: IN", __FUNCTION__);
  247. if (mii_info->autoneg) {
  248. config_genmii_advert(mii_info);
  249. genmii_restart_aneg(mii_info);
  250. } else
  251. genmii_setup_forced(mii_info);
  252. return 0;
  253. }
  254. static int genmii_update_link(struct ugeth_mii_info *mii_info)
  255. {
  256. u16 status;
  257. ugphy_vdbg("%s: IN", __FUNCTION__);
  258. /* Do a fake read */
  259. ucc_geth_phy_read(mii_info, MII_BMSR);
  260. /* Read link and autonegotiation status */
  261. status = ucc_geth_phy_read(mii_info, MII_BMSR);
  262. if ((status & BMSR_LSTATUS) == 0)
  263. mii_info->link = 0;
  264. else
  265. mii_info->link = 1;
  266. /* If we are autonegotiating, and not done,
  267. * return an error */
  268. if (mii_info->autoneg && !(status & BMSR_ANEGCOMPLETE))
  269. return -EAGAIN;
  270. return 0;
  271. }
  272. static int genmii_read_status(struct ugeth_mii_info *mii_info)
  273. {
  274. u16 status;
  275. int err;
  276. ugphy_vdbg("%s: IN", __FUNCTION__);
  277. /* Update the link, but return if there
  278. * was an error */
  279. err = genmii_update_link(mii_info);
  280. if (err)
  281. return err;
  282. if (mii_info->autoneg) {
  283. status = ucc_geth_phy_read(mii_info, MII_LPA);
  284. if (status & (LPA_10FULL | LPA_100FULL))
  285. mii_info->duplex = DUPLEX_FULL;
  286. else
  287. mii_info->duplex = DUPLEX_HALF;
  288. if (status & (LPA_100FULL | LPA_100HALF))
  289. mii_info->speed = SPEED_100;
  290. else
  291. mii_info->speed = SPEED_10;
  292. mii_info->pause = 0;
  293. }
  294. /* On non-aneg, we assume what we put in BMCR is the speed,
  295. * though magic-aneg shouldn't prevent this case from occurring
  296. */
  297. return 0;
  298. }
  299. static int marvell_init(struct ugeth_mii_info *mii_info)
  300. {
  301. ugphy_vdbg("%s: IN", __FUNCTION__);
  302. ucc_geth_phy_write(mii_info, 0x14, 0x0cd2);
  303. ucc_geth_phy_write(mii_info, 0x1b,
  304. (ucc_geth_phy_read(mii_info, 0x1b) & ~0x000f) | 0x000b);
  305. ucc_geth_phy_write(mii_info, MII_BMCR,
  306. ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
  307. msleep(4000);
  308. return 0;
  309. }
  310. static int marvell_config_aneg(struct ugeth_mii_info *mii_info)
  311. {
  312. ugphy_vdbg("%s: IN", __FUNCTION__);
  313. /* The Marvell PHY has an errata which requires
  314. * that certain registers get written in order
  315. * to restart autonegotiation */
  316. ucc_geth_phy_write(mii_info, MII_BMCR, BMCR_RESET);
  317. ucc_geth_phy_write(mii_info, 0x1d, 0x1f);
  318. ucc_geth_phy_write(mii_info, 0x1e, 0x200c);
  319. ucc_geth_phy_write(mii_info, 0x1d, 0x5);
  320. ucc_geth_phy_write(mii_info, 0x1e, 0);
  321. ucc_geth_phy_write(mii_info, 0x1e, 0x100);
  322. gbit_config_aneg(mii_info);
  323. return 0;
  324. }
  325. static int marvell_read_status(struct ugeth_mii_info *mii_info)
  326. {
  327. u16 status;
  328. int err;
  329. ugphy_vdbg("%s: IN", __FUNCTION__);
  330. /* Update the link, but return if there
  331. * was an error */
  332. err = genmii_update_link(mii_info);
  333. if (err)
  334. return err;
  335. /* If the link is up, read the speed and duplex */
  336. /* If we aren't autonegotiating, assume speeds
  337. * are as set */
  338. if (mii_info->autoneg && mii_info->link) {
  339. int speed;
  340. status = ucc_geth_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
  341. /* Get the duplexity */
  342. if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
  343. mii_info->duplex = DUPLEX_FULL;
  344. else
  345. mii_info->duplex = DUPLEX_HALF;
  346. /* Get the speed */
  347. speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
  348. switch (speed) {
  349. case MII_M1011_PHY_SPEC_STATUS_1000:
  350. mii_info->speed = SPEED_1000;
  351. break;
  352. case MII_M1011_PHY_SPEC_STATUS_100:
  353. mii_info->speed = SPEED_100;
  354. break;
  355. default:
  356. mii_info->speed = SPEED_10;
  357. break;
  358. }
  359. mii_info->pause = 0;
  360. }
  361. return 0;
  362. }
  363. static int marvell_ack_interrupt(struct ugeth_mii_info *mii_info)
  364. {
  365. ugphy_vdbg("%s: IN", __FUNCTION__);
  366. /* Clear the interrupts by reading the reg */
  367. ucc_geth_phy_read(mii_info, MII_M1011_IEVENT);
  368. return 0;
  369. }
  370. static int marvell_config_intr(struct ugeth_mii_info *mii_info)
  371. {
  372. ugphy_vdbg("%s: IN", __FUNCTION__);
  373. if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
  374. ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
  375. else
  376. ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
  377. return 0;
  378. }
  379. static int cis820x_init(struct ugeth_mii_info *mii_info)
  380. {
  381. ugphy_vdbg("%s: IN", __FUNCTION__);
  382. ucc_geth_phy_write(mii_info, MII_CIS8201_AUX_CONSTAT,
  383. MII_CIS8201_AUXCONSTAT_INIT);
  384. ucc_geth_phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT);
  385. return 0;
  386. }
  387. static int cis820x_read_status(struct ugeth_mii_info *mii_info)
  388. {
  389. u16 status;
  390. int err;
  391. ugphy_vdbg("%s: IN", __FUNCTION__);
  392. /* Update the link, but return if there
  393. * was an error */
  394. err = genmii_update_link(mii_info);
  395. if (err)
  396. return err;
  397. /* If the link is up, read the speed and duplex */
  398. /* If we aren't autonegotiating, assume speeds
  399. * are as set */
  400. if (mii_info->autoneg && mii_info->link) {
  401. int speed;
  402. status = ucc_geth_phy_read(mii_info, MII_CIS8201_AUX_CONSTAT);
  403. if (status & MII_CIS8201_AUXCONSTAT_DUPLEX)
  404. mii_info->duplex = DUPLEX_FULL;
  405. else
  406. mii_info->duplex = DUPLEX_HALF;
  407. speed = status & MII_CIS8201_AUXCONSTAT_SPEED;
  408. switch (speed) {
  409. case MII_CIS8201_AUXCONSTAT_GBIT:
  410. mii_info->speed = SPEED_1000;
  411. break;
  412. case MII_CIS8201_AUXCONSTAT_100:
  413. mii_info->speed = SPEED_100;
  414. break;
  415. default:
  416. mii_info->speed = SPEED_10;
  417. break;
  418. }
  419. }
  420. return 0;
  421. }
  422. static int cis820x_ack_interrupt(struct ugeth_mii_info *mii_info)
  423. {
  424. ugphy_vdbg("%s: IN", __FUNCTION__);
  425. ucc_geth_phy_read(mii_info, MII_CIS8201_ISTAT);
  426. return 0;
  427. }
  428. static int cis820x_config_intr(struct ugeth_mii_info *mii_info)
  429. {
  430. ugphy_vdbg("%s: IN", __FUNCTION__);
  431. if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
  432. ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK);
  433. else
  434. ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, 0);
  435. return 0;
  436. }
  437. #define DM9161_DELAY 10
  438. static int dm9161_read_status(struct ugeth_mii_info *mii_info)
  439. {
  440. u16 status;
  441. int err;
  442. ugphy_vdbg("%s: IN", __FUNCTION__);
  443. /* Update the link, but return if there
  444. * was an error */
  445. err = genmii_update_link(mii_info);
  446. if (err)
  447. return err;
  448. /* If the link is up, read the speed and duplex */
  449. /* If we aren't autonegotiating, assume speeds
  450. * are as set */
  451. if (mii_info->autoneg && mii_info->link) {
  452. status = ucc_geth_phy_read(mii_info, MII_DM9161_SCSR);
  453. if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
  454. mii_info->speed = SPEED_100;
  455. else
  456. mii_info->speed = SPEED_10;
  457. if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
  458. mii_info->duplex = DUPLEX_FULL;
  459. else
  460. mii_info->duplex = DUPLEX_HALF;
  461. }
  462. return 0;
  463. }
  464. static int dm9161_config_aneg(struct ugeth_mii_info *mii_info)
  465. {
  466. struct dm9161_private *priv = mii_info->priv;
  467. ugphy_vdbg("%s: IN", __FUNCTION__);
  468. if (0 == priv->resetdone)
  469. return -EAGAIN;
  470. return 0;
  471. }
  472. static void dm9161_timer(unsigned long data)
  473. {
  474. struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
  475. struct dm9161_private *priv = mii_info->priv;
  476. u16 status = ucc_geth_phy_read(mii_info, MII_BMSR);
  477. ugphy_vdbg("%s: IN", __FUNCTION__);
  478. if (status & BMSR_ANEGCOMPLETE) {
  479. priv->resetdone = 1;
  480. } else
  481. mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
  482. }
  483. static int dm9161_init(struct ugeth_mii_info *mii_info)
  484. {
  485. struct dm9161_private *priv;
  486. ugphy_vdbg("%s: IN", __FUNCTION__);
  487. /* Allocate the private data structure */
  488. priv = kmalloc(sizeof(struct dm9161_private), GFP_KERNEL);
  489. if (NULL == priv)
  490. return -ENOMEM;
  491. mii_info->priv = priv;
  492. /* Reset is not done yet */
  493. priv->resetdone = 0;
  494. ucc_geth_phy_write(mii_info, MII_BMCR,
  495. ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
  496. ucc_geth_phy_write(mii_info, MII_BMCR,
  497. ucc_geth_phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE);
  498. config_genmii_advert(mii_info);
  499. /* Start/Restart aneg */
  500. genmii_config_aneg(mii_info);
  501. /* Start a timer for DM9161_DELAY seconds to wait
  502. * for the PHY to be ready */
  503. init_timer(&priv->timer);
  504. priv->timer.function = &dm9161_timer;
  505. priv->timer.data = (unsigned long)mii_info;
  506. mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
  507. return 0;
  508. }
  509. static void dm9161_close(struct ugeth_mii_info *mii_info)
  510. {
  511. struct dm9161_private *priv = mii_info->priv;
  512. ugphy_vdbg("%s: IN", __FUNCTION__);
  513. del_timer_sync(&priv->timer);
  514. kfree(priv);
  515. }
  516. static int dm9161_ack_interrupt(struct ugeth_mii_info *mii_info)
  517. {
  518. ugphy_vdbg("%s: IN", __FUNCTION__);
  519. /* Clear the interrupts by reading the reg */
  520. ucc_geth_phy_read(mii_info, MII_DM9161_INTR);
  521. return 0;
  522. }
  523. static int dm9161_config_intr(struct ugeth_mii_info *mii_info)
  524. {
  525. ugphy_vdbg("%s: IN", __FUNCTION__);
  526. if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
  527. ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
  528. else
  529. ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
  530. return 0;
  531. }
  532. /* Cicada 820x */
  533. static struct phy_info phy_info_cis820x = {
  534. .phy_id = 0x000fc440,
  535. .name = "Cicada Cis8204",
  536. .phy_id_mask = 0x000fffc0,
  537. .features = MII_GBIT_FEATURES,
  538. .init = &cis820x_init,
  539. .config_aneg = &gbit_config_aneg,
  540. .read_status = &cis820x_read_status,
  541. .ack_interrupt = &cis820x_ack_interrupt,
  542. .config_intr = &cis820x_config_intr,
  543. };
  544. static struct phy_info phy_info_dm9161 = {
  545. .phy_id = 0x0181b880,
  546. .phy_id_mask = 0x0ffffff0,
  547. .name = "Davicom DM9161E",
  548. .init = dm9161_init,
  549. .config_aneg = dm9161_config_aneg,
  550. .read_status = dm9161_read_status,
  551. .close = dm9161_close,
  552. };
  553. static struct phy_info phy_info_dm9161a = {
  554. .phy_id = 0x0181b8a0,
  555. .phy_id_mask = 0x0ffffff0,
  556. .name = "Davicom DM9161A",
  557. .features = MII_BASIC_FEATURES,
  558. .init = dm9161_init,
  559. .config_aneg = dm9161_config_aneg,
  560. .read_status = dm9161_read_status,
  561. .ack_interrupt = dm9161_ack_interrupt,
  562. .config_intr = dm9161_config_intr,
  563. .close = dm9161_close,
  564. };
  565. static struct phy_info phy_info_marvell = {
  566. .phy_id = 0x01410c00,
  567. .phy_id_mask = 0xffffff00,
  568. .name = "Marvell 88E11x1",
  569. .features = MII_GBIT_FEATURES,
  570. .init = &marvell_init,
  571. .config_aneg = &marvell_config_aneg,
  572. .read_status = &marvell_read_status,
  573. .ack_interrupt = &marvell_ack_interrupt,
  574. .config_intr = &marvell_config_intr,
  575. };
  576. static struct phy_info phy_info_genmii = {
  577. .phy_id = 0x00000000,
  578. .phy_id_mask = 0x00000000,
  579. .name = "Generic MII",
  580. .features = MII_BASIC_FEATURES,
  581. .config_aneg = genmii_config_aneg,
  582. .read_status = genmii_read_status,
  583. };
  584. static struct phy_info *phy_info[] = {
  585. &phy_info_cis820x,
  586. &phy_info_marvell,
  587. &phy_info_dm9161,
  588. &phy_info_dm9161a,
  589. &phy_info_genmii,
  590. NULL
  591. };
  592. /* Use the PHY ID registers to determine what type of PHY is attached
  593. * to device dev. return a struct phy_info structure describing that PHY
  594. */
  595. struct phy_info *get_phy_info(struct ugeth_mii_info *mii_info)
  596. {
  597. u16 phy_reg;
  598. u32 phy_ID;
  599. int i;
  600. struct phy_info *theInfo = NULL;
  601. struct net_device *dev = mii_info->dev;
  602. ugphy_vdbg("%s: IN", __FUNCTION__);
  603. /* Grab the bits from PHYIR1, and put them in the upper half */
  604. phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID1);
  605. phy_ID = (phy_reg & 0xffff) << 16;
  606. /* Grab the bits from PHYIR2, and put them in the lower half */
  607. phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID2);
  608. phy_ID |= (phy_reg & 0xffff);
  609. /* loop through all the known PHY types, and find one that */
  610. /* matches the ID we read from the PHY. */
  611. for (i = 0; phy_info[i]; i++)
  612. if (phy_info[i]->phy_id == (phy_ID & phy_info[i]->phy_id_mask)){
  613. theInfo = phy_info[i];
  614. break;
  615. }
  616. /* This shouldn't happen, as we have generic PHY support */
  617. if (theInfo == NULL) {
  618. ugphy_info("%s: PHY id %x is not supported!", dev->name,
  619. phy_ID);
  620. return NULL;
  621. } else {
  622. ugphy_info("%s: PHY is %s (%x)", dev->name, theInfo->name,
  623. phy_ID);
  624. }
  625. return theInfo;
  626. }