ucc_geth.h 50 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Author: Shlomi Gridish <gridish@freescale.com>
  5. *
  6. * Description:
  7. * Internal header file for UCC Gigabit Ethernet unit routines.
  8. *
  9. * Changelog:
  10. * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11. * - Rearrange code and style fixes
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #ifndef __UCC_GETH_H__
  19. #define __UCC_GETH_H__
  20. #include <linux/kernel.h>
  21. #include <linux/list.h>
  22. #include <linux/fsl_devices.h>
  23. #include <asm/immap_qe.h>
  24. #include <asm/qe.h>
  25. #include <asm/ucc.h>
  26. #include <asm/ucc_fast.h>
  27. #define NUM_TX_QUEUES 8
  28. #define NUM_RX_QUEUES 8
  29. #define NUM_BDS_IN_PREFETCHED_BDS 4
  30. #define TX_IP_OFFSET_ENTRY_MAX 8
  31. #define NUM_OF_PADDRS 4
  32. #define ENET_INIT_PARAM_MAX_ENTRIES_RX 9
  33. #define ENET_INIT_PARAM_MAX_ENTRIES_TX 8
  34. struct ucc_mii_mng {
  35. u32 miimcfg; /* MII management configuration reg */
  36. u32 miimcom; /* MII management command reg */
  37. u32 miimadd; /* MII management address reg */
  38. u32 miimcon; /* MII management control reg */
  39. u32 miimstat; /* MII management status reg */
  40. u32 miimind; /* MII management indication reg */
  41. } __attribute__ ((packed));
  42. struct ucc_geth {
  43. struct ucc_fast uccf;
  44. u32 maccfg1; /* mac configuration reg. 1 */
  45. u32 maccfg2; /* mac configuration reg. 2 */
  46. u32 ipgifg; /* interframe gap reg. */
  47. u32 hafdup; /* half-duplex reg. */
  48. u8 res1[0x10];
  49. struct ucc_mii_mng miimng; /* MII management structure */
  50. u32 ifctl; /* interface control reg */
  51. u32 ifstat; /* interface statux reg */
  52. u32 macstnaddr1; /* mac station address part 1 reg */
  53. u32 macstnaddr2; /* mac station address part 2 reg */
  54. u8 res2[0x8];
  55. u32 uempr; /* UCC Ethernet Mac parameter reg */
  56. u32 utbipar; /* UCC tbi address reg */
  57. u16 uescr; /* UCC Ethernet statistics control reg */
  58. u8 res3[0x180 - 0x15A];
  59. u32 tx64; /* Total number of frames (including bad
  60. frames) transmitted that were exactly of the
  61. minimal length (64 for un tagged, 68 for
  62. tagged, or with length exactly equal to the
  63. parameter MINLength */
  64. u32 tx127; /* Total number of frames (including bad
  65. frames) transmitted that were between
  66. MINLength (Including FCS length==4) and 127
  67. octets */
  68. u32 tx255; /* Total number of frames (including bad
  69. frames) transmitted that were between 128
  70. (Including FCS length==4) and 255 octets */
  71. u32 rx64; /* Total number of frames received including
  72. bad frames that were exactly of the mninimal
  73. length (64 bytes) */
  74. u32 rx127; /* Total number of frames (including bad
  75. frames) received that were between MINLength
  76. (Including FCS length==4) and 127 octets */
  77. u32 rx255; /* Total number of frames (including bad
  78. frames) received that were between 128
  79. (Including FCS length==4) and 255 octets */
  80. u32 txok; /* Total number of octets residing in frames
  81. that where involved in succesfull
  82. transmission */
  83. u16 txcf; /* Total number of PAUSE control frames
  84. transmitted by this MAC */
  85. u8 res4[0x2];
  86. u32 tmca; /* Total number of frames that were transmitted
  87. succesfully with the group address bit set
  88. that are not broadcast frames */
  89. u32 tbca; /* Total number of frames transmitted
  90. succesfully that had destination address
  91. field equal to the broadcast address */
  92. u32 rxfok; /* Total number of frames received OK */
  93. u32 rxbok; /* Total number of octets received OK */
  94. u32 rbyt; /* Total number of octets received including
  95. octets in bad frames. Must be implemented in
  96. HW because it includes octets in frames that
  97. never even reach the UCC */
  98. u32 rmca; /* Total number of frames that were received
  99. succesfully with the group address bit set
  100. that are not broadcast frames */
  101. u32 rbca; /* Total number of frames received succesfully
  102. that had destination address equal to the
  103. broadcast address */
  104. u32 scar; /* Statistics carry register */
  105. u32 scam; /* Statistics caryy mask register */
  106. u8 res5[0x200 - 0x1c4];
  107. } __attribute__ ((packed));
  108. /* UCC GETH TEMODR Register */
  109. #define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics
  110. */
  111. #define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */
  112. #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4
  113. checksums */
  114. #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance
  115. optimization
  116. enhancement (mode1) */
  117. #define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics
  118. */
  119. #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<
  120. shift */
  121. /* UCC GETH TEMODR Register */
  122. #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx
  123. statistics */
  124. #define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable
  125. extended
  126. features */
  127. #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation
  128. tagged << shift */
  129. #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
  130. tagged << shift */
  131. #define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift
  132. */
  133. #define REMODER_RMON_STATISTICS 0x00001000 /* enable rx
  134. statistics */
  135. #define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended
  136. filtering
  137. vs.
  138. mpc82xx-like
  139. filtering */
  140. #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues <<
  141. shift */
  142. #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable
  143. dynamic max
  144. frame length
  145. */
  146. #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable
  147. dynamic min
  148. frame length
  149. */
  150. #define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4
  151. checksums */
  152. #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip
  153. address to
  154. 4-byte
  155. boundary */
  156. /* UCC GETH Event Register */
  157. #define UCCE_MPD 0x80000000 /* Magic packet
  158. detection */
  159. #define UCCE_SCAR 0x40000000
  160. #define UCCE_GRA 0x20000000 /* Tx graceful
  161. stop
  162. complete */
  163. #define UCCE_CBPR 0x10000000
  164. #define UCCE_BSY 0x08000000
  165. #define UCCE_RXC 0x04000000
  166. #define UCCE_TXC 0x02000000
  167. #define UCCE_TXE 0x01000000
  168. #define UCCE_TXB7 0x00800000
  169. #define UCCE_TXB6 0x00400000
  170. #define UCCE_TXB5 0x00200000
  171. #define UCCE_TXB4 0x00100000
  172. #define UCCE_TXB3 0x00080000
  173. #define UCCE_TXB2 0x00040000
  174. #define UCCE_TXB1 0x00020000
  175. #define UCCE_TXB0 0x00010000
  176. #define UCCE_RXB7 0x00008000
  177. #define UCCE_RXB6 0x00004000
  178. #define UCCE_RXB5 0x00002000
  179. #define UCCE_RXB4 0x00001000
  180. #define UCCE_RXB3 0x00000800
  181. #define UCCE_RXB2 0x00000400
  182. #define UCCE_RXB1 0x00000200
  183. #define UCCE_RXB0 0x00000100
  184. #define UCCE_RXF7 0x00000080
  185. #define UCCE_RXF6 0x00000040
  186. #define UCCE_RXF5 0x00000020
  187. #define UCCE_RXF4 0x00000010
  188. #define UCCE_RXF3 0x00000008
  189. #define UCCE_RXF2 0x00000004
  190. #define UCCE_RXF1 0x00000002
  191. #define UCCE_RXF0 0x00000001
  192. #define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0)
  193. #define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0)
  194. #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\
  195. UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
  196. #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\
  197. UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
  198. #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\
  199. UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
  200. #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\
  201. UCCE_RXC | UCCE_TXC | UCCE_TXE)
  202. /* UCC GETH UPSMR (Protocol Specific Mode Register) */
  203. #define UPSMR_ECM 0x04000000 /* Enable CAM
  204. Miss or
  205. Enable
  206. Filtering
  207. Miss */
  208. #define UPSMR_HSE 0x02000000 /* Hardware
  209. Statistics
  210. Enable */
  211. #define UPSMR_PRO 0x00400000 /* Promiscuous*/
  212. #define UPSMR_CAP 0x00200000 /* CAM polarity
  213. */
  214. #define UPSMR_RSH 0x00100000 /* Receive
  215. Short Frames
  216. */
  217. #define UPSMR_RPM 0x00080000 /* Reduced Pin
  218. Mode
  219. interfaces */
  220. #define UPSMR_R10M 0x00040000 /* RGMII/RMII
  221. 10 Mode */
  222. #define UPSMR_RLPB 0x00020000 /* RMII
  223. Loopback
  224. Mode */
  225. #define UPSMR_TBIM 0x00010000 /* Ten-bit
  226. Interface
  227. Mode */
  228. #define UPSMR_RMM 0x00001000 /* RMII/RGMII
  229. Mode */
  230. #define UPSMR_CAM 0x00000400 /* CAM Address
  231. Matching */
  232. #define UPSMR_BRO 0x00000200 /* Broadcast
  233. Address */
  234. #define UPSMR_RES1 0x00002000 /* Reserved
  235. feild - must
  236. be 1 */
  237. /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
  238. #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
  239. Rx */
  240. #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control
  241. Tx */
  242. #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable
  243. synchronized
  244. to Rx stream
  245. */
  246. #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
  247. #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable
  248. synchronized
  249. to Tx stream
  250. */
  251. #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
  252. /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
  253. #define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble
  254. Length <<
  255. shift */
  256. #define MACCFG2_PREL_MASK 0x0000f000 /* Preamble
  257. Length mask */
  258. #define MACCFG2_SRP 0x00000080 /* Soft Receive
  259. Preamble */
  260. #define MACCFG2_STP 0x00000040 /* Soft
  261. Transmit
  262. Preamble */
  263. #define MACCFG2_RESERVED_1 0x00000020 /* Reserved -
  264. must be set
  265. to 1 */
  266. #define MACCFG2_LC 0x00000010 /* Length Check
  267. */
  268. #define MACCFG2_MPE 0x00000008 /* Magic packet
  269. detect */
  270. #define MACCFG2_FDX 0x00000001 /* Full Duplex */
  271. #define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex
  272. mask */
  273. #define MACCFG2_PAD_CRC 0x00000004
  274. #define MACCFG2_CRC_EN 0x00000002
  275. #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither
  276. Padding
  277. short frames
  278. nor CRC */
  279. #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC
  280. only */
  281. #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
  282. #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode
  283. (MII/RMII/RGMII
  284. 10/100bps) */
  285. #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode
  286. (GMII/TBI/RTB/RGMII
  287. 1000bps ) */
  288. #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask
  289. covering all
  290. relevant
  291. bits */
  292. /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
  293. #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non
  294. back-to-back
  295. inter frame
  296. gap part 1.
  297. << shift */
  298. #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non
  299. back-to-back
  300. inter frame
  301. gap part 2.
  302. << shift */
  303. #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG
  304. Enforcement
  305. << shift */
  306. #define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back
  307. inter frame
  308. gap << shift
  309. */
  310. #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back
  311. inter frame gap part
  312. 1. max val */
  313. #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back
  314. inter frame gap part
  315. 2. max val */
  316. #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG
  317. Enforcement max val */
  318. #define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter
  319. frame gap max val */
  320. #define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000
  321. #define IPGIFG_NBTB_IPG_MASK 0x007F0000
  322. #define IPGIFG_MIN_IFG_MASK 0x0000FF00
  323. #define IPGIFG_BTB_IPG_MASK 0x0000007F
  324. /* UCC GETH HAFDUP (Half Duplex Register) */
  325. #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate
  326. Binary
  327. Exponential
  328. Backoff
  329. Truncation
  330. << shift */
  331. #define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary
  332. Exponential Backoff
  333. Truncation max val */
  334. #define HALFDUP_ALT_BEB 0x00080000 /* Alternate
  335. Binary
  336. Exponential
  337. Backoff */
  338. #define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back
  339. pressure no
  340. backoff */
  341. #define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */
  342. #define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive
  343. Defer */
  344. #define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum
  345. Retransmission
  346. << shift */
  347. #define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum
  348. Retransmission max
  349. val */
  350. #define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision
  351. Window <<
  352. shift */
  353. #define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max
  354. val */
  355. #define HALFDUP_ALT_BEB_TR_MASK 0x00F00000
  356. #define HALFDUP_RETRANS_MASK 0x0000F000
  357. #define HALFDUP_COL_WINDOW_MASK 0x0000003F
  358. /* UCC GETH UCCS (Ethernet Status Register) */
  359. #define UCCS_BPR 0x02 /* Back pressure (in
  360. half duplex mode) */
  361. #define UCCS_PAU 0x02 /* Pause state (in full
  362. duplex mode) */
  363. #define UCCS_MPD 0x01 /* Magic Packet
  364. Detected */
  365. /* UCC GETH MIIMCFG (MII Management Configuration Register) */
  366. #define MIIMCFG_RESET_MANAGEMENT 0x80000000 /* Reset
  367. management */
  368. #define MIIMCFG_NO_PREAMBLE 0x00000010 /* Preamble
  369. suppress */
  370. #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) /* clock divide
  371. << shift */
  372. #define MIIMCFG_CLOCK_DIVIDE_MAX 0xf /* clock divide max val
  373. */
  374. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_2 0x00000000 /* divide by 2 */
  375. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 /* divide by 4 */
  376. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 /* divide by 6 */
  377. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 /* divide by 8 */
  378. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 /* divide by 10
  379. */
  380. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 /* divide by 14
  381. */
  382. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_16 0x00000008 /* divide by 16
  383. */
  384. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 /* divide by 20
  385. */
  386. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 /* divide by 28
  387. */
  388. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_32 0x00000009 /* divide by 32
  389. */
  390. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_48 0x0000000a /* divide by 48
  391. */
  392. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_64 0x0000000b /* divide by 64
  393. */
  394. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_80 0x0000000c /* divide by 80
  395. */
  396. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112 0x0000000d /* divide by
  397. 112 */
  398. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_160 0x0000000e /* divide by
  399. 160 */
  400. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_224 0x0000000f /* divide by
  401. 224 */
  402. /* UCC GETH MIIMCOM (MII Management Command Register) */
  403. #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
  404. #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
  405. /* UCC GETH MIIMADD (MII Management Address Register) */
  406. #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) /* PHY Address
  407. << shift */
  408. #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) /* PHY Register
  409. << shift */
  410. /* UCC GETH MIIMCON (MII Management Control Register) */
  411. #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) /* PHY Control
  412. << shift */
  413. #define MIIMCON_PHY_STATUS_SHIFT (31 - 31) /* PHY Status
  414. << shift */
  415. /* UCC GETH MIIMIND (MII Management Indicator Register) */
  416. #define MIIMIND_NOT_VALID 0x00000004 /* Not valid */
  417. #define MIIMIND_SCAN 0x00000002 /* Scan in
  418. progress */
  419. #define MIIMIND_BUSY 0x00000001
  420. /* UCC GETH IFSTAT (Interface Status Register) */
  421. #define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive
  422. transmission
  423. defer */
  424. /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
  425. #define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station
  426. address 6th
  427. octet <<
  428. shift */
  429. #define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station
  430. address 5th
  431. octet <<
  432. shift */
  433. #define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station
  434. address 4th
  435. octet <<
  436. shift */
  437. #define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station
  438. address 3rd
  439. octet <<
  440. shift */
  441. /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
  442. #define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station
  443. address 2nd
  444. octet <<
  445. shift */
  446. #define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station
  447. address 1st
  448. octet <<
  449. shift */
  450. /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
  451. #define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time
  452. value <<
  453. shift */
  454. #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended
  455. pause time
  456. value <<
  457. shift */
  458. /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
  459. #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address
  460. << shift */
  461. #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address
  462. mask */
  463. /* UCC GETH UESCR (Ethernet Statistics Control Register) */
  464. #define UESCR_AUTOZ 0x8000 /* Automatically zero
  465. addressed
  466. statistical counter
  467. values */
  468. #define UESCR_CLRCNT 0x4000 /* Clear all statistics
  469. counters */
  470. #define UESCR_MAXCOV_SHIFT (15 - 7) /* Max
  471. Coalescing
  472. Value <<
  473. shift */
  474. #define UESCR_SCOV_SHIFT (15 - 15) /* Status
  475. Coalescing
  476. Value <<
  477. shift */
  478. /* UCC GETH UDSR (Data Synchronization Register) */
  479. #define UDSR_MAGIC 0x067E
  480. struct ucc_geth_thread_data_tx {
  481. u8 res0[104];
  482. } __attribute__ ((packed));
  483. struct ucc_geth_thread_data_rx {
  484. u8 res0[40];
  485. } __attribute__ ((packed));
  486. /* Send Queue Queue-Descriptor */
  487. struct ucc_geth_send_queue_qd {
  488. u32 bd_ring_base; /* pointer to BD ring base address */
  489. u8 res0[0x8];
  490. u32 last_bd_completed_address;/* initialize to last entry in BD ring */
  491. u8 res1[0x30];
  492. } __attribute__ ((packed));
  493. struct ucc_geth_send_queue_mem_region {
  494. struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
  495. } __attribute__ ((packed));
  496. struct ucc_geth_thread_tx_pram {
  497. u8 res0[64];
  498. } __attribute__ ((packed));
  499. struct ucc_geth_thread_rx_pram {
  500. u8 res0[128];
  501. } __attribute__ ((packed));
  502. #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64
  503. #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64
  504. #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96
  505. struct ucc_geth_scheduler {
  506. u16 cpucount0; /* CPU packet counter */
  507. u16 cpucount1; /* CPU packet counter */
  508. u16 cecount0; /* QE packet counter */
  509. u16 cecount1; /* QE packet counter */
  510. u16 cpucount2; /* CPU packet counter */
  511. u16 cpucount3; /* CPU packet counter */
  512. u16 cecount2; /* QE packet counter */
  513. u16 cecount3; /* QE packet counter */
  514. u16 cpucount4; /* CPU packet counter */
  515. u16 cpucount5; /* CPU packet counter */
  516. u16 cecount4; /* QE packet counter */
  517. u16 cecount5; /* QE packet counter */
  518. u16 cpucount6; /* CPU packet counter */
  519. u16 cpucount7; /* CPU packet counter */
  520. u16 cecount6; /* QE packet counter */
  521. u16 cecount7; /* QE packet counter */
  522. u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */
  523. u32 rtsrshadow; /* temporary variable handled by QE */
  524. u32 time; /* temporary variable handled by QE */
  525. u32 ttl; /* temporary variable handled by QE */
  526. u32 mblinterval; /* max burst length interval */
  527. u16 nortsrbytetime; /* normalized value of byte time in tsr units */
  528. u8 fracsiz; /* radix 2 log value of denom. of
  529. NorTSRByteTime */
  530. u8 res0[1];
  531. u8 strictpriorityq; /* Strict Priority Mask register */
  532. u8 txasap; /* Transmit ASAP register */
  533. u8 extrabw; /* Extra BandWidth register */
  534. u8 oldwfqmask; /* temporary variable handled by QE */
  535. u8 weightfactor[NUM_TX_QUEUES];
  536. /**< weight factor for queues */
  537. u32 minw; /* temporary variable handled by QE */
  538. u8 res1[0x70 - 0x64];
  539. } __attribute__ ((packed));
  540. struct ucc_geth_tx_firmware_statistics_pram {
  541. u32 sicoltx; /* single collision */
  542. u32 mulcoltx; /* multiple collision */
  543. u32 latecoltxfr; /* late collision */
  544. u32 frabortduecol; /* frames aborted due to transmit collision */
  545. u32 frlostinmactxer; /* frames lost due to internal MAC error
  546. transmission that are not counted on any
  547. other counter */
  548. u32 carriersenseertx; /* carrier sense error */
  549. u32 frtxok; /* frames transmitted OK */
  550. u32 txfrexcessivedefer; /* frames with defferal time greater than
  551. specified threshold */
  552. u32 txpkts256; /* total packets (including bad) between 256
  553. and 511 octets */
  554. u32 txpkts512; /* total packets (including bad) between 512
  555. and 1023 octets */
  556. u32 txpkts1024; /* total packets (including bad) between 1024
  557. and 1518 octets */
  558. u32 txpktsjumbo; /* total packets (including bad) between 1024
  559. and MAXLength octets */
  560. } __attribute__ ((packed));
  561. struct ucc_geth_rx_firmware_statistics_pram {
  562. u32 frrxfcser; /* frames with crc error */
  563. u32 fraligner; /* frames with alignment error */
  564. u32 inrangelenrxer; /* in range length error */
  565. u32 outrangelenrxer; /* out of range length error */
  566. u32 frtoolong; /* frame too long */
  567. u32 runt; /* runt */
  568. u32 verylongevent; /* very long event */
  569. u32 symbolerror; /* symbol error */
  570. u32 dropbsy; /* drop because of BD not ready */
  571. u8 res0[0x8];
  572. u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
  573. or type mismatch) */
  574. u32 underpkts; /* total frames less than 64 octets */
  575. u32 pkts256; /* total frames (including bad) between 256 and
  576. 511 octets */
  577. u32 pkts512; /* total frames (including bad) between 512 and
  578. 1023 octets */
  579. u32 pkts1024; /* total frames (including bad) between 1024
  580. and 1518 octets */
  581. u32 pktsjumbo; /* total frames (including bad) between 1024
  582. and MAXLength octets */
  583. u32 frlossinmacer; /* frames lost because of internal MAC error
  584. that is not counted in any other counter */
  585. u32 pausefr; /* pause frames */
  586. u8 res1[0x4];
  587. u32 removevlan; /* total frames that had their VLAN tag removed
  588. */
  589. u32 replacevlan; /* total frames that had their VLAN tag
  590. replaced */
  591. u32 insertvlan; /* total frames that had their VLAN tag
  592. inserted */
  593. } __attribute__ ((packed));
  594. struct ucc_geth_rx_interrupt_coalescing_entry {
  595. u32 interruptcoalescingmaxvalue; /* interrupt coalescing max
  596. value */
  597. u32 interruptcoalescingcounter; /* interrupt coalescing counter,
  598. initialize to
  599. interruptcoalescingmaxvalue */
  600. } __attribute__ ((packed));
  601. struct ucc_geth_rx_interrupt_coalescing_table {
  602. struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
  603. /**< interrupt coalescing entry */
  604. } __attribute__ ((packed));
  605. struct ucc_geth_rx_prefetched_bds {
  606. struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */
  607. } __attribute__ ((packed));
  608. struct ucc_geth_rx_bd_queues_entry {
  609. u32 bdbaseptr; /* BD base pointer */
  610. u32 bdptr; /* BD pointer */
  611. u32 externalbdbaseptr; /* external BD base pointer */
  612. u32 externalbdptr; /* external BD pointer */
  613. } __attribute__ ((packed));
  614. struct ucc_geth_tx_global_pram {
  615. u16 temoder;
  616. u8 res0[0x38 - 0x02];
  617. u32 sqptr; /* a base pointer to send queue memory region */
  618. u32 schedulerbasepointer; /* a base pointer to scheduler memory
  619. region */
  620. u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */
  621. u32 tstate; /* tx internal state. High byte contains
  622. function code */
  623. u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
  624. u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */
  625. u32 tqptr; /* a base pointer to the Tx Queues Memory
  626. Region */
  627. u8 res2[0x80 - 0x74];
  628. } __attribute__ ((packed));
  629. /* structure representing Extended Filtering Global Parameters in PRAM */
  630. struct ucc_geth_exf_global_pram {
  631. u32 l2pcdptr; /* individual address filter, high */
  632. u8 res0[0x10 - 0x04];
  633. } __attribute__ ((packed));
  634. struct ucc_geth_rx_global_pram {
  635. u32 remoder; /* ethernet mode reg. */
  636. u32 rqptr; /* base pointer to the Rx Queues Memory Region*/
  637. u32 res0[0x1];
  638. u8 res1[0x20 - 0xC];
  639. u16 typeorlen; /* cutoff point less than which, type/len field
  640. is considered length */
  641. u8 res2[0x1];
  642. u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/
  643. u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */
  644. u8 res3[0x30 - 0x28];
  645. u32 intcoalescingptr; /* Interrupt coalescing table pointer */
  646. u8 res4[0x36 - 0x34];
  647. u8 rstate; /* rx internal state. High byte contains
  648. function code */
  649. u8 res5[0x46 - 0x37];
  650. u16 mrblr; /* max receive buffer length reg. */
  651. u32 rbdqptr; /* base pointer to RxBD parameter table
  652. description */
  653. u16 mflr; /* max frame length reg. */
  654. u16 minflr; /* min frame length reg. */
  655. u16 maxd1; /* max dma1 length reg. */
  656. u16 maxd2; /* max dma2 length reg. */
  657. u32 ecamptr; /* external CAM address */
  658. u32 l2qt; /* VLAN priority mapping table. */
  659. u32 l3qt[0x8]; /* IP priority mapping table. */
  660. u16 vlantype; /* vlan type */
  661. u16 vlantci; /* default vlan tci */
  662. u8 addressfiltering[64]; /* address filtering data structure */
  663. u32 exfGlobalParam; /* base address for extended filtering global
  664. parameters */
  665. u8 res6[0x100 - 0xC4]; /* Initialize to zero */
  666. } __attribute__ ((packed));
  667. #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
  668. /* structure representing InitEnet command */
  669. struct ucc_geth_init_pram {
  670. u8 resinit1;
  671. u8 resinit2;
  672. u8 resinit3;
  673. u8 resinit4;
  674. u16 resinit5;
  675. u8 res1[0x1];
  676. u8 largestexternallookupkeysize;
  677. u32 rgftgfrxglobal;
  678. u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */
  679. u8 res2[0x38 - 0x30];
  680. u32 txglobal; /* tx global */
  681. u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */
  682. u8 res3[0x1];
  683. } __attribute__ ((packed));
  684. #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
  685. #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
  686. #define ENET_INIT_PARAM_RISC_MASK 0x0000003f
  687. #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
  688. #define ENET_INIT_PARAM_SNUM_MASK 0xff000000
  689. #define ENET_INIT_PARAM_SNUM_SHIFT 24
  690. #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06
  691. #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30
  692. #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff
  693. #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00
  694. #define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400
  695. /* structure representing 82xx Address Filtering Enet Address in PRAM */
  696. struct ucc_geth_82xx_enet_address {
  697. u8 res1[0x2];
  698. u16 h; /* address (MSB) */
  699. u16 m; /* address */
  700. u16 l; /* address (LSB) */
  701. } __attribute__ ((packed));
  702. /* structure representing 82xx Address Filtering PRAM */
  703. struct ucc_geth_82xx_address_filtering_pram {
  704. u32 iaddr_h; /* individual address filter, high */
  705. u32 iaddr_l; /* individual address filter, low */
  706. u32 gaddr_h; /* group address filter, high */
  707. u32 gaddr_l; /* group address filter, low */
  708. struct ucc_geth_82xx_enet_address taddr;
  709. struct ucc_geth_82xx_enet_address paddr[NUM_OF_PADDRS];
  710. u8 res0[0x40 - 0x38];
  711. } __attribute__ ((packed));
  712. /* GETH Tx firmware statistics structure, used when calling
  713. UCC_GETH_GetStatistics. */
  714. struct ucc_geth_tx_firmware_statistics {
  715. u32 sicoltx; /* single collision */
  716. u32 mulcoltx; /* multiple collision */
  717. u32 latecoltxfr; /* late collision */
  718. u32 frabortduecol; /* frames aborted due to transmit collision */
  719. u32 frlostinmactxer; /* frames lost due to internal MAC error
  720. transmission that are not counted on any
  721. other counter */
  722. u32 carriersenseertx; /* carrier sense error */
  723. u32 frtxok; /* frames transmitted OK */
  724. u32 txfrexcessivedefer; /* frames with defferal time greater than
  725. specified threshold */
  726. u32 txpkts256; /* total packets (including bad) between 256
  727. and 511 octets */
  728. u32 txpkts512; /* total packets (including bad) between 512
  729. and 1023 octets */
  730. u32 txpkts1024; /* total packets (including bad) between 1024
  731. and 1518 octets */
  732. u32 txpktsjumbo; /* total packets (including bad) between 1024
  733. and MAXLength octets */
  734. } __attribute__ ((packed));
  735. /* GETH Rx firmware statistics structure, used when calling
  736. UCC_GETH_GetStatistics. */
  737. struct ucc_geth_rx_firmware_statistics {
  738. u32 frrxfcser; /* frames with crc error */
  739. u32 fraligner; /* frames with alignment error */
  740. u32 inrangelenrxer; /* in range length error */
  741. u32 outrangelenrxer; /* out of range length error */
  742. u32 frtoolong; /* frame too long */
  743. u32 runt; /* runt */
  744. u32 verylongevent; /* very long event */
  745. u32 symbolerror; /* symbol error */
  746. u32 dropbsy; /* drop because of BD not ready */
  747. u8 res0[0x8];
  748. u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
  749. or type mismatch) */
  750. u32 underpkts; /* total frames less than 64 octets */
  751. u32 pkts256; /* total frames (including bad) between 256 and
  752. 511 octets */
  753. u32 pkts512; /* total frames (including bad) between 512 and
  754. 1023 octets */
  755. u32 pkts1024; /* total frames (including bad) between 1024
  756. and 1518 octets */
  757. u32 pktsjumbo; /* total frames (including bad) between 1024
  758. and MAXLength octets */
  759. u32 frlossinmacer; /* frames lost because of internal MAC error
  760. that is not counted in any other counter */
  761. u32 pausefr; /* pause frames */
  762. u8 res1[0x4];
  763. u32 removevlan; /* total frames that had their VLAN tag removed
  764. */
  765. u32 replacevlan; /* total frames that had their VLAN tag
  766. replaced */
  767. u32 insertvlan; /* total frames that had their VLAN tag
  768. inserted */
  769. } __attribute__ ((packed));
  770. /* GETH hardware statistics structure, used when calling
  771. UCC_GETH_GetStatistics. */
  772. struct ucc_geth_hardware_statistics {
  773. u32 tx64; /* Total number of frames (including bad
  774. frames) transmitted that were exactly of the
  775. minimal length (64 for un tagged, 68 for
  776. tagged, or with length exactly equal to the
  777. parameter MINLength */
  778. u32 tx127; /* Total number of frames (including bad
  779. frames) transmitted that were between
  780. MINLength (Including FCS length==4) and 127
  781. octets */
  782. u32 tx255; /* Total number of frames (including bad
  783. frames) transmitted that were between 128
  784. (Including FCS length==4) and 255 octets */
  785. u32 rx64; /* Total number of frames received including
  786. bad frames that were exactly of the mninimal
  787. length (64 bytes) */
  788. u32 rx127; /* Total number of frames (including bad
  789. frames) received that were between MINLength
  790. (Including FCS length==4) and 127 octets */
  791. u32 rx255; /* Total number of frames (including bad
  792. frames) received that were between 128
  793. (Including FCS length==4) and 255 octets */
  794. u32 txok; /* Total number of octets residing in frames
  795. that where involved in succesfull
  796. transmission */
  797. u16 txcf; /* Total number of PAUSE control frames
  798. transmitted by this MAC */
  799. u32 tmca; /* Total number of frames that were transmitted
  800. succesfully with the group address bit set
  801. that are not broadcast frames */
  802. u32 tbca; /* Total number of frames transmitted
  803. succesfully that had destination address
  804. field equal to the broadcast address */
  805. u32 rxfok; /* Total number of frames received OK */
  806. u32 rxbok; /* Total number of octets received OK */
  807. u32 rbyt; /* Total number of octets received including
  808. octets in bad frames. Must be implemented in
  809. HW because it includes octets in frames that
  810. never even reach the UCC */
  811. u32 rmca; /* Total number of frames that were received
  812. succesfully with the group address bit set
  813. that are not broadcast frames */
  814. u32 rbca; /* Total number of frames received succesfully
  815. that had destination address equal to the
  816. broadcast address */
  817. } __attribute__ ((packed));
  818. /* UCC GETH Tx errors returned via TxConf callback */
  819. #define TX_ERRORS_DEF 0x0200
  820. #define TX_ERRORS_EXDEF 0x0100
  821. #define TX_ERRORS_LC 0x0080
  822. #define TX_ERRORS_RL 0x0040
  823. #define TX_ERRORS_RC_MASK 0x003C
  824. #define TX_ERRORS_RC_SHIFT 2
  825. #define TX_ERRORS_UN 0x0002
  826. #define TX_ERRORS_CSL 0x0001
  827. /* UCC GETH Rx errors returned via RxStore callback */
  828. #define RX_ERRORS_CMR 0x0200
  829. #define RX_ERRORS_M 0x0100
  830. #define RX_ERRORS_BC 0x0080
  831. #define RX_ERRORS_MC 0x0040
  832. /* Transmit BD. These are in addition to values defined in uccf. */
  833. #define T_VID 0x003c0000 /* insert VLAN id index mask. */
  834. #define T_DEF (((u32) TX_ERRORS_DEF ) << 16)
  835. #define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16)
  836. #define T_LC (((u32) TX_ERRORS_LC ) << 16)
  837. #define T_RL (((u32) TX_ERRORS_RL ) << 16)
  838. #define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16)
  839. #define T_UN (((u32) TX_ERRORS_UN ) << 16)
  840. #define T_CSL (((u32) TX_ERRORS_CSL ) << 16)
  841. #define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
  842. | T_UN | T_CSL) /* transmit errors to report */
  843. /* Receive BD. These are in addition to values defined in uccf. */
  844. #define R_LG 0x00200000 /* Frame length violation. */
  845. #define R_NO 0x00100000 /* Non-octet aligned frame. */
  846. #define R_SH 0x00080000 /* Short frame. */
  847. #define R_CR 0x00040000 /* CRC error. */
  848. #define R_OV 0x00020000 /* Overrun. */
  849. #define R_IPCH 0x00010000 /* IP checksum check failed. */
  850. #define R_CMR (((u32) RX_ERRORS_CMR ) << 16)
  851. #define R_M (((u32) RX_ERRORS_M ) << 16)
  852. #define R_BC (((u32) RX_ERRORS_BC ) << 16)
  853. #define R_MC (((u32) RX_ERRORS_MC ) << 16)
  854. #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to
  855. report */
  856. #define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \
  857. R_OV | R_IPCH) /* receive errors to discard */
  858. /* Alignments */
  859. #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256
  860. #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128
  861. #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128
  862. #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64
  863. #define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values
  864. based on num of
  865. threads, but always
  866. using the maximum is
  867. easier */
  868. #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
  869. #define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */
  870. #define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */
  871. #define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */
  872. #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 4 /* This is a
  873. guess */
  874. #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */
  875. #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */
  876. #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This
  877. is a
  878. guess
  879. */
  880. #define UCC_GETH_RX_BD_RING_ALIGNMENT 32
  881. #define UCC_GETH_TX_BD_RING_ALIGNMENT 32
  882. #define UCC_GETH_MRBLR_ALIGNMENT 128
  883. #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4
  884. #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
  885. #define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64
  886. #define UCC_GETH_TAD_EF 0x80
  887. #define UCC_GETH_TAD_V 0x40
  888. #define UCC_GETH_TAD_REJ 0x20
  889. #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2
  890. #define UCC_GETH_TAD_VTAG_OP_SHIFT 6
  891. #define UCC_GETH_TAD_V_NON_VTAG_OP 0x20
  892. #define UCC_GETH_TAD_RQOS_SHIFT 0
  893. #define UCC_GETH_TAD_V_PRIORITY_SHIFT 5
  894. #define UCC_GETH_TAD_CFI 0x10
  895. #define UCC_GETH_VLAN_PRIORITY_MAX 8
  896. #define UCC_GETH_IP_PRIORITY_MAX 64
  897. #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8
  898. #define UCC_GETH_RX_BD_RING_SIZE_MIN 8
  899. #define UCC_GETH_TX_BD_RING_SIZE_MIN 2
  900. #define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD
  901. /* Driver definitions */
  902. #define TX_BD_RING_LEN 0x10
  903. #define RX_BD_RING_LEN 0x10
  904. #define UCC_GETH_DEV_WEIGHT TX_BD_RING_LEN
  905. #define TX_RING_MOD_MASK(size) (size-1)
  906. #define RX_RING_MOD_MASK(size) (size-1)
  907. #define ENET_NUM_OCTETS_PER_ADDRESS 6
  908. #define ENET_GROUP_ADDR 0x01 /* Group address mask
  909. for ethernet
  910. addresses */
  911. #define TX_TIMEOUT (1*HZ)
  912. #define SKB_ALLOC_TIMEOUT 100000
  913. #define PHY_INIT_TIMEOUT 100000
  914. #define PHY_CHANGE_TIME 2
  915. /* Fast Ethernet (10/100 Mbps) */
  916. #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size
  917. */
  918. #define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */
  919. #define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */
  920. #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size
  921. */
  922. #define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */
  923. #define UCC_GETH_UTFTT_INIT 128
  924. /* Gigabit Ethernet (1000 Mbps) */
  925. #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual
  926. FIFO size */
  927. #define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */
  928. #define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */
  929. #define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual
  930. FIFO size */
  931. #define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */
  932. #define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */
  933. #define UCC_GETH_REMODER_INIT 0 /* bits that must be
  934. set */
  935. #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */
  936. #define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value
  937. for this
  938. register */
  939. #define UCC_GETH_MACCFG1_INIT 0
  940. #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1)
  941. #define UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT \
  942. (MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112)
  943. /* Ethernet speed */
  944. enum enet_speed {
  945. ENET_SPEED_10BT, /* 10 Base T */
  946. ENET_SPEED_100BT, /* 100 Base T */
  947. ENET_SPEED_1000BT /* 1000 Base T */
  948. };
  949. /* Ethernet Address Type. */
  950. enum enet_addr_type {
  951. ENET_ADDR_TYPE_INDIVIDUAL,
  952. ENET_ADDR_TYPE_GROUP,
  953. ENET_ADDR_TYPE_BROADCAST
  954. };
  955. /* TBI / MII Set Register */
  956. enum enet_tbi_mii_reg {
  957. ENET_TBI_MII_CR = 0x00, /* Control (CR ) */
  958. ENET_TBI_MII_SR = 0x01, /* Status (SR ) */
  959. ENET_TBI_MII_ANA = 0x04, /* AN advertisement (ANA ) */
  960. ENET_TBI_MII_ANLPBPA = 0x05, /* AN link partner base page ability
  961. (ANLPBPA) */
  962. ENET_TBI_MII_ANEX = 0x06, /* AN expansion (ANEX ) */
  963. ENET_TBI_MII_ANNPT = 0x07, /* AN next page transmit (ANNPT ) */
  964. ENET_TBI_MII_ANLPANP = 0x08, /* AN link partner ability next page
  965. (ANLPANP) */
  966. ENET_TBI_MII_EXST = 0x0F, /* Extended status (EXST ) */
  967. ENET_TBI_MII_JD = 0x10, /* Jitter diagnostics (JD ) */
  968. ENET_TBI_MII_TBICON = 0x11 /* TBI control (TBICON ) */
  969. };
  970. /* UCC GETH 82xx Ethernet Address Recognition Location */
  971. enum ucc_geth_enet_address_recognition_location {
  972. UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
  973. address */
  974. UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
  975. station
  976. address
  977. paddr1 */
  978. UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional
  979. station
  980. address
  981. paddr2 */
  982. UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional
  983. station
  984. address
  985. paddr3 */
  986. UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional
  987. station
  988. address
  989. paddr4 */
  990. UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */
  991. UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
  992. hash */
  993. };
  994. /* UCC GETH vlan operation tagged */
  995. enum ucc_geth_vlan_operation_tagged {
  996. UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */
  997. UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
  998. = 0x1, /* Tagged - replace vid portion of q tag */
  999. UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
  1000. = 0x2, /* Tagged - if vid0 replace vid with default value */
  1001. UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
  1002. = 0x3 /* Tagged - extract q tag from frame */
  1003. };
  1004. /* UCC GETH vlan operation non-tagged */
  1005. enum ucc_geth_vlan_operation_non_tagged {
  1006. UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */
  1007. UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -
  1008. q tag insert
  1009. */
  1010. };
  1011. /* UCC GETH Rx Quality of Service Mode */
  1012. enum ucc_geth_qos_mode {
  1013. UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */
  1014. UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue
  1015. determined
  1016. by L2
  1017. criteria */
  1018. UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue
  1019. determined
  1020. by L3
  1021. criteria */
  1022. };
  1023. /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
  1024. for combined functionality */
  1025. enum ucc_geth_statistics_gathering_mode {
  1026. UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No
  1027. statistics
  1028. gathering */
  1029. UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
  1030. hardware
  1031. statistics
  1032. gathering
  1033. */
  1034. UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
  1035. firmware
  1036. tx
  1037. statistics
  1038. gathering
  1039. */
  1040. UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
  1041. firmware
  1042. rx
  1043. statistics
  1044. gathering
  1045. */
  1046. };
  1047. /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
  1048. enum ucc_geth_maccfg2_pad_and_crc_mode {
  1049. UCC_GETH_PAD_AND_CRC_MODE_NONE
  1050. = MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding
  1051. short frames
  1052. nor CRC */
  1053. UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
  1054. = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append
  1055. CRC only */
  1056. UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
  1057. MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
  1058. };
  1059. /* UCC GETH upsmr Flow Control Mode */
  1060. enum ucc_geth_flow_control_mode {
  1061. UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic
  1062. flow control
  1063. */
  1064. UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
  1065. = 0x00004000 /* Send pause frame when RxFIFO reaches its
  1066. emergency threshold */
  1067. };
  1068. /* UCC GETH number of threads */
  1069. enum ucc_geth_num_of_threads {
  1070. UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */
  1071. UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */
  1072. UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */
  1073. UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */
  1074. UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
  1075. };
  1076. /* UCC GETH number of station addresses */
  1077. enum ucc_geth_num_of_station_addresses {
  1078. UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */
  1079. UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */
  1080. };
  1081. /* UCC GETH 82xx Ethernet Address Container */
  1082. struct enet_addr_container {
  1083. u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
  1084. enum ucc_geth_enet_address_recognition_location location; /* location in
  1085. 82xx address
  1086. recognition
  1087. hardware */
  1088. struct list_head node;
  1089. };
  1090. #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
  1091. /* UCC GETH Termination Action Descriptor (TAD) structure. */
  1092. struct ucc_geth_tad_params {
  1093. int rx_non_dynamic_extended_features_mode;
  1094. int reject_frame;
  1095. enum ucc_geth_vlan_operation_tagged vtag_op;
  1096. enum ucc_geth_vlan_operation_non_tagged vnontag_op;
  1097. enum ucc_geth_qos_mode rqos;
  1098. u8 vpri;
  1099. u16 vid;
  1100. };
  1101. /* GETH protocol initialization structure */
  1102. struct ucc_geth_info {
  1103. struct ucc_fast_info uf_info;
  1104. u8 numQueuesTx;
  1105. u8 numQueuesRx;
  1106. int ipCheckSumCheck;
  1107. int ipCheckSumGenerate;
  1108. int rxExtendedFiltering;
  1109. u32 extendedFilteringChainPointer;
  1110. u16 typeorlen;
  1111. int dynamicMaxFrameLength;
  1112. int dynamicMinFrameLength;
  1113. u8 nonBackToBackIfgPart1;
  1114. u8 nonBackToBackIfgPart2;
  1115. u8 miminumInterFrameGapEnforcement;
  1116. u8 backToBackInterFrameGap;
  1117. int ipAddressAlignment;
  1118. int lengthCheckRx;
  1119. u32 mblinterval;
  1120. u16 nortsrbytetime;
  1121. u8 fracsiz;
  1122. u8 strictpriorityq;
  1123. u8 txasap;
  1124. u8 extrabw;
  1125. int miiPreambleSupress;
  1126. u8 altBebTruncation;
  1127. int altBeb;
  1128. int backPressureNoBackoff;
  1129. int noBackoff;
  1130. int excessDefer;
  1131. u8 maxRetransmission;
  1132. u8 collisionWindow;
  1133. int pro;
  1134. int cap;
  1135. int rsh;
  1136. int rlpb;
  1137. int cam;
  1138. int bro;
  1139. int ecm;
  1140. int receiveFlowControl;
  1141. u8 maxGroupAddrInHash;
  1142. u8 maxIndAddrInHash;
  1143. u8 prel;
  1144. u16 maxFrameLength;
  1145. u16 minFrameLength;
  1146. u16 maxD1Length;
  1147. u16 maxD2Length;
  1148. u16 vlantype;
  1149. u16 vlantci;
  1150. u32 ecamptr;
  1151. u32 eventRegMask;
  1152. u16 pausePeriod;
  1153. u16 extensionField;
  1154. u8 phy_address;
  1155. u32 board_flags;
  1156. u32 phy_interrupt;
  1157. u8 weightfactor[NUM_TX_QUEUES];
  1158. u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
  1159. u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
  1160. u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
  1161. u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
  1162. u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
  1163. u16 bdRingLenTx[NUM_TX_QUEUES];
  1164. u16 bdRingLenRx[NUM_RX_QUEUES];
  1165. enum enet_interface enet_interface;
  1166. enum ucc_geth_num_of_station_addresses numStationAddresses;
  1167. enum qe_fltr_largest_external_tbl_lookup_key_size
  1168. largestexternallookupkeysize;
  1169. enum ucc_geth_statistics_gathering_mode statisticsMode;
  1170. enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
  1171. enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
  1172. enum ucc_geth_qos_mode rxQoSMode;
  1173. enum ucc_geth_flow_control_mode aufc;
  1174. enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
  1175. enum ucc_geth_num_of_threads numThreadsTx;
  1176. enum ucc_geth_num_of_threads numThreadsRx;
  1177. enum qe_risc_allocation riscTx;
  1178. enum qe_risc_allocation riscRx;
  1179. };
  1180. /* structure representing UCC GETH */
  1181. struct ucc_geth_private {
  1182. struct ucc_geth_info *ug_info;
  1183. struct ucc_fast_private *uccf;
  1184. struct net_device *dev;
  1185. struct net_device_stats stats; /* linux network statistics */
  1186. struct ucc_geth *ug_regs;
  1187. struct ucc_geth_init_pram *p_init_enet_param_shadow;
  1188. struct ucc_geth_exf_global_pram *p_exf_glbl_param;
  1189. u32 exf_glbl_param_offset;
  1190. struct ucc_geth_rx_global_pram *p_rx_glbl_pram;
  1191. u32 rx_glbl_pram_offset;
  1192. struct ucc_geth_tx_global_pram *p_tx_glbl_pram;
  1193. u32 tx_glbl_pram_offset;
  1194. struct ucc_geth_send_queue_mem_region *p_send_q_mem_reg;
  1195. u32 send_q_mem_reg_offset;
  1196. struct ucc_geth_thread_data_tx *p_thread_data_tx;
  1197. u32 thread_dat_tx_offset;
  1198. struct ucc_geth_thread_data_rx *p_thread_data_rx;
  1199. u32 thread_dat_rx_offset;
  1200. struct ucc_geth_scheduler *p_scheduler;
  1201. u32 scheduler_offset;
  1202. struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
  1203. u32 tx_fw_statistics_pram_offset;
  1204. struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
  1205. u32 rx_fw_statistics_pram_offset;
  1206. struct ucc_geth_rx_interrupt_coalescing_table *p_rx_irq_coalescing_tbl;
  1207. u32 rx_irq_coalescing_tbl_offset;
  1208. struct ucc_geth_rx_bd_queues_entry *p_rx_bd_qs_tbl;
  1209. u32 rx_bd_qs_tbl_offset;
  1210. u8 *p_tx_bd_ring[NUM_TX_QUEUES];
  1211. u32 tx_bd_ring_offset[NUM_TX_QUEUES];
  1212. u8 *p_rx_bd_ring[NUM_RX_QUEUES];
  1213. u32 rx_bd_ring_offset[NUM_RX_QUEUES];
  1214. u8 *confBd[NUM_TX_QUEUES];
  1215. u8 *txBd[NUM_TX_QUEUES];
  1216. u8 *rxBd[NUM_RX_QUEUES];
  1217. int badFrame[NUM_RX_QUEUES];
  1218. u16 cpucount[NUM_TX_QUEUES];
  1219. volatile u16 *p_cpucount[NUM_TX_QUEUES];
  1220. int indAddrRegUsed[NUM_OF_PADDRS];
  1221. u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
  1222. u8 numGroupAddrInHash;
  1223. u8 numIndAddrInHash;
  1224. u8 numIndAddrInReg;
  1225. int rx_extended_features;
  1226. int rx_non_dynamic_extended_features;
  1227. struct list_head conf_skbs;
  1228. struct list_head group_hash_q;
  1229. struct list_head ind_hash_q;
  1230. u32 saved_uccm;
  1231. spinlock_t lock;
  1232. /* pointers to arrays of skbuffs for tx and rx */
  1233. struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
  1234. struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
  1235. /* indices pointing to the next free sbk in skb arrays */
  1236. u16 skb_curtx[NUM_TX_QUEUES];
  1237. u16 skb_currx[NUM_RX_QUEUES];
  1238. /* index of the first skb which hasn't been transmitted yet. */
  1239. u16 skb_dirtytx[NUM_TX_QUEUES];
  1240. struct work_struct tq;
  1241. struct timer_list phy_info_timer;
  1242. struct ugeth_mii_info *mii_info;
  1243. int oldspeed;
  1244. int oldduplex;
  1245. int oldlink;
  1246. };
  1247. #endif /* __UCC_GETH_H__ */