typhoon.h 22 KB

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  1. /* typhoon.h: chip info for the 3Com 3CR990 family of controllers */
  2. /*
  3. Written 2002-2003 by David Dillow <dave@thedillows.org>
  4. This software may be used and distributed according to the terms of
  5. the GNU General Public License (GPL), incorporated herein by reference.
  6. Drivers based on or derived from this code fall under the GPL and must
  7. retain the authorship, copyright and license notice. This file is not
  8. a complete program and may only be used when the entire operating
  9. system is licensed under the GPL.
  10. This software is available on a public web site. It may enable
  11. cryptographic capabilities of the 3Com hardware, and may be
  12. exported from the United States under License Exception "TSU"
  13. pursuant to 15 C.F.R. Section 740.13(e).
  14. This work was funded by the National Library of Medicine under
  15. the Department of Energy project number 0274DD06D1 and NLM project
  16. number Y1-LM-2015-01.
  17. */
  18. /* All Typhoon ring positions are specificed in bytes, and point to the
  19. * first "clean" entry in the ring -- ie the next entry we use for whatever
  20. * purpose.
  21. */
  22. /* The Typhoon basic ring
  23. * ringBase: where this ring lives (our virtual address)
  24. * lastWrite: the next entry we'll use
  25. */
  26. struct basic_ring {
  27. u8 *ringBase;
  28. u32 lastWrite;
  29. };
  30. /* The Typoon transmit ring -- same as a basic ring, plus:
  31. * lastRead: where we're at in regard to cleaning up the ring
  32. * writeRegister: register to use for writing (different for Hi & Lo rings)
  33. */
  34. struct transmit_ring {
  35. u8 *ringBase;
  36. u32 lastWrite;
  37. u32 lastRead;
  38. int writeRegister;
  39. };
  40. /* The host<->Typhoon ring index structure
  41. * This indicates the current positions in the rings
  42. *
  43. * All values must be in little endian format for the 3XP
  44. *
  45. * rxHiCleared: entry we've cleared to in the Hi receive ring
  46. * rxLoCleared: entry we've cleared to in the Lo receive ring
  47. * rxBuffReady: next entry we'll put a free buffer in
  48. * respCleared: entry we've cleared to in the response ring
  49. *
  50. * txLoCleared: entry the NIC has cleared to in the Lo transmit ring
  51. * txHiCleared: entry the NIC has cleared to in the Hi transmit ring
  52. * rxLoReady: entry the NIC has filled to in the Lo receive ring
  53. * rxBuffCleared: entry the NIC has cleared in the free buffer ring
  54. * cmdCleared: entry the NIC has cleared in the command ring
  55. * respReady: entry the NIC has filled to in the response ring
  56. * rxHiReady: entry the NIC has filled to in the Hi receive ring
  57. */
  58. struct typhoon_indexes {
  59. /* The first four are written by the host, and read by the NIC */
  60. volatile u32 rxHiCleared;
  61. volatile u32 rxLoCleared;
  62. volatile u32 rxBuffReady;
  63. volatile u32 respCleared;
  64. /* The remaining are written by the NIC, and read by the host */
  65. volatile u32 txLoCleared;
  66. volatile u32 txHiCleared;
  67. volatile u32 rxLoReady;
  68. volatile u32 rxBuffCleared;
  69. volatile u32 cmdCleared;
  70. volatile u32 respReady;
  71. volatile u32 rxHiReady;
  72. } __attribute__ ((packed));
  73. /* The host<->Typhoon interface
  74. * Our means of communicating where things are
  75. *
  76. * All values must be in little endian format for the 3XP
  77. *
  78. * ringIndex: 64 bit bus address of the index structure
  79. * txLoAddr: 64 bit bus address of the Lo transmit ring
  80. * txLoSize: size (in bytes) of the Lo transmit ring
  81. * txHi*: as above for the Hi priority transmit ring
  82. * rxLo*: as above for the Lo priority receive ring
  83. * rxBuff*: as above for the free buffer ring
  84. * cmd*: as above for the command ring
  85. * resp*: as above for the response ring
  86. * zeroAddr: 64 bit bus address of a zero word (for DMA)
  87. * rxHi*: as above for the Hi Priority receive ring
  88. *
  89. * While there is room for 64 bit addresses, current versions of the 3XP
  90. * only do 32 bit addresses, so the *Hi for each of the above will always
  91. * be zero.
  92. */
  93. struct typhoon_interface {
  94. u32 ringIndex;
  95. u32 ringIndexHi;
  96. u32 txLoAddr;
  97. u32 txLoAddrHi;
  98. u32 txLoSize;
  99. u32 txHiAddr;
  100. u32 txHiAddrHi;
  101. u32 txHiSize;
  102. u32 rxLoAddr;
  103. u32 rxLoAddrHi;
  104. u32 rxLoSize;
  105. u32 rxBuffAddr;
  106. u32 rxBuffAddrHi;
  107. u32 rxBuffSize;
  108. u32 cmdAddr;
  109. u32 cmdAddrHi;
  110. u32 cmdSize;
  111. u32 respAddr;
  112. u32 respAddrHi;
  113. u32 respSize;
  114. u32 zeroAddr;
  115. u32 zeroAddrHi;
  116. u32 rxHiAddr;
  117. u32 rxHiAddrHi;
  118. u32 rxHiSize;
  119. } __attribute__ ((packed));
  120. /* The Typhoon transmit/fragment descriptor
  121. *
  122. * A packet is described by a packet descriptor, followed by option descriptors,
  123. * if any, then one or more fragment descriptors.
  124. *
  125. * Packet descriptor:
  126. * flags: Descriptor type
  127. * len:i zero, or length of this packet
  128. * addr*: 8 bytes of opaque data to the firmware -- for skb pointer
  129. * processFlags: Determine offload tasks to perform on this packet.
  130. *
  131. * Fragment descriptor:
  132. * flags: Descriptor type
  133. * len:i length of this fragment
  134. * addr: low bytes of DMA address for this part of the packet
  135. * addrHi: hi bytes of DMA address for this part of the packet
  136. * processFlags: must be zero
  137. *
  138. * TYPHOON_DESC_VALID is not mentioned in their docs, but their Linux
  139. * driver uses it.
  140. */
  141. struct tx_desc {
  142. u8 flags;
  143. #define TYPHOON_TYPE_MASK 0x07
  144. #define TYPHOON_FRAG_DESC 0x00
  145. #define TYPHOON_TX_DESC 0x01
  146. #define TYPHOON_CMD_DESC 0x02
  147. #define TYPHOON_OPT_DESC 0x03
  148. #define TYPHOON_RX_DESC 0x04
  149. #define TYPHOON_RESP_DESC 0x05
  150. #define TYPHOON_OPT_TYPE_MASK 0xf0
  151. #define TYPHOON_OPT_IPSEC 0x00
  152. #define TYPHOON_OPT_TCP_SEG 0x10
  153. #define TYPHOON_CMD_RESPOND 0x40
  154. #define TYPHOON_RESP_ERROR 0x40
  155. #define TYPHOON_RX_ERROR 0x40
  156. #define TYPHOON_DESC_VALID 0x80
  157. u8 numDesc;
  158. u16 len;
  159. u32 addr;
  160. u32 addrHi;
  161. u32 processFlags;
  162. #define TYPHOON_TX_PF_NO_CRC __constant_cpu_to_le32(0x00000001)
  163. #define TYPHOON_TX_PF_IP_CHKSUM __constant_cpu_to_le32(0x00000002)
  164. #define TYPHOON_TX_PF_TCP_CHKSUM __constant_cpu_to_le32(0x00000004)
  165. #define TYPHOON_TX_PF_TCP_SEGMENT __constant_cpu_to_le32(0x00000008)
  166. #define TYPHOON_TX_PF_INSERT_VLAN __constant_cpu_to_le32(0x00000010)
  167. #define TYPHOON_TX_PF_IPSEC __constant_cpu_to_le32(0x00000020)
  168. #define TYPHOON_TX_PF_VLAN_PRIORITY __constant_cpu_to_le32(0x00000040)
  169. #define TYPHOON_TX_PF_UDP_CHKSUM __constant_cpu_to_le32(0x00000080)
  170. #define TYPHOON_TX_PF_PAD_FRAME __constant_cpu_to_le32(0x00000100)
  171. #define TYPHOON_TX_PF_RESERVED __constant_cpu_to_le32(0x00000e00)
  172. #define TYPHOON_TX_PF_VLAN_MASK __constant_cpu_to_le32(0x0ffff000)
  173. #define TYPHOON_TX_PF_INTERNAL __constant_cpu_to_le32(0xf0000000)
  174. #define TYPHOON_TX_PF_VLAN_TAG_SHIFT 12
  175. } __attribute__ ((packed));
  176. /* The TCP Segmentation offload option descriptor
  177. *
  178. * flags: descriptor type
  179. * numDesc: must be 1
  180. * mss_flags: bits 0-11 (little endian) are MSS, 12 is first TSO descriptor
  181. * 13 is list TSO descriptor, set both if only one TSO
  182. * respAddrLo: low bytes of address of the bytesTx field of this descriptor
  183. * bytesTx: total number of bytes in this TSO request
  184. * status: 0 on completion
  185. */
  186. struct tcpopt_desc {
  187. u8 flags;
  188. u8 numDesc;
  189. u16 mss_flags;
  190. #define TYPHOON_TSO_FIRST __constant_cpu_to_le16(0x1000)
  191. #define TYPHOON_TSO_LAST __constant_cpu_to_le16(0x2000)
  192. u32 respAddrLo;
  193. u32 bytesTx;
  194. u32 status;
  195. } __attribute__ ((packed));
  196. /* The IPSEC Offload descriptor
  197. *
  198. * flags: descriptor type
  199. * numDesc: must be 1
  200. * ipsecFlags: bit 0: 0 -- generate IV, 1 -- use supplied IV
  201. * sa1, sa2: Security Association IDs for this packet
  202. * reserved: set to 0
  203. */
  204. struct ipsec_desc {
  205. u8 flags;
  206. u8 numDesc;
  207. u16 ipsecFlags;
  208. #define TYPHOON_IPSEC_GEN_IV __constant_cpu_to_le16(0x0000)
  209. #define TYPHOON_IPSEC_USE_IV __constant_cpu_to_le16(0x0001)
  210. u32 sa1;
  211. u32 sa2;
  212. u32 reserved;
  213. } __attribute__ ((packed));
  214. /* The Typhoon receive descriptor (Updated by NIC)
  215. *
  216. * flags: Descriptor type, error indication
  217. * numDesc: Always zero
  218. * frameLen: the size of the packet received
  219. * addr: low 32 bytes of the virtual addr passed in for this buffer
  220. * addrHi: high 32 bytes of the virtual addr passed in for this buffer
  221. * rxStatus: Error if set in flags, otherwise result of offload processing
  222. * filterResults: results of filtering on packet, not used
  223. * ipsecResults: Results of IPSEC processing
  224. * vlanTag: the 801.2q TCI from the packet
  225. */
  226. struct rx_desc {
  227. u8 flags;
  228. u8 numDesc;
  229. u16 frameLen;
  230. u32 addr;
  231. u32 addrHi;
  232. u32 rxStatus;
  233. #define TYPHOON_RX_ERR_INTERNAL __constant_cpu_to_le32(0x00000000)
  234. #define TYPHOON_RX_ERR_FIFO_UNDERRUN __constant_cpu_to_le32(0x00000001)
  235. #define TYPHOON_RX_ERR_BAD_SSD __constant_cpu_to_le32(0x00000002)
  236. #define TYPHOON_RX_ERR_RUNT __constant_cpu_to_le32(0x00000003)
  237. #define TYPHOON_RX_ERR_CRC __constant_cpu_to_le32(0x00000004)
  238. #define TYPHOON_RX_ERR_OVERSIZE __constant_cpu_to_le32(0x00000005)
  239. #define TYPHOON_RX_ERR_ALIGN __constant_cpu_to_le32(0x00000006)
  240. #define TYPHOON_RX_ERR_DRIBBLE __constant_cpu_to_le32(0x00000007)
  241. #define TYPHOON_RX_PROTO_MASK __constant_cpu_to_le32(0x00000003)
  242. #define TYPHOON_RX_PROTO_UNKNOWN __constant_cpu_to_le32(0x00000000)
  243. #define TYPHOON_RX_PROTO_IP __constant_cpu_to_le32(0x00000001)
  244. #define TYPHOON_RX_PROTO_IPX __constant_cpu_to_le32(0x00000002)
  245. #define TYPHOON_RX_VLAN __constant_cpu_to_le32(0x00000004)
  246. #define TYPHOON_RX_IP_FRAG __constant_cpu_to_le32(0x00000008)
  247. #define TYPHOON_RX_IPSEC __constant_cpu_to_le32(0x00000010)
  248. #define TYPHOON_RX_IP_CHK_FAIL __constant_cpu_to_le32(0x00000020)
  249. #define TYPHOON_RX_TCP_CHK_FAIL __constant_cpu_to_le32(0x00000040)
  250. #define TYPHOON_RX_UDP_CHK_FAIL __constant_cpu_to_le32(0x00000080)
  251. #define TYPHOON_RX_IP_CHK_GOOD __constant_cpu_to_le32(0x00000100)
  252. #define TYPHOON_RX_TCP_CHK_GOOD __constant_cpu_to_le32(0x00000200)
  253. #define TYPHOON_RX_UDP_CHK_GOOD __constant_cpu_to_le32(0x00000400)
  254. u16 filterResults;
  255. #define TYPHOON_RX_FILTER_MASK __constant_cpu_to_le16(0x7fff)
  256. #define TYPHOON_RX_FILTERED __constant_cpu_to_le16(0x8000)
  257. u16 ipsecResults;
  258. #define TYPHOON_RX_OUTER_AH_GOOD __constant_cpu_to_le16(0x0001)
  259. #define TYPHOON_RX_OUTER_ESP_GOOD __constant_cpu_to_le16(0x0002)
  260. #define TYPHOON_RX_INNER_AH_GOOD __constant_cpu_to_le16(0x0004)
  261. #define TYPHOON_RX_INNER_ESP_GOOD __constant_cpu_to_le16(0x0008)
  262. #define TYPHOON_RX_OUTER_AH_FAIL __constant_cpu_to_le16(0x0010)
  263. #define TYPHOON_RX_OUTER_ESP_FAIL __constant_cpu_to_le16(0x0020)
  264. #define TYPHOON_RX_INNER_AH_FAIL __constant_cpu_to_le16(0x0040)
  265. #define TYPHOON_RX_INNER_ESP_FAIL __constant_cpu_to_le16(0x0080)
  266. #define TYPHOON_RX_UNKNOWN_SA __constant_cpu_to_le16(0x0100)
  267. #define TYPHOON_RX_ESP_FORMAT_ERR __constant_cpu_to_le16(0x0200)
  268. u32 vlanTag;
  269. } __attribute__ ((packed));
  270. /* The Typhoon free buffer descriptor, used to give a buffer to the NIC
  271. *
  272. * physAddr: low 32 bits of the bus address of the buffer
  273. * physAddrHi: high 32 bits of the bus address of the buffer, always zero
  274. * virtAddr: low 32 bits of the skb address
  275. * virtAddrHi: high 32 bits of the skb address, always zero
  276. *
  277. * the virt* address is basically two 32 bit cookies, just passed back
  278. * from the NIC
  279. */
  280. struct rx_free {
  281. u32 physAddr;
  282. u32 physAddrHi;
  283. u32 virtAddr;
  284. u32 virtAddrHi;
  285. } __attribute__ ((packed));
  286. /* The Typhoon command descriptor, used for commands and responses
  287. *
  288. * flags: descriptor type
  289. * numDesc: number of descriptors following in this command/response,
  290. * ie, zero for a one descriptor command
  291. * cmd: the command
  292. * seqNo: sequence number (unused)
  293. * parm1: use varies by command
  294. * parm2: use varies by command
  295. * parm3: use varies by command
  296. */
  297. struct cmd_desc {
  298. u8 flags;
  299. u8 numDesc;
  300. u16 cmd;
  301. #define TYPHOON_CMD_TX_ENABLE __constant_cpu_to_le16(0x0001)
  302. #define TYPHOON_CMD_TX_DISABLE __constant_cpu_to_le16(0x0002)
  303. #define TYPHOON_CMD_RX_ENABLE __constant_cpu_to_le16(0x0003)
  304. #define TYPHOON_CMD_RX_DISABLE __constant_cpu_to_le16(0x0004)
  305. #define TYPHOON_CMD_SET_RX_FILTER __constant_cpu_to_le16(0x0005)
  306. #define TYPHOON_CMD_READ_STATS __constant_cpu_to_le16(0x0007)
  307. #define TYPHOON_CMD_XCVR_SELECT __constant_cpu_to_le16(0x0013)
  308. #define TYPHOON_CMD_SET_MAX_PKT_SIZE __constant_cpu_to_le16(0x001a)
  309. #define TYPHOON_CMD_READ_MEDIA_STATUS __constant_cpu_to_le16(0x001b)
  310. #define TYPHOON_CMD_GOTO_SLEEP __constant_cpu_to_le16(0x0023)
  311. #define TYPHOON_CMD_SET_MULTICAST_HASH __constant_cpu_to_le16(0x0025)
  312. #define TYPHOON_CMD_SET_MAC_ADDRESS __constant_cpu_to_le16(0x0026)
  313. #define TYPHOON_CMD_READ_MAC_ADDRESS __constant_cpu_to_le16(0x0027)
  314. #define TYPHOON_CMD_VLAN_TYPE_WRITE __constant_cpu_to_le16(0x002b)
  315. #define TYPHOON_CMD_CREATE_SA __constant_cpu_to_le16(0x0034)
  316. #define TYPHOON_CMD_DELETE_SA __constant_cpu_to_le16(0x0035)
  317. #define TYPHOON_CMD_READ_VERSIONS __constant_cpu_to_le16(0x0043)
  318. #define TYPHOON_CMD_IRQ_COALESCE_CTRL __constant_cpu_to_le16(0x0045)
  319. #define TYPHOON_CMD_ENABLE_WAKE_EVENTS __constant_cpu_to_le16(0x0049)
  320. #define TYPHOON_CMD_SET_OFFLOAD_TASKS __constant_cpu_to_le16(0x004f)
  321. #define TYPHOON_CMD_HELLO_RESP __constant_cpu_to_le16(0x0057)
  322. #define TYPHOON_CMD_HALT __constant_cpu_to_le16(0x005d)
  323. #define TYPHOON_CMD_READ_IPSEC_INFO __constant_cpu_to_le16(0x005e)
  324. #define TYPHOON_CMD_GET_IPSEC_ENABLE __constant_cpu_to_le16(0x0067)
  325. #define TYPHOON_CMD_GET_CMD_LVL __constant_cpu_to_le16(0x0069)
  326. u16 seqNo;
  327. u16 parm1;
  328. u32 parm2;
  329. u32 parm3;
  330. } __attribute__ ((packed));
  331. /* The Typhoon response descriptor, see command descriptor for details
  332. */
  333. struct resp_desc {
  334. u8 flags;
  335. u8 numDesc;
  336. u16 cmd;
  337. u16 seqNo;
  338. u16 parm1;
  339. u32 parm2;
  340. u32 parm3;
  341. } __attribute__ ((packed));
  342. #define INIT_COMMAND_NO_RESPONSE(x, command) \
  343. do { struct cmd_desc *_ptr = (x); \
  344. memset(_ptr, 0, sizeof(struct cmd_desc)); \
  345. _ptr->flags = TYPHOON_CMD_DESC | TYPHOON_DESC_VALID; \
  346. _ptr->cmd = command; \
  347. } while(0)
  348. /* We set seqNo to 1 if we're expecting a response from this command */
  349. #define INIT_COMMAND_WITH_RESPONSE(x, command) \
  350. do { struct cmd_desc *_ptr = (x); \
  351. memset(_ptr, 0, sizeof(struct cmd_desc)); \
  352. _ptr->flags = TYPHOON_CMD_RESPOND | TYPHOON_CMD_DESC; \
  353. _ptr->flags |= TYPHOON_DESC_VALID; \
  354. _ptr->cmd = command; \
  355. _ptr->seqNo = 1; \
  356. } while(0)
  357. /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1)
  358. */
  359. #define TYPHOON_RX_FILTER_DIRECTED __constant_cpu_to_le16(0x0001)
  360. #define TYPHOON_RX_FILTER_ALL_MCAST __constant_cpu_to_le16(0x0002)
  361. #define TYPHOON_RX_FILTER_BROADCAST __constant_cpu_to_le16(0x0004)
  362. #define TYPHOON_RX_FILTER_PROMISCOUS __constant_cpu_to_le16(0x0008)
  363. #define TYPHOON_RX_FILTER_MCAST_HASH __constant_cpu_to_le16(0x0010)
  364. /* TYPHOON_CMD_READ_STATS response format
  365. */
  366. struct stats_resp {
  367. u8 flags;
  368. u8 numDesc;
  369. u16 cmd;
  370. u16 seqNo;
  371. u16 unused;
  372. u32 txPackets;
  373. u64 txBytes;
  374. u32 txDeferred;
  375. u32 txLateCollisions;
  376. u32 txCollisions;
  377. u32 txCarrierLost;
  378. u32 txMultipleCollisions;
  379. u32 txExcessiveCollisions;
  380. u32 txFifoUnderruns;
  381. u32 txMulticastTxOverflows;
  382. u32 txFiltered;
  383. u32 rxPacketsGood;
  384. u64 rxBytesGood;
  385. u32 rxFifoOverruns;
  386. u32 BadSSD;
  387. u32 rxCrcErrors;
  388. u32 rxOversized;
  389. u32 rxBroadcast;
  390. u32 rxMulticast;
  391. u32 rxOverflow;
  392. u32 rxFiltered;
  393. u32 linkStatus;
  394. #define TYPHOON_LINK_STAT_MASK __constant_cpu_to_le32(0x00000001)
  395. #define TYPHOON_LINK_GOOD __constant_cpu_to_le32(0x00000001)
  396. #define TYPHOON_LINK_BAD __constant_cpu_to_le32(0x00000000)
  397. #define TYPHOON_LINK_SPEED_MASK __constant_cpu_to_le32(0x00000002)
  398. #define TYPHOON_LINK_100MBPS __constant_cpu_to_le32(0x00000002)
  399. #define TYPHOON_LINK_10MBPS __constant_cpu_to_le32(0x00000000)
  400. #define TYPHOON_LINK_DUPLEX_MASK __constant_cpu_to_le32(0x00000004)
  401. #define TYPHOON_LINK_FULL_DUPLEX __constant_cpu_to_le32(0x00000004)
  402. #define TYPHOON_LINK_HALF_DUPLEX __constant_cpu_to_le32(0x00000000)
  403. u32 unused2;
  404. u32 unused3;
  405. } __attribute__ ((packed));
  406. /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1)
  407. */
  408. #define TYPHOON_XCVR_10HALF __constant_cpu_to_le16(0x0000)
  409. #define TYPHOON_XCVR_10FULL __constant_cpu_to_le16(0x0001)
  410. #define TYPHOON_XCVR_100HALF __constant_cpu_to_le16(0x0002)
  411. #define TYPHOON_XCVR_100FULL __constant_cpu_to_le16(0x0003)
  412. #define TYPHOON_XCVR_AUTONEG __constant_cpu_to_le16(0x0004)
  413. /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1)
  414. */
  415. #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE __constant_cpu_to_le16(0x0004)
  416. #define TYPHOON_MEDIA_STAT_COLLISION_DETECT __constant_cpu_to_le16(0x0010)
  417. #define TYPHOON_MEDIA_STAT_CARRIER_SENSE __constant_cpu_to_le16(0x0020)
  418. #define TYPHOON_MEDIA_STAT_POLARITY_REV __constant_cpu_to_le16(0x0400)
  419. #define TYPHOON_MEDIA_STAT_NO_LINK __constant_cpu_to_le16(0x0800)
  420. /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1)
  421. */
  422. #define TYPHOON_MCAST_HASH_DISABLE __constant_cpu_to_le16(0x0000)
  423. #define TYPHOON_MCAST_HASH_ENABLE __constant_cpu_to_le16(0x0001)
  424. #define TYPHOON_MCAST_HASH_SET __constant_cpu_to_le16(0x0002)
  425. /* TYPHOON_CMD_CREATE_SA descriptor and settings
  426. */
  427. struct sa_descriptor {
  428. u8 flags;
  429. u8 numDesc;
  430. u16 cmd;
  431. u16 seqNo;
  432. u16 mode;
  433. #define TYPHOON_SA_MODE_NULL __constant_cpu_to_le16(0x0000)
  434. #define TYPHOON_SA_MODE_AH __constant_cpu_to_le16(0x0001)
  435. #define TYPHOON_SA_MODE_ESP __constant_cpu_to_le16(0x0002)
  436. u8 hashFlags;
  437. #define TYPHOON_SA_HASH_ENABLE 0x01
  438. #define TYPHOON_SA_HASH_SHA1 0x02
  439. #define TYPHOON_SA_HASH_MD5 0x04
  440. u8 direction;
  441. #define TYPHOON_SA_DIR_RX 0x00
  442. #define TYPHOON_SA_DIR_TX 0x01
  443. u8 encryptionFlags;
  444. #define TYPHOON_SA_ENCRYPT_ENABLE 0x01
  445. #define TYPHOON_SA_ENCRYPT_DES 0x02
  446. #define TYPHOON_SA_ENCRYPT_3DES 0x00
  447. #define TYPHOON_SA_ENCRYPT_3DES_2KEY 0x00
  448. #define TYPHOON_SA_ENCRYPT_3DES_3KEY 0x04
  449. #define TYPHOON_SA_ENCRYPT_CBC 0x08
  450. #define TYPHOON_SA_ENCRYPT_ECB 0x00
  451. u8 specifyIndex;
  452. #define TYPHOON_SA_SPECIFY_INDEX 0x01
  453. #define TYPHOON_SA_GENERATE_INDEX 0x00
  454. u32 SPI;
  455. u32 destAddr;
  456. u32 destMask;
  457. u8 integKey[20];
  458. u8 confKey[24];
  459. u32 index;
  460. u32 unused;
  461. u32 unused2;
  462. } __attribute__ ((packed));
  463. /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx))
  464. * This is all for IPv4.
  465. */
  466. #define TYPHOON_OFFLOAD_TCP_CHKSUM __constant_cpu_to_le32(0x00000002)
  467. #define TYPHOON_OFFLOAD_UDP_CHKSUM __constant_cpu_to_le32(0x00000004)
  468. #define TYPHOON_OFFLOAD_IP_CHKSUM __constant_cpu_to_le32(0x00000008)
  469. #define TYPHOON_OFFLOAD_IPSEC __constant_cpu_to_le32(0x00000010)
  470. #define TYPHOON_OFFLOAD_BCAST_THROTTLE __constant_cpu_to_le32(0x00000020)
  471. #define TYPHOON_OFFLOAD_DHCP_PREVENT __constant_cpu_to_le32(0x00000040)
  472. #define TYPHOON_OFFLOAD_VLAN __constant_cpu_to_le32(0x00000080)
  473. #define TYPHOON_OFFLOAD_FILTERING __constant_cpu_to_le32(0x00000100)
  474. #define TYPHOON_OFFLOAD_TCP_SEGMENT __constant_cpu_to_le32(0x00000200)
  475. /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1)
  476. */
  477. #define TYPHOON_WAKE_MAGIC_PKT __constant_cpu_to_le16(0x01)
  478. #define TYPHOON_WAKE_LINK_EVENT __constant_cpu_to_le16(0x02)
  479. #define TYPHOON_WAKE_ICMP_ECHO __constant_cpu_to_le16(0x04)
  480. #define TYPHOON_WAKE_ARP __constant_cpu_to_le16(0x08)
  481. /* These are used to load the firmware image on the NIC
  482. */
  483. struct typhoon_file_header {
  484. u8 tag[8];
  485. u32 version;
  486. u32 numSections;
  487. u32 startAddr;
  488. u32 hmacDigest[5];
  489. } __attribute__ ((packed));
  490. struct typhoon_section_header {
  491. u32 len;
  492. u16 checksum;
  493. u16 reserved;
  494. u32 startAddr;
  495. } __attribute__ ((packed));
  496. /* The Typhoon Register offsets
  497. */
  498. #define TYPHOON_REG_SOFT_RESET 0x00
  499. #define TYPHOON_REG_INTR_STATUS 0x04
  500. #define TYPHOON_REG_INTR_ENABLE 0x08
  501. #define TYPHOON_REG_INTR_MASK 0x0c
  502. #define TYPHOON_REG_SELF_INTERRUPT 0x10
  503. #define TYPHOON_REG_HOST2ARM7 0x14
  504. #define TYPHOON_REG_HOST2ARM6 0x18
  505. #define TYPHOON_REG_HOST2ARM5 0x1c
  506. #define TYPHOON_REG_HOST2ARM4 0x20
  507. #define TYPHOON_REG_HOST2ARM3 0x24
  508. #define TYPHOON_REG_HOST2ARM2 0x28
  509. #define TYPHOON_REG_HOST2ARM1 0x2c
  510. #define TYPHOON_REG_HOST2ARM0 0x30
  511. #define TYPHOON_REG_ARM2HOST3 0x34
  512. #define TYPHOON_REG_ARM2HOST2 0x38
  513. #define TYPHOON_REG_ARM2HOST1 0x3c
  514. #define TYPHOON_REG_ARM2HOST0 0x40
  515. #define TYPHOON_REG_BOOT_DATA_LO TYPHOON_REG_HOST2ARM5
  516. #define TYPHOON_REG_BOOT_DATA_HI TYPHOON_REG_HOST2ARM4
  517. #define TYPHOON_REG_BOOT_DEST_ADDR TYPHOON_REG_HOST2ARM3
  518. #define TYPHOON_REG_BOOT_CHECKSUM TYPHOON_REG_HOST2ARM2
  519. #define TYPHOON_REG_BOOT_LENGTH TYPHOON_REG_HOST2ARM1
  520. #define TYPHOON_REG_DOWNLOAD_BOOT_ADDR TYPHOON_REG_HOST2ARM1
  521. #define TYPHOON_REG_DOWNLOAD_HMAC_0 TYPHOON_REG_HOST2ARM2
  522. #define TYPHOON_REG_DOWNLOAD_HMAC_1 TYPHOON_REG_HOST2ARM3
  523. #define TYPHOON_REG_DOWNLOAD_HMAC_2 TYPHOON_REG_HOST2ARM4
  524. #define TYPHOON_REG_DOWNLOAD_HMAC_3 TYPHOON_REG_HOST2ARM5
  525. #define TYPHOON_REG_DOWNLOAD_HMAC_4 TYPHOON_REG_HOST2ARM6
  526. #define TYPHOON_REG_BOOT_RECORD_ADDR_HI TYPHOON_REG_HOST2ARM2
  527. #define TYPHOON_REG_BOOT_RECORD_ADDR_LO TYPHOON_REG_HOST2ARM1
  528. #define TYPHOON_REG_TX_LO_READY TYPHOON_REG_HOST2ARM3
  529. #define TYPHOON_REG_CMD_READY TYPHOON_REG_HOST2ARM2
  530. #define TYPHOON_REG_TX_HI_READY TYPHOON_REG_HOST2ARM1
  531. #define TYPHOON_REG_COMMAND TYPHOON_REG_HOST2ARM0
  532. #define TYPHOON_REG_HEARTBEAT TYPHOON_REG_ARM2HOST3
  533. #define TYPHOON_REG_STATUS TYPHOON_REG_ARM2HOST0
  534. /* 3XP Reset values (TYPHOON_REG_SOFT_RESET)
  535. */
  536. #define TYPHOON_RESET_ALL 0x7f
  537. #define TYPHOON_RESET_NONE 0x00
  538. /* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK})
  539. *
  540. * Some of these came from OpenBSD, as the 3Com docs have it wrong
  541. * (INTR_SELF) or don't list it at all (INTR_*_ABORT)
  542. *
  543. * Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq
  544. * about every 8ms, so don't do it.
  545. */
  546. #define TYPHOON_INTR_HOST_INT 0x00000001
  547. #define TYPHOON_INTR_ARM2HOST0 0x00000002
  548. #define TYPHOON_INTR_ARM2HOST1 0x00000004
  549. #define TYPHOON_INTR_ARM2HOST2 0x00000008
  550. #define TYPHOON_INTR_ARM2HOST3 0x00000010
  551. #define TYPHOON_INTR_DMA0 0x00000020
  552. #define TYPHOON_INTR_DMA1 0x00000040
  553. #define TYPHOON_INTR_DMA2 0x00000080
  554. #define TYPHOON_INTR_DMA3 0x00000100
  555. #define TYPHOON_INTR_MASTER_ABORT 0x00000200
  556. #define TYPHOON_INTR_TARGET_ABORT 0x00000400
  557. #define TYPHOON_INTR_SELF 0x00000800
  558. #define TYPHOON_INTR_RESERVED 0xfffff000
  559. #define TYPHOON_INTR_BOOTCMD TYPHOON_INTR_ARM2HOST0
  560. #define TYPHOON_INTR_ENABLE_ALL 0xffffffef
  561. #define TYPHOON_INTR_ALL 0xffffffff
  562. #define TYPHOON_INTR_NONE 0x00000000
  563. /* The commands for the 3XP chip (TYPHOON_REG_COMMAND)
  564. */
  565. #define TYPHOON_BOOTCMD_BOOT 0x00
  566. #define TYPHOON_BOOTCMD_WAKEUP 0xfa
  567. #define TYPHOON_BOOTCMD_DNLD_COMPLETE 0xfb
  568. #define TYPHOON_BOOTCMD_SEG_AVAILABLE 0xfc
  569. #define TYPHOON_BOOTCMD_RUNTIME_IMAGE 0xfd
  570. #define TYPHOON_BOOTCMD_REG_BOOT_RECORD 0xff
  571. /* 3XP Status values (TYPHOON_REG_STATUS)
  572. */
  573. #define TYPHOON_STATUS_WAITING_FOR_BOOT 0x07
  574. #define TYPHOON_STATUS_SECOND_INIT 0x08
  575. #define TYPHOON_STATUS_RUNNING 0x09
  576. #define TYPHOON_STATUS_WAITING_FOR_HOST 0x0d
  577. #define TYPHOON_STATUS_WAITING_FOR_SEGMENT 0x10
  578. #define TYPHOON_STATUS_SLEEPING 0x11
  579. #define TYPHOON_STATUS_HALTED 0x14