tsi108_eth.h 12 KB

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  1. /*
  2. * (C) Copyright 2005 Tundra Semiconductor Corp.
  3. * Kong Lai, <kong.lai@tundra.com).
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * net/tsi108_eth.h - definitions for Tsi108 GIGE network controller.
  25. */
  26. #ifndef __TSI108_ETH_H
  27. #define __TSI108_ETH_H
  28. #include <linux/types.h>
  29. #define TSI_WRITE(offset, val) \
  30. out_be32((data->regs + (offset)), val)
  31. #define TSI_READ(offset) \
  32. in_be32((data->regs + (offset)))
  33. #define TSI_WRITE_PHY(offset, val) \
  34. out_be32((data->phyregs + (offset)), val)
  35. #define TSI_READ_PHY(offset) \
  36. in_be32((data->phyregs + (offset)))
  37. /*
  38. * PHY Configuration Options
  39. *
  40. * NOTE: Enable set of definitions corresponding to your board type
  41. */
  42. #define PHY_MV88E 1 /* Marvel 88Exxxx PHY */
  43. #define PHY_BCM54XX 2 /* Broardcom BCM54xx PHY */
  44. #define TSI108_PHY_TYPE PHY_MV88E
  45. /*
  46. * TSI108 GIGE port registers
  47. */
  48. #define TSI108_ETH_PORT_NUM 2
  49. #define TSI108_PBM_PORT 2
  50. #define TSI108_SDRAM_PORT 4
  51. #define TSI108_MAC_CFG1 (0x000)
  52. #define TSI108_MAC_CFG1_SOFTRST (1 << 31)
  53. #define TSI108_MAC_CFG1_LOOPBACK (1 << 8)
  54. #define TSI108_MAC_CFG1_RXEN (1 << 2)
  55. #define TSI108_MAC_CFG1_TXEN (1 << 0)
  56. #define TSI108_MAC_CFG2 (0x004)
  57. #define TSI108_MAC_CFG2_DFLT_PREAMBLE (7 << 12)
  58. #define TSI108_MAC_CFG2_IFACE_MASK (3 << 8)
  59. #define TSI108_MAC_CFG2_NOGIG (1 << 8)
  60. #define TSI108_MAC_CFG2_GIG (2 << 8)
  61. #define TSI108_MAC_CFG2_PADCRC (1 << 2)
  62. #define TSI108_MAC_CFG2_FULLDUPLEX (1 << 0)
  63. #define TSI108_MAC_MII_MGMT_CFG (0x020)
  64. #define TSI108_MAC_MII_MGMT_CLK (7 << 0)
  65. #define TSI108_MAC_MII_MGMT_RST (1 << 31)
  66. #define TSI108_MAC_MII_CMD (0x024)
  67. #define TSI108_MAC_MII_CMD_READ (1 << 0)
  68. #define TSI108_MAC_MII_ADDR (0x028)
  69. #define TSI108_MAC_MII_ADDR_REG 0
  70. #define TSI108_MAC_MII_ADDR_PHY 8
  71. #define TSI108_MAC_MII_DATAOUT (0x02c)
  72. #define TSI108_MAC_MII_DATAIN (0x030)
  73. #define TSI108_MAC_MII_IND (0x034)
  74. #define TSI108_MAC_MII_IND_NOTVALID (1 << 2)
  75. #define TSI108_MAC_MII_IND_SCANNING (1 << 1)
  76. #define TSI108_MAC_MII_IND_BUSY (1 << 0)
  77. #define TSI108_MAC_IFCTRL (0x038)
  78. #define TSI108_MAC_IFCTRL_PHYMODE (1 << 24)
  79. #define TSI108_MAC_ADDR1 (0x040)
  80. #define TSI108_MAC_ADDR2 (0x044)
  81. #define TSI108_STAT_RXBYTES (0x06c)
  82. #define TSI108_STAT_RXBYTES_CARRY (1 << 24)
  83. #define TSI108_STAT_RXPKTS (0x070)
  84. #define TSI108_STAT_RXPKTS_CARRY (1 << 18)
  85. #define TSI108_STAT_RXFCS (0x074)
  86. #define TSI108_STAT_RXFCS_CARRY (1 << 12)
  87. #define TSI108_STAT_RXMCAST (0x078)
  88. #define TSI108_STAT_RXMCAST_CARRY (1 << 18)
  89. #define TSI108_STAT_RXALIGN (0x08c)
  90. #define TSI108_STAT_RXALIGN_CARRY (1 << 12)
  91. #define TSI108_STAT_RXLENGTH (0x090)
  92. #define TSI108_STAT_RXLENGTH_CARRY (1 << 12)
  93. #define TSI108_STAT_RXRUNT (0x09c)
  94. #define TSI108_STAT_RXRUNT_CARRY (1 << 12)
  95. #define TSI108_STAT_RXJUMBO (0x0a0)
  96. #define TSI108_STAT_RXJUMBO_CARRY (1 << 12)
  97. #define TSI108_STAT_RXFRAG (0x0a4)
  98. #define TSI108_STAT_RXFRAG_CARRY (1 << 12)
  99. #define TSI108_STAT_RXJABBER (0x0a8)
  100. #define TSI108_STAT_RXJABBER_CARRY (1 << 12)
  101. #define TSI108_STAT_RXDROP (0x0ac)
  102. #define TSI108_STAT_RXDROP_CARRY (1 << 12)
  103. #define TSI108_STAT_TXBYTES (0x0b0)
  104. #define TSI108_STAT_TXBYTES_CARRY (1 << 24)
  105. #define TSI108_STAT_TXPKTS (0x0b4)
  106. #define TSI108_STAT_TXPKTS_CARRY (1 << 18)
  107. #define TSI108_STAT_TXEXDEF (0x0c8)
  108. #define TSI108_STAT_TXEXDEF_CARRY (1 << 12)
  109. #define TSI108_STAT_TXEXCOL (0x0d8)
  110. #define TSI108_STAT_TXEXCOL_CARRY (1 << 12)
  111. #define TSI108_STAT_TXTCOL (0x0dc)
  112. #define TSI108_STAT_TXTCOL_CARRY (1 << 13)
  113. #define TSI108_STAT_TXPAUSEDROP (0x0e4)
  114. #define TSI108_STAT_TXPAUSEDROP_CARRY (1 << 12)
  115. #define TSI108_STAT_CARRY1 (0x100)
  116. #define TSI108_STAT_CARRY1_RXBYTES (1 << 16)
  117. #define TSI108_STAT_CARRY1_RXPKTS (1 << 15)
  118. #define TSI108_STAT_CARRY1_RXFCS (1 << 14)
  119. #define TSI108_STAT_CARRY1_RXMCAST (1 << 13)
  120. #define TSI108_STAT_CARRY1_RXALIGN (1 << 8)
  121. #define TSI108_STAT_CARRY1_RXLENGTH (1 << 7)
  122. #define TSI108_STAT_CARRY1_RXRUNT (1 << 4)
  123. #define TSI108_STAT_CARRY1_RXJUMBO (1 << 3)
  124. #define TSI108_STAT_CARRY1_RXFRAG (1 << 2)
  125. #define TSI108_STAT_CARRY1_RXJABBER (1 << 1)
  126. #define TSI108_STAT_CARRY1_RXDROP (1 << 0)
  127. #define TSI108_STAT_CARRY2 (0x104)
  128. #define TSI108_STAT_CARRY2_TXBYTES (1 << 13)
  129. #define TSI108_STAT_CARRY2_TXPKTS (1 << 12)
  130. #define TSI108_STAT_CARRY2_TXEXDEF (1 << 7)
  131. #define TSI108_STAT_CARRY2_TXEXCOL (1 << 3)
  132. #define TSI108_STAT_CARRY2_TXTCOL (1 << 2)
  133. #define TSI108_STAT_CARRY2_TXPAUSE (1 << 0)
  134. #define TSI108_STAT_CARRYMASK1 (0x108)
  135. #define TSI108_STAT_CARRYMASK2 (0x10c)
  136. #define TSI108_EC_PORTCTRL (0x200)
  137. #define TSI108_EC_PORTCTRL_STATRST (1 << 31)
  138. #define TSI108_EC_PORTCTRL_STATEN (1 << 28)
  139. #define TSI108_EC_PORTCTRL_NOGIG (1 << 18)
  140. #define TSI108_EC_PORTCTRL_HALFDUPLEX (1 << 16)
  141. #define TSI108_EC_INTSTAT (0x204)
  142. #define TSI108_EC_INTMASK (0x208)
  143. #define TSI108_INT_ANY (1 << 31)
  144. #define TSI108_INT_SFN (1 << 30)
  145. #define TSI108_INT_RXIDLE (1 << 29)
  146. #define TSI108_INT_RXABORT (1 << 28)
  147. #define TSI108_INT_RXERROR (1 << 27)
  148. #define TSI108_INT_RXOVERRUN (1 << 26)
  149. #define TSI108_INT_RXTHRESH (1 << 25)
  150. #define TSI108_INT_RXWAIT (1 << 24)
  151. #define TSI108_INT_RXQUEUE0 (1 << 16)
  152. #define TSI108_INT_STATCARRY (1 << 15)
  153. #define TSI108_INT_TXIDLE (1 << 13)
  154. #define TSI108_INT_TXABORT (1 << 12)
  155. #define TSI108_INT_TXERROR (1 << 11)
  156. #define TSI108_INT_TXUNDERRUN (1 << 10)
  157. #define TSI108_INT_TXTHRESH (1 << 9)
  158. #define TSI108_INT_TXWAIT (1 << 8)
  159. #define TSI108_INT_TXQUEUE0 (1 << 0)
  160. #define TSI108_EC_TXCFG (0x220)
  161. #define TSI108_EC_TXCFG_RST (1 << 31)
  162. #define TSI108_EC_TXCTRL (0x224)
  163. #define TSI108_EC_TXCTRL_IDLEINT (1 << 31)
  164. #define TSI108_EC_TXCTRL_ABORT (1 << 30)
  165. #define TSI108_EC_TXCTRL_GO (1 << 15)
  166. #define TSI108_EC_TXCTRL_QUEUE0 (1 << 0)
  167. #define TSI108_EC_TXSTAT (0x228)
  168. #define TSI108_EC_TXSTAT_ACTIVE (1 << 15)
  169. #define TSI108_EC_TXSTAT_QUEUE0 (1 << 0)
  170. #define TSI108_EC_TXESTAT (0x22c)
  171. #define TSI108_EC_TXESTAT_Q0_ERR (1 << 24)
  172. #define TSI108_EC_TXESTAT_Q0_DESCINT (1 << 16)
  173. #define TSI108_EC_TXESTAT_Q0_EOF (1 << 8)
  174. #define TSI108_EC_TXESTAT_Q0_EOQ (1 << 0)
  175. #define TSI108_EC_TXERR (0x278)
  176. #define TSI108_EC_TXQ_CFG (0x280)
  177. #define TSI108_EC_TXQ_CFG_DESC_INT (1 << 20)
  178. #define TSI108_EC_TXQ_CFG_EOQ_OWN_INT (1 << 19)
  179. #define TSI108_EC_TXQ_CFG_WSWP (1 << 11)
  180. #define TSI108_EC_TXQ_CFG_BSWP (1 << 10)
  181. #define TSI108_EC_TXQ_CFG_SFNPORT 0
  182. #define TSI108_EC_TXQ_BUFCFG (0x284)
  183. #define TSI108_EC_TXQ_BUFCFG_BURST8 (0 << 8)
  184. #define TSI108_EC_TXQ_BUFCFG_BURST32 (1 << 8)
  185. #define TSI108_EC_TXQ_BUFCFG_BURST128 (2 << 8)
  186. #define TSI108_EC_TXQ_BUFCFG_BURST256 (3 << 8)
  187. #define TSI108_EC_TXQ_BUFCFG_WSWP (1 << 11)
  188. #define TSI108_EC_TXQ_BUFCFG_BSWP (1 << 10)
  189. #define TSI108_EC_TXQ_BUFCFG_SFNPORT 0
  190. #define TSI108_EC_TXQ_PTRLOW (0x288)
  191. #define TSI108_EC_TXQ_PTRHIGH (0x28c)
  192. #define TSI108_EC_TXQ_PTRHIGH_VALID (1 << 31)
  193. #define TSI108_EC_TXTHRESH (0x230)
  194. #define TSI108_EC_TXTHRESH_STARTFILL 0
  195. #define TSI108_EC_TXTHRESH_STOPFILL 16
  196. #define TSI108_EC_RXCFG (0x320)
  197. #define TSI108_EC_RXCFG_RST (1 << 31)
  198. #define TSI108_EC_RXSTAT (0x328)
  199. #define TSI108_EC_RXSTAT_ACTIVE (1 << 15)
  200. #define TSI108_EC_RXSTAT_QUEUE0 (1 << 0)
  201. #define TSI108_EC_RXESTAT (0x32c)
  202. #define TSI108_EC_RXESTAT_Q0_ERR (1 << 24)
  203. #define TSI108_EC_RXESTAT_Q0_DESCINT (1 << 16)
  204. #define TSI108_EC_RXESTAT_Q0_EOF (1 << 8)
  205. #define TSI108_EC_RXESTAT_Q0_EOQ (1 << 0)
  206. #define TSI108_EC_HASHADDR (0x360)
  207. #define TSI108_EC_HASHADDR_AUTOINC (1 << 31)
  208. #define TSI108_EC_HASHADDR_DO1STREAD (1 << 30)
  209. #define TSI108_EC_HASHADDR_UNICAST (0 << 4)
  210. #define TSI108_EC_HASHADDR_MCAST (1 << 4)
  211. #define TSI108_EC_HASHDATA (0x364)
  212. #define TSI108_EC_RXQ_PTRLOW (0x388)
  213. #define TSI108_EC_RXQ_PTRHIGH (0x38c)
  214. #define TSI108_EC_RXQ_PTRHIGH_VALID (1 << 31)
  215. /* Station Enable -- accept packets destined for us */
  216. #define TSI108_EC_RXCFG_SE (1 << 13)
  217. /* Unicast Frame Enable -- for packets not destined for us */
  218. #define TSI108_EC_RXCFG_UFE (1 << 12)
  219. /* Multicast Frame Enable */
  220. #define TSI108_EC_RXCFG_MFE (1 << 11)
  221. /* Broadcast Frame Enable */
  222. #define TSI108_EC_RXCFG_BFE (1 << 10)
  223. #define TSI108_EC_RXCFG_UC_HASH (1 << 9)
  224. #define TSI108_EC_RXCFG_MC_HASH (1 << 8)
  225. #define TSI108_EC_RXQ_CFG (0x380)
  226. #define TSI108_EC_RXQ_CFG_DESC_INT (1 << 20)
  227. #define TSI108_EC_RXQ_CFG_EOQ_OWN_INT (1 << 19)
  228. #define TSI108_EC_RXQ_CFG_WSWP (1 << 11)
  229. #define TSI108_EC_RXQ_CFG_BSWP (1 << 10)
  230. #define TSI108_EC_RXQ_CFG_SFNPORT 0
  231. #define TSI108_EC_RXQ_BUFCFG (0x384)
  232. #define TSI108_EC_RXQ_BUFCFG_BURST8 (0 << 8)
  233. #define TSI108_EC_RXQ_BUFCFG_BURST32 (1 << 8)
  234. #define TSI108_EC_RXQ_BUFCFG_BURST128 (2 << 8)
  235. #define TSI108_EC_RXQ_BUFCFG_BURST256 (3 << 8)
  236. #define TSI108_EC_RXQ_BUFCFG_WSWP (1 << 11)
  237. #define TSI108_EC_RXQ_BUFCFG_BSWP (1 << 10)
  238. #define TSI108_EC_RXQ_BUFCFG_SFNPORT 0
  239. #define TSI108_EC_RXCTRL (0x324)
  240. #define TSI108_EC_RXCTRL_ABORT (1 << 30)
  241. #define TSI108_EC_RXCTRL_GO (1 << 15)
  242. #define TSI108_EC_RXCTRL_QUEUE0 (1 << 0)
  243. #define TSI108_EC_RXERR (0x378)
  244. #define TSI108_TX_EOF (1 << 0) /* End of frame; last fragment of packet */
  245. #define TSI108_TX_SOF (1 << 1) /* Start of frame; first frag. of packet */
  246. #define TSI108_TX_VLAN (1 << 2) /* Per-frame VLAN: enables VLAN override */
  247. #define TSI108_TX_HUGE (1 << 3) /* Huge frame enable */
  248. #define TSI108_TX_PAD (1 << 4) /* Pad the packet if too short */
  249. #define TSI108_TX_CRC (1 << 5) /* Generate CRC for this packet */
  250. #define TSI108_TX_INT (1 << 14) /* Generate an IRQ after frag. processed */
  251. #define TSI108_TX_RETRY (0xf << 16) /* 4 bit field indicating num. of retries */
  252. #define TSI108_TX_COL (1 << 20) /* Set if a collision occured */
  253. #define TSI108_TX_LCOL (1 << 24) /* Set if a late collision occured */
  254. #define TSI108_TX_UNDER (1 << 25) /* Set if a FIFO underrun occured */
  255. #define TSI108_TX_RLIM (1 << 26) /* Set if the retry limit was reached */
  256. #define TSI108_TX_OK (1 << 30) /* Set if the frame TX was successful */
  257. #define TSI108_TX_OWN (1 << 31) /* Set if the device owns the descriptor */
  258. /* Note: the descriptor layouts assume big-endian byte order. */
  259. typedef struct {
  260. u32 buf0;
  261. u32 buf1; /* Base address of buffer */
  262. u32 next0; /* Address of next descriptor, if any */
  263. u32 next1;
  264. u16 vlan; /* VLAN, if override enabled for this packet */
  265. u16 len; /* Length of buffer in bytes */
  266. u32 misc; /* See TSI108_TX_* above */
  267. u32 reserved0; /*reserved0 and reserved1 are added to make the desc */
  268. u32 reserved1; /* 32-byte aligned */
  269. } __attribute__ ((aligned(32))) tx_desc;
  270. #define TSI108_RX_EOF (1 << 0) /* End of frame; last fragment of packet */
  271. #define TSI108_RX_SOF (1 << 1) /* Start of frame; first frag. of packet */
  272. #define TSI108_RX_VLAN (1 << 2) /* Set on SOF if packet has a VLAN */
  273. #define TSI108_RX_FTYPE (1 << 3) /* Length/Type field is type, not length */
  274. #define TSI108_RX_RUNT (1 << 4)/* Packet is less than minimum size */
  275. #define TSI108_RX_HASH (1 << 7)/* Hash table match */
  276. #define TSI108_RX_BAD (1 << 8) /* Bad frame */
  277. #define TSI108_RX_OVER (1 << 9) /* FIFO overrun occured */
  278. #define TSI108_RX_TRUNC (1 << 11) /* Packet truncated due to excess length */
  279. #define TSI108_RX_CRC (1 << 12) /* Packet had a CRC error */
  280. #define TSI108_RX_INT (1 << 13) /* Generate an IRQ after frag. processed */
  281. #define TSI108_RX_OWN (1 << 15) /* Set if the device owns the descriptor */
  282. #define TSI108_RX_SKB_SIZE 1536 /* The RX skb length */
  283. typedef struct {
  284. u32 buf0; /* Base address of buffer */
  285. u32 buf1; /* Base address of buffer */
  286. u32 next0; /* Address of next descriptor, if any */
  287. u32 next1; /* Address of next descriptor, if any */
  288. u16 vlan; /* VLAN of received packet, first frag only */
  289. u16 len; /* Length of received fragment in bytes */
  290. u16 blen; /* Length of buffer in bytes */
  291. u16 misc; /* See TSI108_RX_* above */
  292. u32 reserved0; /* reserved0 and reserved1 are added to make the desc */
  293. u32 reserved1; /* 32-byte aligned */
  294. } __attribute__ ((aligned(32))) rx_desc;
  295. #endif /* __TSI108_ETH_H */