tlan.h 15 KB

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  1. #ifndef TLAN_H
  2. #define TLAN_H
  3. /********************************************************************
  4. *
  5. * Linux ThunderLAN Driver
  6. *
  7. * tlan.h
  8. * by James Banks
  9. *
  10. * (C) 1997-1998 Caldera, Inc.
  11. * (C) 1999-2001 Torben Mathiasen
  12. *
  13. * This software may be used and distributed according to the terms
  14. * of the GNU General Public License, incorporated herein by reference.
  15. *
  16. ** This file is best viewed/edited with tabstop=4, colums>=132
  17. *
  18. *
  19. * Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com>
  20. * New Maintainer
  21. *
  22. ********************************************************************/
  23. #include <asm/io.h>
  24. #include <asm/types.h>
  25. #include <linux/netdevice.h>
  26. /*****************************************************************
  27. * TLan Definitions
  28. *
  29. ****************************************************************/
  30. #define FALSE 0
  31. #define TRUE 1
  32. #define TLAN_MIN_FRAME_SIZE 64
  33. #define TLAN_MAX_FRAME_SIZE 1600
  34. #define TLAN_NUM_RX_LISTS 32
  35. #define TLAN_NUM_TX_LISTS 64
  36. #define TLAN_IGNORE 0
  37. #define TLAN_RECORD 1
  38. #define TLAN_DBG(lvl, format, args...) if (debug&lvl) printk(KERN_DEBUG "TLAN: " format, ##args );
  39. #define TLAN_DEBUG_GNRL 0x0001
  40. #define TLAN_DEBUG_TX 0x0002
  41. #define TLAN_DEBUG_RX 0x0004
  42. #define TLAN_DEBUG_LIST 0x0008
  43. #define TLAN_DEBUG_PROBE 0x0010
  44. #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */
  45. #define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */
  46. /*****************************************************************
  47. * Device Identification Definitions
  48. *
  49. ****************************************************************/
  50. #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
  51. #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
  52. #ifndef PCI_DEVICE_ID_OLICOM_OC2183
  53. #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
  54. #endif
  55. #ifndef PCI_DEVICE_ID_OLICOM_OC2325
  56. #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
  57. #endif
  58. #ifndef PCI_DEVICE_ID_OLICOM_OC2326
  59. #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
  60. #endif
  61. typedef struct tlan_adapter_entry {
  62. u16 vendorId;
  63. u16 deviceId;
  64. char *deviceLabel;
  65. u32 flags;
  66. u16 addrOfs;
  67. } TLanAdapterEntry;
  68. #define TLAN_ADAPTER_NONE 0x00000000
  69. #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
  70. #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
  71. #define TLAN_ADAPTER_USE_INTERN_10 0x00000004
  72. #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
  73. #define TLAN_SPEED_DEFAULT 0
  74. #define TLAN_SPEED_10 10
  75. #define TLAN_SPEED_100 100
  76. #define TLAN_DUPLEX_DEFAULT 0
  77. #define TLAN_DUPLEX_HALF 1
  78. #define TLAN_DUPLEX_FULL 2
  79. /*****************************************************************
  80. * EISA Definitions
  81. *
  82. ****************************************************************/
  83. #define EISA_ID 0xc80 /* EISA ID Registers */
  84. #define EISA_ID0 0xc80 /* EISA ID Register 0 */
  85. #define EISA_ID1 0xc81 /* EISA ID Register 1 */
  86. #define EISA_ID2 0xc82 /* EISA ID Register 2 */
  87. #define EISA_ID3 0xc83 /* EISA ID Register 3 */
  88. #define EISA_CR 0xc84 /* EISA Control Register */
  89. #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
  90. #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
  91. #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
  92. #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
  93. #define EISA_APROM 0xc90 /* Ethernet Address PROM */
  94. /*****************************************************************
  95. * Rx/Tx List Definitions
  96. *
  97. ****************************************************************/
  98. #define TLAN_BUFFERS_PER_LIST 10
  99. #define TLAN_LAST_BUFFER 0x80000000
  100. #define TLAN_CSTAT_UNUSED 0x8000
  101. #define TLAN_CSTAT_FRM_CMP 0x4000
  102. #define TLAN_CSTAT_READY 0x3000
  103. #define TLAN_CSTAT_EOC 0x0800
  104. #define TLAN_CSTAT_RX_ERROR 0x0400
  105. #define TLAN_CSTAT_PASS_CRC 0x0200
  106. #define TLAN_CSTAT_DP_PR 0x0100
  107. typedef struct tlan_buffer_ref_tag {
  108. u32 count;
  109. u32 address;
  110. } TLanBufferRef;
  111. typedef struct tlan_list_tag {
  112. u32 forward;
  113. u16 cStat;
  114. u16 frameSize;
  115. TLanBufferRef buffer[TLAN_BUFFERS_PER_LIST];
  116. } TLanList;
  117. typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
  118. /*****************************************************************
  119. * PHY definitions
  120. *
  121. ****************************************************************/
  122. #define TLAN_PHY_MAX_ADDR 0x1F
  123. #define TLAN_PHY_NONE 0x20
  124. /*****************************************************************
  125. * TLAN Private Information Structure
  126. *
  127. ****************************************************************/
  128. typedef struct tlan_private_tag {
  129. struct net_device *nextDevice;
  130. struct pci_dev *pciDev;
  131. struct net_device *dev;
  132. void *dmaStorage;
  133. dma_addr_t dmaStorageDMA;
  134. unsigned int dmaSize;
  135. u8 *padBuffer;
  136. TLanList *rxList;
  137. dma_addr_t rxListDMA;
  138. u8 *rxBuffer;
  139. dma_addr_t rxBufferDMA;
  140. u32 rxHead;
  141. u32 rxTail;
  142. u32 rxEocCount;
  143. TLanList *txList;
  144. dma_addr_t txListDMA;
  145. u8 *txBuffer;
  146. dma_addr_t txBufferDMA;
  147. u32 txHead;
  148. u32 txInProgress;
  149. u32 txTail;
  150. u32 txBusyCount;
  151. u32 phyOnline;
  152. u32 timerSetAt;
  153. u32 timerType;
  154. struct timer_list timer;
  155. struct net_device_stats stats;
  156. struct board *adapter;
  157. u32 adapterRev;
  158. u32 aui;
  159. u32 debug;
  160. u32 duplex;
  161. u32 phy[2];
  162. u32 phyNum;
  163. u32 speed;
  164. u8 tlanRev;
  165. u8 tlanFullDuplex;
  166. char devName[8];
  167. spinlock_t lock;
  168. u8 link;
  169. u8 is_eisa;
  170. struct work_struct tlan_tqueue;
  171. u8 neg_be_verbose;
  172. } TLanPrivateInfo;
  173. /*****************************************************************
  174. * TLan Driver Timer Definitions
  175. *
  176. ****************************************************************/
  177. #define TLAN_TIMER_LINK_BEAT 1
  178. #define TLAN_TIMER_ACTIVITY 2
  179. #define TLAN_TIMER_PHY_PDOWN 3
  180. #define TLAN_TIMER_PHY_PUP 4
  181. #define TLAN_TIMER_PHY_RESET 5
  182. #define TLAN_TIMER_PHY_START_LINK 6
  183. #define TLAN_TIMER_PHY_FINISH_AN 7
  184. #define TLAN_TIMER_FINISH_RESET 8
  185. #define TLAN_TIMER_ACT_DELAY (HZ/10)
  186. /*****************************************************************
  187. * TLan Driver Eeprom Definitions
  188. *
  189. ****************************************************************/
  190. #define TLAN_EEPROM_ACK 0
  191. #define TLAN_EEPROM_STOP 1
  192. /*****************************************************************
  193. * Host Register Offsets and Contents
  194. *
  195. ****************************************************************/
  196. #define TLAN_HOST_CMD 0x00
  197. #define TLAN_HC_GO 0x80000000
  198. #define TLAN_HC_STOP 0x40000000
  199. #define TLAN_HC_ACK 0x20000000
  200. #define TLAN_HC_CS_MASK 0x1FE00000
  201. #define TLAN_HC_EOC 0x00100000
  202. #define TLAN_HC_RT 0x00080000
  203. #define TLAN_HC_NES 0x00040000
  204. #define TLAN_HC_AD_RST 0x00008000
  205. #define TLAN_HC_LD_TMR 0x00004000
  206. #define TLAN_HC_LD_THR 0x00002000
  207. #define TLAN_HC_REQ_INT 0x00001000
  208. #define TLAN_HC_INT_OFF 0x00000800
  209. #define TLAN_HC_INT_ON 0x00000400
  210. #define TLAN_HC_AC_MASK 0x000000FF
  211. #define TLAN_CH_PARM 0x04
  212. #define TLAN_DIO_ADR 0x08
  213. #define TLAN_DA_ADR_INC 0x8000
  214. #define TLAN_DA_RAM_ADR 0x4000
  215. #define TLAN_HOST_INT 0x0A
  216. #define TLAN_HI_IV_MASK 0x1FE0
  217. #define TLAN_HI_IT_MASK 0x001C
  218. #define TLAN_DIO_DATA 0x0C
  219. /* ThunderLAN Internal Register DIO Offsets */
  220. #define TLAN_NET_CMD 0x00
  221. #define TLAN_NET_CMD_NRESET 0x80
  222. #define TLAN_NET_CMD_NWRAP 0x40
  223. #define TLAN_NET_CMD_CSF 0x20
  224. #define TLAN_NET_CMD_CAF 0x10
  225. #define TLAN_NET_CMD_NOBRX 0x08
  226. #define TLAN_NET_CMD_DUPLEX 0x04
  227. #define TLAN_NET_CMD_TRFRAM 0x02
  228. #define TLAN_NET_CMD_TXPACE 0x01
  229. #define TLAN_NET_SIO 0x01
  230. #define TLAN_NET_SIO_MINTEN 0x80
  231. #define TLAN_NET_SIO_ECLOK 0x40
  232. #define TLAN_NET_SIO_ETXEN 0x20
  233. #define TLAN_NET_SIO_EDATA 0x10
  234. #define TLAN_NET_SIO_NMRST 0x08
  235. #define TLAN_NET_SIO_MCLK 0x04
  236. #define TLAN_NET_SIO_MTXEN 0x02
  237. #define TLAN_NET_SIO_MDATA 0x01
  238. #define TLAN_NET_STS 0x02
  239. #define TLAN_NET_STS_MIRQ 0x80
  240. #define TLAN_NET_STS_HBEAT 0x40
  241. #define TLAN_NET_STS_TXSTOP 0x20
  242. #define TLAN_NET_STS_RXSTOP 0x10
  243. #define TLAN_NET_STS_RSRVD 0x0F
  244. #define TLAN_NET_MASK 0x03
  245. #define TLAN_NET_MASK_MASK7 0x80
  246. #define TLAN_NET_MASK_MASK6 0x40
  247. #define TLAN_NET_MASK_MASK5 0x20
  248. #define TLAN_NET_MASK_MASK4 0x10
  249. #define TLAN_NET_MASK_RSRVD 0x0F
  250. #define TLAN_NET_CONFIG 0x04
  251. #define TLAN_NET_CFG_RCLK 0x8000
  252. #define TLAN_NET_CFG_TCLK 0x4000
  253. #define TLAN_NET_CFG_BIT 0x2000
  254. #define TLAN_NET_CFG_RXCRC 0x1000
  255. #define TLAN_NET_CFG_PEF 0x0800
  256. #define TLAN_NET_CFG_1FRAG 0x0400
  257. #define TLAN_NET_CFG_1CHAN 0x0200
  258. #define TLAN_NET_CFG_MTEST 0x0100
  259. #define TLAN_NET_CFG_PHY_EN 0x0080
  260. #define TLAN_NET_CFG_MSMASK 0x007F
  261. #define TLAN_MAN_TEST 0x06
  262. #define TLAN_DEF_VENDOR_ID 0x08
  263. #define TLAN_DEF_DEVICE_ID 0x0A
  264. #define TLAN_DEF_REVISION 0x0C
  265. #define TLAN_DEF_SUBCLASS 0x0D
  266. #define TLAN_DEF_MIN_LAT 0x0E
  267. #define TLAN_DEF_MAX_LAT 0x0F
  268. #define TLAN_AREG_0 0x10
  269. #define TLAN_AREG_1 0x16
  270. #define TLAN_AREG_2 0x1C
  271. #define TLAN_AREG_3 0x22
  272. #define TLAN_HASH_1 0x28
  273. #define TLAN_HASH_2 0x2C
  274. #define TLAN_GOOD_TX_FRMS 0x30
  275. #define TLAN_TX_UNDERUNS 0x33
  276. #define TLAN_GOOD_RX_FRMS 0x34
  277. #define TLAN_RX_OVERRUNS 0x37
  278. #define TLAN_DEFERRED_TX 0x38
  279. #define TLAN_CRC_ERRORS 0x3A
  280. #define TLAN_CODE_ERRORS 0x3B
  281. #define TLAN_MULTICOL_FRMS 0x3C
  282. #define TLAN_SINGLECOL_FRMS 0x3E
  283. #define TLAN_EXCESSCOL_FRMS 0x40
  284. #define TLAN_LATE_COLS 0x41
  285. #define TLAN_CARRIER_LOSS 0x42
  286. #define TLAN_ACOMMIT 0x43
  287. #define TLAN_LED_REG 0x44
  288. #define TLAN_LED_ACT 0x10
  289. #define TLAN_LED_LINK 0x01
  290. #define TLAN_BSIZE_REG 0x45
  291. #define TLAN_MAX_RX 0x46
  292. #define TLAN_INT_DIS 0x48
  293. #define TLAN_ID_TX_EOC 0x04
  294. #define TLAN_ID_RX_EOF 0x02
  295. #define TLAN_ID_RX_EOC 0x01
  296. /* ThunderLAN Interrupt Codes */
  297. #define TLAN_INT_NUMBER_OF_INTS 8
  298. #define TLAN_INT_NONE 0x0000
  299. #define TLAN_INT_TX_EOF 0x0001
  300. #define TLAN_INT_STAT_OVERFLOW 0x0002
  301. #define TLAN_INT_RX_EOF 0x0003
  302. #define TLAN_INT_DUMMY 0x0004
  303. #define TLAN_INT_TX_EOC 0x0005
  304. #define TLAN_INT_STATUS_CHECK 0x0006
  305. #define TLAN_INT_RX_EOC 0x0007
  306. /* ThunderLAN MII Registers */
  307. /* Generic MII/PHY Registers */
  308. #define MII_GEN_CTL 0x00
  309. #define MII_GC_RESET 0x8000
  310. #define MII_GC_LOOPBK 0x4000
  311. #define MII_GC_SPEEDSEL 0x2000
  312. #define MII_GC_AUTOENB 0x1000
  313. #define MII_GC_PDOWN 0x0800
  314. #define MII_GC_ISOLATE 0x0400
  315. #define MII_GC_AUTORSRT 0x0200
  316. #define MII_GC_DUPLEX 0x0100
  317. #define MII_GC_COLTEST 0x0080
  318. #define MII_GC_RESERVED 0x007F
  319. #define MII_GEN_STS 0x01
  320. #define MII_GS_100BT4 0x8000
  321. #define MII_GS_100BTXFD 0x4000
  322. #define MII_GS_100BTXHD 0x2000
  323. #define MII_GS_10BTFD 0x1000
  324. #define MII_GS_10BTHD 0x0800
  325. #define MII_GS_RESERVED 0x07C0
  326. #define MII_GS_AUTOCMPLT 0x0020
  327. #define MII_GS_RFLT 0x0010
  328. #define MII_GS_AUTONEG 0x0008
  329. #define MII_GS_LINK 0x0004
  330. #define MII_GS_JABBER 0x0002
  331. #define MII_GS_EXTCAP 0x0001
  332. #define MII_GEN_ID_HI 0x02
  333. #define MII_GEN_ID_LO 0x03
  334. #define MII_GIL_OUI 0xFC00
  335. #define MII_GIL_MODEL 0x03F0
  336. #define MII_GIL_REVISION 0x000F
  337. #define MII_AN_ADV 0x04
  338. #define MII_AN_LPA 0x05
  339. #define MII_AN_EXP 0x06
  340. /* ThunderLAN Specific MII/PHY Registers */
  341. #define TLAN_TLPHY_ID 0x10
  342. #define TLAN_TLPHY_CTL 0x11
  343. #define TLAN_TC_IGLINK 0x8000
  344. #define TLAN_TC_SWAPOL 0x4000
  345. #define TLAN_TC_AUISEL 0x2000
  346. #define TLAN_TC_SQEEN 0x1000
  347. #define TLAN_TC_MTEST 0x0800
  348. #define TLAN_TC_RESERVED 0x07F8
  349. #define TLAN_TC_NFEW 0x0004
  350. #define TLAN_TC_INTEN 0x0002
  351. #define TLAN_TC_TINT 0x0001
  352. #define TLAN_TLPHY_STS 0x12
  353. #define TLAN_TS_MINT 0x8000
  354. #define TLAN_TS_PHOK 0x4000
  355. #define TLAN_TS_POLOK 0x2000
  356. #define TLAN_TS_TPENERGY 0x1000
  357. #define TLAN_TS_RESERVED 0x0FFF
  358. #define TLAN_TLPHY_PAR 0x19
  359. #define TLAN_PHY_CIM_STAT 0x0020
  360. #define TLAN_PHY_SPEED_100 0x0040
  361. #define TLAN_PHY_DUPLEX_FULL 0x0080
  362. #define TLAN_PHY_AN_EN_STAT 0x0400
  363. /* National Sem. & Level1 PHY id's */
  364. #define NAT_SEM_ID1 0x2000
  365. #define NAT_SEM_ID2 0x5C01
  366. #define LEVEL1_ID1 0x7810
  367. #define LEVEL1_ID2 0x0000
  368. #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
  369. /* Routines to access internal registers. */
  370. static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
  371. {
  372. outw(internal_addr, base_addr + TLAN_DIO_ADR);
  373. return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
  374. } /* TLan_DioRead8 */
  375. static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
  376. {
  377. outw(internal_addr, base_addr + TLAN_DIO_ADR);
  378. return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
  379. } /* TLan_DioRead16 */
  380. static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
  381. {
  382. outw(internal_addr, base_addr + TLAN_DIO_ADR);
  383. return (inl(base_addr + TLAN_DIO_DATA));
  384. } /* TLan_DioRead32 */
  385. static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
  386. {
  387. outw(internal_addr, base_addr + TLAN_DIO_ADR);
  388. outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
  389. }
  390. static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
  391. {
  392. outw(internal_addr, base_addr + TLAN_DIO_ADR);
  393. outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
  394. }
  395. static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
  396. {
  397. outw(internal_addr, base_addr + TLAN_DIO_ADR);
  398. outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
  399. }
  400. #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port)
  401. #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit))
  402. #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port)
  403. /*
  404. * given 6 bytes, view them as 8 6-bit numbers and return the XOR of those
  405. * the code below is about seven times as fast as the original code
  406. *
  407. * The original code was:
  408. *
  409. * u32 xor( u32 a, u32 b ) { return ( ( a && ! b ) || ( ! a && b ) ); }
  410. *
  411. * #define XOR8( a, b, c, d, e, f, g, h ) \
  412. * xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
  413. * #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
  414. *
  415. * hash = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), DA(a,36), DA(a,42) );
  416. * hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), DA(a,37), DA(a,43) ) << 1;
  417. * hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), DA(a,38), DA(a,44) ) << 2;
  418. * hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), DA(a,39), DA(a,45) ) << 3;
  419. * hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), DA(a,40), DA(a,46) ) << 4;
  420. * hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), DA(a,41), DA(a,47) ) << 5;
  421. *
  422. */
  423. static inline u32 TLan_HashFunc( const u8 *a )
  424. {
  425. u8 hash;
  426. hash = (a[0]^a[3]); /* & 077 */
  427. hash ^= ((a[0]^a[3])>>6); /* & 003 */
  428. hash ^= ((a[1]^a[4])<<2); /* & 074 */
  429. hash ^= ((a[1]^a[4])>>4); /* & 017 */
  430. hash ^= ((a[2]^a[5])<<4); /* & 060 */
  431. hash ^= ((a[2]^a[5])>>2); /* & 077 */
  432. return (hash & 077);
  433. }
  434. #endif