tg3.h 87 KB

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  1. /* $Id: tg3.h,v 1.1.1.1 2007/06/12 07:27:11 eyryu Exp $
  2. * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. */
  8. #ifndef _T3_H
  9. #define _T3_H
  10. #define TG3_64BIT_REG_HIGH 0x00UL
  11. #define TG3_64BIT_REG_LOW 0x04UL
  12. /* Descriptor block info. */
  13. #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
  14. #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
  15. #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
  16. #define BDINFO_FLAGS_DISABLED 0x00000002
  17. #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
  18. #define BDINFO_FLAGS_MAXLEN_SHIFT 16
  19. #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
  20. #define TG3_BDINFO_SIZE 0x10UL
  21. #define RX_COPY_THRESHOLD 256
  22. #define TG3_RX_INTERNAL_RING_SZ_5906 32
  23. #define RX_STD_MAX_SIZE 1536
  24. #define RX_STD_MAX_SIZE_5705 512
  25. #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
  26. /* First 256 bytes are a mirror of PCI config space. */
  27. #define TG3PCI_VENDOR 0x00000000
  28. #define TG3PCI_VENDOR_BROADCOM 0x14e4
  29. #define TG3PCI_DEVICE 0x00000002
  30. #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
  31. #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
  32. #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
  33. #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
  34. #define TG3PCI_COMMAND 0x00000004
  35. #define TG3PCI_STATUS 0x00000006
  36. #define TG3PCI_CCREVID 0x00000008
  37. #define TG3PCI_CACHELINESZ 0x0000000c
  38. #define TG3PCI_LATTIMER 0x0000000d
  39. #define TG3PCI_HEADERTYPE 0x0000000e
  40. #define TG3PCI_BIST 0x0000000f
  41. #define TG3PCI_BASE0_LOW 0x00000010
  42. #define TG3PCI_BASE0_HIGH 0x00000014
  43. /* 0x18 --> 0x2c unused */
  44. #define TG3PCI_SUBSYSVENID 0x0000002c
  45. #define TG3PCI_SUBSYSID 0x0000002e
  46. #define TG3PCI_ROMADDR 0x00000030
  47. #define TG3PCI_CAPLIST 0x00000034
  48. /* 0x35 --> 0x3c unused */
  49. #define TG3PCI_IRQ_LINE 0x0000003c
  50. #define TG3PCI_IRQ_PIN 0x0000003d
  51. #define TG3PCI_MIN_GNT 0x0000003e
  52. #define TG3PCI_MAX_LAT 0x0000003f
  53. #define TG3PCI_X_CAPS 0x00000040
  54. #define PCIX_CAPS_RELAXED_ORDERING 0x00020000
  55. #define PCIX_CAPS_SPLIT_MASK 0x00700000
  56. #define PCIX_CAPS_SPLIT_SHIFT 20
  57. #define PCIX_CAPS_BURST_MASK 0x000c0000
  58. #define PCIX_CAPS_BURST_SHIFT 18
  59. #define PCIX_CAPS_MAX_BURST_CPIOB 2
  60. #define TG3PCI_PM_CAP_PTR 0x00000041
  61. #define TG3PCI_X_COMMAND 0x00000042
  62. #define TG3PCI_X_STATUS 0x00000044
  63. #define TG3PCI_PM_CAP_ID 0x00000048
  64. #define TG3PCI_VPD_CAP_PTR 0x00000049
  65. #define TG3PCI_PM_CAPS 0x0000004a
  66. #define TG3PCI_PM_CTRL_STAT 0x0000004c
  67. #define TG3PCI_BR_SUPP_EXT 0x0000004e
  68. #define TG3PCI_PM_DATA 0x0000004f
  69. #define TG3PCI_VPD_CAP_ID 0x00000050
  70. #define TG3PCI_MSI_CAP_PTR 0x00000051
  71. #define TG3PCI_VPD_ADDR_FLAG 0x00000052
  72. #define VPD_ADDR_FLAG_WRITE 0x00008000
  73. #define TG3PCI_VPD_DATA 0x00000054
  74. #define TG3PCI_MSI_CAP_ID 0x00000058
  75. #define TG3PCI_NXT_CAP_PTR 0x00000059
  76. #define TG3PCI_MSI_CTRL 0x0000005a
  77. #define TG3PCI_MSI_ADDR_LOW 0x0000005c
  78. #define TG3PCI_MSI_ADDR_HIGH 0x00000060
  79. #define TG3PCI_MSI_DATA 0x00000064
  80. /* 0x66 --> 0x68 unused */
  81. #define TG3PCI_MISC_HOST_CTRL 0x00000068
  82. #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
  83. #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
  84. #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
  85. #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
  86. #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
  87. #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
  88. #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
  89. #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
  90. #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
  91. #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
  92. #define MISC_HOST_CTRL_CHIPREV 0xffff0000
  93. #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
  94. #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
  95. (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
  96. MISC_HOST_CTRL_CHIPREV_SHIFT)
  97. #define CHIPREV_ID_5700_A0 0x7000
  98. #define CHIPREV_ID_5700_A1 0x7001
  99. #define CHIPREV_ID_5700_B0 0x7100
  100. #define CHIPREV_ID_5700_B1 0x7101
  101. #define CHIPREV_ID_5700_B3 0x7102
  102. #define CHIPREV_ID_5700_ALTIMA 0x7104
  103. #define CHIPREV_ID_5700_C0 0x7200
  104. #define CHIPREV_ID_5701_A0 0x0000
  105. #define CHIPREV_ID_5701_B0 0x0100
  106. #define CHIPREV_ID_5701_B2 0x0102
  107. #define CHIPREV_ID_5701_B5 0x0105
  108. #define CHIPREV_ID_5703_A0 0x1000
  109. #define CHIPREV_ID_5703_A1 0x1001
  110. #define CHIPREV_ID_5703_A2 0x1002
  111. #define CHIPREV_ID_5703_A3 0x1003
  112. #define CHIPREV_ID_5704_A0 0x2000
  113. #define CHIPREV_ID_5704_A1 0x2001
  114. #define CHIPREV_ID_5704_A2 0x2002
  115. #define CHIPREV_ID_5704_A3 0x2003
  116. #define CHIPREV_ID_5705_A0 0x3000
  117. #define CHIPREV_ID_5705_A1 0x3001
  118. #define CHIPREV_ID_5705_A2 0x3002
  119. #define CHIPREV_ID_5705_A3 0x3003
  120. #define CHIPREV_ID_5750_A0 0x4000
  121. #define CHIPREV_ID_5750_A1 0x4001
  122. #define CHIPREV_ID_5750_A3 0x4003
  123. #define CHIPREV_ID_5750_C2 0x4202
  124. #define CHIPREV_ID_5752_A0_HW 0x5000
  125. #define CHIPREV_ID_5752_A0 0x6000
  126. #define CHIPREV_ID_5752_A1 0x6001
  127. #define CHIPREV_ID_5906_A1 0xc001
  128. #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
  129. #define ASIC_REV_5700 0x07
  130. #define ASIC_REV_5701 0x00
  131. #define ASIC_REV_5703 0x01
  132. #define ASIC_REV_5704 0x02
  133. #define ASIC_REV_5705 0x03
  134. #define ASIC_REV_5750 0x04
  135. #define ASIC_REV_5752 0x06
  136. #define ASIC_REV_5780 0x08
  137. #define ASIC_REV_5714 0x09
  138. #define ASIC_REV_5755 0x0a
  139. #define ASIC_REV_5787 0x0b
  140. #define ASIC_REV_5906 0x0c
  141. #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
  142. #define CHIPREV_5700_AX 0x70
  143. #define CHIPREV_5700_BX 0x71
  144. #define CHIPREV_5700_CX 0x72
  145. #define CHIPREV_5701_AX 0x00
  146. #define CHIPREV_5703_AX 0x10
  147. #define CHIPREV_5704_AX 0x20
  148. #define CHIPREV_5704_BX 0x21
  149. #define CHIPREV_5750_AX 0x40
  150. #define CHIPREV_5750_BX 0x41
  151. #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
  152. #define METAL_REV_A0 0x00
  153. #define METAL_REV_A1 0x01
  154. #define METAL_REV_B0 0x00
  155. #define METAL_REV_B1 0x01
  156. #define METAL_REV_B2 0x02
  157. #define TG3PCI_DMA_RW_CTRL 0x0000006c
  158. #define DMA_RWCTRL_MIN_DMA 0x000000ff
  159. #define DMA_RWCTRL_MIN_DMA_SHIFT 0
  160. #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
  161. #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
  162. #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
  163. #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
  164. #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
  165. #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
  166. #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
  167. #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
  168. #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
  169. #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
  170. #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
  171. #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
  172. #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
  173. #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
  174. #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
  175. #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
  176. #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
  177. #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
  178. #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
  179. #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
  180. #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
  181. #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
  182. #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
  183. #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
  184. #define DMA_RWCTRL_ONE_DMA 0x00004000
  185. #define DMA_RWCTRL_READ_WATER 0x00070000
  186. #define DMA_RWCTRL_READ_WATER_SHIFT 16
  187. #define DMA_RWCTRL_WRITE_WATER 0x00380000
  188. #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
  189. #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
  190. #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
  191. #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
  192. #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
  193. #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
  194. #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
  195. #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
  196. #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
  197. #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
  198. #define TG3PCI_PCISTATE 0x00000070
  199. #define PCISTATE_FORCE_RESET 0x00000001
  200. #define PCISTATE_INT_NOT_ACTIVE 0x00000002
  201. #define PCISTATE_CONV_PCI_MODE 0x00000004
  202. #define PCISTATE_BUS_SPEED_HIGH 0x00000008
  203. #define PCISTATE_BUS_32BIT 0x00000010
  204. #define PCISTATE_ROM_ENABLE 0x00000020
  205. #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
  206. #define PCISTATE_FLAT_VIEW 0x00000100
  207. #define PCISTATE_RETRY_SAME_DMA 0x00002000
  208. #define TG3PCI_CLOCK_CTRL 0x00000074
  209. #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
  210. #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
  211. #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
  212. #define CLOCK_CTRL_ALTCLK 0x00001000
  213. #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
  214. #define CLOCK_CTRL_44MHZ_CORE 0x00040000
  215. #define CLOCK_CTRL_625_CORE 0x00100000
  216. #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
  217. #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
  218. #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
  219. #define TG3PCI_REG_BASE_ADDR 0x00000078
  220. #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
  221. #define TG3PCI_REG_DATA 0x00000080
  222. #define TG3PCI_MEM_WIN_DATA 0x00000084
  223. #define TG3PCI_MODE_CTRL 0x00000088
  224. #define TG3PCI_MISC_CFG 0x0000008c
  225. #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
  226. /* 0x94 --> 0x98 unused */
  227. #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
  228. #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
  229. #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
  230. /* 0xb0 --> 0xb8 unused */
  231. #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
  232. #define DUAL_MAC_CTRL_CH_MASK 0x00000003
  233. #define DUAL_MAC_CTRL_ID 0x00000004
  234. /* 0xbc --> 0x100 unused */
  235. /* 0x100 --> 0x200 unused */
  236. /* Mailbox registers */
  237. #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
  238. #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
  239. #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
  240. #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
  241. #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
  242. #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
  243. #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
  244. #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
  245. #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
  246. #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
  247. #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
  248. #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
  249. #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
  250. #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
  251. #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
  252. #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
  253. #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
  254. #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
  255. #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
  256. #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
  257. #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
  258. #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
  259. #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
  260. #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
  261. #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
  262. #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
  263. #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
  264. #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
  265. #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
  266. #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
  267. #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
  268. #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
  269. #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
  270. #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
  271. #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
  272. #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
  273. #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
  274. #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
  275. #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
  276. #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
  277. #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
  278. #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
  279. #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
  280. #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
  281. #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
  282. #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
  283. #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
  284. #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
  285. #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
  286. #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
  287. #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
  288. #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
  289. #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
  290. #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
  291. #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
  292. #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
  293. #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
  294. #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
  295. #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
  296. #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
  297. #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
  298. #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
  299. #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
  300. #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
  301. /* MAC control registers */
  302. #define MAC_MODE 0x00000400
  303. #define MAC_MODE_RESET 0x00000001
  304. #define MAC_MODE_HALF_DUPLEX 0x00000002
  305. #define MAC_MODE_PORT_MODE_MASK 0x0000000c
  306. #define MAC_MODE_PORT_MODE_TBI 0x0000000c
  307. #define MAC_MODE_PORT_MODE_GMII 0x00000008
  308. #define MAC_MODE_PORT_MODE_MII 0x00000004
  309. #define MAC_MODE_PORT_MODE_NONE 0x00000000
  310. #define MAC_MODE_PORT_INT_LPBACK 0x00000010
  311. #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
  312. #define MAC_MODE_TX_BURSTING 0x00000100
  313. #define MAC_MODE_MAX_DEFER 0x00000200
  314. #define MAC_MODE_LINK_POLARITY 0x00000400
  315. #define MAC_MODE_RXSTAT_ENABLE 0x00000800
  316. #define MAC_MODE_RXSTAT_CLEAR 0x00001000
  317. #define MAC_MODE_RXSTAT_FLUSH 0x00002000
  318. #define MAC_MODE_TXSTAT_ENABLE 0x00004000
  319. #define MAC_MODE_TXSTAT_CLEAR 0x00008000
  320. #define MAC_MODE_TXSTAT_FLUSH 0x00010000
  321. #define MAC_MODE_SEND_CONFIGS 0x00020000
  322. #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
  323. #define MAC_MODE_ACPI_ENABLE 0x00080000
  324. #define MAC_MODE_MIP_ENABLE 0x00100000
  325. #define MAC_MODE_TDE_ENABLE 0x00200000
  326. #define MAC_MODE_RDE_ENABLE 0x00400000
  327. #define MAC_MODE_FHDE_ENABLE 0x00800000
  328. #define MAC_STATUS 0x00000404
  329. #define MAC_STATUS_PCS_SYNCED 0x00000001
  330. #define MAC_STATUS_SIGNAL_DET 0x00000002
  331. #define MAC_STATUS_RCVD_CFG 0x00000004
  332. #define MAC_STATUS_CFG_CHANGED 0x00000008
  333. #define MAC_STATUS_SYNC_CHANGED 0x00000010
  334. #define MAC_STATUS_PORT_DEC_ERR 0x00000400
  335. #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
  336. #define MAC_STATUS_MI_COMPLETION 0x00400000
  337. #define MAC_STATUS_MI_INTERRUPT 0x00800000
  338. #define MAC_STATUS_AP_ERROR 0x01000000
  339. #define MAC_STATUS_ODI_ERROR 0x02000000
  340. #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
  341. #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
  342. #define MAC_EVENT 0x00000408
  343. #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
  344. #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
  345. #define MAC_EVENT_MI_COMPLETION 0x00400000
  346. #define MAC_EVENT_MI_INTERRUPT 0x00800000
  347. #define MAC_EVENT_AP_ERROR 0x01000000
  348. #define MAC_EVENT_ODI_ERROR 0x02000000
  349. #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
  350. #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
  351. #define MAC_LED_CTRL 0x0000040c
  352. #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
  353. #define LED_CTRL_1000MBPS_ON 0x00000002
  354. #define LED_CTRL_100MBPS_ON 0x00000004
  355. #define LED_CTRL_10MBPS_ON 0x00000008
  356. #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
  357. #define LED_CTRL_TRAFFIC_BLINK 0x00000020
  358. #define LED_CTRL_TRAFFIC_LED 0x00000040
  359. #define LED_CTRL_1000MBPS_STATUS 0x00000080
  360. #define LED_CTRL_100MBPS_STATUS 0x00000100
  361. #define LED_CTRL_10MBPS_STATUS 0x00000200
  362. #define LED_CTRL_TRAFFIC_STATUS 0x00000400
  363. #define LED_CTRL_MODE_MAC 0x00000000
  364. #define LED_CTRL_MODE_PHY_1 0x00000800
  365. #define LED_CTRL_MODE_PHY_2 0x00001000
  366. #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
  367. #define LED_CTRL_MODE_SHARED 0x00004000
  368. #define LED_CTRL_MODE_COMBO 0x00008000
  369. #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
  370. #define LED_CTRL_BLINK_RATE_SHIFT 19
  371. #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
  372. #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
  373. #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
  374. #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
  375. #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
  376. #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
  377. #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
  378. #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
  379. #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
  380. #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
  381. #define MAC_ACPI_MBUF_PTR 0x00000430
  382. #define MAC_ACPI_LEN_OFFSET 0x00000434
  383. #define ACPI_LENOFF_LEN_MASK 0x0000ffff
  384. #define ACPI_LENOFF_LEN_SHIFT 0
  385. #define ACPI_LENOFF_OFF_MASK 0x0fff0000
  386. #define ACPI_LENOFF_OFF_SHIFT 16
  387. #define MAC_TX_BACKOFF_SEED 0x00000438
  388. #define TX_BACKOFF_SEED_MASK 0x000003ff
  389. #define MAC_RX_MTU_SIZE 0x0000043c
  390. #define RX_MTU_SIZE_MASK 0x0000ffff
  391. #define MAC_PCS_TEST 0x00000440
  392. #define PCS_TEST_PATTERN_MASK 0x000fffff
  393. #define PCS_TEST_PATTERN_SHIFT 0
  394. #define PCS_TEST_ENABLE 0x00100000
  395. #define MAC_TX_AUTO_NEG 0x00000444
  396. #define TX_AUTO_NEG_MASK 0x0000ffff
  397. #define TX_AUTO_NEG_SHIFT 0
  398. #define MAC_RX_AUTO_NEG 0x00000448
  399. #define RX_AUTO_NEG_MASK 0x0000ffff
  400. #define RX_AUTO_NEG_SHIFT 0
  401. #define MAC_MI_COM 0x0000044c
  402. #define MI_COM_CMD_MASK 0x0c000000
  403. #define MI_COM_CMD_WRITE 0x04000000
  404. #define MI_COM_CMD_READ 0x08000000
  405. #define MI_COM_READ_FAILED 0x10000000
  406. #define MI_COM_START 0x20000000
  407. #define MI_COM_BUSY 0x20000000
  408. #define MI_COM_PHY_ADDR_MASK 0x03e00000
  409. #define MI_COM_PHY_ADDR_SHIFT 21
  410. #define MI_COM_REG_ADDR_MASK 0x001f0000
  411. #define MI_COM_REG_ADDR_SHIFT 16
  412. #define MI_COM_DATA_MASK 0x0000ffff
  413. #define MAC_MI_STAT 0x00000450
  414. #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
  415. #define MAC_MI_MODE 0x00000454
  416. #define MAC_MI_MODE_CLK_10MHZ 0x00000001
  417. #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
  418. #define MAC_MI_MODE_AUTO_POLL 0x00000010
  419. #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
  420. #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
  421. #define MAC_AUTO_POLL_STATUS 0x00000458
  422. #define MAC_AUTO_POLL_ERROR 0x00000001
  423. #define MAC_TX_MODE 0x0000045c
  424. #define TX_MODE_RESET 0x00000001
  425. #define TX_MODE_ENABLE 0x00000002
  426. #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
  427. #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
  428. #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
  429. #define MAC_TX_STATUS 0x00000460
  430. #define TX_STATUS_XOFFED 0x00000001
  431. #define TX_STATUS_SENT_XOFF 0x00000002
  432. #define TX_STATUS_SENT_XON 0x00000004
  433. #define TX_STATUS_LINK_UP 0x00000008
  434. #define TX_STATUS_ODI_UNDERRUN 0x00000010
  435. #define TX_STATUS_ODI_OVERRUN 0x00000020
  436. #define MAC_TX_LENGTHS 0x00000464
  437. #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
  438. #define TX_LENGTHS_SLOT_TIME_SHIFT 0
  439. #define TX_LENGTHS_IPG_MASK 0x00000f00
  440. #define TX_LENGTHS_IPG_SHIFT 8
  441. #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
  442. #define TX_LENGTHS_IPG_CRS_SHIFT 12
  443. #define MAC_RX_MODE 0x00000468
  444. #define RX_MODE_RESET 0x00000001
  445. #define RX_MODE_ENABLE 0x00000002
  446. #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
  447. #define RX_MODE_KEEP_MAC_CTRL 0x00000008
  448. #define RX_MODE_KEEP_PAUSE 0x00000010
  449. #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
  450. #define RX_MODE_ACCEPT_RUNTS 0x00000040
  451. #define RX_MODE_LEN_CHECK 0x00000080
  452. #define RX_MODE_PROMISC 0x00000100
  453. #define RX_MODE_NO_CRC_CHECK 0x00000200
  454. #define RX_MODE_KEEP_VLAN_TAG 0x00000400
  455. #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
  456. #define MAC_RX_STATUS 0x0000046c
  457. #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
  458. #define RX_STATUS_XOFF_RCVD 0x00000002
  459. #define RX_STATUS_XON_RCVD 0x00000004
  460. #define MAC_HASH_REG_0 0x00000470
  461. #define MAC_HASH_REG_1 0x00000474
  462. #define MAC_HASH_REG_2 0x00000478
  463. #define MAC_HASH_REG_3 0x0000047c
  464. #define MAC_RCV_RULE_0 0x00000480
  465. #define MAC_RCV_VALUE_0 0x00000484
  466. #define MAC_RCV_RULE_1 0x00000488
  467. #define MAC_RCV_VALUE_1 0x0000048c
  468. #define MAC_RCV_RULE_2 0x00000490
  469. #define MAC_RCV_VALUE_2 0x00000494
  470. #define MAC_RCV_RULE_3 0x00000498
  471. #define MAC_RCV_VALUE_3 0x0000049c
  472. #define MAC_RCV_RULE_4 0x000004a0
  473. #define MAC_RCV_VALUE_4 0x000004a4
  474. #define MAC_RCV_RULE_5 0x000004a8
  475. #define MAC_RCV_VALUE_5 0x000004ac
  476. #define MAC_RCV_RULE_6 0x000004b0
  477. #define MAC_RCV_VALUE_6 0x000004b4
  478. #define MAC_RCV_RULE_7 0x000004b8
  479. #define MAC_RCV_VALUE_7 0x000004bc
  480. #define MAC_RCV_RULE_8 0x000004c0
  481. #define MAC_RCV_VALUE_8 0x000004c4
  482. #define MAC_RCV_RULE_9 0x000004c8
  483. #define MAC_RCV_VALUE_9 0x000004cc
  484. #define MAC_RCV_RULE_10 0x000004d0
  485. #define MAC_RCV_VALUE_10 0x000004d4
  486. #define MAC_RCV_RULE_11 0x000004d8
  487. #define MAC_RCV_VALUE_11 0x000004dc
  488. #define MAC_RCV_RULE_12 0x000004e0
  489. #define MAC_RCV_VALUE_12 0x000004e4
  490. #define MAC_RCV_RULE_13 0x000004e8
  491. #define MAC_RCV_VALUE_13 0x000004ec
  492. #define MAC_RCV_RULE_14 0x000004f0
  493. #define MAC_RCV_VALUE_14 0x000004f4
  494. #define MAC_RCV_RULE_15 0x000004f8
  495. #define MAC_RCV_VALUE_15 0x000004fc
  496. #define RCV_RULE_DISABLE_MASK 0x7fffffff
  497. #define MAC_RCV_RULE_CFG 0x00000500
  498. #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
  499. #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
  500. /* 0x508 --> 0x520 unused */
  501. #define MAC_HASHREGU_0 0x00000520
  502. #define MAC_HASHREGU_1 0x00000524
  503. #define MAC_HASHREGU_2 0x00000528
  504. #define MAC_HASHREGU_3 0x0000052c
  505. #define MAC_EXTADDR_0_HIGH 0x00000530
  506. #define MAC_EXTADDR_0_LOW 0x00000534
  507. #define MAC_EXTADDR_1_HIGH 0x00000538
  508. #define MAC_EXTADDR_1_LOW 0x0000053c
  509. #define MAC_EXTADDR_2_HIGH 0x00000540
  510. #define MAC_EXTADDR_2_LOW 0x00000544
  511. #define MAC_EXTADDR_3_HIGH 0x00000548
  512. #define MAC_EXTADDR_3_LOW 0x0000054c
  513. #define MAC_EXTADDR_4_HIGH 0x00000550
  514. #define MAC_EXTADDR_4_LOW 0x00000554
  515. #define MAC_EXTADDR_5_HIGH 0x00000558
  516. #define MAC_EXTADDR_5_LOW 0x0000055c
  517. #define MAC_EXTADDR_6_HIGH 0x00000560
  518. #define MAC_EXTADDR_6_LOW 0x00000564
  519. #define MAC_EXTADDR_7_HIGH 0x00000568
  520. #define MAC_EXTADDR_7_LOW 0x0000056c
  521. #define MAC_EXTADDR_8_HIGH 0x00000570
  522. #define MAC_EXTADDR_8_LOW 0x00000574
  523. #define MAC_EXTADDR_9_HIGH 0x00000578
  524. #define MAC_EXTADDR_9_LOW 0x0000057c
  525. #define MAC_EXTADDR_10_HIGH 0x00000580
  526. #define MAC_EXTADDR_10_LOW 0x00000584
  527. #define MAC_EXTADDR_11_HIGH 0x00000588
  528. #define MAC_EXTADDR_11_LOW 0x0000058c
  529. #define MAC_SERDES_CFG 0x00000590
  530. #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
  531. #define MAC_SERDES_STAT 0x00000594
  532. /* 0x598 --> 0x5b0 unused */
  533. #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
  534. #define SERDES_RX_SIG_DETECT 0x00000400
  535. #define SG_DIG_CTRL 0x000005b0
  536. #define SG_DIG_USING_HW_AUTONEG 0x80000000
  537. #define SG_DIG_SOFT_RESET 0x40000000
  538. #define SG_DIG_DISABLE_LINKRDY 0x20000000
  539. #define SG_DIG_CRC16_CLEAR_N 0x01000000
  540. #define SG_DIG_EN10B 0x00800000
  541. #define SG_DIG_CLEAR_STATUS 0x00400000
  542. #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
  543. #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
  544. #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
  545. #define SG_DIG_SPEED_STATUS_SHIFT 18
  546. #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
  547. #define SG_DIG_RESTART_AUTONEG 0x00010000
  548. #define SG_DIG_FIBER_MODE 0x00008000
  549. #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
  550. #define SG_DIG_PAUSE_MASK 0x00001800
  551. #define SG_DIG_GBIC_ENABLE 0x00000400
  552. #define SG_DIG_CHECK_END_ENABLE 0x00000200
  553. #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
  554. #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
  555. #define SG_DIG_GMII_INPUT_SELECT 0x00000040
  556. #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
  557. #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
  558. #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
  559. #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
  560. #define SG_DIG_REMOTE_LOOPBACK 0x00000002
  561. #define SG_DIG_LOOPBACK 0x00000001
  562. #define SG_DIG_STATUS 0x000005b4
  563. #define SG_DIG_CRC16_BUS_MASK 0xffff0000
  564. #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
  565. #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
  566. #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
  567. #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
  568. #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
  569. #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
  570. #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
  571. #define SG_DIG_COMMA_DETECTOR 0x00000008
  572. #define SG_DIG_MAC_ACK_STATUS 0x00000004
  573. #define SG_DIG_AUTONEG_COMPLETE 0x00000002
  574. #define SG_DIG_AUTONEG_ERROR 0x00000001
  575. /* 0x5b8 --> 0x600 unused */
  576. #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
  577. #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
  578. /* 0x624 --> 0x800 unused */
  579. #define MAC_TX_STATS_OCTETS 0x00000800
  580. #define MAC_TX_STATS_RESV1 0x00000804
  581. #define MAC_TX_STATS_COLLISIONS 0x00000808
  582. #define MAC_TX_STATS_XON_SENT 0x0000080c
  583. #define MAC_TX_STATS_XOFF_SENT 0x00000810
  584. #define MAC_TX_STATS_RESV2 0x00000814
  585. #define MAC_TX_STATS_MAC_ERRORS 0x00000818
  586. #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
  587. #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
  588. #define MAC_TX_STATS_DEFERRED 0x00000824
  589. #define MAC_TX_STATS_RESV3 0x00000828
  590. #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
  591. #define MAC_TX_STATS_LATE_COL 0x00000830
  592. #define MAC_TX_STATS_RESV4_1 0x00000834
  593. #define MAC_TX_STATS_RESV4_2 0x00000838
  594. #define MAC_TX_STATS_RESV4_3 0x0000083c
  595. #define MAC_TX_STATS_RESV4_4 0x00000840
  596. #define MAC_TX_STATS_RESV4_5 0x00000844
  597. #define MAC_TX_STATS_RESV4_6 0x00000848
  598. #define MAC_TX_STATS_RESV4_7 0x0000084c
  599. #define MAC_TX_STATS_RESV4_8 0x00000850
  600. #define MAC_TX_STATS_RESV4_9 0x00000854
  601. #define MAC_TX_STATS_RESV4_10 0x00000858
  602. #define MAC_TX_STATS_RESV4_11 0x0000085c
  603. #define MAC_TX_STATS_RESV4_12 0x00000860
  604. #define MAC_TX_STATS_RESV4_13 0x00000864
  605. #define MAC_TX_STATS_RESV4_14 0x00000868
  606. #define MAC_TX_STATS_UCAST 0x0000086c
  607. #define MAC_TX_STATS_MCAST 0x00000870
  608. #define MAC_TX_STATS_BCAST 0x00000874
  609. #define MAC_TX_STATS_RESV5_1 0x00000878
  610. #define MAC_TX_STATS_RESV5_2 0x0000087c
  611. #define MAC_RX_STATS_OCTETS 0x00000880
  612. #define MAC_RX_STATS_RESV1 0x00000884
  613. #define MAC_RX_STATS_FRAGMENTS 0x00000888
  614. #define MAC_RX_STATS_UCAST 0x0000088c
  615. #define MAC_RX_STATS_MCAST 0x00000890
  616. #define MAC_RX_STATS_BCAST 0x00000894
  617. #define MAC_RX_STATS_FCS_ERRORS 0x00000898
  618. #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
  619. #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
  620. #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
  621. #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
  622. #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
  623. #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
  624. #define MAC_RX_STATS_JABBERS 0x000008b4
  625. #define MAC_RX_STATS_UNDERSIZE 0x000008b8
  626. /* 0x8bc --> 0xc00 unused */
  627. /* Send data initiator control registers */
  628. #define SNDDATAI_MODE 0x00000c00
  629. #define SNDDATAI_MODE_RESET 0x00000001
  630. #define SNDDATAI_MODE_ENABLE 0x00000002
  631. #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
  632. #define SNDDATAI_STATUS 0x00000c04
  633. #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
  634. #define SNDDATAI_STATSCTRL 0x00000c08
  635. #define SNDDATAI_SCTRL_ENABLE 0x00000001
  636. #define SNDDATAI_SCTRL_FASTUPD 0x00000002
  637. #define SNDDATAI_SCTRL_CLEAR 0x00000004
  638. #define SNDDATAI_SCTRL_FLUSH 0x00000008
  639. #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
  640. #define SNDDATAI_STATSENAB 0x00000c0c
  641. #define SNDDATAI_STATSINCMASK 0x00000c10
  642. #define ISO_PKT_TX 0x00000c20
  643. /* 0xc24 --> 0xc80 unused */
  644. #define SNDDATAI_COS_CNT_0 0x00000c80
  645. #define SNDDATAI_COS_CNT_1 0x00000c84
  646. #define SNDDATAI_COS_CNT_2 0x00000c88
  647. #define SNDDATAI_COS_CNT_3 0x00000c8c
  648. #define SNDDATAI_COS_CNT_4 0x00000c90
  649. #define SNDDATAI_COS_CNT_5 0x00000c94
  650. #define SNDDATAI_COS_CNT_6 0x00000c98
  651. #define SNDDATAI_COS_CNT_7 0x00000c9c
  652. #define SNDDATAI_COS_CNT_8 0x00000ca0
  653. #define SNDDATAI_COS_CNT_9 0x00000ca4
  654. #define SNDDATAI_COS_CNT_10 0x00000ca8
  655. #define SNDDATAI_COS_CNT_11 0x00000cac
  656. #define SNDDATAI_COS_CNT_12 0x00000cb0
  657. #define SNDDATAI_COS_CNT_13 0x00000cb4
  658. #define SNDDATAI_COS_CNT_14 0x00000cb8
  659. #define SNDDATAI_COS_CNT_15 0x00000cbc
  660. #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
  661. #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
  662. #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
  663. #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
  664. #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
  665. #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
  666. #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
  667. #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
  668. /* 0xce0 --> 0x1000 unused */
  669. /* Send data completion control registers */
  670. #define SNDDATAC_MODE 0x00001000
  671. #define SNDDATAC_MODE_RESET 0x00000001
  672. #define SNDDATAC_MODE_ENABLE 0x00000002
  673. /* 0x1004 --> 0x1400 unused */
  674. /* Send BD ring selector */
  675. #define SNDBDS_MODE 0x00001400
  676. #define SNDBDS_MODE_RESET 0x00000001
  677. #define SNDBDS_MODE_ENABLE 0x00000002
  678. #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
  679. #define SNDBDS_STATUS 0x00001404
  680. #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
  681. #define SNDBDS_HWDIAG 0x00001408
  682. /* 0x140c --> 0x1440 */
  683. #define SNDBDS_SEL_CON_IDX_0 0x00001440
  684. #define SNDBDS_SEL_CON_IDX_1 0x00001444
  685. #define SNDBDS_SEL_CON_IDX_2 0x00001448
  686. #define SNDBDS_SEL_CON_IDX_3 0x0000144c
  687. #define SNDBDS_SEL_CON_IDX_4 0x00001450
  688. #define SNDBDS_SEL_CON_IDX_5 0x00001454
  689. #define SNDBDS_SEL_CON_IDX_6 0x00001458
  690. #define SNDBDS_SEL_CON_IDX_7 0x0000145c
  691. #define SNDBDS_SEL_CON_IDX_8 0x00001460
  692. #define SNDBDS_SEL_CON_IDX_9 0x00001464
  693. #define SNDBDS_SEL_CON_IDX_10 0x00001468
  694. #define SNDBDS_SEL_CON_IDX_11 0x0000146c
  695. #define SNDBDS_SEL_CON_IDX_12 0x00001470
  696. #define SNDBDS_SEL_CON_IDX_13 0x00001474
  697. #define SNDBDS_SEL_CON_IDX_14 0x00001478
  698. #define SNDBDS_SEL_CON_IDX_15 0x0000147c
  699. /* 0x1480 --> 0x1800 unused */
  700. /* Send BD initiator control registers */
  701. #define SNDBDI_MODE 0x00001800
  702. #define SNDBDI_MODE_RESET 0x00000001
  703. #define SNDBDI_MODE_ENABLE 0x00000002
  704. #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
  705. #define SNDBDI_STATUS 0x00001804
  706. #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
  707. #define SNDBDI_IN_PROD_IDX_0 0x00001808
  708. #define SNDBDI_IN_PROD_IDX_1 0x0000180c
  709. #define SNDBDI_IN_PROD_IDX_2 0x00001810
  710. #define SNDBDI_IN_PROD_IDX_3 0x00001814
  711. #define SNDBDI_IN_PROD_IDX_4 0x00001818
  712. #define SNDBDI_IN_PROD_IDX_5 0x0000181c
  713. #define SNDBDI_IN_PROD_IDX_6 0x00001820
  714. #define SNDBDI_IN_PROD_IDX_7 0x00001824
  715. #define SNDBDI_IN_PROD_IDX_8 0x00001828
  716. #define SNDBDI_IN_PROD_IDX_9 0x0000182c
  717. #define SNDBDI_IN_PROD_IDX_10 0x00001830
  718. #define SNDBDI_IN_PROD_IDX_11 0x00001834
  719. #define SNDBDI_IN_PROD_IDX_12 0x00001838
  720. #define SNDBDI_IN_PROD_IDX_13 0x0000183c
  721. #define SNDBDI_IN_PROD_IDX_14 0x00001840
  722. #define SNDBDI_IN_PROD_IDX_15 0x00001844
  723. /* 0x1848 --> 0x1c00 unused */
  724. /* Send BD completion control registers */
  725. #define SNDBDC_MODE 0x00001c00
  726. #define SNDBDC_MODE_RESET 0x00000001
  727. #define SNDBDC_MODE_ENABLE 0x00000002
  728. #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
  729. /* 0x1c04 --> 0x2000 unused */
  730. /* Receive list placement control registers */
  731. #define RCVLPC_MODE 0x00002000
  732. #define RCVLPC_MODE_RESET 0x00000001
  733. #define RCVLPC_MODE_ENABLE 0x00000002
  734. #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
  735. #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
  736. #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
  737. #define RCVLPC_STATUS 0x00002004
  738. #define RCVLPC_STATUS_CLASS0 0x00000004
  739. #define RCVLPC_STATUS_MAPOOR 0x00000008
  740. #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
  741. #define RCVLPC_LOCK 0x00002008
  742. #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
  743. #define RCVLPC_LOCK_REQ_SHIFT 0
  744. #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
  745. #define RCVLPC_LOCK_GRANT_SHIFT 16
  746. #define RCVLPC_NON_EMPTY_BITS 0x0000200c
  747. #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
  748. #define RCVLPC_CONFIG 0x00002010
  749. #define RCVLPC_STATSCTRL 0x00002014
  750. #define RCVLPC_STATSCTRL_ENABLE 0x00000001
  751. #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
  752. #define RCVLPC_STATS_ENABLE 0x00002018
  753. #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
  754. #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
  755. #define RCVLPC_STATS_INCMASK 0x0000201c
  756. /* 0x2020 --> 0x2100 unused */
  757. #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
  758. #define SELLST_TAIL 0x00000004
  759. #define SELLST_CONT 0x00000008
  760. #define SELLST_UNUSED 0x0000000c
  761. #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
  762. #define RCVLPC_DROP_FILTER_CNT 0x00002240
  763. #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
  764. #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
  765. #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
  766. #define RCVLPC_IN_DISCARDS_CNT 0x00002250
  767. #define RCVLPC_IN_ERRORS_CNT 0x00002254
  768. #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
  769. /* 0x225c --> 0x2400 unused */
  770. /* Receive Data and Receive BD Initiator Control */
  771. #define RCVDBDI_MODE 0x00002400
  772. #define RCVDBDI_MODE_RESET 0x00000001
  773. #define RCVDBDI_MODE_ENABLE 0x00000002
  774. #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
  775. #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
  776. #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
  777. #define RCVDBDI_STATUS 0x00002404
  778. #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
  779. #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
  780. #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
  781. #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
  782. /* 0x240c --> 0x2440 unused */
  783. #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
  784. #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
  785. #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
  786. #define RCVDBDI_JUMBO_CON_IDX 0x00002470
  787. #define RCVDBDI_STD_CON_IDX 0x00002474
  788. #define RCVDBDI_MINI_CON_IDX 0x00002478
  789. /* 0x247c --> 0x2480 unused */
  790. #define RCVDBDI_BD_PROD_IDX_0 0x00002480
  791. #define RCVDBDI_BD_PROD_IDX_1 0x00002484
  792. #define RCVDBDI_BD_PROD_IDX_2 0x00002488
  793. #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
  794. #define RCVDBDI_BD_PROD_IDX_4 0x00002490
  795. #define RCVDBDI_BD_PROD_IDX_5 0x00002494
  796. #define RCVDBDI_BD_PROD_IDX_6 0x00002498
  797. #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
  798. #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
  799. #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
  800. #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
  801. #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
  802. #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
  803. #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
  804. #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
  805. #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
  806. #define RCVDBDI_HWDIAG 0x000024c0
  807. /* 0x24c4 --> 0x2800 unused */
  808. /* Receive Data Completion Control */
  809. #define RCVDCC_MODE 0x00002800
  810. #define RCVDCC_MODE_RESET 0x00000001
  811. #define RCVDCC_MODE_ENABLE 0x00000002
  812. #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
  813. /* 0x2804 --> 0x2c00 unused */
  814. /* Receive BD Initiator Control Registers */
  815. #define RCVBDI_MODE 0x00002c00
  816. #define RCVBDI_MODE_RESET 0x00000001
  817. #define RCVBDI_MODE_ENABLE 0x00000002
  818. #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
  819. #define RCVBDI_STATUS 0x00002c04
  820. #define RCVBDI_STATUS_RCB_ATTN 0x00000004
  821. #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
  822. #define RCVBDI_STD_PROD_IDX 0x00002c0c
  823. #define RCVBDI_MINI_PROD_IDX 0x00002c10
  824. #define RCVBDI_MINI_THRESH 0x00002c14
  825. #define RCVBDI_STD_THRESH 0x00002c18
  826. #define RCVBDI_JUMBO_THRESH 0x00002c1c
  827. /* 0x2c20 --> 0x3000 unused */
  828. /* Receive BD Completion Control Registers */
  829. #define RCVCC_MODE 0x00003000
  830. #define RCVCC_MODE_RESET 0x00000001
  831. #define RCVCC_MODE_ENABLE 0x00000002
  832. #define RCVCC_MODE_ATTN_ENABLE 0x00000004
  833. #define RCVCC_STATUS 0x00003004
  834. #define RCVCC_STATUS_ERROR_ATTN 0x00000004
  835. #define RCVCC_JUMP_PROD_IDX 0x00003008
  836. #define RCVCC_STD_PROD_IDX 0x0000300c
  837. #define RCVCC_MINI_PROD_IDX 0x00003010
  838. /* 0x3014 --> 0x3400 unused */
  839. /* Receive list selector control registers */
  840. #define RCVLSC_MODE 0x00003400
  841. #define RCVLSC_MODE_RESET 0x00000001
  842. #define RCVLSC_MODE_ENABLE 0x00000002
  843. #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
  844. #define RCVLSC_STATUS 0x00003404
  845. #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
  846. /* 0x3408 --> 0x3800 unused */
  847. /* Mbuf cluster free registers */
  848. #define MBFREE_MODE 0x00003800
  849. #define MBFREE_MODE_RESET 0x00000001
  850. #define MBFREE_MODE_ENABLE 0x00000002
  851. #define MBFREE_STATUS 0x00003804
  852. /* 0x3808 --> 0x3c00 unused */
  853. /* Host coalescing control registers */
  854. #define HOSTCC_MODE 0x00003c00
  855. #define HOSTCC_MODE_RESET 0x00000001
  856. #define HOSTCC_MODE_ENABLE 0x00000002
  857. #define HOSTCC_MODE_ATTN 0x00000004
  858. #define HOSTCC_MODE_NOW 0x00000008
  859. #define HOSTCC_MODE_FULL_STATUS 0x00000000
  860. #define HOSTCC_MODE_64BYTE 0x00000080
  861. #define HOSTCC_MODE_32BYTE 0x00000100
  862. #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
  863. #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
  864. #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
  865. #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
  866. #define HOSTCC_STATUS 0x00003c04
  867. #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
  868. #define HOSTCC_RXCOL_TICKS 0x00003c08
  869. #define LOW_RXCOL_TICKS 0x00000032
  870. #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
  871. #define DEFAULT_RXCOL_TICKS 0x00000048
  872. #define HIGH_RXCOL_TICKS 0x00000096
  873. #define MAX_RXCOL_TICKS 0x000003ff
  874. #define HOSTCC_TXCOL_TICKS 0x00003c0c
  875. #define LOW_TXCOL_TICKS 0x00000096
  876. #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
  877. #define DEFAULT_TXCOL_TICKS 0x0000012c
  878. #define HIGH_TXCOL_TICKS 0x00000145
  879. #define MAX_TXCOL_TICKS 0x000003ff
  880. #define HOSTCC_RXMAX_FRAMES 0x00003c10
  881. #define LOW_RXMAX_FRAMES 0x00000005
  882. #define DEFAULT_RXMAX_FRAMES 0x00000008
  883. #define HIGH_RXMAX_FRAMES 0x00000012
  884. #define MAX_RXMAX_FRAMES 0x000000ff
  885. #define HOSTCC_TXMAX_FRAMES 0x00003c14
  886. #define LOW_TXMAX_FRAMES 0x00000035
  887. #define DEFAULT_TXMAX_FRAMES 0x0000004b
  888. #define HIGH_TXMAX_FRAMES 0x00000052
  889. #define MAX_TXMAX_FRAMES 0x000000ff
  890. #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
  891. #define DEFAULT_RXCOAL_TICK_INT 0x00000019
  892. #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
  893. #define MAX_RXCOAL_TICK_INT 0x000003ff
  894. #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
  895. #define DEFAULT_TXCOAL_TICK_INT 0x00000019
  896. #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
  897. #define MAX_TXCOAL_TICK_INT 0x000003ff
  898. #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
  899. #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
  900. #define MAX_RXCOAL_MAXF_INT 0x000000ff
  901. #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
  902. #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
  903. #define MAX_TXCOAL_MAXF_INT 0x000000ff
  904. #define HOSTCC_STAT_COAL_TICKS 0x00003c28
  905. #define DEFAULT_STAT_COAL_TICKS 0x000f4240
  906. #define MAX_STAT_COAL_TICKS 0xd693d400
  907. #define MIN_STAT_COAL_TICKS 0x00000064
  908. /* 0x3c2c --> 0x3c30 unused */
  909. #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
  910. #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
  911. #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
  912. #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
  913. #define HOSTCC_FLOW_ATTN 0x00003c48
  914. /* 0x3c4c --> 0x3c50 unused */
  915. #define HOSTCC_JUMBO_CON_IDX 0x00003c50
  916. #define HOSTCC_STD_CON_IDX 0x00003c54
  917. #define HOSTCC_MINI_CON_IDX 0x00003c58
  918. /* 0x3c5c --> 0x3c80 unused */
  919. #define HOSTCC_RET_PROD_IDX_0 0x00003c80
  920. #define HOSTCC_RET_PROD_IDX_1 0x00003c84
  921. #define HOSTCC_RET_PROD_IDX_2 0x00003c88
  922. #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
  923. #define HOSTCC_RET_PROD_IDX_4 0x00003c90
  924. #define HOSTCC_RET_PROD_IDX_5 0x00003c94
  925. #define HOSTCC_RET_PROD_IDX_6 0x00003c98
  926. #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
  927. #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
  928. #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
  929. #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
  930. #define HOSTCC_RET_PROD_IDX_11 0x00003cac
  931. #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
  932. #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
  933. #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
  934. #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
  935. #define HOSTCC_SND_CON_IDX_0 0x00003cc0
  936. #define HOSTCC_SND_CON_IDX_1 0x00003cc4
  937. #define HOSTCC_SND_CON_IDX_2 0x00003cc8
  938. #define HOSTCC_SND_CON_IDX_3 0x00003ccc
  939. #define HOSTCC_SND_CON_IDX_4 0x00003cd0
  940. #define HOSTCC_SND_CON_IDX_5 0x00003cd4
  941. #define HOSTCC_SND_CON_IDX_6 0x00003cd8
  942. #define HOSTCC_SND_CON_IDX_7 0x00003cdc
  943. #define HOSTCC_SND_CON_IDX_8 0x00003ce0
  944. #define HOSTCC_SND_CON_IDX_9 0x00003ce4
  945. #define HOSTCC_SND_CON_IDX_10 0x00003ce8
  946. #define HOSTCC_SND_CON_IDX_11 0x00003cec
  947. #define HOSTCC_SND_CON_IDX_12 0x00003cf0
  948. #define HOSTCC_SND_CON_IDX_13 0x00003cf4
  949. #define HOSTCC_SND_CON_IDX_14 0x00003cf8
  950. #define HOSTCC_SND_CON_IDX_15 0x00003cfc
  951. /* 0x3d00 --> 0x4000 unused */
  952. /* Memory arbiter control registers */
  953. #define MEMARB_MODE 0x00004000
  954. #define MEMARB_MODE_RESET 0x00000001
  955. #define MEMARB_MODE_ENABLE 0x00000002
  956. #define MEMARB_STATUS 0x00004004
  957. #define MEMARB_TRAP_ADDR_LOW 0x00004008
  958. #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
  959. /* 0x4010 --> 0x4400 unused */
  960. /* Buffer manager control registers */
  961. #define BUFMGR_MODE 0x00004400
  962. #define BUFMGR_MODE_RESET 0x00000001
  963. #define BUFMGR_MODE_ENABLE 0x00000002
  964. #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
  965. #define BUFMGR_MODE_BM_TEST 0x00000008
  966. #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
  967. #define BUFMGR_STATUS 0x00004404
  968. #define BUFMGR_STATUS_ERROR 0x00000004
  969. #define BUFMGR_STATUS_MBLOW 0x00000010
  970. #define BUFMGR_MB_POOL_ADDR 0x00004408
  971. #define BUFMGR_MB_POOL_SIZE 0x0000440c
  972. #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
  973. #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
  974. #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
  975. #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
  976. #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
  977. #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
  978. #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
  979. #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
  980. #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
  981. #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
  982. #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
  983. #define BUFMGR_MB_HIGH_WATER 0x00004418
  984. #define DEFAULT_MB_HIGH_WATER 0x00000060
  985. #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
  986. #define DEFAULT_MB_HIGH_WATER_5906 0x00000010
  987. #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
  988. #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
  989. #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
  990. #define BUFMGR_MB_ALLOC_BIT 0x10000000
  991. #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
  992. #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
  993. #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
  994. #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
  995. #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
  996. #define BUFMGR_DMA_LOW_WATER 0x00004434
  997. #define DEFAULT_DMA_LOW_WATER 0x00000005
  998. #define BUFMGR_DMA_HIGH_WATER 0x00004438
  999. #define DEFAULT_DMA_HIGH_WATER 0x0000000a
  1000. #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
  1001. #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
  1002. #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
  1003. #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
  1004. #define BUFMGR_HWDIAG_0 0x0000444c
  1005. #define BUFMGR_HWDIAG_1 0x00004450
  1006. #define BUFMGR_HWDIAG_2 0x00004454
  1007. /* 0x4458 --> 0x4800 unused */
  1008. /* Read DMA control registers */
  1009. #define RDMAC_MODE 0x00004800
  1010. #define RDMAC_MODE_RESET 0x00000001
  1011. #define RDMAC_MODE_ENABLE 0x00000002
  1012. #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
  1013. #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
  1014. #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
  1015. #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
  1016. #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
  1017. #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
  1018. #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
  1019. #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
  1020. #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
  1021. #define RDMAC_MODE_SPLIT_RESET 0x00001000
  1022. #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
  1023. #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
  1024. #define RDMAC_STATUS 0x00004804
  1025. #define RDMAC_STATUS_TGTABORT 0x00000004
  1026. #define RDMAC_STATUS_MSTABORT 0x00000008
  1027. #define RDMAC_STATUS_PARITYERR 0x00000010
  1028. #define RDMAC_STATUS_ADDROFLOW 0x00000020
  1029. #define RDMAC_STATUS_FIFOOFLOW 0x00000040
  1030. #define RDMAC_STATUS_FIFOURUN 0x00000080
  1031. #define RDMAC_STATUS_FIFOOREAD 0x00000100
  1032. #define RDMAC_STATUS_LNGREAD 0x00000200
  1033. /* 0x4808 --> 0x4c00 unused */
  1034. /* Write DMA control registers */
  1035. #define WDMAC_MODE 0x00004c00
  1036. #define WDMAC_MODE_RESET 0x00000001
  1037. #define WDMAC_MODE_ENABLE 0x00000002
  1038. #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
  1039. #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
  1040. #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
  1041. #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
  1042. #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
  1043. #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
  1044. #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
  1045. #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
  1046. #define WDMAC_MODE_RX_ACCEL 0x00000400
  1047. #define WDMAC_STATUS 0x00004c04
  1048. #define WDMAC_STATUS_TGTABORT 0x00000004
  1049. #define WDMAC_STATUS_MSTABORT 0x00000008
  1050. #define WDMAC_STATUS_PARITYERR 0x00000010
  1051. #define WDMAC_STATUS_ADDROFLOW 0x00000020
  1052. #define WDMAC_STATUS_FIFOOFLOW 0x00000040
  1053. #define WDMAC_STATUS_FIFOURUN 0x00000080
  1054. #define WDMAC_STATUS_FIFOOREAD 0x00000100
  1055. #define WDMAC_STATUS_LNGREAD 0x00000200
  1056. /* 0x4c08 --> 0x5000 unused */
  1057. /* Per-cpu register offsets (arm9) */
  1058. #define CPU_MODE 0x00000000
  1059. #define CPU_MODE_RESET 0x00000001
  1060. #define CPU_MODE_HALT 0x00000400
  1061. #define CPU_STATE 0x00000004
  1062. #define CPU_EVTMASK 0x00000008
  1063. /* 0xc --> 0x1c reserved */
  1064. #define CPU_PC 0x0000001c
  1065. #define CPU_INSN 0x00000020
  1066. #define CPU_SPAD_UFLOW 0x00000024
  1067. #define CPU_WDOG_CLEAR 0x00000028
  1068. #define CPU_WDOG_VECTOR 0x0000002c
  1069. #define CPU_WDOG_PC 0x00000030
  1070. #define CPU_HW_BP 0x00000034
  1071. /* 0x38 --> 0x44 unused */
  1072. #define CPU_WDOG_SAVED_STATE 0x00000044
  1073. #define CPU_LAST_BRANCH_ADDR 0x00000048
  1074. #define CPU_SPAD_UFLOW_SET 0x0000004c
  1075. /* 0x50 --> 0x200 unused */
  1076. #define CPU_R0 0x00000200
  1077. #define CPU_R1 0x00000204
  1078. #define CPU_R2 0x00000208
  1079. #define CPU_R3 0x0000020c
  1080. #define CPU_R4 0x00000210
  1081. #define CPU_R5 0x00000214
  1082. #define CPU_R6 0x00000218
  1083. #define CPU_R7 0x0000021c
  1084. #define CPU_R8 0x00000220
  1085. #define CPU_R9 0x00000224
  1086. #define CPU_R10 0x00000228
  1087. #define CPU_R11 0x0000022c
  1088. #define CPU_R12 0x00000230
  1089. #define CPU_R13 0x00000234
  1090. #define CPU_R14 0x00000238
  1091. #define CPU_R15 0x0000023c
  1092. #define CPU_R16 0x00000240
  1093. #define CPU_R17 0x00000244
  1094. #define CPU_R18 0x00000248
  1095. #define CPU_R19 0x0000024c
  1096. #define CPU_R20 0x00000250
  1097. #define CPU_R21 0x00000254
  1098. #define CPU_R22 0x00000258
  1099. #define CPU_R23 0x0000025c
  1100. #define CPU_R24 0x00000260
  1101. #define CPU_R25 0x00000264
  1102. #define CPU_R26 0x00000268
  1103. #define CPU_R27 0x0000026c
  1104. #define CPU_R28 0x00000270
  1105. #define CPU_R29 0x00000274
  1106. #define CPU_R30 0x00000278
  1107. #define CPU_R31 0x0000027c
  1108. /* 0x280 --> 0x400 unused */
  1109. #define RX_CPU_BASE 0x00005000
  1110. #define RX_CPU_MODE 0x00005000
  1111. #define RX_CPU_STATE 0x00005004
  1112. #define RX_CPU_PGMCTR 0x0000501c
  1113. #define RX_CPU_HWBKPT 0x00005034
  1114. #define TX_CPU_BASE 0x00005400
  1115. #define TX_CPU_MODE 0x00005400
  1116. #define TX_CPU_STATE 0x00005404
  1117. #define TX_CPU_PGMCTR 0x0000541c
  1118. #define VCPU_STATUS 0x00005100
  1119. #define VCPU_STATUS_INIT_DONE 0x04000000
  1120. #define VCPU_STATUS_DRV_RESET 0x08000000
  1121. /* Mailboxes */
  1122. #define GRCMBOX_BASE 0x00005600
  1123. #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
  1124. #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
  1125. #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
  1126. #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
  1127. #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
  1128. #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
  1129. #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
  1130. #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
  1131. #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
  1132. #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
  1133. #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
  1134. #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
  1135. #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
  1136. #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
  1137. #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
  1138. #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
  1139. #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
  1140. #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
  1141. #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
  1142. #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
  1143. #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
  1144. #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
  1145. #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
  1146. #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
  1147. #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
  1148. #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
  1149. #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
  1150. #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
  1151. #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
  1152. #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
  1153. #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
  1154. #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
  1155. #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
  1156. #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
  1157. #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
  1158. #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
  1159. #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
  1160. #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
  1161. #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
  1162. #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
  1163. #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
  1164. #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
  1165. #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
  1166. #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
  1167. #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
  1168. #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
  1169. #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
  1170. #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
  1171. #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
  1172. #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
  1173. #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
  1174. #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
  1175. #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
  1176. #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
  1177. #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
  1178. #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
  1179. #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
  1180. #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
  1181. #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
  1182. #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
  1183. #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
  1184. #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
  1185. #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
  1186. #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
  1187. #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
  1188. #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
  1189. #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
  1190. #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
  1191. /* 0x5a10 --> 0x5c00 */
  1192. /* Flow Through queues */
  1193. #define FTQ_RESET 0x00005c00
  1194. /* 0x5c04 --> 0x5c10 unused */
  1195. #define FTQ_DMA_NORM_READ_CTL 0x00005c10
  1196. #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
  1197. #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
  1198. #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
  1199. #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
  1200. #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
  1201. #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
  1202. #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
  1203. #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
  1204. #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
  1205. #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
  1206. #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
  1207. #define FTQ_SEND_BD_COMP_CTL 0x00005c40
  1208. #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
  1209. #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
  1210. #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
  1211. #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
  1212. #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
  1213. #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
  1214. #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
  1215. #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
  1216. #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
  1217. #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
  1218. #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
  1219. #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
  1220. #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
  1221. #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
  1222. #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
  1223. #define FTQ_SWTYPE1_CTL 0x00005c80
  1224. #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
  1225. #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
  1226. #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
  1227. #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
  1228. #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
  1229. #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
  1230. #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
  1231. #define FTQ_HOST_COAL_CTL 0x00005ca0
  1232. #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
  1233. #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
  1234. #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
  1235. #define FTQ_MAC_TX_CTL 0x00005cb0
  1236. #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
  1237. #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
  1238. #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
  1239. #define FTQ_MB_FREE_CTL 0x00005cc0
  1240. #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
  1241. #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
  1242. #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
  1243. #define FTQ_RCVBD_COMP_CTL 0x00005cd0
  1244. #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
  1245. #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
  1246. #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
  1247. #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
  1248. #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
  1249. #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
  1250. #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
  1251. #define FTQ_RCVDATA_INI_CTL 0x00005cf0
  1252. #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
  1253. #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
  1254. #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
  1255. #define FTQ_RCVDATA_COMP_CTL 0x00005d00
  1256. #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
  1257. #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
  1258. #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
  1259. #define FTQ_SWTYPE2_CTL 0x00005d10
  1260. #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
  1261. #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
  1262. #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
  1263. /* 0x5d20 --> 0x6000 unused */
  1264. /* Message signaled interrupt registers */
  1265. #define MSGINT_MODE 0x00006000
  1266. #define MSGINT_MODE_RESET 0x00000001
  1267. #define MSGINT_MODE_ENABLE 0x00000002
  1268. #define MSGINT_STATUS 0x00006004
  1269. #define MSGINT_FIFO 0x00006008
  1270. /* 0x600c --> 0x6400 unused */
  1271. /* DMA completion registers */
  1272. #define DMAC_MODE 0x00006400
  1273. #define DMAC_MODE_RESET 0x00000001
  1274. #define DMAC_MODE_ENABLE 0x00000002
  1275. /* 0x6404 --> 0x6800 unused */
  1276. /* GRC registers */
  1277. #define GRC_MODE 0x00006800
  1278. #define GRC_MODE_UPD_ON_COAL 0x00000001
  1279. #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
  1280. #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
  1281. #define GRC_MODE_BSWAP_DATA 0x00000010
  1282. #define GRC_MODE_WSWAP_DATA 0x00000020
  1283. #define GRC_MODE_SPLITHDR 0x00000100
  1284. #define GRC_MODE_NOFRM_CRACKING 0x00000200
  1285. #define GRC_MODE_INCL_CRC 0x00000400
  1286. #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
  1287. #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
  1288. #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
  1289. #define GRC_MODE_FORCE_PCI32BIT 0x00008000
  1290. #define GRC_MODE_HOST_STACKUP 0x00010000
  1291. #define GRC_MODE_HOST_SENDBDS 0x00020000
  1292. #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
  1293. #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
  1294. #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
  1295. #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
  1296. #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
  1297. #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
  1298. #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
  1299. #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
  1300. #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
  1301. #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
  1302. #define GRC_MISC_CFG 0x00006804
  1303. #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
  1304. #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
  1305. #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
  1306. #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
  1307. #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
  1308. #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
  1309. #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
  1310. #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
  1311. #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
  1312. #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
  1313. #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
  1314. #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
  1315. #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
  1316. #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
  1317. #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
  1318. #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
  1319. #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
  1320. #define GRC_LOCAL_CTRL 0x00006808
  1321. #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
  1322. #define GRC_LCLCTRL_CLEARINT 0x00000002
  1323. #define GRC_LCLCTRL_SETINT 0x00000004
  1324. #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
  1325. #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
  1326. #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
  1327. #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
  1328. #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
  1329. #define GRC_LCLCTRL_GPIO_OE3 0x00000040
  1330. #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
  1331. #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
  1332. #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
  1333. #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
  1334. #define GRC_LCLCTRL_GPIO_OE0 0x00000800
  1335. #define GRC_LCLCTRL_GPIO_OE1 0x00001000
  1336. #define GRC_LCLCTRL_GPIO_OE2 0x00002000
  1337. #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
  1338. #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
  1339. #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
  1340. #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
  1341. #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
  1342. #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
  1343. #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
  1344. #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
  1345. #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
  1346. #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
  1347. #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
  1348. #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
  1349. #define GRC_LCLCTRL_BANK_SELECT 0x00200000
  1350. #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
  1351. #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
  1352. #define GRC_TIMER 0x0000680c
  1353. #define GRC_RX_CPU_EVENT 0x00006810
  1354. #define GRC_RX_TIMER_REF 0x00006814
  1355. #define GRC_RX_CPU_SEM 0x00006818
  1356. #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
  1357. #define GRC_TX_CPU_EVENT 0x00006820
  1358. #define GRC_TX_TIMER_REF 0x00006824
  1359. #define GRC_TX_CPU_SEM 0x00006828
  1360. #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
  1361. #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
  1362. #define GRC_EEPROM_ADDR 0x00006838
  1363. #define EEPROM_ADDR_WRITE 0x00000000
  1364. #define EEPROM_ADDR_READ 0x80000000
  1365. #define EEPROM_ADDR_COMPLETE 0x40000000
  1366. #define EEPROM_ADDR_FSM_RESET 0x20000000
  1367. #define EEPROM_ADDR_DEVID_MASK 0x1c000000
  1368. #define EEPROM_ADDR_DEVID_SHIFT 26
  1369. #define EEPROM_ADDR_START 0x02000000
  1370. #define EEPROM_ADDR_CLKPERD_SHIFT 16
  1371. #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
  1372. #define EEPROM_ADDR_ADDR_SHIFT 0
  1373. #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
  1374. #define EEPROM_CHIP_SIZE (64 * 1024)
  1375. #define GRC_EEPROM_DATA 0x0000683c
  1376. #define GRC_EEPROM_CTRL 0x00006840
  1377. #define GRC_MDI_CTRL 0x00006844
  1378. #define GRC_SEEPROM_DELAY 0x00006848
  1379. /* 0x684c --> 0x6890 unused */
  1380. #define GRC_VCPU_EXT_CTRL 0x00006890
  1381. #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
  1382. #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
  1383. #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
  1384. /* 0x6c00 --> 0x7000 unused */
  1385. /* NVRAM Control registers */
  1386. #define NVRAM_CMD 0x00007000
  1387. #define NVRAM_CMD_RESET 0x00000001
  1388. #define NVRAM_CMD_DONE 0x00000008
  1389. #define NVRAM_CMD_GO 0x00000010
  1390. #define NVRAM_CMD_WR 0x00000020
  1391. #define NVRAM_CMD_RD 0x00000000
  1392. #define NVRAM_CMD_ERASE 0x00000040
  1393. #define NVRAM_CMD_FIRST 0x00000080
  1394. #define NVRAM_CMD_LAST 0x00000100
  1395. #define NVRAM_CMD_WREN 0x00010000
  1396. #define NVRAM_CMD_WRDI 0x00020000
  1397. #define NVRAM_STAT 0x00007004
  1398. #define NVRAM_WRDATA 0x00007008
  1399. #define NVRAM_ADDR 0x0000700c
  1400. #define NVRAM_ADDR_MSK 0x00ffffff
  1401. #define NVRAM_RDDATA 0x00007010
  1402. #define NVRAM_CFG1 0x00007014
  1403. #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
  1404. #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
  1405. #define NVRAM_CFG1_PASS_THRU 0x00000004
  1406. #define NVRAM_CFG1_STATUS_BITS 0x00000070
  1407. #define NVRAM_CFG1_BIT_BANG 0x00000008
  1408. #define NVRAM_CFG1_FLASH_SIZE 0x02000000
  1409. #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
  1410. #define NVRAM_CFG1_VENDOR_MASK 0x03000003
  1411. #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
  1412. #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
  1413. #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
  1414. #define FLASH_VENDOR_ST 0x03000001
  1415. #define FLASH_VENDOR_SAIFUN 0x01000003
  1416. #define FLASH_VENDOR_SST_SMALL 0x00000001
  1417. #define FLASH_VENDOR_SST_LARGE 0x02000001
  1418. #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
  1419. #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
  1420. #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
  1421. #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
  1422. #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
  1423. #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
  1424. #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
  1425. #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
  1426. #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
  1427. #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
  1428. #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
  1429. #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
  1430. #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
  1431. #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
  1432. #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
  1433. #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
  1434. #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
  1435. #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
  1436. #define FLASH_5752PAGE_SIZE_256 0x00000000
  1437. #define FLASH_5752PAGE_SIZE_512 0x10000000
  1438. #define FLASH_5752PAGE_SIZE_1K 0x20000000
  1439. #define FLASH_5752PAGE_SIZE_2K 0x30000000
  1440. #define FLASH_5752PAGE_SIZE_4K 0x40000000
  1441. #define FLASH_5752PAGE_SIZE_264 0x50000000
  1442. #define NVRAM_CFG2 0x00007018
  1443. #define NVRAM_CFG3 0x0000701c
  1444. #define NVRAM_SWARB 0x00007020
  1445. #define SWARB_REQ_SET0 0x00000001
  1446. #define SWARB_REQ_SET1 0x00000002
  1447. #define SWARB_REQ_SET2 0x00000004
  1448. #define SWARB_REQ_SET3 0x00000008
  1449. #define SWARB_REQ_CLR0 0x00000010
  1450. #define SWARB_REQ_CLR1 0x00000020
  1451. #define SWARB_REQ_CLR2 0x00000040
  1452. #define SWARB_REQ_CLR3 0x00000080
  1453. #define SWARB_GNT0 0x00000100
  1454. #define SWARB_GNT1 0x00000200
  1455. #define SWARB_GNT2 0x00000400
  1456. #define SWARB_GNT3 0x00000800
  1457. #define SWARB_REQ0 0x00001000
  1458. #define SWARB_REQ1 0x00002000
  1459. #define SWARB_REQ2 0x00004000
  1460. #define SWARB_REQ3 0x00008000
  1461. #define NVRAM_ACCESS 0x00007024
  1462. #define ACCESS_ENABLE 0x00000001
  1463. #define ACCESS_WR_ENABLE 0x00000002
  1464. #define NVRAM_WRITE1 0x00007028
  1465. /* 0x702c --> 0x7400 unused */
  1466. /* 0x7400 --> 0x7c00 unused */
  1467. #define PCIE_TRANSACTION_CFG 0x00007c04
  1468. #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
  1469. #define PCIE_TRANS_CFG_LOM 0x00000020
  1470. #define TG3_EEPROM_MAGIC 0x669955aa
  1471. #define TG3_EEPROM_MAGIC_FW 0xa5000000
  1472. #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
  1473. #define TG3_EEPROM_MAGIC_HW 0xabcd
  1474. #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
  1475. /* 32K Window into NIC internal memory */
  1476. #define NIC_SRAM_WIN_BASE 0x00008000
  1477. /* Offsets into first 32k of NIC internal memory. */
  1478. #define NIC_SRAM_PAGE_ZERO 0x00000000
  1479. #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
  1480. #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
  1481. #define NIC_SRAM_STATS_BLK 0x00000300
  1482. #define NIC_SRAM_STATUS_BLK 0x00000b00
  1483. #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
  1484. #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
  1485. #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
  1486. #define NIC_SRAM_DATA_SIG 0x00000b54
  1487. #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
  1488. #define NIC_SRAM_DATA_CFG 0x00000b58
  1489. #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
  1490. #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
  1491. #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
  1492. #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
  1493. #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
  1494. #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
  1495. #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
  1496. #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
  1497. #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
  1498. #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
  1499. #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
  1500. #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
  1501. #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
  1502. #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
  1503. #define NIC_SRAM_DATA_VER 0x00000b5c
  1504. #define NIC_SRAM_DATA_VER_SHIFT 16
  1505. #define NIC_SRAM_DATA_PHY_ID 0x00000b74
  1506. #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
  1507. #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
  1508. #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
  1509. #define FWCMD_NICDRV_ALIVE 0x00000001
  1510. #define FWCMD_NICDRV_PAUSE_FW 0x00000002
  1511. #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
  1512. #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
  1513. #define FWCMD_NICDRV_FIX_DMAR 0x00000005
  1514. #define FWCMD_NICDRV_FIX_DMAW 0x00000006
  1515. #define FWCMD_NICDRV_ALIVE2 0x0000000d
  1516. #define FWCMD_NICDRV_ALIVE3 0x0000000e
  1517. #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
  1518. #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
  1519. #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
  1520. #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
  1521. #define DRV_STATE_START 0x00000001
  1522. #define DRV_STATE_START_DONE 0x80000001
  1523. #define DRV_STATE_UNLOAD 0x00000002
  1524. #define DRV_STATE_UNLOAD_DONE 0x80000002
  1525. #define DRV_STATE_WOL 0x00000003
  1526. #define DRV_STATE_SUSPEND 0x00000004
  1527. #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
  1528. #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
  1529. #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
  1530. #define NIC_SRAM_WOL_MBOX 0x00000d30
  1531. #define WOL_SIGNATURE 0x474c0000
  1532. #define WOL_DRV_STATE_SHUTDOWN 0x00000001
  1533. #define WOL_DRV_WOL 0x00000002
  1534. #define WOL_SET_MAGIC_PKT 0x00000004
  1535. #define NIC_SRAM_DATA_CFG_2 0x00000d38
  1536. #define SHASTA_EXT_LED_MODE_MASK 0x00018000
  1537. #define SHASTA_EXT_LED_LEGACY 0x00000000
  1538. #define SHASTA_EXT_LED_SHARED 0x00008000
  1539. #define SHASTA_EXT_LED_MAC 0x00010000
  1540. #define SHASTA_EXT_LED_COMBO 0x00018000
  1541. #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
  1542. #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
  1543. #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
  1544. #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
  1545. #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
  1546. #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
  1547. #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
  1548. #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
  1549. #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
  1550. #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
  1551. #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
  1552. /* Currently this is fixed. */
  1553. #define PHY_ADDR 0x01
  1554. /* Tigon3 specific PHY MII registers. */
  1555. #define TG3_BMCR_SPEED1000 0x0040
  1556. #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
  1557. #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
  1558. #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
  1559. #define MII_TG3_CTRL_AS_MASTER 0x0800
  1560. #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
  1561. #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
  1562. #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
  1563. #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
  1564. #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
  1565. #define MII_TG3_EXT_CTRL_TBI 0x8000
  1566. #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
  1567. #define MII_TG3_EXT_STAT_LPASS 0x0100
  1568. #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
  1569. #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
  1570. #define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
  1571. #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
  1572. #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
  1573. #define MII_TG3_AUX_STAT_LPASS 0x0004
  1574. #define MII_TG3_AUX_STAT_SPDMASK 0x0700
  1575. #define MII_TG3_AUX_STAT_10HALF 0x0100
  1576. #define MII_TG3_AUX_STAT_10FULL 0x0200
  1577. #define MII_TG3_AUX_STAT_100HALF 0x0300
  1578. #define MII_TG3_AUX_STAT_100_4 0x0400
  1579. #define MII_TG3_AUX_STAT_100FULL 0x0500
  1580. #define MII_TG3_AUX_STAT_1000HALF 0x0600
  1581. #define MII_TG3_AUX_STAT_1000FULL 0x0700
  1582. #define MII_TG3_AUX_STAT_100 0x0008
  1583. #define MII_TG3_AUX_STAT_FULL 0x0001
  1584. #define MII_TG3_ISTAT 0x1a /* IRQ status register */
  1585. #define MII_TG3_IMASK 0x1b /* IRQ mask register */
  1586. /* ISTAT/IMASK event bits */
  1587. #define MII_TG3_INT_LINKCHG 0x0002
  1588. #define MII_TG3_INT_SPEEDCHG 0x0004
  1589. #define MII_TG3_INT_DUPLEXCHG 0x0008
  1590. #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
  1591. #define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
  1592. #define MII_TG3_EPHY_SHADOW_EN 0x80
  1593. #define MII_TG3_TEST1 0x1e
  1594. #define MII_TG3_TEST1_TRIM_EN 0x0010
  1595. #define MII_TG3_TEST1_CRC_EN 0x8000
  1596. /* There are two ways to manage the TX descriptors on the tigon3.
  1597. * Either the descriptors are in host DMA'able memory, or they
  1598. * exist only in the cards on-chip SRAM. All 16 send bds are under
  1599. * the same mode, they may not be configured individually.
  1600. *
  1601. * This driver always uses host memory TX descriptors.
  1602. *
  1603. * To use host memory TX descriptors:
  1604. * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
  1605. * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
  1606. * 2) Allocate DMA'able memory.
  1607. * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
  1608. * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
  1609. * obtained in step 2
  1610. * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
  1611. * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
  1612. * of TX descriptors. Leave flags field clear.
  1613. * 4) Access TX descriptors via host memory. The chip
  1614. * will refetch into local SRAM as needed when producer
  1615. * index mailboxes are updated.
  1616. *
  1617. * To use on-chip TX descriptors:
  1618. * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
  1619. * Make sure GRC_MODE_HOST_SENDBDS is clear.
  1620. * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
  1621. * a) Set TG3_BDINFO_HOST_ADDR to zero.
  1622. * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
  1623. * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
  1624. * 3) Access TX descriptors directly in on-chip SRAM
  1625. * using normal {read,write}l(). (and not using
  1626. * pointer dereferencing of ioremap()'d memory like
  1627. * the broken Broadcom driver does)
  1628. *
  1629. * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
  1630. * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
  1631. */
  1632. struct tg3_tx_buffer_desc {
  1633. u32 addr_hi;
  1634. u32 addr_lo;
  1635. u32 len_flags;
  1636. #define TXD_FLAG_TCPUDP_CSUM 0x0001
  1637. #define TXD_FLAG_IP_CSUM 0x0002
  1638. #define TXD_FLAG_END 0x0004
  1639. #define TXD_FLAG_IP_FRAG 0x0008
  1640. #define TXD_FLAG_IP_FRAG_END 0x0010
  1641. #define TXD_FLAG_VLAN 0x0040
  1642. #define TXD_FLAG_COAL_NOW 0x0080
  1643. #define TXD_FLAG_CPU_PRE_DMA 0x0100
  1644. #define TXD_FLAG_CPU_POST_DMA 0x0200
  1645. #define TXD_FLAG_ADD_SRC_ADDR 0x1000
  1646. #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
  1647. #define TXD_FLAG_NO_CRC 0x8000
  1648. #define TXD_LEN_SHIFT 16
  1649. u32 vlan_tag;
  1650. #define TXD_VLAN_TAG_SHIFT 0
  1651. #define TXD_MSS_SHIFT 16
  1652. };
  1653. #define TXD_ADDR 0x00UL /* 64-bit */
  1654. #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
  1655. #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
  1656. #define TXD_SIZE 0x10UL
  1657. struct tg3_rx_buffer_desc {
  1658. u32 addr_hi;
  1659. u32 addr_lo;
  1660. u32 idx_len;
  1661. #define RXD_IDX_MASK 0xffff0000
  1662. #define RXD_IDX_SHIFT 16
  1663. #define RXD_LEN_MASK 0x0000ffff
  1664. #define RXD_LEN_SHIFT 0
  1665. u32 type_flags;
  1666. #define RXD_TYPE_SHIFT 16
  1667. #define RXD_FLAGS_SHIFT 0
  1668. #define RXD_FLAG_END 0x0004
  1669. #define RXD_FLAG_MINI 0x0800
  1670. #define RXD_FLAG_JUMBO 0x0020
  1671. #define RXD_FLAG_VLAN 0x0040
  1672. #define RXD_FLAG_ERROR 0x0400
  1673. #define RXD_FLAG_IP_CSUM 0x1000
  1674. #define RXD_FLAG_TCPUDP_CSUM 0x2000
  1675. #define RXD_FLAG_IS_TCP 0x4000
  1676. u32 ip_tcp_csum;
  1677. #define RXD_IPCSUM_MASK 0xffff0000
  1678. #define RXD_IPCSUM_SHIFT 16
  1679. #define RXD_TCPCSUM_MASK 0x0000ffff
  1680. #define RXD_TCPCSUM_SHIFT 0
  1681. u32 err_vlan;
  1682. #define RXD_VLAN_MASK 0x0000ffff
  1683. #define RXD_ERR_BAD_CRC 0x00010000
  1684. #define RXD_ERR_COLLISION 0x00020000
  1685. #define RXD_ERR_LINK_LOST 0x00040000
  1686. #define RXD_ERR_PHY_DECODE 0x00080000
  1687. #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
  1688. #define RXD_ERR_MAC_ABRT 0x00200000
  1689. #define RXD_ERR_TOO_SMALL 0x00400000
  1690. #define RXD_ERR_NO_RESOURCES 0x00800000
  1691. #define RXD_ERR_HUGE_FRAME 0x01000000
  1692. #define RXD_ERR_MASK 0xffff0000
  1693. u32 reserved;
  1694. u32 opaque;
  1695. #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
  1696. #define RXD_OPAQUE_INDEX_SHIFT 0
  1697. #define RXD_OPAQUE_RING_STD 0x00010000
  1698. #define RXD_OPAQUE_RING_JUMBO 0x00020000
  1699. #define RXD_OPAQUE_RING_MINI 0x00040000
  1700. #define RXD_OPAQUE_RING_MASK 0x00070000
  1701. };
  1702. struct tg3_ext_rx_buffer_desc {
  1703. struct {
  1704. u32 addr_hi;
  1705. u32 addr_lo;
  1706. } addrlist[3];
  1707. u32 len2_len1;
  1708. u32 resv_len3;
  1709. struct tg3_rx_buffer_desc std;
  1710. };
  1711. /* We only use this when testing out the DMA engine
  1712. * at probe time. This is the internal format of buffer
  1713. * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
  1714. */
  1715. struct tg3_internal_buffer_desc {
  1716. u32 addr_hi;
  1717. u32 addr_lo;
  1718. u32 nic_mbuf;
  1719. /* XXX FIX THIS */
  1720. #ifdef __BIG_ENDIAN
  1721. u16 cqid_sqid;
  1722. u16 len;
  1723. #else
  1724. u16 len;
  1725. u16 cqid_sqid;
  1726. #endif
  1727. u32 flags;
  1728. u32 __cookie1;
  1729. u32 __cookie2;
  1730. u32 __cookie3;
  1731. };
  1732. #define TG3_HW_STATUS_SIZE 0x50
  1733. struct tg3_hw_status {
  1734. u32 status;
  1735. #define SD_STATUS_UPDATED 0x00000001
  1736. #define SD_STATUS_LINK_CHG 0x00000002
  1737. #define SD_STATUS_ERROR 0x00000004
  1738. u32 status_tag;
  1739. #ifdef __BIG_ENDIAN
  1740. u16 rx_consumer;
  1741. u16 rx_jumbo_consumer;
  1742. #else
  1743. u16 rx_jumbo_consumer;
  1744. u16 rx_consumer;
  1745. #endif
  1746. #ifdef __BIG_ENDIAN
  1747. u16 reserved;
  1748. u16 rx_mini_consumer;
  1749. #else
  1750. u16 rx_mini_consumer;
  1751. u16 reserved;
  1752. #endif
  1753. struct {
  1754. #ifdef __BIG_ENDIAN
  1755. u16 tx_consumer;
  1756. u16 rx_producer;
  1757. #else
  1758. u16 rx_producer;
  1759. u16 tx_consumer;
  1760. #endif
  1761. } idx[16];
  1762. };
  1763. typedef struct {
  1764. u32 high, low;
  1765. } tg3_stat64_t;
  1766. struct tg3_hw_stats {
  1767. u8 __reserved0[0x400-0x300];
  1768. /* Statistics maintained by Receive MAC. */
  1769. tg3_stat64_t rx_octets;
  1770. u64 __reserved1;
  1771. tg3_stat64_t rx_fragments;
  1772. tg3_stat64_t rx_ucast_packets;
  1773. tg3_stat64_t rx_mcast_packets;
  1774. tg3_stat64_t rx_bcast_packets;
  1775. tg3_stat64_t rx_fcs_errors;
  1776. tg3_stat64_t rx_align_errors;
  1777. tg3_stat64_t rx_xon_pause_rcvd;
  1778. tg3_stat64_t rx_xoff_pause_rcvd;
  1779. tg3_stat64_t rx_mac_ctrl_rcvd;
  1780. tg3_stat64_t rx_xoff_entered;
  1781. tg3_stat64_t rx_frame_too_long_errors;
  1782. tg3_stat64_t rx_jabbers;
  1783. tg3_stat64_t rx_undersize_packets;
  1784. tg3_stat64_t rx_in_length_errors;
  1785. tg3_stat64_t rx_out_length_errors;
  1786. tg3_stat64_t rx_64_or_less_octet_packets;
  1787. tg3_stat64_t rx_65_to_127_octet_packets;
  1788. tg3_stat64_t rx_128_to_255_octet_packets;
  1789. tg3_stat64_t rx_256_to_511_octet_packets;
  1790. tg3_stat64_t rx_512_to_1023_octet_packets;
  1791. tg3_stat64_t rx_1024_to_1522_octet_packets;
  1792. tg3_stat64_t rx_1523_to_2047_octet_packets;
  1793. tg3_stat64_t rx_2048_to_4095_octet_packets;
  1794. tg3_stat64_t rx_4096_to_8191_octet_packets;
  1795. tg3_stat64_t rx_8192_to_9022_octet_packets;
  1796. u64 __unused0[37];
  1797. /* Statistics maintained by Transmit MAC. */
  1798. tg3_stat64_t tx_octets;
  1799. u64 __reserved2;
  1800. tg3_stat64_t tx_collisions;
  1801. tg3_stat64_t tx_xon_sent;
  1802. tg3_stat64_t tx_xoff_sent;
  1803. tg3_stat64_t tx_flow_control;
  1804. tg3_stat64_t tx_mac_errors;
  1805. tg3_stat64_t tx_single_collisions;
  1806. tg3_stat64_t tx_mult_collisions;
  1807. tg3_stat64_t tx_deferred;
  1808. u64 __reserved3;
  1809. tg3_stat64_t tx_excessive_collisions;
  1810. tg3_stat64_t tx_late_collisions;
  1811. tg3_stat64_t tx_collide_2times;
  1812. tg3_stat64_t tx_collide_3times;
  1813. tg3_stat64_t tx_collide_4times;
  1814. tg3_stat64_t tx_collide_5times;
  1815. tg3_stat64_t tx_collide_6times;
  1816. tg3_stat64_t tx_collide_7times;
  1817. tg3_stat64_t tx_collide_8times;
  1818. tg3_stat64_t tx_collide_9times;
  1819. tg3_stat64_t tx_collide_10times;
  1820. tg3_stat64_t tx_collide_11times;
  1821. tg3_stat64_t tx_collide_12times;
  1822. tg3_stat64_t tx_collide_13times;
  1823. tg3_stat64_t tx_collide_14times;
  1824. tg3_stat64_t tx_collide_15times;
  1825. tg3_stat64_t tx_ucast_packets;
  1826. tg3_stat64_t tx_mcast_packets;
  1827. tg3_stat64_t tx_bcast_packets;
  1828. tg3_stat64_t tx_carrier_sense_errors;
  1829. tg3_stat64_t tx_discards;
  1830. tg3_stat64_t tx_errors;
  1831. u64 __unused1[31];
  1832. /* Statistics maintained by Receive List Placement. */
  1833. tg3_stat64_t COS_rx_packets[16];
  1834. tg3_stat64_t COS_rx_filter_dropped;
  1835. tg3_stat64_t dma_writeq_full;
  1836. tg3_stat64_t dma_write_prioq_full;
  1837. tg3_stat64_t rxbds_empty;
  1838. tg3_stat64_t rx_discards;
  1839. tg3_stat64_t rx_errors;
  1840. tg3_stat64_t rx_threshold_hit;
  1841. u64 __unused2[9];
  1842. /* Statistics maintained by Send Data Initiator. */
  1843. tg3_stat64_t COS_out_packets[16];
  1844. tg3_stat64_t dma_readq_full;
  1845. tg3_stat64_t dma_read_prioq_full;
  1846. tg3_stat64_t tx_comp_queue_full;
  1847. /* Statistics maintained by Host Coalescing. */
  1848. tg3_stat64_t ring_set_send_prod_index;
  1849. tg3_stat64_t ring_status_update;
  1850. tg3_stat64_t nic_irqs;
  1851. tg3_stat64_t nic_avoided_irqs;
  1852. tg3_stat64_t nic_tx_threshold_hit;
  1853. u8 __reserved4[0xb00-0x9c0];
  1854. };
  1855. /* 'mapping' is superfluous as the chip does not write into
  1856. * the tx/rx post rings so we could just fetch it from there.
  1857. * But the cache behavior is better how we are doing it now.
  1858. */
  1859. struct ring_info {
  1860. struct sk_buff *skb;
  1861. DECLARE_PCI_UNMAP_ADDR(mapping)
  1862. };
  1863. struct tx_ring_info {
  1864. struct sk_buff *skb;
  1865. DECLARE_PCI_UNMAP_ADDR(mapping)
  1866. u32 prev_vlan_tag;
  1867. };
  1868. struct tg3_config_info {
  1869. u32 flags;
  1870. };
  1871. struct tg3_link_config {
  1872. /* Describes what we're trying to get. */
  1873. u32 advertising;
  1874. u16 speed;
  1875. u8 duplex;
  1876. u8 autoneg;
  1877. /* Describes what we actually have. */
  1878. u16 active_speed;
  1879. u8 active_duplex;
  1880. #define SPEED_INVALID 0xffff
  1881. #define DUPLEX_INVALID 0xff
  1882. #define AUTONEG_INVALID 0xff
  1883. /* When we go in and out of low power mode we need
  1884. * to swap with this state.
  1885. */
  1886. int phy_is_low_power;
  1887. u16 orig_speed;
  1888. u8 orig_duplex;
  1889. u8 orig_autoneg;
  1890. };
  1891. struct tg3_bufmgr_config {
  1892. u32 mbuf_read_dma_low_water;
  1893. u32 mbuf_mac_rx_low_water;
  1894. u32 mbuf_high_water;
  1895. u32 mbuf_read_dma_low_water_jumbo;
  1896. u32 mbuf_mac_rx_low_water_jumbo;
  1897. u32 mbuf_high_water_jumbo;
  1898. u32 dma_low_water;
  1899. u32 dma_high_water;
  1900. };
  1901. struct tg3_ethtool_stats {
  1902. /* Statistics maintained by Receive MAC. */
  1903. u64 rx_octets;
  1904. u64 rx_fragments;
  1905. u64 rx_ucast_packets;
  1906. u64 rx_mcast_packets;
  1907. u64 rx_bcast_packets;
  1908. u64 rx_fcs_errors;
  1909. u64 rx_align_errors;
  1910. u64 rx_xon_pause_rcvd;
  1911. u64 rx_xoff_pause_rcvd;
  1912. u64 rx_mac_ctrl_rcvd;
  1913. u64 rx_xoff_entered;
  1914. u64 rx_frame_too_long_errors;
  1915. u64 rx_jabbers;
  1916. u64 rx_undersize_packets;
  1917. u64 rx_in_length_errors;
  1918. u64 rx_out_length_errors;
  1919. u64 rx_64_or_less_octet_packets;
  1920. u64 rx_65_to_127_octet_packets;
  1921. u64 rx_128_to_255_octet_packets;
  1922. u64 rx_256_to_511_octet_packets;
  1923. u64 rx_512_to_1023_octet_packets;
  1924. u64 rx_1024_to_1522_octet_packets;
  1925. u64 rx_1523_to_2047_octet_packets;
  1926. u64 rx_2048_to_4095_octet_packets;
  1927. u64 rx_4096_to_8191_octet_packets;
  1928. u64 rx_8192_to_9022_octet_packets;
  1929. /* Statistics maintained by Transmit MAC. */
  1930. u64 tx_octets;
  1931. u64 tx_collisions;
  1932. u64 tx_xon_sent;
  1933. u64 tx_xoff_sent;
  1934. u64 tx_flow_control;
  1935. u64 tx_mac_errors;
  1936. u64 tx_single_collisions;
  1937. u64 tx_mult_collisions;
  1938. u64 tx_deferred;
  1939. u64 tx_excessive_collisions;
  1940. u64 tx_late_collisions;
  1941. u64 tx_collide_2times;
  1942. u64 tx_collide_3times;
  1943. u64 tx_collide_4times;
  1944. u64 tx_collide_5times;
  1945. u64 tx_collide_6times;
  1946. u64 tx_collide_7times;
  1947. u64 tx_collide_8times;
  1948. u64 tx_collide_9times;
  1949. u64 tx_collide_10times;
  1950. u64 tx_collide_11times;
  1951. u64 tx_collide_12times;
  1952. u64 tx_collide_13times;
  1953. u64 tx_collide_14times;
  1954. u64 tx_collide_15times;
  1955. u64 tx_ucast_packets;
  1956. u64 tx_mcast_packets;
  1957. u64 tx_bcast_packets;
  1958. u64 tx_carrier_sense_errors;
  1959. u64 tx_discards;
  1960. u64 tx_errors;
  1961. /* Statistics maintained by Receive List Placement. */
  1962. u64 dma_writeq_full;
  1963. u64 dma_write_prioq_full;
  1964. u64 rxbds_empty;
  1965. u64 rx_discards;
  1966. u64 rx_errors;
  1967. u64 rx_threshold_hit;
  1968. /* Statistics maintained by Send Data Initiator. */
  1969. u64 dma_readq_full;
  1970. u64 dma_read_prioq_full;
  1971. u64 tx_comp_queue_full;
  1972. /* Statistics maintained by Host Coalescing. */
  1973. u64 ring_set_send_prod_index;
  1974. u64 ring_status_update;
  1975. u64 nic_irqs;
  1976. u64 nic_avoided_irqs;
  1977. u64 nic_tx_threshold_hit;
  1978. };
  1979. struct tg3 {
  1980. /* begin "general, frequently-used members" cacheline section */
  1981. /* If the IRQ handler (which runs lockless) needs to be
  1982. * quiesced, the following bitmask state is used. The
  1983. * SYNC flag is set by non-IRQ context code to initiate
  1984. * the quiescence.
  1985. *
  1986. * When the IRQ handler notices that SYNC is set, it
  1987. * disables interrupts and returns.
  1988. *
  1989. * When all outstanding IRQ handlers have returned after
  1990. * the SYNC flag has been set, the setter can be assured
  1991. * that interrupts will no longer get run.
  1992. *
  1993. * In this way all SMP driver locks are never acquired
  1994. * in hw IRQ context, only sw IRQ context or lower.
  1995. */
  1996. unsigned int irq_sync;
  1997. /* SMP locking strategy:
  1998. *
  1999. * lock: Held during reset, PHY access, timer, and when
  2000. * updating tg3_flags and tg3_flags2.
  2001. *
  2002. * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
  2003. * netif_tx_lock when it needs to call
  2004. * netif_wake_queue.
  2005. *
  2006. * Both of these locks are to be held with BH safety.
  2007. *
  2008. * Because the IRQ handler, tg3_poll, and tg3_start_xmit
  2009. * are running lockless, it is necessary to completely
  2010. * quiesce the chip with tg3_netif_stop and tg3_full_lock
  2011. * before reconfiguring the device.
  2012. *
  2013. * indirect_lock: Held when accessing registers indirectly
  2014. * with IRQ disabling.
  2015. */
  2016. spinlock_t lock;
  2017. spinlock_t indirect_lock;
  2018. u32 (*read32) (struct tg3 *, u32);
  2019. void (*write32) (struct tg3 *, u32, u32);
  2020. u32 (*read32_mbox) (struct tg3 *, u32);
  2021. void (*write32_mbox) (struct tg3 *, u32,
  2022. u32);
  2023. void __iomem *regs;
  2024. struct net_device *dev;
  2025. struct pci_dev *pdev;
  2026. struct tg3_hw_status *hw_status;
  2027. dma_addr_t status_mapping;
  2028. u32 last_tag;
  2029. u32 msg_enable;
  2030. /* begin "tx thread" cacheline section */
  2031. void (*write32_tx_mbox) (struct tg3 *, u32,
  2032. u32);
  2033. u32 tx_prod;
  2034. u32 tx_cons;
  2035. u32 tx_pending;
  2036. struct tg3_tx_buffer_desc *tx_ring;
  2037. struct tx_ring_info *tx_buffers;
  2038. dma_addr_t tx_desc_mapping;
  2039. /* begin "rx thread" cacheline section */
  2040. void (*write32_rx_mbox) (struct tg3 *, u32,
  2041. u32);
  2042. u32 rx_rcb_ptr;
  2043. u32 rx_std_ptr;
  2044. u32 rx_jumbo_ptr;
  2045. u32 rx_pending;
  2046. u32 rx_jumbo_pending;
  2047. #if TG3_VLAN_TAG_USED
  2048. struct vlan_group *vlgrp;
  2049. #endif
  2050. struct tg3_rx_buffer_desc *rx_std;
  2051. struct ring_info *rx_std_buffers;
  2052. dma_addr_t rx_std_mapping;
  2053. u32 rx_std_max_post;
  2054. struct tg3_rx_buffer_desc *rx_jumbo;
  2055. struct ring_info *rx_jumbo_buffers;
  2056. dma_addr_t rx_jumbo_mapping;
  2057. struct tg3_rx_buffer_desc *rx_rcb;
  2058. dma_addr_t rx_rcb_mapping;
  2059. u32 rx_pkt_buf_sz;
  2060. /* begin "everything else" cacheline(s) section */
  2061. struct net_device_stats net_stats;
  2062. struct net_device_stats net_stats_prev;
  2063. struct tg3_ethtool_stats estats;
  2064. struct tg3_ethtool_stats estats_prev;
  2065. unsigned long phy_crc_errors;
  2066. u32 rx_offset;
  2067. u32 tg3_flags;
  2068. #define TG3_FLAG_TAGGED_STATUS 0x00000001
  2069. #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
  2070. #define TG3_FLAG_RX_CHECKSUMS 0x00000004
  2071. #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
  2072. #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
  2073. #define TG3_FLAG_ENABLE_ASF 0x00000020
  2074. #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
  2075. #define TG3_FLAG_POLL_SERDES 0x00000080
  2076. #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
  2077. #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
  2078. #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
  2079. #define TG3_FLAG_WOL_ENABLE 0x00000800
  2080. #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
  2081. #define TG3_FLAG_NVRAM 0x00002000
  2082. #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
  2083. #define TG3_FLAG_RX_PAUSE 0x00008000
  2084. #define TG3_FLAG_TX_PAUSE 0x00010000
  2085. #define TG3_FLAG_PCIX_MODE 0x00020000
  2086. #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
  2087. #define TG3_FLAG_PCI_32BIT 0x00080000
  2088. #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
  2089. #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
  2090. #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
  2091. #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
  2092. #define TG3_FLAG_10_100_ONLY 0x01000000
  2093. #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
  2094. #define TG3_FLAG_IN_RESET_TASK 0x04000000
  2095. #define TG3_FLAG_40BIT_DMA_BUG 0x08000000
  2096. #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
  2097. #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
  2098. #define TG3_FLAG_CHIP_RESETTING 0x40000000
  2099. #define TG3_FLAG_INIT_COMPLETE 0x80000000
  2100. u32 tg3_flags2;
  2101. #define TG3_FLG2_RESTART_TIMER 0x00000001
  2102. #define TG3_FLG2_TSO_BUG 0x00000002
  2103. #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
  2104. #define TG3_FLG2_IS_5788 0x00000008
  2105. #define TG3_FLG2_MAX_RXPEND_64 0x00000010
  2106. #define TG3_FLG2_TSO_CAPABLE 0x00000020
  2107. #define TG3_FLG2_PHY_ADC_BUG 0x00000040
  2108. #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
  2109. #define TG3_FLG2_PHY_BER_BUG 0x00000100
  2110. #define TG3_FLG2_PCI_EXPRESS 0x00000200
  2111. #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
  2112. #define TG3_FLG2_HW_AUTONEG 0x00000800
  2113. #define TG3_FLG2_IS_NIC 0x00001000
  2114. #define TG3_FLG2_PHY_SERDES 0x00002000
  2115. #define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
  2116. #define TG3_FLG2_FLASH 0x00008000
  2117. #define TG3_FLG2_HW_TSO_1 0x00010000
  2118. #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
  2119. #define TG3_FLG2_5705_PLUS 0x00040000
  2120. #define TG3_FLG2_5750_PLUS 0x00080000
  2121. #define TG3_FLG2_PROTECTED_NVRAM 0x00100000
  2122. #define TG3_FLG2_USING_MSI 0x00200000
  2123. #define TG3_FLG2_JUMBO_CAPABLE 0x00400000
  2124. #define TG3_FLG2_MII_SERDES 0x00800000
  2125. #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
  2126. TG3_FLG2_MII_SERDES)
  2127. #define TG3_FLG2_PARALLEL_DETECT 0x01000000
  2128. #define TG3_FLG2_ICH_WORKAROUND 0x02000000
  2129. #define TG3_FLG2_5780_CLASS 0x04000000
  2130. #define TG3_FLG2_HW_TSO_2 0x08000000
  2131. #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
  2132. #define TG3_FLG2_1SHOT_MSI 0x10000000
  2133. #define TG3_FLG2_PHY_JITTER_BUG 0x20000000
  2134. #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
  2135. #define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
  2136. struct timer_list timer;
  2137. u16 timer_counter;
  2138. u16 timer_multiplier;
  2139. u32 timer_offset;
  2140. u16 asf_counter;
  2141. u16 asf_multiplier;
  2142. /* 1 second counter for transient serdes link events */
  2143. u32 serdes_counter;
  2144. #define SERDES_AN_TIMEOUT_5704S 2
  2145. #define SERDES_PARALLEL_DET_TIMEOUT 1
  2146. #define SERDES_AN_TIMEOUT_5714S 1
  2147. struct tg3_link_config link_config;
  2148. struct tg3_bufmgr_config bufmgr_config;
  2149. /* cache h/w values, often passed straight to h/w */
  2150. u32 rx_mode;
  2151. u32 tx_mode;
  2152. u32 mac_mode;
  2153. u32 mi_mode;
  2154. u32 misc_host_ctrl;
  2155. u32 grc_mode;
  2156. u32 grc_local_ctrl;
  2157. u32 dma_rwctrl;
  2158. u32 coalesce_mode;
  2159. /* PCI block */
  2160. u16 pci_chip_rev_id;
  2161. u8 pci_cacheline_sz;
  2162. u8 pci_lat_timer;
  2163. u8 pci_hdr_type;
  2164. u8 pci_bist;
  2165. int pm_cap;
  2166. int msi_cap;
  2167. /* PHY info */
  2168. u32 phy_id;
  2169. #define PHY_ID_MASK 0xfffffff0
  2170. #define PHY_ID_BCM5400 0x60008040
  2171. #define PHY_ID_BCM5401 0x60008050
  2172. #define PHY_ID_BCM5411 0x60008070
  2173. #define PHY_ID_BCM5701 0x60008110
  2174. #define PHY_ID_BCM5703 0x60008160
  2175. #define PHY_ID_BCM5704 0x60008190
  2176. #define PHY_ID_BCM5705 0x600081a0
  2177. #define PHY_ID_BCM5750 0x60008180
  2178. #define PHY_ID_BCM5752 0x60008100
  2179. #define PHY_ID_BCM5714 0x60008340
  2180. #define PHY_ID_BCM5780 0x60008350
  2181. #define PHY_ID_BCM5755 0xbc050cc0
  2182. #define PHY_ID_BCM5787 0xbc050ce0
  2183. #define PHY_ID_BCM5756 0xbc050ed0
  2184. #define PHY_ID_BCM5906 0xdc00ac40
  2185. #define PHY_ID_BCM8002 0x60010140
  2186. #define PHY_ID_INVALID 0xffffffff
  2187. #define PHY_ID_REV_MASK 0x0000000f
  2188. #define PHY_REV_BCM5401_B0 0x1
  2189. #define PHY_REV_BCM5401_B2 0x3
  2190. #define PHY_REV_BCM5401_C0 0x6
  2191. #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
  2192. u32 led_ctrl;
  2193. char board_part_number[24];
  2194. char fw_ver[16];
  2195. u32 nic_sram_data_cfg;
  2196. u32 pci_clock_ctrl;
  2197. struct pci_dev *pdev_peer;
  2198. /* This macro assumes the passed PHY ID is already masked
  2199. * with PHY_ID_MASK.
  2200. */
  2201. #define KNOWN_PHY_ID(X) \
  2202. ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
  2203. (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
  2204. (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
  2205. (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
  2206. (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
  2207. (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
  2208. (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
  2209. (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002)
  2210. struct tg3_hw_stats *hw_stats;
  2211. dma_addr_t stats_mapping;
  2212. struct work_struct reset_task;
  2213. int nvram_lock_cnt;
  2214. u32 nvram_size;
  2215. u32 nvram_pagesize;
  2216. u32 nvram_jedecnum;
  2217. #define JEDEC_ATMEL 0x1f
  2218. #define JEDEC_ST 0x20
  2219. #define JEDEC_SAIFUN 0x4f
  2220. #define JEDEC_SST 0xbf
  2221. #define ATMEL_AT24C64_CHIP_SIZE (64 * 1024)
  2222. #define ATMEL_AT24C64_PAGE_SIZE (32)
  2223. #define ATMEL_AT24C512_CHIP_SIZE (512 * 1024)
  2224. #define ATMEL_AT24C512_PAGE_SIZE (128)
  2225. #define ATMEL_AT45DB0X1B_PAGE_POS 9
  2226. #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
  2227. #define ATMEL_AT25F512_PAGE_SIZE 256
  2228. #define ST_M45PEX0_PAGE_SIZE 256
  2229. #define SAIFUN_SA25F0XX_PAGE_SIZE 256
  2230. #define SST_25VF0X0_PAGE_SIZE 4098
  2231. struct ethtool_coalesce coal;
  2232. };
  2233. #endif /* !(_T3_H) */