tg3.c 347 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2007 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/compiler.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/in.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/mii.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/ip.h>
  35. #include <linux/tcp.h>
  36. #include <linux/workqueue.h>
  37. #include <linux/prefetch.h>
  38. #include <linux/dma-mapping.h>
  39. #include <net/checksum.h>
  40. #include <asm/system.h>
  41. #include <asm/io.h>
  42. #include <asm/byteorder.h>
  43. #include <asm/uaccess.h>
  44. #ifdef CONFIG_SPARC64
  45. #include <asm/idprom.h>
  46. #include <asm/oplib.h>
  47. #include <asm/pbm.h>
  48. #endif
  49. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  50. #define TG3_VLAN_TAG_USED 1
  51. #else
  52. #define TG3_VLAN_TAG_USED 0
  53. #endif
  54. #define TG3_TSO_SUPPORT 1
  55. #include "tg3.h"
  56. #define DRV_MODULE_NAME "tg3"
  57. #define PFX DRV_MODULE_NAME ": "
  58. #define DRV_MODULE_VERSION "3.75.2"
  59. #define DRV_MODULE_RELDATE "June 5, 2007"
  60. #define TG3_DEF_MAC_MODE 0
  61. #define TG3_DEF_RX_MODE 0
  62. #define TG3_DEF_TX_MODE 0
  63. #define TG3_DEF_MSG_ENABLE \
  64. (NETIF_MSG_DRV | \
  65. NETIF_MSG_PROBE | \
  66. NETIF_MSG_LINK | \
  67. NETIF_MSG_TIMER | \
  68. NETIF_MSG_IFDOWN | \
  69. NETIF_MSG_IFUP | \
  70. NETIF_MSG_RX_ERR | \
  71. NETIF_MSG_TX_ERR)
  72. /* length of time before we decide the hardware is borked,
  73. * and dev->tx_timeout() should be called to fix the problem
  74. */
  75. #define TG3_TX_TIMEOUT (5 * HZ)
  76. /* hardware minimum and maximum for a single frame's data payload */
  77. #define TG3_MIN_MTU 60
  78. #define TG3_MAX_MTU(tp) \
  79. ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  80. /* These numbers seem to be hard coded in the NIC firmware somehow.
  81. * You can't change the ring sizes, but you can change where you place
  82. * them in the NIC onboard memory.
  83. */
  84. #define TG3_RX_RING_SIZE 512
  85. #define TG3_DEF_RX_RING_PENDING 200
  86. #define TG3_RX_JUMBO_RING_SIZE 256
  87. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  88. /* Do not place this n-ring entries value into the tp struct itself,
  89. * we really want to expose these constants to GCC so that modulo et
  90. * al. operations are done with shifts and masks instead of with
  91. * hw multiply/modulo instructions. Another solution would be to
  92. * replace things like '% foo' with '& (foo - 1)'.
  93. */
  94. #define TG3_RX_RCB_RING_SIZE(tp) \
  95. ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
  96. #define TG3_TX_RING_SIZE 512
  97. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  98. #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  99. TG3_RX_RING_SIZE)
  100. #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  101. TG3_RX_JUMBO_RING_SIZE)
  102. #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
  103. TG3_RX_RCB_RING_SIZE(tp))
  104. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  105. TG3_TX_RING_SIZE)
  106. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  107. #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
  108. #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
  109. /* minimum number of free TX descriptors required to wake up TX process */
  110. #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
  111. /* number of ETHTOOL_GSTATS u64's */
  112. #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
  113. #define TG3_NUM_TEST 6
  114. static char version[] __devinitdata =
  115. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  116. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  117. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  118. MODULE_LICENSE("GPL");
  119. MODULE_VERSION(DRV_MODULE_VERSION);
  120. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  121. module_param(tg3_debug, int, 0);
  122. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  123. static struct pci_device_id tg3_pci_tbl[] = {
  124. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  125. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  126. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  127. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  128. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  129. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  130. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  131. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  132. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  133. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  134. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  135. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  158. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  159. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  160. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  161. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  162. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  163. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  164. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  165. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  166. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  167. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  168. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  169. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  170. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  171. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  172. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  173. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  174. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  175. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  176. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  177. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  178. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  179. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  180. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  181. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  182. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  183. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  184. {}
  185. };
  186. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  187. static const struct {
  188. const char string[ETH_GSTRING_LEN];
  189. } ethtool_stats_keys[TG3_NUM_STATS] = {
  190. { "rx_octets" },
  191. { "rx_fragments" },
  192. { "rx_ucast_packets" },
  193. { "rx_mcast_packets" },
  194. { "rx_bcast_packets" },
  195. { "rx_fcs_errors" },
  196. { "rx_align_errors" },
  197. { "rx_xon_pause_rcvd" },
  198. { "rx_xoff_pause_rcvd" },
  199. { "rx_mac_ctrl_rcvd" },
  200. { "rx_xoff_entered" },
  201. { "rx_frame_too_long_errors" },
  202. { "rx_jabbers" },
  203. { "rx_undersize_packets" },
  204. { "rx_in_length_errors" },
  205. { "rx_out_length_errors" },
  206. { "rx_64_or_less_octet_packets" },
  207. { "rx_65_to_127_octet_packets" },
  208. { "rx_128_to_255_octet_packets" },
  209. { "rx_256_to_511_octet_packets" },
  210. { "rx_512_to_1023_octet_packets" },
  211. { "rx_1024_to_1522_octet_packets" },
  212. { "rx_1523_to_2047_octet_packets" },
  213. { "rx_2048_to_4095_octet_packets" },
  214. { "rx_4096_to_8191_octet_packets" },
  215. { "rx_8192_to_9022_octet_packets" },
  216. { "tx_octets" },
  217. { "tx_collisions" },
  218. { "tx_xon_sent" },
  219. { "tx_xoff_sent" },
  220. { "tx_flow_control" },
  221. { "tx_mac_errors" },
  222. { "tx_single_collisions" },
  223. { "tx_mult_collisions" },
  224. { "tx_deferred" },
  225. { "tx_excessive_collisions" },
  226. { "tx_late_collisions" },
  227. { "tx_collide_2times" },
  228. { "tx_collide_3times" },
  229. { "tx_collide_4times" },
  230. { "tx_collide_5times" },
  231. { "tx_collide_6times" },
  232. { "tx_collide_7times" },
  233. { "tx_collide_8times" },
  234. { "tx_collide_9times" },
  235. { "tx_collide_10times" },
  236. { "tx_collide_11times" },
  237. { "tx_collide_12times" },
  238. { "tx_collide_13times" },
  239. { "tx_collide_14times" },
  240. { "tx_collide_15times" },
  241. { "tx_ucast_packets" },
  242. { "tx_mcast_packets" },
  243. { "tx_bcast_packets" },
  244. { "tx_carrier_sense_errors" },
  245. { "tx_discards" },
  246. { "tx_errors" },
  247. { "dma_writeq_full" },
  248. { "dma_write_prioq_full" },
  249. { "rxbds_empty" },
  250. { "rx_discards" },
  251. { "rx_errors" },
  252. { "rx_threshold_hit" },
  253. { "dma_readq_full" },
  254. { "dma_read_prioq_full" },
  255. { "tx_comp_queue_full" },
  256. { "ring_set_send_prod_index" },
  257. { "ring_status_update" },
  258. { "nic_irqs" },
  259. { "nic_avoided_irqs" },
  260. { "nic_tx_threshold_hit" }
  261. };
  262. static const struct {
  263. const char string[ETH_GSTRING_LEN];
  264. } ethtool_test_keys[TG3_NUM_TEST] = {
  265. { "nvram test (online) " },
  266. { "link test (online) " },
  267. { "register test (offline)" },
  268. { "memory test (offline)" },
  269. { "loopback test (offline)" },
  270. { "interrupt test (offline)" },
  271. };
  272. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  273. {
  274. writel(val, tp->regs + off);
  275. }
  276. static u32 tg3_read32(struct tg3 *tp, u32 off)
  277. {
  278. return (readl(tp->regs + off));
  279. }
  280. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  281. {
  282. unsigned long flags;
  283. spin_lock_irqsave(&tp->indirect_lock, flags);
  284. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  285. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  286. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  287. }
  288. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  289. {
  290. writel(val, tp->regs + off);
  291. readl(tp->regs + off);
  292. }
  293. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  294. {
  295. unsigned long flags;
  296. u32 val;
  297. spin_lock_irqsave(&tp->indirect_lock, flags);
  298. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  299. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  300. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  301. return val;
  302. }
  303. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  304. {
  305. unsigned long flags;
  306. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  307. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  308. TG3_64BIT_REG_LOW, val);
  309. return;
  310. }
  311. if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
  312. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  313. TG3_64BIT_REG_LOW, val);
  314. return;
  315. }
  316. spin_lock_irqsave(&tp->indirect_lock, flags);
  317. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  318. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  319. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  320. /* In indirect mode when disabling interrupts, we also need
  321. * to clear the interrupt bit in the GRC local ctrl register.
  322. */
  323. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  324. (val == 0x1)) {
  325. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  326. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  327. }
  328. }
  329. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  330. {
  331. unsigned long flags;
  332. u32 val;
  333. spin_lock_irqsave(&tp->indirect_lock, flags);
  334. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  335. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  336. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  337. return val;
  338. }
  339. /* usec_wait specifies the wait time in usec when writing to certain registers
  340. * where it is unsafe to read back the register without some delay.
  341. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  342. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  343. */
  344. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  345. {
  346. if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
  347. (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  348. /* Non-posted methods */
  349. tp->write32(tp, off, val);
  350. else {
  351. /* Posted method */
  352. tg3_write32(tp, off, val);
  353. if (usec_wait)
  354. udelay(usec_wait);
  355. tp->read32(tp, off);
  356. }
  357. /* Wait again after the read for the posted method to guarantee that
  358. * the wait time is met.
  359. */
  360. if (usec_wait)
  361. udelay(usec_wait);
  362. }
  363. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  364. {
  365. tp->write32_mbox(tp, off, val);
  366. if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  367. !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  368. tp->read32_mbox(tp, off);
  369. }
  370. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  371. {
  372. void __iomem *mbox = tp->regs + off;
  373. writel(val, mbox);
  374. if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  375. writel(val, mbox);
  376. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  377. readl(mbox);
  378. }
  379. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  380. {
  381. return (readl(tp->regs + off + GRCMBOX_BASE));
  382. }
  383. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  384. {
  385. writel(val, tp->regs + off + GRCMBOX_BASE);
  386. }
  387. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  388. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  389. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  390. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  391. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  392. #define tw32(reg,val) tp->write32(tp, reg, val)
  393. #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
  394. #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
  395. #define tr32(reg) tp->read32(tp, reg)
  396. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  397. {
  398. unsigned long flags;
  399. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  400. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  401. return;
  402. spin_lock_irqsave(&tp->indirect_lock, flags);
  403. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  404. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  405. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  406. /* Always leave this as zero. */
  407. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  408. } else {
  409. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  410. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  411. /* Always leave this as zero. */
  412. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  413. }
  414. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  415. }
  416. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  417. {
  418. unsigned long flags;
  419. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  420. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  421. *val = 0;
  422. return;
  423. }
  424. spin_lock_irqsave(&tp->indirect_lock, flags);
  425. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  426. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  427. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  428. /* Always leave this as zero. */
  429. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  430. } else {
  431. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  432. *val = tr32(TG3PCI_MEM_WIN_DATA);
  433. /* Always leave this as zero. */
  434. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  435. }
  436. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  437. }
  438. static void tg3_disable_ints(struct tg3 *tp)
  439. {
  440. tw32(TG3PCI_MISC_HOST_CTRL,
  441. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  442. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  443. }
  444. static inline void tg3_cond_int(struct tg3 *tp)
  445. {
  446. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  447. (tp->hw_status->status & SD_STATUS_UPDATED))
  448. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  449. else
  450. tw32(HOSTCC_MODE, tp->coalesce_mode |
  451. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  452. }
  453. static void tg3_enable_ints(struct tg3 *tp)
  454. {
  455. tp->irq_sync = 0;
  456. wmb();
  457. tw32(TG3PCI_MISC_HOST_CTRL,
  458. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  459. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  460. (tp->last_tag << 24));
  461. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  462. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  463. (tp->last_tag << 24));
  464. tg3_cond_int(tp);
  465. }
  466. static inline unsigned int tg3_has_work(struct tg3 *tp)
  467. {
  468. struct tg3_hw_status *sblk = tp->hw_status;
  469. unsigned int work_exists = 0;
  470. /* check for phy events */
  471. if (!(tp->tg3_flags &
  472. (TG3_FLAG_USE_LINKCHG_REG |
  473. TG3_FLAG_POLL_SERDES))) {
  474. if (sblk->status & SD_STATUS_LINK_CHG)
  475. work_exists = 1;
  476. }
  477. /* check for RX/TX work to do */
  478. if (sblk->idx[0].tx_consumer != tp->tx_cons ||
  479. sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  480. work_exists = 1;
  481. return work_exists;
  482. }
  483. /* tg3_restart_ints
  484. * similar to tg3_enable_ints, but it accurately determines whether there
  485. * is new work pending and can return without flushing the PIO write
  486. * which reenables interrupts
  487. */
  488. static void tg3_restart_ints(struct tg3 *tp)
  489. {
  490. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  491. tp->last_tag << 24);
  492. mmiowb();
  493. /* When doing tagged status, this work check is unnecessary.
  494. * The last_tag we write above tells the chip which piece of
  495. * work we've completed.
  496. */
  497. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  498. tg3_has_work(tp))
  499. tw32(HOSTCC_MODE, tp->coalesce_mode |
  500. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  501. }
  502. static inline void tg3_netif_stop(struct tg3 *tp)
  503. {
  504. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  505. netif_poll_disable(tp->dev);
  506. netif_tx_disable(tp->dev);
  507. }
  508. static inline void tg3_netif_start(struct tg3 *tp)
  509. {
  510. netif_wake_queue(tp->dev);
  511. /* NOTE: unconditional netif_wake_queue is only appropriate
  512. * so long as all callers are assured to have free tx slots
  513. * (such as after tg3_init_hw)
  514. */
  515. netif_poll_enable(tp->dev);
  516. tp->hw_status->status |= SD_STATUS_UPDATED;
  517. tg3_enable_ints(tp);
  518. }
  519. static void tg3_switch_clocks(struct tg3 *tp)
  520. {
  521. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  522. u32 orig_clock_ctrl;
  523. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  524. return;
  525. orig_clock_ctrl = clock_ctrl;
  526. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  527. CLOCK_CTRL_CLKRUN_OENABLE |
  528. 0x1f);
  529. tp->pci_clock_ctrl = clock_ctrl;
  530. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  531. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  532. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  533. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  534. }
  535. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  536. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  537. clock_ctrl |
  538. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  539. 40);
  540. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  541. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  542. 40);
  543. }
  544. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  545. }
  546. #define PHY_BUSY_LOOPS 5000
  547. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  548. {
  549. u32 frame_val;
  550. unsigned int loops;
  551. int ret;
  552. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  553. tw32_f(MAC_MI_MODE,
  554. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  555. udelay(80);
  556. }
  557. *val = 0x0;
  558. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  559. MI_COM_PHY_ADDR_MASK);
  560. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  561. MI_COM_REG_ADDR_MASK);
  562. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  563. tw32_f(MAC_MI_COM, frame_val);
  564. loops = PHY_BUSY_LOOPS;
  565. while (loops != 0) {
  566. udelay(10);
  567. frame_val = tr32(MAC_MI_COM);
  568. if ((frame_val & MI_COM_BUSY) == 0) {
  569. udelay(5);
  570. frame_val = tr32(MAC_MI_COM);
  571. break;
  572. }
  573. loops -= 1;
  574. }
  575. ret = -EBUSY;
  576. if (loops != 0) {
  577. *val = frame_val & MI_COM_DATA_MASK;
  578. ret = 0;
  579. }
  580. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  581. tw32_f(MAC_MI_MODE, tp->mi_mode);
  582. udelay(80);
  583. }
  584. return ret;
  585. }
  586. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  587. {
  588. u32 frame_val;
  589. unsigned int loops;
  590. int ret;
  591. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
  592. (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
  593. return 0;
  594. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  595. tw32_f(MAC_MI_MODE,
  596. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  597. udelay(80);
  598. }
  599. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  600. MI_COM_PHY_ADDR_MASK);
  601. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  602. MI_COM_REG_ADDR_MASK);
  603. frame_val |= (val & MI_COM_DATA_MASK);
  604. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  605. tw32_f(MAC_MI_COM, frame_val);
  606. loops = PHY_BUSY_LOOPS;
  607. while (loops != 0) {
  608. udelay(10);
  609. frame_val = tr32(MAC_MI_COM);
  610. if ((frame_val & MI_COM_BUSY) == 0) {
  611. udelay(5);
  612. frame_val = tr32(MAC_MI_COM);
  613. break;
  614. }
  615. loops -= 1;
  616. }
  617. ret = -EBUSY;
  618. if (loops != 0)
  619. ret = 0;
  620. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  621. tw32_f(MAC_MI_MODE, tp->mi_mode);
  622. udelay(80);
  623. }
  624. return ret;
  625. }
  626. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  627. {
  628. u32 val;
  629. if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
  630. return;
  631. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
  632. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
  633. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  634. (val | (1 << 15) | (1 << 4)));
  635. }
  636. static int tg3_bmcr_reset(struct tg3 *tp)
  637. {
  638. u32 phy_control;
  639. int limit, err;
  640. /* OK, reset it, and poll the BMCR_RESET bit until it
  641. * clears or we time out.
  642. */
  643. phy_control = BMCR_RESET;
  644. err = tg3_writephy(tp, MII_BMCR, phy_control);
  645. if (err != 0)
  646. return -EBUSY;
  647. limit = 5000;
  648. while (limit--) {
  649. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  650. if (err != 0)
  651. return -EBUSY;
  652. if ((phy_control & BMCR_RESET) == 0) {
  653. udelay(40);
  654. break;
  655. }
  656. udelay(10);
  657. }
  658. if (limit <= 0)
  659. return -EBUSY;
  660. return 0;
  661. }
  662. static int tg3_wait_macro_done(struct tg3 *tp)
  663. {
  664. int limit = 100;
  665. while (limit--) {
  666. u32 tmp32;
  667. if (!tg3_readphy(tp, 0x16, &tmp32)) {
  668. if ((tmp32 & 0x1000) == 0)
  669. break;
  670. }
  671. }
  672. if (limit <= 0)
  673. return -EBUSY;
  674. return 0;
  675. }
  676. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  677. {
  678. static const u32 test_pat[4][6] = {
  679. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  680. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  681. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  682. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  683. };
  684. int chan;
  685. for (chan = 0; chan < 4; chan++) {
  686. int i;
  687. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  688. (chan * 0x2000) | 0x0200);
  689. tg3_writephy(tp, 0x16, 0x0002);
  690. for (i = 0; i < 6; i++)
  691. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  692. test_pat[chan][i]);
  693. tg3_writephy(tp, 0x16, 0x0202);
  694. if (tg3_wait_macro_done(tp)) {
  695. *resetp = 1;
  696. return -EBUSY;
  697. }
  698. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  699. (chan * 0x2000) | 0x0200);
  700. tg3_writephy(tp, 0x16, 0x0082);
  701. if (tg3_wait_macro_done(tp)) {
  702. *resetp = 1;
  703. return -EBUSY;
  704. }
  705. tg3_writephy(tp, 0x16, 0x0802);
  706. if (tg3_wait_macro_done(tp)) {
  707. *resetp = 1;
  708. return -EBUSY;
  709. }
  710. for (i = 0; i < 6; i += 2) {
  711. u32 low, high;
  712. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  713. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  714. tg3_wait_macro_done(tp)) {
  715. *resetp = 1;
  716. return -EBUSY;
  717. }
  718. low &= 0x7fff;
  719. high &= 0x000f;
  720. if (low != test_pat[chan][i] ||
  721. high != test_pat[chan][i+1]) {
  722. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  723. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  724. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  725. return -EBUSY;
  726. }
  727. }
  728. }
  729. return 0;
  730. }
  731. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  732. {
  733. int chan;
  734. for (chan = 0; chan < 4; chan++) {
  735. int i;
  736. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  737. (chan * 0x2000) | 0x0200);
  738. tg3_writephy(tp, 0x16, 0x0002);
  739. for (i = 0; i < 6; i++)
  740. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  741. tg3_writephy(tp, 0x16, 0x0202);
  742. if (tg3_wait_macro_done(tp))
  743. return -EBUSY;
  744. }
  745. return 0;
  746. }
  747. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  748. {
  749. u32 reg32, phy9_orig;
  750. int retries, do_phy_reset, err;
  751. retries = 10;
  752. do_phy_reset = 1;
  753. do {
  754. if (do_phy_reset) {
  755. err = tg3_bmcr_reset(tp);
  756. if (err)
  757. return err;
  758. do_phy_reset = 0;
  759. }
  760. /* Disable transmitter and interrupt. */
  761. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  762. continue;
  763. reg32 |= 0x3000;
  764. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  765. /* Set full-duplex, 1000 mbps. */
  766. tg3_writephy(tp, MII_BMCR,
  767. BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
  768. /* Set to master mode. */
  769. if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
  770. continue;
  771. tg3_writephy(tp, MII_TG3_CTRL,
  772. (MII_TG3_CTRL_AS_MASTER |
  773. MII_TG3_CTRL_ENABLE_AS_MASTER));
  774. /* Enable SM_DSP_CLOCK and 6dB. */
  775. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  776. /* Block the PHY control access. */
  777. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  778. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
  779. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  780. if (!err)
  781. break;
  782. } while (--retries);
  783. err = tg3_phy_reset_chanpat(tp);
  784. if (err)
  785. return err;
  786. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  787. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
  788. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  789. tg3_writephy(tp, 0x16, 0x0000);
  790. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  791. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  792. /* Set Extended packet length bit for jumbo frames */
  793. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
  794. }
  795. else {
  796. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  797. }
  798. tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
  799. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  800. reg32 &= ~0x3000;
  801. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  802. } else if (!err)
  803. err = -EBUSY;
  804. return err;
  805. }
  806. static void tg3_link_report(struct tg3 *);
  807. /* This will reset the tigon3 PHY if there is no valid
  808. * link unless the FORCE argument is non-zero.
  809. */
  810. static int tg3_phy_reset(struct tg3 *tp)
  811. {
  812. u32 phy_status;
  813. int err;
  814. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  815. u32 val;
  816. val = tr32(GRC_MISC_CFG);
  817. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  818. udelay(40);
  819. }
  820. err = tg3_readphy(tp, MII_BMSR, &phy_status);
  821. err |= tg3_readphy(tp, MII_BMSR, &phy_status);
  822. if (err != 0)
  823. return -EBUSY;
  824. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  825. netif_carrier_off(tp->dev);
  826. tg3_link_report(tp);
  827. }
  828. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  829. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  830. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  831. err = tg3_phy_reset_5703_4_5(tp);
  832. if (err)
  833. return err;
  834. goto out;
  835. }
  836. err = tg3_bmcr_reset(tp);
  837. if (err)
  838. return err;
  839. out:
  840. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
  841. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  842. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  843. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
  844. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  845. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
  846. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  847. }
  848. if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
  849. tg3_writephy(tp, 0x1c, 0x8d68);
  850. tg3_writephy(tp, 0x1c, 0x8d68);
  851. }
  852. if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
  853. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  854. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  855. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
  856. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  857. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
  858. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
  859. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
  860. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  861. }
  862. else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
  863. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  864. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  865. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
  866. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  867. tg3_writephy(tp, MII_TG3_TEST1,
  868. MII_TG3_TEST1_TRIM_EN | 0x4);
  869. } else
  870. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  871. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  872. }
  873. /* Set Extended packet length bit (bit 14) on all chips that */
  874. /* support jumbo frames */
  875. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  876. /* Cannot do read-modify-write on 5401 */
  877. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  878. } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  879. u32 phy_reg;
  880. /* Set bit 14 with read-modify-write to preserve other bits */
  881. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
  882. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
  883. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
  884. }
  885. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  886. * jumbo frames transmission.
  887. */
  888. if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  889. u32 phy_reg;
  890. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
  891. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  892. phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  893. }
  894. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  895. u32 phy_reg;
  896. /* adjust output voltage */
  897. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
  898. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
  899. u32 phy_reg2;
  900. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  901. phy_reg | MII_TG3_EPHY_SHADOW_EN);
  902. /* Enable auto-MDIX */
  903. if (!tg3_readphy(tp, 0x10, &phy_reg2))
  904. tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
  905. tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
  906. }
  907. }
  908. tg3_phy_set_wirespeed(tp);
  909. return 0;
  910. }
  911. static void tg3_frob_aux_power(struct tg3 *tp)
  912. {
  913. struct tg3 *tp_peer = tp;
  914. if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
  915. return;
  916. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  917. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  918. struct net_device *dev_peer;
  919. dev_peer = pci_get_drvdata(tp->pdev_peer);
  920. /* remove_one() may have been run on the peer. */
  921. if (!dev_peer)
  922. tp_peer = tp;
  923. else
  924. tp_peer = netdev_priv(dev_peer);
  925. }
  926. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  927. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  928. (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  929. (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  930. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  931. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  932. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  933. (GRC_LCLCTRL_GPIO_OE0 |
  934. GRC_LCLCTRL_GPIO_OE1 |
  935. GRC_LCLCTRL_GPIO_OE2 |
  936. GRC_LCLCTRL_GPIO_OUTPUT0 |
  937. GRC_LCLCTRL_GPIO_OUTPUT1),
  938. 100);
  939. } else {
  940. u32 no_gpio2;
  941. u32 grc_local_ctrl = 0;
  942. if (tp_peer != tp &&
  943. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  944. return;
  945. /* Workaround to prevent overdrawing Amps. */
  946. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  947. ASIC_REV_5714) {
  948. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  949. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  950. grc_local_ctrl, 100);
  951. }
  952. /* On 5753 and variants, GPIO2 cannot be used. */
  953. no_gpio2 = tp->nic_sram_data_cfg &
  954. NIC_SRAM_DATA_CFG_NO_GPIO2;
  955. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  956. GRC_LCLCTRL_GPIO_OE1 |
  957. GRC_LCLCTRL_GPIO_OE2 |
  958. GRC_LCLCTRL_GPIO_OUTPUT1 |
  959. GRC_LCLCTRL_GPIO_OUTPUT2;
  960. if (no_gpio2) {
  961. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  962. GRC_LCLCTRL_GPIO_OUTPUT2);
  963. }
  964. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  965. grc_local_ctrl, 100);
  966. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  967. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  968. grc_local_ctrl, 100);
  969. if (!no_gpio2) {
  970. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  971. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  972. grc_local_ctrl, 100);
  973. }
  974. }
  975. } else {
  976. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  977. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  978. if (tp_peer != tp &&
  979. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  980. return;
  981. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  982. (GRC_LCLCTRL_GPIO_OE1 |
  983. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  984. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  985. GRC_LCLCTRL_GPIO_OE1, 100);
  986. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  987. (GRC_LCLCTRL_GPIO_OE1 |
  988. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  989. }
  990. }
  991. }
  992. static int tg3_setup_phy(struct tg3 *, int);
  993. #define RESET_KIND_SHUTDOWN 0
  994. #define RESET_KIND_INIT 1
  995. #define RESET_KIND_SUSPEND 2
  996. static void tg3_write_sig_post_reset(struct tg3 *, int);
  997. static int tg3_halt_cpu(struct tg3 *, u32);
  998. static int tg3_nvram_lock(struct tg3 *);
  999. static void tg3_nvram_unlock(struct tg3 *);
  1000. static void tg3_power_down_phy(struct tg3 *tp)
  1001. {
  1002. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  1003. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1004. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  1005. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  1006. sg_dig_ctrl |=
  1007. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  1008. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  1009. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  1010. }
  1011. return;
  1012. }
  1013. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1014. u32 val;
  1015. tg3_bmcr_reset(tp);
  1016. val = tr32(GRC_MISC_CFG);
  1017. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  1018. udelay(40);
  1019. return;
  1020. } else {
  1021. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1022. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  1023. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
  1024. }
  1025. /* The PHY should not be powered down on some chips because
  1026. * of bugs.
  1027. */
  1028. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1029. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1030. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  1031. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  1032. return;
  1033. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  1034. }
  1035. static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  1036. {
  1037. u32 misc_host_ctrl;
  1038. u16 power_control, power_caps;
  1039. int pm = tp->pm_cap;
  1040. /* Make sure register accesses (indirect or otherwise)
  1041. * will function correctly.
  1042. */
  1043. pci_write_config_dword(tp->pdev,
  1044. TG3PCI_MISC_HOST_CTRL,
  1045. tp->misc_host_ctrl);
  1046. pci_read_config_word(tp->pdev,
  1047. pm + PCI_PM_CTRL,
  1048. &power_control);
  1049. power_control |= PCI_PM_CTRL_PME_STATUS;
  1050. power_control &= ~(PCI_PM_CTRL_STATE_MASK);
  1051. switch (state) {
  1052. case PCI_D0:
  1053. power_control |= 0;
  1054. pci_write_config_word(tp->pdev,
  1055. pm + PCI_PM_CTRL,
  1056. power_control);
  1057. udelay(100); /* Delay after power state change */
  1058. /* Switch out of Vaux if it is a NIC */
  1059. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  1060. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
  1061. return 0;
  1062. case PCI_D1:
  1063. power_control |= 1;
  1064. break;
  1065. case PCI_D2:
  1066. power_control |= 2;
  1067. break;
  1068. case PCI_D3hot:
  1069. power_control |= 3;
  1070. break;
  1071. default:
  1072. printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
  1073. "requested.\n",
  1074. tp->dev->name, state);
  1075. return -EINVAL;
  1076. };
  1077. power_control |= PCI_PM_CTRL_PME_ENABLE;
  1078. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  1079. tw32(TG3PCI_MISC_HOST_CTRL,
  1080. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  1081. if (tp->link_config.phy_is_low_power == 0) {
  1082. tp->link_config.phy_is_low_power = 1;
  1083. tp->link_config.orig_speed = tp->link_config.speed;
  1084. tp->link_config.orig_duplex = tp->link_config.duplex;
  1085. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  1086. }
  1087. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  1088. tp->link_config.speed = SPEED_10;
  1089. tp->link_config.duplex = DUPLEX_HALF;
  1090. tp->link_config.autoneg = AUTONEG_ENABLE;
  1091. tg3_setup_phy(tp, 0);
  1092. }
  1093. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1094. u32 val;
  1095. val = tr32(GRC_VCPU_EXT_CTRL);
  1096. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  1097. } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1098. int i;
  1099. u32 val;
  1100. for (i = 0; i < 200; i++) {
  1101. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  1102. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1103. break;
  1104. msleep(1);
  1105. }
  1106. }
  1107. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  1108. WOL_DRV_STATE_SHUTDOWN |
  1109. WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
  1110. pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
  1111. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
  1112. u32 mac_mode;
  1113. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  1114. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
  1115. udelay(40);
  1116. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  1117. mac_mode = MAC_MODE_PORT_MODE_GMII;
  1118. else
  1119. mac_mode = MAC_MODE_PORT_MODE_MII;
  1120. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
  1121. !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
  1122. mac_mode |= MAC_MODE_LINK_POLARITY;
  1123. } else {
  1124. mac_mode = MAC_MODE_PORT_MODE_TBI;
  1125. }
  1126. if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  1127. tw32(MAC_LED_CTRL, tp->led_ctrl);
  1128. if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
  1129. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
  1130. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  1131. tw32_f(MAC_MODE, mac_mode);
  1132. udelay(100);
  1133. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  1134. udelay(10);
  1135. }
  1136. if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
  1137. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1138. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  1139. u32 base_val;
  1140. base_val = tp->pci_clock_ctrl;
  1141. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  1142. CLOCK_CTRL_TXCLK_DISABLE);
  1143. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  1144. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  1145. } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1146. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
  1147. /* do nothing */
  1148. } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1149. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
  1150. u32 newbits1, newbits2;
  1151. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1152. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1153. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  1154. CLOCK_CTRL_TXCLK_DISABLE |
  1155. CLOCK_CTRL_ALTCLK);
  1156. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1157. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  1158. newbits1 = CLOCK_CTRL_625_CORE;
  1159. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  1160. } else {
  1161. newbits1 = CLOCK_CTRL_ALTCLK;
  1162. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1163. }
  1164. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  1165. 40);
  1166. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  1167. 40);
  1168. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  1169. u32 newbits3;
  1170. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1171. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1172. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  1173. CLOCK_CTRL_TXCLK_DISABLE |
  1174. CLOCK_CTRL_44MHZ_CORE);
  1175. } else {
  1176. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  1177. }
  1178. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  1179. tp->pci_clock_ctrl | newbits3, 40);
  1180. }
  1181. }
  1182. if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
  1183. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  1184. tg3_power_down_phy(tp);
  1185. tg3_frob_aux_power(tp);
  1186. /* Workaround for unstable PLL clock */
  1187. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  1188. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  1189. u32 val = tr32(0x7d00);
  1190. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  1191. tw32(0x7d00, val);
  1192. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1193. int err;
  1194. err = tg3_nvram_lock(tp);
  1195. tg3_halt_cpu(tp, RX_CPU_BASE);
  1196. if (!err)
  1197. tg3_nvram_unlock(tp);
  1198. }
  1199. }
  1200. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  1201. /* Finally, set the new power state. */
  1202. pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
  1203. udelay(100); /* Delay after power state change */
  1204. return 0;
  1205. }
  1206. static void tg3_link_report(struct tg3 *tp)
  1207. {
  1208. if (!netif_carrier_ok(tp->dev)) {
  1209. if (netif_msg_link(tp))
  1210. printk(KERN_INFO PFX "%s: Link is down.\n",
  1211. tp->dev->name);
  1212. } else if (netif_msg_link(tp)) {
  1213. printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
  1214. tp->dev->name,
  1215. (tp->link_config.active_speed == SPEED_1000 ?
  1216. 1000 :
  1217. (tp->link_config.active_speed == SPEED_100 ?
  1218. 100 : 10)),
  1219. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1220. "full" : "half"));
  1221. printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
  1222. "%s for RX.\n",
  1223. tp->dev->name,
  1224. (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
  1225. (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
  1226. }
  1227. }
  1228. static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
  1229. {
  1230. u32 new_tg3_flags = 0;
  1231. u32 old_rx_mode = tp->rx_mode;
  1232. u32 old_tx_mode = tp->tx_mode;
  1233. if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
  1234. /* Convert 1000BaseX flow control bits to 1000BaseT
  1235. * bits before resolving flow control.
  1236. */
  1237. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  1238. local_adv &= ~(ADVERTISE_PAUSE_CAP |
  1239. ADVERTISE_PAUSE_ASYM);
  1240. remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  1241. if (local_adv & ADVERTISE_1000XPAUSE)
  1242. local_adv |= ADVERTISE_PAUSE_CAP;
  1243. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  1244. local_adv |= ADVERTISE_PAUSE_ASYM;
  1245. if (remote_adv & LPA_1000XPAUSE)
  1246. remote_adv |= LPA_PAUSE_CAP;
  1247. if (remote_adv & LPA_1000XPAUSE_ASYM)
  1248. remote_adv |= LPA_PAUSE_ASYM;
  1249. }
  1250. if (local_adv & ADVERTISE_PAUSE_CAP) {
  1251. if (local_adv & ADVERTISE_PAUSE_ASYM) {
  1252. if (remote_adv & LPA_PAUSE_CAP)
  1253. new_tg3_flags |=
  1254. (TG3_FLAG_RX_PAUSE |
  1255. TG3_FLAG_TX_PAUSE);
  1256. else if (remote_adv & LPA_PAUSE_ASYM)
  1257. new_tg3_flags |=
  1258. (TG3_FLAG_RX_PAUSE);
  1259. } else {
  1260. if (remote_adv & LPA_PAUSE_CAP)
  1261. new_tg3_flags |=
  1262. (TG3_FLAG_RX_PAUSE |
  1263. TG3_FLAG_TX_PAUSE);
  1264. }
  1265. } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  1266. if ((remote_adv & LPA_PAUSE_CAP) &&
  1267. (remote_adv & LPA_PAUSE_ASYM))
  1268. new_tg3_flags |= TG3_FLAG_TX_PAUSE;
  1269. }
  1270. tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
  1271. tp->tg3_flags |= new_tg3_flags;
  1272. } else {
  1273. new_tg3_flags = tp->tg3_flags;
  1274. }
  1275. if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
  1276. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1277. else
  1278. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1279. if (old_rx_mode != tp->rx_mode) {
  1280. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1281. }
  1282. if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
  1283. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1284. else
  1285. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1286. if (old_tx_mode != tp->tx_mode) {
  1287. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1288. }
  1289. }
  1290. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  1291. {
  1292. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  1293. case MII_TG3_AUX_STAT_10HALF:
  1294. *speed = SPEED_10;
  1295. *duplex = DUPLEX_HALF;
  1296. break;
  1297. case MII_TG3_AUX_STAT_10FULL:
  1298. *speed = SPEED_10;
  1299. *duplex = DUPLEX_FULL;
  1300. break;
  1301. case MII_TG3_AUX_STAT_100HALF:
  1302. *speed = SPEED_100;
  1303. *duplex = DUPLEX_HALF;
  1304. break;
  1305. case MII_TG3_AUX_STAT_100FULL:
  1306. *speed = SPEED_100;
  1307. *duplex = DUPLEX_FULL;
  1308. break;
  1309. case MII_TG3_AUX_STAT_1000HALF:
  1310. *speed = SPEED_1000;
  1311. *duplex = DUPLEX_HALF;
  1312. break;
  1313. case MII_TG3_AUX_STAT_1000FULL:
  1314. *speed = SPEED_1000;
  1315. *duplex = DUPLEX_FULL;
  1316. break;
  1317. default:
  1318. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1319. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  1320. SPEED_10;
  1321. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  1322. DUPLEX_HALF;
  1323. break;
  1324. }
  1325. *speed = SPEED_INVALID;
  1326. *duplex = DUPLEX_INVALID;
  1327. break;
  1328. };
  1329. }
  1330. static void tg3_phy_copper_begin(struct tg3 *tp)
  1331. {
  1332. u32 new_adv;
  1333. int i;
  1334. if (tp->link_config.phy_is_low_power) {
  1335. /* Entering low power mode. Disable gigabit and
  1336. * 100baseT advertisements.
  1337. */
  1338. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1339. new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  1340. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1341. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  1342. new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
  1343. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1344. } else if (tp->link_config.speed == SPEED_INVALID) {
  1345. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  1346. tp->link_config.advertising &=
  1347. ~(ADVERTISED_1000baseT_Half |
  1348. ADVERTISED_1000baseT_Full);
  1349. new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1350. if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
  1351. new_adv |= ADVERTISE_10HALF;
  1352. if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
  1353. new_adv |= ADVERTISE_10FULL;
  1354. if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
  1355. new_adv |= ADVERTISE_100HALF;
  1356. if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
  1357. new_adv |= ADVERTISE_100FULL;
  1358. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1359. if (tp->link_config.advertising &
  1360. (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
  1361. new_adv = 0;
  1362. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  1363. new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
  1364. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  1365. new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
  1366. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  1367. (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1368. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
  1369. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1370. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1371. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1372. } else {
  1373. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1374. }
  1375. } else {
  1376. /* Asking for a specific link mode. */
  1377. if (tp->link_config.speed == SPEED_1000) {
  1378. new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1379. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1380. if (tp->link_config.duplex == DUPLEX_FULL)
  1381. new_adv = MII_TG3_CTRL_ADV_1000_FULL;
  1382. else
  1383. new_adv = MII_TG3_CTRL_ADV_1000_HALF;
  1384. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1385. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  1386. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1387. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1388. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1389. } else {
  1390. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1391. new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1392. if (tp->link_config.speed == SPEED_100) {
  1393. if (tp->link_config.duplex == DUPLEX_FULL)
  1394. new_adv |= ADVERTISE_100FULL;
  1395. else
  1396. new_adv |= ADVERTISE_100HALF;
  1397. } else {
  1398. if (tp->link_config.duplex == DUPLEX_FULL)
  1399. new_adv |= ADVERTISE_10FULL;
  1400. else
  1401. new_adv |= ADVERTISE_10HALF;
  1402. }
  1403. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1404. }
  1405. }
  1406. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  1407. tp->link_config.speed != SPEED_INVALID) {
  1408. u32 bmcr, orig_bmcr;
  1409. tp->link_config.active_speed = tp->link_config.speed;
  1410. tp->link_config.active_duplex = tp->link_config.duplex;
  1411. bmcr = 0;
  1412. switch (tp->link_config.speed) {
  1413. default:
  1414. case SPEED_10:
  1415. break;
  1416. case SPEED_100:
  1417. bmcr |= BMCR_SPEED100;
  1418. break;
  1419. case SPEED_1000:
  1420. bmcr |= TG3_BMCR_SPEED1000;
  1421. break;
  1422. };
  1423. if (tp->link_config.duplex == DUPLEX_FULL)
  1424. bmcr |= BMCR_FULLDPLX;
  1425. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  1426. (bmcr != orig_bmcr)) {
  1427. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  1428. for (i = 0; i < 1500; i++) {
  1429. u32 tmp;
  1430. udelay(10);
  1431. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  1432. tg3_readphy(tp, MII_BMSR, &tmp))
  1433. continue;
  1434. if (!(tmp & BMSR_LSTATUS)) {
  1435. udelay(40);
  1436. break;
  1437. }
  1438. }
  1439. tg3_writephy(tp, MII_BMCR, bmcr);
  1440. udelay(40);
  1441. }
  1442. } else {
  1443. tg3_writephy(tp, MII_BMCR,
  1444. BMCR_ANENABLE | BMCR_ANRESTART);
  1445. }
  1446. }
  1447. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  1448. {
  1449. int err;
  1450. /* Turn off tap power management. */
  1451. /* Set Extended packet length bit */
  1452. err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1453. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
  1454. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
  1455. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
  1456. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
  1457. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1458. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
  1459. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1460. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
  1461. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1462. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
  1463. udelay(40);
  1464. return err;
  1465. }
  1466. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  1467. {
  1468. u32 adv_reg, all_mask = 0;
  1469. if (mask & ADVERTISED_10baseT_Half)
  1470. all_mask |= ADVERTISE_10HALF;
  1471. if (mask & ADVERTISED_10baseT_Full)
  1472. all_mask |= ADVERTISE_10FULL;
  1473. if (mask & ADVERTISED_100baseT_Half)
  1474. all_mask |= ADVERTISE_100HALF;
  1475. if (mask & ADVERTISED_100baseT_Full)
  1476. all_mask |= ADVERTISE_100FULL;
  1477. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  1478. return 0;
  1479. if ((adv_reg & all_mask) != all_mask)
  1480. return 0;
  1481. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  1482. u32 tg3_ctrl;
  1483. all_mask = 0;
  1484. if (mask & ADVERTISED_1000baseT_Half)
  1485. all_mask |= ADVERTISE_1000HALF;
  1486. if (mask & ADVERTISED_1000baseT_Full)
  1487. all_mask |= ADVERTISE_1000FULL;
  1488. if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
  1489. return 0;
  1490. if ((tg3_ctrl & all_mask) != all_mask)
  1491. return 0;
  1492. }
  1493. return 1;
  1494. }
  1495. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  1496. {
  1497. int current_link_up;
  1498. u32 bmsr, dummy;
  1499. u16 current_speed;
  1500. u8 current_duplex;
  1501. int i, err;
  1502. tw32(MAC_EVENT, 0);
  1503. tw32_f(MAC_STATUS,
  1504. (MAC_STATUS_SYNC_CHANGED |
  1505. MAC_STATUS_CFG_CHANGED |
  1506. MAC_STATUS_MI_COMPLETION |
  1507. MAC_STATUS_LNKSTATE_CHANGED));
  1508. udelay(40);
  1509. tp->mi_mode = MAC_MI_MODE_BASE;
  1510. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1511. udelay(80);
  1512. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
  1513. /* Some third-party PHYs need to be reset on link going
  1514. * down.
  1515. */
  1516. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1517. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1518. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  1519. netif_carrier_ok(tp->dev)) {
  1520. tg3_readphy(tp, MII_BMSR, &bmsr);
  1521. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1522. !(bmsr & BMSR_LSTATUS))
  1523. force_reset = 1;
  1524. }
  1525. if (force_reset)
  1526. tg3_phy_reset(tp);
  1527. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  1528. tg3_readphy(tp, MII_BMSR, &bmsr);
  1529. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  1530. !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
  1531. bmsr = 0;
  1532. if (!(bmsr & BMSR_LSTATUS)) {
  1533. err = tg3_init_5401phy_dsp(tp);
  1534. if (err)
  1535. return err;
  1536. tg3_readphy(tp, MII_BMSR, &bmsr);
  1537. for (i = 0; i < 1000; i++) {
  1538. udelay(10);
  1539. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1540. (bmsr & BMSR_LSTATUS)) {
  1541. udelay(40);
  1542. break;
  1543. }
  1544. }
  1545. if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
  1546. !(bmsr & BMSR_LSTATUS) &&
  1547. tp->link_config.active_speed == SPEED_1000) {
  1548. err = tg3_phy_reset(tp);
  1549. if (!err)
  1550. err = tg3_init_5401phy_dsp(tp);
  1551. if (err)
  1552. return err;
  1553. }
  1554. }
  1555. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1556. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  1557. /* 5701 {A0,B0} CRC bug workaround */
  1558. tg3_writephy(tp, 0x15, 0x0a75);
  1559. tg3_writephy(tp, 0x1c, 0x8c68);
  1560. tg3_writephy(tp, 0x1c, 0x8d68);
  1561. tg3_writephy(tp, 0x1c, 0x8c68);
  1562. }
  1563. /* Clear pending interrupts... */
  1564. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1565. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1566. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
  1567. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  1568. else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  1569. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  1570. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1571. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1572. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  1573. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1574. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  1575. else
  1576. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  1577. }
  1578. current_link_up = 0;
  1579. current_speed = SPEED_INVALID;
  1580. current_duplex = DUPLEX_INVALID;
  1581. if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
  1582. u32 val;
  1583. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
  1584. tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  1585. if (!(val & (1 << 10))) {
  1586. val |= (1 << 10);
  1587. tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
  1588. goto relink;
  1589. }
  1590. }
  1591. bmsr = 0;
  1592. for (i = 0; i < 100; i++) {
  1593. tg3_readphy(tp, MII_BMSR, &bmsr);
  1594. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1595. (bmsr & BMSR_LSTATUS))
  1596. break;
  1597. udelay(40);
  1598. }
  1599. if (bmsr & BMSR_LSTATUS) {
  1600. u32 aux_stat, bmcr;
  1601. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  1602. for (i = 0; i < 2000; i++) {
  1603. udelay(10);
  1604. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  1605. aux_stat)
  1606. break;
  1607. }
  1608. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  1609. &current_speed,
  1610. &current_duplex);
  1611. bmcr = 0;
  1612. for (i = 0; i < 200; i++) {
  1613. tg3_readphy(tp, MII_BMCR, &bmcr);
  1614. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  1615. continue;
  1616. if (bmcr && bmcr != 0x7fff)
  1617. break;
  1618. udelay(10);
  1619. }
  1620. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  1621. if (bmcr & BMCR_ANENABLE) {
  1622. current_link_up = 1;
  1623. /* Force autoneg restart if we are exiting
  1624. * low power mode.
  1625. */
  1626. if (!tg3_copper_is_advertising_all(tp,
  1627. tp->link_config.advertising))
  1628. current_link_up = 0;
  1629. } else {
  1630. current_link_up = 0;
  1631. }
  1632. } else {
  1633. if (!(bmcr & BMCR_ANENABLE) &&
  1634. tp->link_config.speed == current_speed &&
  1635. tp->link_config.duplex == current_duplex) {
  1636. current_link_up = 1;
  1637. } else {
  1638. current_link_up = 0;
  1639. }
  1640. }
  1641. tp->link_config.active_speed = current_speed;
  1642. tp->link_config.active_duplex = current_duplex;
  1643. }
  1644. if (current_link_up == 1 &&
  1645. (tp->link_config.active_duplex == DUPLEX_FULL) &&
  1646. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  1647. u32 local_adv, remote_adv;
  1648. if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
  1649. local_adv = 0;
  1650. local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  1651. if (tg3_readphy(tp, MII_LPA, &remote_adv))
  1652. remote_adv = 0;
  1653. remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  1654. /* If we are not advertising full pause capability,
  1655. * something is wrong. Bring the link down and reconfigure.
  1656. */
  1657. if (local_adv != ADVERTISE_PAUSE_CAP) {
  1658. current_link_up = 0;
  1659. } else {
  1660. tg3_setup_flow_control(tp, local_adv, remote_adv);
  1661. }
  1662. }
  1663. relink:
  1664. if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
  1665. u32 tmp;
  1666. tg3_phy_copper_begin(tp);
  1667. tg3_readphy(tp, MII_BMSR, &tmp);
  1668. if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  1669. (tmp & BMSR_LSTATUS))
  1670. current_link_up = 1;
  1671. }
  1672. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  1673. if (current_link_up == 1) {
  1674. if (tp->link_config.active_speed == SPEED_100 ||
  1675. tp->link_config.active_speed == SPEED_10)
  1676. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  1677. else
  1678. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1679. } else
  1680. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1681. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  1682. if (tp->link_config.active_duplex == DUPLEX_HALF)
  1683. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  1684. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1685. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  1686. if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
  1687. (current_link_up == 1 &&
  1688. tp->link_config.active_speed == SPEED_10))
  1689. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  1690. } else {
  1691. if (current_link_up == 1)
  1692. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  1693. }
  1694. /* ??? Without this setting Netgear GA302T PHY does not
  1695. * ??? send/receive packets...
  1696. */
  1697. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
  1698. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  1699. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  1700. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1701. udelay(80);
  1702. }
  1703. tw32_f(MAC_MODE, tp->mac_mode);
  1704. udelay(40);
  1705. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  1706. /* Polled via timer. */
  1707. tw32_f(MAC_EVENT, 0);
  1708. } else {
  1709. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  1710. }
  1711. udelay(40);
  1712. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  1713. current_link_up == 1 &&
  1714. tp->link_config.active_speed == SPEED_1000 &&
  1715. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  1716. (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  1717. udelay(120);
  1718. tw32_f(MAC_STATUS,
  1719. (MAC_STATUS_SYNC_CHANGED |
  1720. MAC_STATUS_CFG_CHANGED));
  1721. udelay(40);
  1722. tg3_write_mem(tp,
  1723. NIC_SRAM_FIRMWARE_MBOX,
  1724. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  1725. }
  1726. if (current_link_up != netif_carrier_ok(tp->dev)) {
  1727. if (current_link_up)
  1728. netif_carrier_on(tp->dev);
  1729. else
  1730. netif_carrier_off(tp->dev);
  1731. tg3_link_report(tp);
  1732. }
  1733. return 0;
  1734. }
  1735. struct tg3_fiber_aneginfo {
  1736. int state;
  1737. #define ANEG_STATE_UNKNOWN 0
  1738. #define ANEG_STATE_AN_ENABLE 1
  1739. #define ANEG_STATE_RESTART_INIT 2
  1740. #define ANEG_STATE_RESTART 3
  1741. #define ANEG_STATE_DISABLE_LINK_OK 4
  1742. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  1743. #define ANEG_STATE_ABILITY_DETECT 6
  1744. #define ANEG_STATE_ACK_DETECT_INIT 7
  1745. #define ANEG_STATE_ACK_DETECT 8
  1746. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  1747. #define ANEG_STATE_COMPLETE_ACK 10
  1748. #define ANEG_STATE_IDLE_DETECT_INIT 11
  1749. #define ANEG_STATE_IDLE_DETECT 12
  1750. #define ANEG_STATE_LINK_OK 13
  1751. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  1752. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  1753. u32 flags;
  1754. #define MR_AN_ENABLE 0x00000001
  1755. #define MR_RESTART_AN 0x00000002
  1756. #define MR_AN_COMPLETE 0x00000004
  1757. #define MR_PAGE_RX 0x00000008
  1758. #define MR_NP_LOADED 0x00000010
  1759. #define MR_TOGGLE_TX 0x00000020
  1760. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  1761. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  1762. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  1763. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  1764. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  1765. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  1766. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  1767. #define MR_TOGGLE_RX 0x00002000
  1768. #define MR_NP_RX 0x00004000
  1769. #define MR_LINK_OK 0x80000000
  1770. unsigned long link_time, cur_time;
  1771. u32 ability_match_cfg;
  1772. int ability_match_count;
  1773. char ability_match, idle_match, ack_match;
  1774. u32 txconfig, rxconfig;
  1775. #define ANEG_CFG_NP 0x00000080
  1776. #define ANEG_CFG_ACK 0x00000040
  1777. #define ANEG_CFG_RF2 0x00000020
  1778. #define ANEG_CFG_RF1 0x00000010
  1779. #define ANEG_CFG_PS2 0x00000001
  1780. #define ANEG_CFG_PS1 0x00008000
  1781. #define ANEG_CFG_HD 0x00004000
  1782. #define ANEG_CFG_FD 0x00002000
  1783. #define ANEG_CFG_INVAL 0x00001f06
  1784. };
  1785. #define ANEG_OK 0
  1786. #define ANEG_DONE 1
  1787. #define ANEG_TIMER_ENAB 2
  1788. #define ANEG_FAILED -1
  1789. #define ANEG_STATE_SETTLE_TIME 10000
  1790. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  1791. struct tg3_fiber_aneginfo *ap)
  1792. {
  1793. unsigned long delta;
  1794. u32 rx_cfg_reg;
  1795. int ret;
  1796. if (ap->state == ANEG_STATE_UNKNOWN) {
  1797. ap->rxconfig = 0;
  1798. ap->link_time = 0;
  1799. ap->cur_time = 0;
  1800. ap->ability_match_cfg = 0;
  1801. ap->ability_match_count = 0;
  1802. ap->ability_match = 0;
  1803. ap->idle_match = 0;
  1804. ap->ack_match = 0;
  1805. }
  1806. ap->cur_time++;
  1807. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  1808. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  1809. if (rx_cfg_reg != ap->ability_match_cfg) {
  1810. ap->ability_match_cfg = rx_cfg_reg;
  1811. ap->ability_match = 0;
  1812. ap->ability_match_count = 0;
  1813. } else {
  1814. if (++ap->ability_match_count > 1) {
  1815. ap->ability_match = 1;
  1816. ap->ability_match_cfg = rx_cfg_reg;
  1817. }
  1818. }
  1819. if (rx_cfg_reg & ANEG_CFG_ACK)
  1820. ap->ack_match = 1;
  1821. else
  1822. ap->ack_match = 0;
  1823. ap->idle_match = 0;
  1824. } else {
  1825. ap->idle_match = 1;
  1826. ap->ability_match_cfg = 0;
  1827. ap->ability_match_count = 0;
  1828. ap->ability_match = 0;
  1829. ap->ack_match = 0;
  1830. rx_cfg_reg = 0;
  1831. }
  1832. ap->rxconfig = rx_cfg_reg;
  1833. ret = ANEG_OK;
  1834. switch(ap->state) {
  1835. case ANEG_STATE_UNKNOWN:
  1836. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  1837. ap->state = ANEG_STATE_AN_ENABLE;
  1838. /* fallthru */
  1839. case ANEG_STATE_AN_ENABLE:
  1840. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  1841. if (ap->flags & MR_AN_ENABLE) {
  1842. ap->link_time = 0;
  1843. ap->cur_time = 0;
  1844. ap->ability_match_cfg = 0;
  1845. ap->ability_match_count = 0;
  1846. ap->ability_match = 0;
  1847. ap->idle_match = 0;
  1848. ap->ack_match = 0;
  1849. ap->state = ANEG_STATE_RESTART_INIT;
  1850. } else {
  1851. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  1852. }
  1853. break;
  1854. case ANEG_STATE_RESTART_INIT:
  1855. ap->link_time = ap->cur_time;
  1856. ap->flags &= ~(MR_NP_LOADED);
  1857. ap->txconfig = 0;
  1858. tw32(MAC_TX_AUTO_NEG, 0);
  1859. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1860. tw32_f(MAC_MODE, tp->mac_mode);
  1861. udelay(40);
  1862. ret = ANEG_TIMER_ENAB;
  1863. ap->state = ANEG_STATE_RESTART;
  1864. /* fallthru */
  1865. case ANEG_STATE_RESTART:
  1866. delta = ap->cur_time - ap->link_time;
  1867. if (delta > ANEG_STATE_SETTLE_TIME) {
  1868. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  1869. } else {
  1870. ret = ANEG_TIMER_ENAB;
  1871. }
  1872. break;
  1873. case ANEG_STATE_DISABLE_LINK_OK:
  1874. ret = ANEG_DONE;
  1875. break;
  1876. case ANEG_STATE_ABILITY_DETECT_INIT:
  1877. ap->flags &= ~(MR_TOGGLE_TX);
  1878. ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
  1879. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  1880. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1881. tw32_f(MAC_MODE, tp->mac_mode);
  1882. udelay(40);
  1883. ap->state = ANEG_STATE_ABILITY_DETECT;
  1884. break;
  1885. case ANEG_STATE_ABILITY_DETECT:
  1886. if (ap->ability_match != 0 && ap->rxconfig != 0) {
  1887. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  1888. }
  1889. break;
  1890. case ANEG_STATE_ACK_DETECT_INIT:
  1891. ap->txconfig |= ANEG_CFG_ACK;
  1892. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  1893. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1894. tw32_f(MAC_MODE, tp->mac_mode);
  1895. udelay(40);
  1896. ap->state = ANEG_STATE_ACK_DETECT;
  1897. /* fallthru */
  1898. case ANEG_STATE_ACK_DETECT:
  1899. if (ap->ack_match != 0) {
  1900. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  1901. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  1902. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  1903. } else {
  1904. ap->state = ANEG_STATE_AN_ENABLE;
  1905. }
  1906. } else if (ap->ability_match != 0 &&
  1907. ap->rxconfig == 0) {
  1908. ap->state = ANEG_STATE_AN_ENABLE;
  1909. }
  1910. break;
  1911. case ANEG_STATE_COMPLETE_ACK_INIT:
  1912. if (ap->rxconfig & ANEG_CFG_INVAL) {
  1913. ret = ANEG_FAILED;
  1914. break;
  1915. }
  1916. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  1917. MR_LP_ADV_HALF_DUPLEX |
  1918. MR_LP_ADV_SYM_PAUSE |
  1919. MR_LP_ADV_ASYM_PAUSE |
  1920. MR_LP_ADV_REMOTE_FAULT1 |
  1921. MR_LP_ADV_REMOTE_FAULT2 |
  1922. MR_LP_ADV_NEXT_PAGE |
  1923. MR_TOGGLE_RX |
  1924. MR_NP_RX);
  1925. if (ap->rxconfig & ANEG_CFG_FD)
  1926. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  1927. if (ap->rxconfig & ANEG_CFG_HD)
  1928. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  1929. if (ap->rxconfig & ANEG_CFG_PS1)
  1930. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  1931. if (ap->rxconfig & ANEG_CFG_PS2)
  1932. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  1933. if (ap->rxconfig & ANEG_CFG_RF1)
  1934. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  1935. if (ap->rxconfig & ANEG_CFG_RF2)
  1936. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  1937. if (ap->rxconfig & ANEG_CFG_NP)
  1938. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  1939. ap->link_time = ap->cur_time;
  1940. ap->flags ^= (MR_TOGGLE_TX);
  1941. if (ap->rxconfig & 0x0008)
  1942. ap->flags |= MR_TOGGLE_RX;
  1943. if (ap->rxconfig & ANEG_CFG_NP)
  1944. ap->flags |= MR_NP_RX;
  1945. ap->flags |= MR_PAGE_RX;
  1946. ap->state = ANEG_STATE_COMPLETE_ACK;
  1947. ret = ANEG_TIMER_ENAB;
  1948. break;
  1949. case ANEG_STATE_COMPLETE_ACK:
  1950. if (ap->ability_match != 0 &&
  1951. ap->rxconfig == 0) {
  1952. ap->state = ANEG_STATE_AN_ENABLE;
  1953. break;
  1954. }
  1955. delta = ap->cur_time - ap->link_time;
  1956. if (delta > ANEG_STATE_SETTLE_TIME) {
  1957. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  1958. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  1959. } else {
  1960. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  1961. !(ap->flags & MR_NP_RX)) {
  1962. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  1963. } else {
  1964. ret = ANEG_FAILED;
  1965. }
  1966. }
  1967. }
  1968. break;
  1969. case ANEG_STATE_IDLE_DETECT_INIT:
  1970. ap->link_time = ap->cur_time;
  1971. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  1972. tw32_f(MAC_MODE, tp->mac_mode);
  1973. udelay(40);
  1974. ap->state = ANEG_STATE_IDLE_DETECT;
  1975. ret = ANEG_TIMER_ENAB;
  1976. break;
  1977. case ANEG_STATE_IDLE_DETECT:
  1978. if (ap->ability_match != 0 &&
  1979. ap->rxconfig == 0) {
  1980. ap->state = ANEG_STATE_AN_ENABLE;
  1981. break;
  1982. }
  1983. delta = ap->cur_time - ap->link_time;
  1984. if (delta > ANEG_STATE_SETTLE_TIME) {
  1985. /* XXX another gem from the Broadcom driver :( */
  1986. ap->state = ANEG_STATE_LINK_OK;
  1987. }
  1988. break;
  1989. case ANEG_STATE_LINK_OK:
  1990. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  1991. ret = ANEG_DONE;
  1992. break;
  1993. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  1994. /* ??? unimplemented */
  1995. break;
  1996. case ANEG_STATE_NEXT_PAGE_WAIT:
  1997. /* ??? unimplemented */
  1998. break;
  1999. default:
  2000. ret = ANEG_FAILED;
  2001. break;
  2002. };
  2003. return ret;
  2004. }
  2005. static int fiber_autoneg(struct tg3 *tp, u32 *flags)
  2006. {
  2007. int res = 0;
  2008. struct tg3_fiber_aneginfo aninfo;
  2009. int status = ANEG_FAILED;
  2010. unsigned int tick;
  2011. u32 tmp;
  2012. tw32_f(MAC_TX_AUTO_NEG, 0);
  2013. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  2014. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  2015. udelay(40);
  2016. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  2017. udelay(40);
  2018. memset(&aninfo, 0, sizeof(aninfo));
  2019. aninfo.flags |= MR_AN_ENABLE;
  2020. aninfo.state = ANEG_STATE_UNKNOWN;
  2021. aninfo.cur_time = 0;
  2022. tick = 0;
  2023. while (++tick < 195000) {
  2024. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  2025. if (status == ANEG_DONE || status == ANEG_FAILED)
  2026. break;
  2027. udelay(1);
  2028. }
  2029. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2030. tw32_f(MAC_MODE, tp->mac_mode);
  2031. udelay(40);
  2032. *flags = aninfo.flags;
  2033. if (status == ANEG_DONE &&
  2034. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  2035. MR_LP_ADV_FULL_DUPLEX)))
  2036. res = 1;
  2037. return res;
  2038. }
  2039. static void tg3_init_bcm8002(struct tg3 *tp)
  2040. {
  2041. u32 mac_status = tr32(MAC_STATUS);
  2042. int i;
  2043. /* Reset when initting first time or we have a link. */
  2044. if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
  2045. !(mac_status & MAC_STATUS_PCS_SYNCED))
  2046. return;
  2047. /* Set PLL lock range. */
  2048. tg3_writephy(tp, 0x16, 0x8007);
  2049. /* SW reset */
  2050. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  2051. /* Wait for reset to complete. */
  2052. /* XXX schedule_timeout() ... */
  2053. for (i = 0; i < 500; i++)
  2054. udelay(10);
  2055. /* Config mode; select PMA/Ch 1 regs. */
  2056. tg3_writephy(tp, 0x10, 0x8411);
  2057. /* Enable auto-lock and comdet, select txclk for tx. */
  2058. tg3_writephy(tp, 0x11, 0x0a10);
  2059. tg3_writephy(tp, 0x18, 0x00a0);
  2060. tg3_writephy(tp, 0x16, 0x41ff);
  2061. /* Assert and deassert POR. */
  2062. tg3_writephy(tp, 0x13, 0x0400);
  2063. udelay(40);
  2064. tg3_writephy(tp, 0x13, 0x0000);
  2065. tg3_writephy(tp, 0x11, 0x0a50);
  2066. udelay(40);
  2067. tg3_writephy(tp, 0x11, 0x0a10);
  2068. /* Wait for signal to stabilize */
  2069. /* XXX schedule_timeout() ... */
  2070. for (i = 0; i < 15000; i++)
  2071. udelay(10);
  2072. /* Deselect the channel register so we can read the PHYID
  2073. * later.
  2074. */
  2075. tg3_writephy(tp, 0x10, 0x8011);
  2076. }
  2077. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  2078. {
  2079. u32 sg_dig_ctrl, sg_dig_status;
  2080. u32 serdes_cfg, expected_sg_dig_ctrl;
  2081. int workaround, port_a;
  2082. int current_link_up;
  2083. serdes_cfg = 0;
  2084. expected_sg_dig_ctrl = 0;
  2085. workaround = 0;
  2086. port_a = 1;
  2087. current_link_up = 0;
  2088. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  2089. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  2090. workaround = 1;
  2091. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  2092. port_a = 0;
  2093. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  2094. /* preserve bits 20-23 for voltage regulator */
  2095. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  2096. }
  2097. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2098. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  2099. if (sg_dig_ctrl & (1 << 31)) {
  2100. if (workaround) {
  2101. u32 val = serdes_cfg;
  2102. if (port_a)
  2103. val |= 0xc010000;
  2104. else
  2105. val |= 0x4010000;
  2106. tw32_f(MAC_SERDES_CFG, val);
  2107. }
  2108. tw32_f(SG_DIG_CTRL, 0x01388400);
  2109. }
  2110. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  2111. tg3_setup_flow_control(tp, 0, 0);
  2112. current_link_up = 1;
  2113. }
  2114. goto out;
  2115. }
  2116. /* Want auto-negotiation. */
  2117. expected_sg_dig_ctrl = 0x81388400;
  2118. /* Pause capability */
  2119. expected_sg_dig_ctrl |= (1 << 11);
  2120. /* Asymettric pause */
  2121. expected_sg_dig_ctrl |= (1 << 12);
  2122. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  2123. if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
  2124. tp->serdes_counter &&
  2125. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  2126. MAC_STATUS_RCVD_CFG)) ==
  2127. MAC_STATUS_PCS_SYNCED)) {
  2128. tp->serdes_counter--;
  2129. current_link_up = 1;
  2130. goto out;
  2131. }
  2132. restart_autoneg:
  2133. if (workaround)
  2134. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  2135. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
  2136. udelay(5);
  2137. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  2138. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2139. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2140. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  2141. MAC_STATUS_SIGNAL_DET)) {
  2142. sg_dig_status = tr32(SG_DIG_STATUS);
  2143. mac_status = tr32(MAC_STATUS);
  2144. if ((sg_dig_status & (1 << 1)) &&
  2145. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  2146. u32 local_adv, remote_adv;
  2147. local_adv = ADVERTISE_PAUSE_CAP;
  2148. remote_adv = 0;
  2149. if (sg_dig_status & (1 << 19))
  2150. remote_adv |= LPA_PAUSE_CAP;
  2151. if (sg_dig_status & (1 << 20))
  2152. remote_adv |= LPA_PAUSE_ASYM;
  2153. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2154. current_link_up = 1;
  2155. tp->serdes_counter = 0;
  2156. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2157. } else if (!(sg_dig_status & (1 << 1))) {
  2158. if (tp->serdes_counter)
  2159. tp->serdes_counter--;
  2160. else {
  2161. if (workaround) {
  2162. u32 val = serdes_cfg;
  2163. if (port_a)
  2164. val |= 0xc010000;
  2165. else
  2166. val |= 0x4010000;
  2167. tw32_f(MAC_SERDES_CFG, val);
  2168. }
  2169. tw32_f(SG_DIG_CTRL, 0x01388400);
  2170. udelay(40);
  2171. /* Link parallel detection - link is up */
  2172. /* only if we have PCS_SYNC and not */
  2173. /* receiving config code words */
  2174. mac_status = tr32(MAC_STATUS);
  2175. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  2176. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  2177. tg3_setup_flow_control(tp, 0, 0);
  2178. current_link_up = 1;
  2179. tp->tg3_flags2 |=
  2180. TG3_FLG2_PARALLEL_DETECT;
  2181. tp->serdes_counter =
  2182. SERDES_PARALLEL_DET_TIMEOUT;
  2183. } else
  2184. goto restart_autoneg;
  2185. }
  2186. }
  2187. } else {
  2188. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2189. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2190. }
  2191. out:
  2192. return current_link_up;
  2193. }
  2194. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  2195. {
  2196. int current_link_up = 0;
  2197. if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
  2198. tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
  2199. goto out;
  2200. }
  2201. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2202. u32 flags;
  2203. int i;
  2204. if (fiber_autoneg(tp, &flags)) {
  2205. u32 local_adv, remote_adv;
  2206. local_adv = ADVERTISE_PAUSE_CAP;
  2207. remote_adv = 0;
  2208. if (flags & MR_LP_ADV_SYM_PAUSE)
  2209. remote_adv |= LPA_PAUSE_CAP;
  2210. if (flags & MR_LP_ADV_ASYM_PAUSE)
  2211. remote_adv |= LPA_PAUSE_ASYM;
  2212. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2213. tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
  2214. current_link_up = 1;
  2215. }
  2216. for (i = 0; i < 30; i++) {
  2217. udelay(20);
  2218. tw32_f(MAC_STATUS,
  2219. (MAC_STATUS_SYNC_CHANGED |
  2220. MAC_STATUS_CFG_CHANGED));
  2221. udelay(40);
  2222. if ((tr32(MAC_STATUS) &
  2223. (MAC_STATUS_SYNC_CHANGED |
  2224. MAC_STATUS_CFG_CHANGED)) == 0)
  2225. break;
  2226. }
  2227. mac_status = tr32(MAC_STATUS);
  2228. if (current_link_up == 0 &&
  2229. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  2230. !(mac_status & MAC_STATUS_RCVD_CFG))
  2231. current_link_up = 1;
  2232. } else {
  2233. /* Forcing 1000FD link up. */
  2234. current_link_up = 1;
  2235. tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
  2236. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  2237. udelay(40);
  2238. }
  2239. out:
  2240. return current_link_up;
  2241. }
  2242. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  2243. {
  2244. u32 orig_pause_cfg;
  2245. u16 orig_active_speed;
  2246. u8 orig_active_duplex;
  2247. u32 mac_status;
  2248. int current_link_up;
  2249. int i;
  2250. orig_pause_cfg =
  2251. (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2252. TG3_FLAG_TX_PAUSE));
  2253. orig_active_speed = tp->link_config.active_speed;
  2254. orig_active_duplex = tp->link_config.active_duplex;
  2255. if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
  2256. netif_carrier_ok(tp->dev) &&
  2257. (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
  2258. mac_status = tr32(MAC_STATUS);
  2259. mac_status &= (MAC_STATUS_PCS_SYNCED |
  2260. MAC_STATUS_SIGNAL_DET |
  2261. MAC_STATUS_CFG_CHANGED |
  2262. MAC_STATUS_RCVD_CFG);
  2263. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  2264. MAC_STATUS_SIGNAL_DET)) {
  2265. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2266. MAC_STATUS_CFG_CHANGED));
  2267. return 0;
  2268. }
  2269. }
  2270. tw32_f(MAC_TX_AUTO_NEG, 0);
  2271. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  2272. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  2273. tw32_f(MAC_MODE, tp->mac_mode);
  2274. udelay(40);
  2275. if (tp->phy_id == PHY_ID_BCM8002)
  2276. tg3_init_bcm8002(tp);
  2277. /* Enable link change event even when serdes polling. */
  2278. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2279. udelay(40);
  2280. current_link_up = 0;
  2281. mac_status = tr32(MAC_STATUS);
  2282. if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
  2283. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  2284. else
  2285. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  2286. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2287. tw32_f(MAC_MODE, tp->mac_mode);
  2288. udelay(40);
  2289. tp->hw_status->status =
  2290. (SD_STATUS_UPDATED |
  2291. (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
  2292. for (i = 0; i < 100; i++) {
  2293. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2294. MAC_STATUS_CFG_CHANGED));
  2295. udelay(5);
  2296. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  2297. MAC_STATUS_CFG_CHANGED |
  2298. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  2299. break;
  2300. }
  2301. mac_status = tr32(MAC_STATUS);
  2302. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  2303. current_link_up = 0;
  2304. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  2305. tp->serdes_counter == 0) {
  2306. tw32_f(MAC_MODE, (tp->mac_mode |
  2307. MAC_MODE_SEND_CONFIGS));
  2308. udelay(1);
  2309. tw32_f(MAC_MODE, tp->mac_mode);
  2310. }
  2311. }
  2312. if (current_link_up == 1) {
  2313. tp->link_config.active_speed = SPEED_1000;
  2314. tp->link_config.active_duplex = DUPLEX_FULL;
  2315. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2316. LED_CTRL_LNKLED_OVERRIDE |
  2317. LED_CTRL_1000MBPS_ON));
  2318. } else {
  2319. tp->link_config.active_speed = SPEED_INVALID;
  2320. tp->link_config.active_duplex = DUPLEX_INVALID;
  2321. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2322. LED_CTRL_LNKLED_OVERRIDE |
  2323. LED_CTRL_TRAFFIC_OVERRIDE));
  2324. }
  2325. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2326. if (current_link_up)
  2327. netif_carrier_on(tp->dev);
  2328. else
  2329. netif_carrier_off(tp->dev);
  2330. tg3_link_report(tp);
  2331. } else {
  2332. u32 now_pause_cfg =
  2333. tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2334. TG3_FLAG_TX_PAUSE);
  2335. if (orig_pause_cfg != now_pause_cfg ||
  2336. orig_active_speed != tp->link_config.active_speed ||
  2337. orig_active_duplex != tp->link_config.active_duplex)
  2338. tg3_link_report(tp);
  2339. }
  2340. return 0;
  2341. }
  2342. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  2343. {
  2344. int current_link_up, err = 0;
  2345. u32 bmsr, bmcr;
  2346. u16 current_speed;
  2347. u8 current_duplex;
  2348. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2349. tw32_f(MAC_MODE, tp->mac_mode);
  2350. udelay(40);
  2351. tw32(MAC_EVENT, 0);
  2352. tw32_f(MAC_STATUS,
  2353. (MAC_STATUS_SYNC_CHANGED |
  2354. MAC_STATUS_CFG_CHANGED |
  2355. MAC_STATUS_MI_COMPLETION |
  2356. MAC_STATUS_LNKSTATE_CHANGED));
  2357. udelay(40);
  2358. if (force_reset)
  2359. tg3_phy_reset(tp);
  2360. current_link_up = 0;
  2361. current_speed = SPEED_INVALID;
  2362. current_duplex = DUPLEX_INVALID;
  2363. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2364. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2365. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  2366. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2367. bmsr |= BMSR_LSTATUS;
  2368. else
  2369. bmsr &= ~BMSR_LSTATUS;
  2370. }
  2371. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  2372. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  2373. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2374. /* do nothing, just check for link up at the end */
  2375. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2376. u32 adv, new_adv;
  2377. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2378. new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  2379. ADVERTISE_1000XPAUSE |
  2380. ADVERTISE_1000XPSE_ASYM |
  2381. ADVERTISE_SLCT);
  2382. /* Always advertise symmetric PAUSE just like copper */
  2383. new_adv |= ADVERTISE_1000XPAUSE;
  2384. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  2385. new_adv |= ADVERTISE_1000XHALF;
  2386. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  2387. new_adv |= ADVERTISE_1000XFULL;
  2388. if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
  2389. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2390. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  2391. tg3_writephy(tp, MII_BMCR, bmcr);
  2392. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2393. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  2394. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2395. return err;
  2396. }
  2397. } else {
  2398. u32 new_bmcr;
  2399. bmcr &= ~BMCR_SPEED1000;
  2400. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  2401. if (tp->link_config.duplex == DUPLEX_FULL)
  2402. new_bmcr |= BMCR_FULLDPLX;
  2403. if (new_bmcr != bmcr) {
  2404. /* BMCR_SPEED1000 is a reserved bit that needs
  2405. * to be set on write.
  2406. */
  2407. new_bmcr |= BMCR_SPEED1000;
  2408. /* Force a linkdown */
  2409. if (netif_carrier_ok(tp->dev)) {
  2410. u32 adv;
  2411. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2412. adv &= ~(ADVERTISE_1000XFULL |
  2413. ADVERTISE_1000XHALF |
  2414. ADVERTISE_SLCT);
  2415. tg3_writephy(tp, MII_ADVERTISE, adv);
  2416. tg3_writephy(tp, MII_BMCR, bmcr |
  2417. BMCR_ANRESTART |
  2418. BMCR_ANENABLE);
  2419. udelay(10);
  2420. netif_carrier_off(tp->dev);
  2421. }
  2422. tg3_writephy(tp, MII_BMCR, new_bmcr);
  2423. bmcr = new_bmcr;
  2424. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2425. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2426. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  2427. ASIC_REV_5714) {
  2428. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2429. bmsr |= BMSR_LSTATUS;
  2430. else
  2431. bmsr &= ~BMSR_LSTATUS;
  2432. }
  2433. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2434. }
  2435. }
  2436. if (bmsr & BMSR_LSTATUS) {
  2437. current_speed = SPEED_1000;
  2438. current_link_up = 1;
  2439. if (bmcr & BMCR_FULLDPLX)
  2440. current_duplex = DUPLEX_FULL;
  2441. else
  2442. current_duplex = DUPLEX_HALF;
  2443. if (bmcr & BMCR_ANENABLE) {
  2444. u32 local_adv, remote_adv, common;
  2445. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  2446. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  2447. common = local_adv & remote_adv;
  2448. if (common & (ADVERTISE_1000XHALF |
  2449. ADVERTISE_1000XFULL)) {
  2450. if (common & ADVERTISE_1000XFULL)
  2451. current_duplex = DUPLEX_FULL;
  2452. else
  2453. current_duplex = DUPLEX_HALF;
  2454. tg3_setup_flow_control(tp, local_adv,
  2455. remote_adv);
  2456. }
  2457. else
  2458. current_link_up = 0;
  2459. }
  2460. }
  2461. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2462. if (tp->link_config.active_duplex == DUPLEX_HALF)
  2463. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2464. tw32_f(MAC_MODE, tp->mac_mode);
  2465. udelay(40);
  2466. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2467. tp->link_config.active_speed = current_speed;
  2468. tp->link_config.active_duplex = current_duplex;
  2469. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2470. if (current_link_up)
  2471. netif_carrier_on(tp->dev);
  2472. else {
  2473. netif_carrier_off(tp->dev);
  2474. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2475. }
  2476. tg3_link_report(tp);
  2477. }
  2478. return err;
  2479. }
  2480. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  2481. {
  2482. if (tp->serdes_counter) {
  2483. /* Give autoneg time to complete. */
  2484. tp->serdes_counter--;
  2485. return;
  2486. }
  2487. if (!netif_carrier_ok(tp->dev) &&
  2488. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  2489. u32 bmcr;
  2490. tg3_readphy(tp, MII_BMCR, &bmcr);
  2491. if (bmcr & BMCR_ANENABLE) {
  2492. u32 phy1, phy2;
  2493. /* Select shadow register 0x1f */
  2494. tg3_writephy(tp, 0x1c, 0x7c00);
  2495. tg3_readphy(tp, 0x1c, &phy1);
  2496. /* Select expansion interrupt status register */
  2497. tg3_writephy(tp, 0x17, 0x0f01);
  2498. tg3_readphy(tp, 0x15, &phy2);
  2499. tg3_readphy(tp, 0x15, &phy2);
  2500. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  2501. /* We have signal detect and not receiving
  2502. * config code words, link is up by parallel
  2503. * detection.
  2504. */
  2505. bmcr &= ~BMCR_ANENABLE;
  2506. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  2507. tg3_writephy(tp, MII_BMCR, bmcr);
  2508. tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
  2509. }
  2510. }
  2511. }
  2512. else if (netif_carrier_ok(tp->dev) &&
  2513. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  2514. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2515. u32 phy2;
  2516. /* Select expansion interrupt status register */
  2517. tg3_writephy(tp, 0x17, 0x0f01);
  2518. tg3_readphy(tp, 0x15, &phy2);
  2519. if (phy2 & 0x20) {
  2520. u32 bmcr;
  2521. /* Config code words received, turn on autoneg. */
  2522. tg3_readphy(tp, MII_BMCR, &bmcr);
  2523. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  2524. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2525. }
  2526. }
  2527. }
  2528. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  2529. {
  2530. int err;
  2531. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  2532. err = tg3_setup_fiber_phy(tp, force_reset);
  2533. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  2534. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  2535. } else {
  2536. err = tg3_setup_copper_phy(tp, force_reset);
  2537. }
  2538. if (tp->link_config.active_speed == SPEED_1000 &&
  2539. tp->link_config.active_duplex == DUPLEX_HALF)
  2540. tw32(MAC_TX_LENGTHS,
  2541. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2542. (6 << TX_LENGTHS_IPG_SHIFT) |
  2543. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2544. else
  2545. tw32(MAC_TX_LENGTHS,
  2546. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2547. (6 << TX_LENGTHS_IPG_SHIFT) |
  2548. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2549. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  2550. if (netif_carrier_ok(tp->dev)) {
  2551. tw32(HOSTCC_STAT_COAL_TICKS,
  2552. tp->coal.stats_block_coalesce_usecs);
  2553. } else {
  2554. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  2555. }
  2556. }
  2557. return err;
  2558. }
  2559. /* This is called whenever we suspect that the system chipset is re-
  2560. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  2561. * is bogus tx completions. We try to recover by setting the
  2562. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  2563. * in the workqueue.
  2564. */
  2565. static void tg3_tx_recover(struct tg3 *tp)
  2566. {
  2567. BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
  2568. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  2569. printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
  2570. "mapped I/O cycles to the network device, attempting to "
  2571. "recover. Please report the problem to the driver maintainer "
  2572. "and include system chipset information.\n", tp->dev->name);
  2573. spin_lock(&tp->lock);
  2574. tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
  2575. spin_unlock(&tp->lock);
  2576. }
  2577. static inline u32 tg3_tx_avail(struct tg3 *tp)
  2578. {
  2579. smp_mb();
  2580. return (tp->tx_pending -
  2581. ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
  2582. }
  2583. /* Tigon3 never reports partial packet sends. So we do not
  2584. * need special logic to handle SKBs that have not had all
  2585. * of their frags sent yet, like SunGEM does.
  2586. */
  2587. static void tg3_tx(struct tg3 *tp)
  2588. {
  2589. u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
  2590. u32 sw_idx = tp->tx_cons;
  2591. while (sw_idx != hw_idx) {
  2592. struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
  2593. struct sk_buff *skb = ri->skb;
  2594. int i, tx_bug = 0;
  2595. if (unlikely(skb == NULL)) {
  2596. tg3_tx_recover(tp);
  2597. return;
  2598. }
  2599. pci_unmap_single(tp->pdev,
  2600. pci_unmap_addr(ri, mapping),
  2601. skb_headlen(skb),
  2602. PCI_DMA_TODEVICE);
  2603. ri->skb = NULL;
  2604. sw_idx = NEXT_TX(sw_idx);
  2605. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2606. ri = &tp->tx_buffers[sw_idx];
  2607. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  2608. tx_bug = 1;
  2609. pci_unmap_page(tp->pdev,
  2610. pci_unmap_addr(ri, mapping),
  2611. skb_shinfo(skb)->frags[i].size,
  2612. PCI_DMA_TODEVICE);
  2613. sw_idx = NEXT_TX(sw_idx);
  2614. }
  2615. dev_kfree_skb(skb);
  2616. if (unlikely(tx_bug)) {
  2617. tg3_tx_recover(tp);
  2618. return;
  2619. }
  2620. }
  2621. tp->tx_cons = sw_idx;
  2622. /* Need to make the tx_cons update visible to tg3_start_xmit()
  2623. * before checking for netif_queue_stopped(). Without the
  2624. * memory barrier, there is a small possibility that tg3_start_xmit()
  2625. * will miss it and cause the queue to be stopped forever.
  2626. */
  2627. smp_mb();
  2628. if (unlikely(netif_queue_stopped(tp->dev) &&
  2629. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
  2630. netif_tx_lock(tp->dev);
  2631. if (netif_queue_stopped(tp->dev) &&
  2632. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
  2633. netif_wake_queue(tp->dev);
  2634. netif_tx_unlock(tp->dev);
  2635. }
  2636. }
  2637. /* Returns size of skb allocated or < 0 on error.
  2638. *
  2639. * We only need to fill in the address because the other members
  2640. * of the RX descriptor are invariant, see tg3_init_rings.
  2641. *
  2642. * Note the purposeful assymetry of cpu vs. chip accesses. For
  2643. * posting buffers we only dirty the first cache line of the RX
  2644. * descriptor (containing the address). Whereas for the RX status
  2645. * buffers the cpu only reads the last cacheline of the RX descriptor
  2646. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  2647. */
  2648. static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
  2649. int src_idx, u32 dest_idx_unmasked)
  2650. {
  2651. struct tg3_rx_buffer_desc *desc;
  2652. struct ring_info *map, *src_map;
  2653. struct sk_buff *skb;
  2654. dma_addr_t mapping;
  2655. int skb_size, dest_idx;
  2656. src_map = NULL;
  2657. switch (opaque_key) {
  2658. case RXD_OPAQUE_RING_STD:
  2659. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2660. desc = &tp->rx_std[dest_idx];
  2661. map = &tp->rx_std_buffers[dest_idx];
  2662. if (src_idx >= 0)
  2663. src_map = &tp->rx_std_buffers[src_idx];
  2664. skb_size = tp->rx_pkt_buf_sz;
  2665. break;
  2666. case RXD_OPAQUE_RING_JUMBO:
  2667. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2668. desc = &tp->rx_jumbo[dest_idx];
  2669. map = &tp->rx_jumbo_buffers[dest_idx];
  2670. if (src_idx >= 0)
  2671. src_map = &tp->rx_jumbo_buffers[src_idx];
  2672. skb_size = RX_JUMBO_PKT_BUF_SZ;
  2673. break;
  2674. default:
  2675. return -EINVAL;
  2676. };
  2677. /* Do not overwrite any of the map or rp information
  2678. * until we are sure we can commit to a new buffer.
  2679. *
  2680. * Callers depend upon this behavior and assume that
  2681. * we leave everything unchanged if we fail.
  2682. */
  2683. skb = netdev_alloc_skb(tp->dev, skb_size);
  2684. if (skb == NULL)
  2685. return -ENOMEM;
  2686. skb_reserve(skb, tp->rx_offset);
  2687. mapping = pci_map_single(tp->pdev, skb->data,
  2688. skb_size - tp->rx_offset,
  2689. PCI_DMA_FROMDEVICE);
  2690. map->skb = skb;
  2691. pci_unmap_addr_set(map, mapping, mapping);
  2692. if (src_map != NULL)
  2693. src_map->skb = NULL;
  2694. desc->addr_hi = ((u64)mapping >> 32);
  2695. desc->addr_lo = ((u64)mapping & 0xffffffff);
  2696. return skb_size;
  2697. }
  2698. /* We only need to move over in the address because the other
  2699. * members of the RX descriptor are invariant. See notes above
  2700. * tg3_alloc_rx_skb for full details.
  2701. */
  2702. static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
  2703. int src_idx, u32 dest_idx_unmasked)
  2704. {
  2705. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  2706. struct ring_info *src_map, *dest_map;
  2707. int dest_idx;
  2708. switch (opaque_key) {
  2709. case RXD_OPAQUE_RING_STD:
  2710. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2711. dest_desc = &tp->rx_std[dest_idx];
  2712. dest_map = &tp->rx_std_buffers[dest_idx];
  2713. src_desc = &tp->rx_std[src_idx];
  2714. src_map = &tp->rx_std_buffers[src_idx];
  2715. break;
  2716. case RXD_OPAQUE_RING_JUMBO:
  2717. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2718. dest_desc = &tp->rx_jumbo[dest_idx];
  2719. dest_map = &tp->rx_jumbo_buffers[dest_idx];
  2720. src_desc = &tp->rx_jumbo[src_idx];
  2721. src_map = &tp->rx_jumbo_buffers[src_idx];
  2722. break;
  2723. default:
  2724. return;
  2725. };
  2726. dest_map->skb = src_map->skb;
  2727. pci_unmap_addr_set(dest_map, mapping,
  2728. pci_unmap_addr(src_map, mapping));
  2729. dest_desc->addr_hi = src_desc->addr_hi;
  2730. dest_desc->addr_lo = src_desc->addr_lo;
  2731. src_map->skb = NULL;
  2732. }
  2733. #if TG3_VLAN_TAG_USED
  2734. static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
  2735. {
  2736. return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
  2737. }
  2738. #endif
  2739. /* The RX ring scheme is composed of multiple rings which post fresh
  2740. * buffers to the chip, and one special ring the chip uses to report
  2741. * status back to the host.
  2742. *
  2743. * The special ring reports the status of received packets to the
  2744. * host. The chip does not write into the original descriptor the
  2745. * RX buffer was obtained from. The chip simply takes the original
  2746. * descriptor as provided by the host, updates the status and length
  2747. * field, then writes this into the next status ring entry.
  2748. *
  2749. * Each ring the host uses to post buffers to the chip is described
  2750. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  2751. * it is first placed into the on-chip ram. When the packet's length
  2752. * is known, it walks down the TG3_BDINFO entries to select the ring.
  2753. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  2754. * which is within the range of the new packet's length is chosen.
  2755. *
  2756. * The "separate ring for rx status" scheme may sound queer, but it makes
  2757. * sense from a cache coherency perspective. If only the host writes
  2758. * to the buffer post rings, and only the chip writes to the rx status
  2759. * rings, then cache lines never move beyond shared-modified state.
  2760. * If both the host and chip were to write into the same ring, cache line
  2761. * eviction could occur since both entities want it in an exclusive state.
  2762. */
  2763. static int tg3_rx(struct tg3 *tp, int budget)
  2764. {
  2765. u32 work_mask, rx_std_posted = 0;
  2766. u32 sw_idx = tp->rx_rcb_ptr;
  2767. u16 hw_idx;
  2768. int received;
  2769. hw_idx = tp->hw_status->idx[0].rx_producer;
  2770. /*
  2771. * We need to order the read of hw_idx and the read of
  2772. * the opaque cookie.
  2773. */
  2774. rmb();
  2775. work_mask = 0;
  2776. received = 0;
  2777. while (sw_idx != hw_idx && budget > 0) {
  2778. struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
  2779. unsigned int len;
  2780. struct sk_buff *skb;
  2781. dma_addr_t dma_addr;
  2782. u32 opaque_key, desc_idx, *post_ptr;
  2783. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  2784. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  2785. if (opaque_key == RXD_OPAQUE_RING_STD) {
  2786. dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
  2787. mapping);
  2788. skb = tp->rx_std_buffers[desc_idx].skb;
  2789. post_ptr = &tp->rx_std_ptr;
  2790. rx_std_posted++;
  2791. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  2792. dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
  2793. mapping);
  2794. skb = tp->rx_jumbo_buffers[desc_idx].skb;
  2795. post_ptr = &tp->rx_jumbo_ptr;
  2796. }
  2797. else {
  2798. goto next_pkt_nopost;
  2799. }
  2800. work_mask |= opaque_key;
  2801. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  2802. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  2803. drop_it:
  2804. tg3_recycle_rx(tp, opaque_key,
  2805. desc_idx, *post_ptr);
  2806. drop_it_no_recycle:
  2807. /* Other statistics kept track of by card. */
  2808. tp->net_stats.rx_dropped++;
  2809. goto next_pkt;
  2810. }
  2811. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
  2812. if (len > RX_COPY_THRESHOLD
  2813. && tp->rx_offset == 2
  2814. /* rx_offset != 2 iff this is a 5701 card running
  2815. * in PCI-X mode [see tg3_get_invariants()] */
  2816. ) {
  2817. int skb_size;
  2818. skb_size = tg3_alloc_rx_skb(tp, opaque_key,
  2819. desc_idx, *post_ptr);
  2820. if (skb_size < 0)
  2821. goto drop_it;
  2822. pci_unmap_single(tp->pdev, dma_addr,
  2823. skb_size - tp->rx_offset,
  2824. PCI_DMA_FROMDEVICE);
  2825. skb_put(skb, len);
  2826. } else {
  2827. struct sk_buff *copy_skb;
  2828. tg3_recycle_rx(tp, opaque_key,
  2829. desc_idx, *post_ptr);
  2830. copy_skb = netdev_alloc_skb(tp->dev, len + 2);
  2831. if (copy_skb == NULL)
  2832. goto drop_it_no_recycle;
  2833. skb_reserve(copy_skb, 2);
  2834. skb_put(copy_skb, len);
  2835. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  2836. memcpy(copy_skb->data, skb->data, len);
  2837. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  2838. /* We'll reuse the original ring buffer. */
  2839. skb = copy_skb;
  2840. }
  2841. if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  2842. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  2843. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  2844. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  2845. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2846. else
  2847. skb->ip_summed = CHECKSUM_NONE;
  2848. skb->protocol = eth_type_trans(skb, tp->dev);
  2849. #if TG3_VLAN_TAG_USED
  2850. if (tp->vlgrp != NULL &&
  2851. desc->type_flags & RXD_FLAG_VLAN) {
  2852. tg3_vlan_rx(tp, skb,
  2853. desc->err_vlan & RXD_VLAN_MASK);
  2854. } else
  2855. #endif
  2856. netif_receive_skb(skb);
  2857. tp->dev->last_rx = jiffies;
  2858. received++;
  2859. budget--;
  2860. next_pkt:
  2861. (*post_ptr)++;
  2862. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  2863. u32 idx = *post_ptr % TG3_RX_RING_SIZE;
  2864. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
  2865. TG3_64BIT_REG_LOW, idx);
  2866. work_mask &= ~RXD_OPAQUE_RING_STD;
  2867. rx_std_posted = 0;
  2868. }
  2869. next_pkt_nopost:
  2870. sw_idx++;
  2871. sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
  2872. /* Refresh hw_idx to see if there is new work */
  2873. if (sw_idx == hw_idx) {
  2874. hw_idx = tp->hw_status->idx[0].rx_producer;
  2875. rmb();
  2876. }
  2877. }
  2878. /* ACK the status ring. */
  2879. tp->rx_rcb_ptr = sw_idx;
  2880. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
  2881. /* Refill RX ring(s). */
  2882. if (work_mask & RXD_OPAQUE_RING_STD) {
  2883. sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
  2884. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  2885. sw_idx);
  2886. }
  2887. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  2888. sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
  2889. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  2890. sw_idx);
  2891. }
  2892. mmiowb();
  2893. return received;
  2894. }
  2895. static int tg3_poll(struct net_device *netdev, int *budget)
  2896. {
  2897. struct tg3 *tp = netdev_priv(netdev);
  2898. struct tg3_hw_status *sblk = tp->hw_status;
  2899. int done;
  2900. /* handle link change and other phy events */
  2901. if (!(tp->tg3_flags &
  2902. (TG3_FLAG_USE_LINKCHG_REG |
  2903. TG3_FLAG_POLL_SERDES))) {
  2904. if (sblk->status & SD_STATUS_LINK_CHG) {
  2905. sblk->status = SD_STATUS_UPDATED |
  2906. (sblk->status & ~SD_STATUS_LINK_CHG);
  2907. spin_lock(&tp->lock);
  2908. tg3_setup_phy(tp, 0);
  2909. spin_unlock(&tp->lock);
  2910. }
  2911. }
  2912. /* run TX completion thread */
  2913. if (sblk->idx[0].tx_consumer != tp->tx_cons) {
  2914. tg3_tx(tp);
  2915. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
  2916. netif_rx_complete(netdev);
  2917. schedule_work(&tp->reset_task);
  2918. return 0;
  2919. }
  2920. }
  2921. /* run RX thread, within the bounds set by NAPI.
  2922. * All RX "locking" is done by ensuring outside
  2923. * code synchronizes with dev->poll()
  2924. */
  2925. if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
  2926. int orig_budget = *budget;
  2927. int work_done;
  2928. if (orig_budget > netdev->quota)
  2929. orig_budget = netdev->quota;
  2930. work_done = tg3_rx(tp, orig_budget);
  2931. *budget -= work_done;
  2932. netdev->quota -= work_done;
  2933. }
  2934. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  2935. tp->last_tag = sblk->status_tag;
  2936. rmb();
  2937. } else
  2938. sblk->status &= ~SD_STATUS_UPDATED;
  2939. /* if no more work, tell net stack and NIC we're done */
  2940. done = !tg3_has_work(tp);
  2941. if (done) {
  2942. netif_rx_complete(netdev);
  2943. tg3_restart_ints(tp);
  2944. }
  2945. return (done ? 0 : 1);
  2946. }
  2947. static void tg3_irq_quiesce(struct tg3 *tp)
  2948. {
  2949. BUG_ON(tp->irq_sync);
  2950. tp->irq_sync = 1;
  2951. smp_mb();
  2952. synchronize_irq(tp->pdev->irq);
  2953. }
  2954. static inline int tg3_irq_sync(struct tg3 *tp)
  2955. {
  2956. return tp->irq_sync;
  2957. }
  2958. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  2959. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  2960. * with as well. Most of the time, this is not necessary except when
  2961. * shutting down the device.
  2962. */
  2963. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  2964. {
  2965. if (irq_sync)
  2966. tg3_irq_quiesce(tp);
  2967. spin_lock_bh(&tp->lock);
  2968. }
  2969. static inline void tg3_full_unlock(struct tg3 *tp)
  2970. {
  2971. spin_unlock_bh(&tp->lock);
  2972. }
  2973. /* One-shot MSI handler - Chip automatically disables interrupt
  2974. * after sending MSI so driver doesn't have to do it.
  2975. */
  2976. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  2977. {
  2978. struct net_device *dev = dev_id;
  2979. struct tg3 *tp = netdev_priv(dev);
  2980. prefetch(tp->hw_status);
  2981. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  2982. if (likely(!tg3_irq_sync(tp)))
  2983. netif_rx_schedule(dev); /* schedule NAPI poll */
  2984. return IRQ_HANDLED;
  2985. }
  2986. /* MSI ISR - No need to check for interrupt sharing and no need to
  2987. * flush status block and interrupt mailbox. PCI ordering rules
  2988. * guarantee that MSI will arrive after the status block.
  2989. */
  2990. static irqreturn_t tg3_msi(int irq, void *dev_id)
  2991. {
  2992. struct net_device *dev = dev_id;
  2993. struct tg3 *tp = netdev_priv(dev);
  2994. prefetch(tp->hw_status);
  2995. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  2996. /*
  2997. * Writing any value to intr-mbox-0 clears PCI INTA# and
  2998. * chip-internal interrupt pending events.
  2999. * Writing non-zero to intr-mbox-0 additional tells the
  3000. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3001. * event coalescing.
  3002. */
  3003. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3004. if (likely(!tg3_irq_sync(tp)))
  3005. netif_rx_schedule(dev); /* schedule NAPI poll */
  3006. return IRQ_RETVAL(1);
  3007. }
  3008. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  3009. {
  3010. struct net_device *dev = dev_id;
  3011. struct tg3 *tp = netdev_priv(dev);
  3012. struct tg3_hw_status *sblk = tp->hw_status;
  3013. unsigned int handled = 1;
  3014. /* In INTx mode, it is possible for the interrupt to arrive at
  3015. * the CPU before the status block posted prior to the interrupt.
  3016. * Reading the PCI State register will confirm whether the
  3017. * interrupt is ours and will flush the status block.
  3018. */
  3019. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  3020. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3021. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3022. handled = 0;
  3023. goto out;
  3024. }
  3025. }
  3026. /*
  3027. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3028. * chip-internal interrupt pending events.
  3029. * Writing non-zero to intr-mbox-0 additional tells the
  3030. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3031. * event coalescing.
  3032. */
  3033. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3034. if (tg3_irq_sync(tp))
  3035. goto out;
  3036. sblk->status &= ~SD_STATUS_UPDATED;
  3037. if (likely(tg3_has_work(tp))) {
  3038. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3039. netif_rx_schedule(dev); /* schedule NAPI poll */
  3040. } else {
  3041. /* No work, shared interrupt perhaps? re-enable
  3042. * interrupts, and flush that PCI write
  3043. */
  3044. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  3045. 0x00000000);
  3046. }
  3047. out:
  3048. return IRQ_RETVAL(handled);
  3049. }
  3050. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  3051. {
  3052. struct net_device *dev = dev_id;
  3053. struct tg3 *tp = netdev_priv(dev);
  3054. struct tg3_hw_status *sblk = tp->hw_status;
  3055. unsigned int handled = 1;
  3056. /* In INTx mode, it is possible for the interrupt to arrive at
  3057. * the CPU before the status block posted prior to the interrupt.
  3058. * Reading the PCI State register will confirm whether the
  3059. * interrupt is ours and will flush the status block.
  3060. */
  3061. if (unlikely(sblk->status_tag == tp->last_tag)) {
  3062. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3063. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3064. handled = 0;
  3065. goto out;
  3066. }
  3067. }
  3068. /*
  3069. * writing any value to intr-mbox-0 clears PCI INTA# and
  3070. * chip-internal interrupt pending events.
  3071. * writing non-zero to intr-mbox-0 additional tells the
  3072. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3073. * event coalescing.
  3074. */
  3075. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3076. if (tg3_irq_sync(tp))
  3077. goto out;
  3078. if (netif_rx_schedule_prep(dev)) {
  3079. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3080. /* Update last_tag to mark that this status has been
  3081. * seen. Because interrupt may be shared, we may be
  3082. * racing with tg3_poll(), so only update last_tag
  3083. * if tg3_poll() is not scheduled.
  3084. */
  3085. tp->last_tag = sblk->status_tag;
  3086. __netif_rx_schedule(dev);
  3087. }
  3088. out:
  3089. return IRQ_RETVAL(handled);
  3090. }
  3091. /* ISR for interrupt test */
  3092. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  3093. {
  3094. struct net_device *dev = dev_id;
  3095. struct tg3 *tp = netdev_priv(dev);
  3096. struct tg3_hw_status *sblk = tp->hw_status;
  3097. if ((sblk->status & SD_STATUS_UPDATED) ||
  3098. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3099. tg3_disable_ints(tp);
  3100. return IRQ_RETVAL(1);
  3101. }
  3102. return IRQ_RETVAL(0);
  3103. }
  3104. static int tg3_init_hw(struct tg3 *, int);
  3105. static int tg3_halt(struct tg3 *, int, int);
  3106. /* Restart hardware after configuration changes, self-test, etc.
  3107. * Invoked with tp->lock held.
  3108. */
  3109. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  3110. {
  3111. int err;
  3112. err = tg3_init_hw(tp, reset_phy);
  3113. if (err) {
  3114. printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
  3115. "aborting.\n", tp->dev->name);
  3116. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3117. tg3_full_unlock(tp);
  3118. del_timer_sync(&tp->timer);
  3119. tp->irq_sync = 0;
  3120. netif_poll_enable(tp->dev);
  3121. dev_close(tp->dev);
  3122. tg3_full_lock(tp, 0);
  3123. }
  3124. return err;
  3125. }
  3126. #ifdef CONFIG_NET_POLL_CONTROLLER
  3127. static void tg3_poll_controller(struct net_device *dev)
  3128. {
  3129. struct tg3 *tp = netdev_priv(dev);
  3130. tg3_interrupt(tp->pdev->irq, dev);
  3131. }
  3132. #endif
  3133. static void tg3_reset_task(struct work_struct *work)
  3134. {
  3135. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  3136. unsigned int restart_timer;
  3137. tg3_full_lock(tp, 0);
  3138. tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
  3139. if (!netif_running(tp->dev)) {
  3140. tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
  3141. tg3_full_unlock(tp);
  3142. return;
  3143. }
  3144. tg3_full_unlock(tp);
  3145. tg3_netif_stop(tp);
  3146. tg3_full_lock(tp, 1);
  3147. restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
  3148. tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
  3149. if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
  3150. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  3151. tp->write32_rx_mbox = tg3_write_flush_reg32;
  3152. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  3153. tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
  3154. }
  3155. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  3156. if (tg3_init_hw(tp, 1))
  3157. goto out;
  3158. tg3_netif_start(tp);
  3159. if (restart_timer)
  3160. mod_timer(&tp->timer, jiffies + 1);
  3161. out:
  3162. tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
  3163. tg3_full_unlock(tp);
  3164. }
  3165. static void tg3_dump_short_state(struct tg3 *tp)
  3166. {
  3167. printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
  3168. tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
  3169. printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
  3170. tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
  3171. }
  3172. static void tg3_tx_timeout(struct net_device *dev)
  3173. {
  3174. struct tg3 *tp = netdev_priv(dev);
  3175. if (netif_msg_tx_err(tp)) {
  3176. printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
  3177. dev->name);
  3178. tg3_dump_short_state(tp);
  3179. }
  3180. schedule_work(&tp->reset_task);
  3181. }
  3182. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  3183. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  3184. {
  3185. u32 base = (u32) mapping & 0xffffffff;
  3186. return ((base > 0xffffdcc0) &&
  3187. (base + len + 8 < base));
  3188. }
  3189. /* Test for DMA addresses > 40-bit */
  3190. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  3191. int len)
  3192. {
  3193. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  3194. if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
  3195. return (((u64) mapping + len) > DMA_40BIT_MASK);
  3196. return 0;
  3197. #else
  3198. return 0;
  3199. #endif
  3200. }
  3201. static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
  3202. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  3203. static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
  3204. u32 last_plus_one, u32 *start,
  3205. u32 base_flags, u32 mss)
  3206. {
  3207. struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
  3208. dma_addr_t new_addr = 0;
  3209. u32 entry = *start;
  3210. int i, ret = 0;
  3211. if (!new_skb) {
  3212. ret = -1;
  3213. } else {
  3214. /* New SKB is guaranteed to be linear. */
  3215. entry = *start;
  3216. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  3217. PCI_DMA_TODEVICE);
  3218. /* Make sure new skb does not cross any 4G boundaries.
  3219. * Drop the packet if it does.
  3220. */
  3221. if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
  3222. ret = -1;
  3223. dev_kfree_skb(new_skb);
  3224. new_skb = NULL;
  3225. } else {
  3226. tg3_set_txd(tp, entry, new_addr, new_skb->len,
  3227. base_flags, 1 | (mss << 1));
  3228. *start = NEXT_TX(entry);
  3229. }
  3230. }
  3231. /* Now clean up the sw ring entries. */
  3232. i = 0;
  3233. while (entry != last_plus_one) {
  3234. int len;
  3235. if (i == 0)
  3236. len = skb_headlen(skb);
  3237. else
  3238. len = skb_shinfo(skb)->frags[i-1].size;
  3239. pci_unmap_single(tp->pdev,
  3240. pci_unmap_addr(&tp->tx_buffers[entry], mapping),
  3241. len, PCI_DMA_TODEVICE);
  3242. if (i == 0) {
  3243. tp->tx_buffers[entry].skb = new_skb;
  3244. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
  3245. } else {
  3246. tp->tx_buffers[entry].skb = NULL;
  3247. }
  3248. entry = NEXT_TX(entry);
  3249. i++;
  3250. }
  3251. dev_kfree_skb(skb);
  3252. return ret;
  3253. }
  3254. static void tg3_set_txd(struct tg3 *tp, int entry,
  3255. dma_addr_t mapping, int len, u32 flags,
  3256. u32 mss_and_is_end)
  3257. {
  3258. struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
  3259. int is_end = (mss_and_is_end & 0x1);
  3260. u32 mss = (mss_and_is_end >> 1);
  3261. u32 vlan_tag = 0;
  3262. if (is_end)
  3263. flags |= TXD_FLAG_END;
  3264. if (flags & TXD_FLAG_VLAN) {
  3265. vlan_tag = flags >> 16;
  3266. flags &= 0xffff;
  3267. }
  3268. vlan_tag |= (mss << TXD_MSS_SHIFT);
  3269. txd->addr_hi = ((u64) mapping >> 32);
  3270. txd->addr_lo = ((u64) mapping & 0xffffffff);
  3271. txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  3272. txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  3273. }
  3274. /* hard_start_xmit for devices that don't have any bugs and
  3275. * support TG3_FLG2_HW_TSO_2 only.
  3276. */
  3277. static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  3278. {
  3279. struct tg3 *tp = netdev_priv(dev);
  3280. dma_addr_t mapping;
  3281. u32 len, entry, base_flags, mss;
  3282. len = skb_headlen(skb);
  3283. /* We are running in BH disabled context with netif_tx_lock
  3284. * and TX reclaim runs via tp->poll inside of a software
  3285. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3286. * no IRQ context deadlocks to worry about either. Rejoice!
  3287. */
  3288. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3289. if (!netif_queue_stopped(dev)) {
  3290. netif_stop_queue(dev);
  3291. /* This is a hard error, log it. */
  3292. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3293. "queue awake!\n", dev->name);
  3294. }
  3295. return NETDEV_TX_BUSY;
  3296. }
  3297. entry = tp->tx_prod;
  3298. base_flags = 0;
  3299. mss = 0;
  3300. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3301. int tcp_opt_len, ip_tcp_len;
  3302. if (skb_header_cloned(skb) &&
  3303. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3304. dev_kfree_skb(skb);
  3305. goto out_unlock;
  3306. }
  3307. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  3308. mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
  3309. else {
  3310. tcp_opt_len = ((skb->h.th->doff - 5) * 4);
  3311. ip_tcp_len = (skb->nh.iph->ihl * 4) +
  3312. sizeof(struct tcphdr);
  3313. skb->nh.iph->check = 0;
  3314. skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
  3315. tcp_opt_len);
  3316. mss |= (ip_tcp_len + tcp_opt_len) << 9;
  3317. }
  3318. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3319. TXD_FLAG_CPU_POST_DMA);
  3320. skb->h.th->check = 0;
  3321. }
  3322. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  3323. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3324. #if TG3_VLAN_TAG_USED
  3325. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3326. base_flags |= (TXD_FLAG_VLAN |
  3327. (vlan_tx_tag_get(skb) << 16));
  3328. #endif
  3329. /* Queue skb data, a.k.a. the main skb fragment. */
  3330. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3331. tp->tx_buffers[entry].skb = skb;
  3332. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3333. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3334. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3335. entry = NEXT_TX(entry);
  3336. /* Now loop through additional data fragments, and queue them. */
  3337. if (skb_shinfo(skb)->nr_frags > 0) {
  3338. unsigned int i, last;
  3339. last = skb_shinfo(skb)->nr_frags - 1;
  3340. for (i = 0; i <= last; i++) {
  3341. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3342. len = frag->size;
  3343. mapping = pci_map_page(tp->pdev,
  3344. frag->page,
  3345. frag->page_offset,
  3346. len, PCI_DMA_TODEVICE);
  3347. tp->tx_buffers[entry].skb = NULL;
  3348. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3349. tg3_set_txd(tp, entry, mapping, len,
  3350. base_flags, (i == last) | (mss << 1));
  3351. entry = NEXT_TX(entry);
  3352. }
  3353. }
  3354. /* Packets are ready, update Tx producer idx local and on card. */
  3355. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3356. tp->tx_prod = entry;
  3357. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3358. netif_stop_queue(dev);
  3359. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3360. netif_wake_queue(tp->dev);
  3361. }
  3362. out_unlock:
  3363. mmiowb();
  3364. dev->trans_start = jiffies;
  3365. return NETDEV_TX_OK;
  3366. }
  3367. static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
  3368. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  3369. * TSO header is greater than 80 bytes.
  3370. */
  3371. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  3372. {
  3373. struct sk_buff *segs, *nskb;
  3374. /* Estimate the number of fragments in the worst case */
  3375. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
  3376. netif_stop_queue(tp->dev);
  3377. if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
  3378. return NETDEV_TX_BUSY;
  3379. netif_wake_queue(tp->dev);
  3380. }
  3381. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  3382. if (unlikely(IS_ERR(segs)))
  3383. goto tg3_tso_bug_end;
  3384. do {
  3385. nskb = segs;
  3386. segs = segs->next;
  3387. nskb->next = NULL;
  3388. tg3_start_xmit_dma_bug(nskb, tp->dev);
  3389. } while (segs);
  3390. tg3_tso_bug_end:
  3391. dev_kfree_skb(skb);
  3392. return NETDEV_TX_OK;
  3393. }
  3394. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  3395. * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
  3396. */
  3397. static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
  3398. {
  3399. struct tg3 *tp = netdev_priv(dev);
  3400. dma_addr_t mapping;
  3401. u32 len, entry, base_flags, mss;
  3402. int would_hit_hwbug;
  3403. len = skb_headlen(skb);
  3404. /* We are running in BH disabled context with netif_tx_lock
  3405. * and TX reclaim runs via tp->poll inside of a software
  3406. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3407. * no IRQ context deadlocks to worry about either. Rejoice!
  3408. */
  3409. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3410. if (!netif_queue_stopped(dev)) {
  3411. netif_stop_queue(dev);
  3412. /* This is a hard error, log it. */
  3413. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3414. "queue awake!\n", dev->name);
  3415. }
  3416. return NETDEV_TX_BUSY;
  3417. }
  3418. entry = tp->tx_prod;
  3419. base_flags = 0;
  3420. if (skb->ip_summed == CHECKSUM_PARTIAL)
  3421. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3422. mss = 0;
  3423. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3424. int tcp_opt_len, ip_tcp_len, hdr_len;
  3425. if (skb_header_cloned(skb) &&
  3426. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3427. dev_kfree_skb(skb);
  3428. goto out_unlock;
  3429. }
  3430. tcp_opt_len = ((skb->h.th->doff - 5) * 4);
  3431. ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
  3432. hdr_len = ip_tcp_len + tcp_opt_len;
  3433. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  3434. (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
  3435. return (tg3_tso_bug(tp, skb));
  3436. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3437. TXD_FLAG_CPU_POST_DMA);
  3438. skb->nh.iph->check = 0;
  3439. skb->nh.iph->tot_len = htons(mss + hdr_len);
  3440. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  3441. skb->h.th->check = 0;
  3442. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  3443. }
  3444. else {
  3445. skb->h.th->check =
  3446. ~csum_tcpudp_magic(skb->nh.iph->saddr,
  3447. skb->nh.iph->daddr,
  3448. 0, IPPROTO_TCP, 0);
  3449. }
  3450. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
  3451. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
  3452. if (tcp_opt_len || skb->nh.iph->ihl > 5) {
  3453. int tsflags;
  3454. tsflags = ((skb->nh.iph->ihl - 5) +
  3455. (tcp_opt_len >> 2));
  3456. mss |= (tsflags << 11);
  3457. }
  3458. } else {
  3459. if (tcp_opt_len || skb->nh.iph->ihl > 5) {
  3460. int tsflags;
  3461. tsflags = ((skb->nh.iph->ihl - 5) +
  3462. (tcp_opt_len >> 2));
  3463. base_flags |= tsflags << 12;
  3464. }
  3465. }
  3466. }
  3467. #if TG3_VLAN_TAG_USED
  3468. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3469. base_flags |= (TXD_FLAG_VLAN |
  3470. (vlan_tx_tag_get(skb) << 16));
  3471. #endif
  3472. /* Queue skb data, a.k.a. the main skb fragment. */
  3473. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3474. tp->tx_buffers[entry].skb = skb;
  3475. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3476. would_hit_hwbug = 0;
  3477. if (tg3_4g_overflow_test(mapping, len))
  3478. would_hit_hwbug = 1;
  3479. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3480. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3481. entry = NEXT_TX(entry);
  3482. /* Now loop through additional data fragments, and queue them. */
  3483. if (skb_shinfo(skb)->nr_frags > 0) {
  3484. unsigned int i, last;
  3485. last = skb_shinfo(skb)->nr_frags - 1;
  3486. for (i = 0; i <= last; i++) {
  3487. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3488. len = frag->size;
  3489. mapping = pci_map_page(tp->pdev,
  3490. frag->page,
  3491. frag->page_offset,
  3492. len, PCI_DMA_TODEVICE);
  3493. tp->tx_buffers[entry].skb = NULL;
  3494. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3495. if (tg3_4g_overflow_test(mapping, len))
  3496. would_hit_hwbug = 1;
  3497. if (tg3_40bit_overflow_test(tp, mapping, len))
  3498. would_hit_hwbug = 1;
  3499. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  3500. tg3_set_txd(tp, entry, mapping, len,
  3501. base_flags, (i == last)|(mss << 1));
  3502. else
  3503. tg3_set_txd(tp, entry, mapping, len,
  3504. base_flags, (i == last));
  3505. entry = NEXT_TX(entry);
  3506. }
  3507. }
  3508. if (would_hit_hwbug) {
  3509. u32 last_plus_one = entry;
  3510. u32 start;
  3511. start = entry - 1 - skb_shinfo(skb)->nr_frags;
  3512. start &= (TG3_TX_RING_SIZE - 1);
  3513. /* If the workaround fails due to memory/mapping
  3514. * failure, silently drop this packet.
  3515. */
  3516. if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
  3517. &start, base_flags, mss))
  3518. goto out_unlock;
  3519. entry = start;
  3520. }
  3521. /* Packets are ready, update Tx producer idx local and on card. */
  3522. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3523. tp->tx_prod = entry;
  3524. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3525. netif_stop_queue(dev);
  3526. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3527. netif_wake_queue(tp->dev);
  3528. }
  3529. out_unlock:
  3530. mmiowb();
  3531. dev->trans_start = jiffies;
  3532. return NETDEV_TX_OK;
  3533. }
  3534. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  3535. int new_mtu)
  3536. {
  3537. dev->mtu = new_mtu;
  3538. if (new_mtu > ETH_DATA_LEN) {
  3539. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  3540. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  3541. ethtool_op_set_tso(dev, 0);
  3542. }
  3543. else
  3544. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  3545. } else {
  3546. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  3547. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  3548. tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
  3549. }
  3550. }
  3551. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  3552. {
  3553. struct tg3 *tp = netdev_priv(dev);
  3554. int err;
  3555. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  3556. return -EINVAL;
  3557. if (!netif_running(dev)) {
  3558. /* We'll just catch it later when the
  3559. * device is up'd.
  3560. */
  3561. tg3_set_mtu(dev, tp, new_mtu);
  3562. return 0;
  3563. }
  3564. tg3_netif_stop(tp);
  3565. tg3_full_lock(tp, 1);
  3566. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3567. tg3_set_mtu(dev, tp, new_mtu);
  3568. err = tg3_restart_hw(tp, 0);
  3569. if (!err)
  3570. tg3_netif_start(tp);
  3571. tg3_full_unlock(tp);
  3572. return err;
  3573. }
  3574. /* Free up pending packets in all rx/tx rings.
  3575. *
  3576. * The chip has been shut down and the driver detached from
  3577. * the networking, so no interrupts or new tx packets will
  3578. * end up in the driver. tp->{tx,}lock is not held and we are not
  3579. * in an interrupt context and thus may sleep.
  3580. */
  3581. static void tg3_free_rings(struct tg3 *tp)
  3582. {
  3583. struct ring_info *rxp;
  3584. int i;
  3585. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  3586. rxp = &tp->rx_std_buffers[i];
  3587. if (rxp->skb == NULL)
  3588. continue;
  3589. pci_unmap_single(tp->pdev,
  3590. pci_unmap_addr(rxp, mapping),
  3591. tp->rx_pkt_buf_sz - tp->rx_offset,
  3592. PCI_DMA_FROMDEVICE);
  3593. dev_kfree_skb_any(rxp->skb);
  3594. rxp->skb = NULL;
  3595. }
  3596. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  3597. rxp = &tp->rx_jumbo_buffers[i];
  3598. if (rxp->skb == NULL)
  3599. continue;
  3600. pci_unmap_single(tp->pdev,
  3601. pci_unmap_addr(rxp, mapping),
  3602. RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
  3603. PCI_DMA_FROMDEVICE);
  3604. dev_kfree_skb_any(rxp->skb);
  3605. rxp->skb = NULL;
  3606. }
  3607. for (i = 0; i < TG3_TX_RING_SIZE; ) {
  3608. struct tx_ring_info *txp;
  3609. struct sk_buff *skb;
  3610. int j;
  3611. txp = &tp->tx_buffers[i];
  3612. skb = txp->skb;
  3613. if (skb == NULL) {
  3614. i++;
  3615. continue;
  3616. }
  3617. pci_unmap_single(tp->pdev,
  3618. pci_unmap_addr(txp, mapping),
  3619. skb_headlen(skb),
  3620. PCI_DMA_TODEVICE);
  3621. txp->skb = NULL;
  3622. i++;
  3623. for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
  3624. txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  3625. pci_unmap_page(tp->pdev,
  3626. pci_unmap_addr(txp, mapping),
  3627. skb_shinfo(skb)->frags[j].size,
  3628. PCI_DMA_TODEVICE);
  3629. i++;
  3630. }
  3631. dev_kfree_skb_any(skb);
  3632. }
  3633. }
  3634. /* Initialize tx/rx rings for packet processing.
  3635. *
  3636. * The chip has been shut down and the driver detached from
  3637. * the networking, so no interrupts or new tx packets will
  3638. * end up in the driver. tp->{tx,}lock are held and thus
  3639. * we may not sleep.
  3640. */
  3641. static int tg3_init_rings(struct tg3 *tp)
  3642. {
  3643. u32 i;
  3644. /* Free up all the SKBs. */
  3645. tg3_free_rings(tp);
  3646. /* Zero out all descriptors. */
  3647. memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
  3648. memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
  3649. memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  3650. memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
  3651. tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
  3652. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  3653. (tp->dev->mtu > ETH_DATA_LEN))
  3654. tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
  3655. /* Initialize invariants of the rings, we only set this
  3656. * stuff once. This works because the card does not
  3657. * write into the rx buffer posting rings.
  3658. */
  3659. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  3660. struct tg3_rx_buffer_desc *rxd;
  3661. rxd = &tp->rx_std[i];
  3662. rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
  3663. << RXD_LEN_SHIFT;
  3664. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  3665. rxd->opaque = (RXD_OPAQUE_RING_STD |
  3666. (i << RXD_OPAQUE_INDEX_SHIFT));
  3667. }
  3668. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  3669. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  3670. struct tg3_rx_buffer_desc *rxd;
  3671. rxd = &tp->rx_jumbo[i];
  3672. rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
  3673. << RXD_LEN_SHIFT;
  3674. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  3675. RXD_FLAG_JUMBO;
  3676. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  3677. (i << RXD_OPAQUE_INDEX_SHIFT));
  3678. }
  3679. }
  3680. /* Now allocate fresh SKBs for each rx ring. */
  3681. for (i = 0; i < tp->rx_pending; i++) {
  3682. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
  3683. printk(KERN_WARNING PFX
  3684. "%s: Using a smaller RX standard ring, "
  3685. "only %d out of %d buffers were allocated "
  3686. "successfully.\n",
  3687. tp->dev->name, i, tp->rx_pending);
  3688. if (i == 0)
  3689. return -ENOMEM;
  3690. tp->rx_pending = i;
  3691. break;
  3692. }
  3693. }
  3694. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  3695. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  3696. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
  3697. -1, i) < 0) {
  3698. printk(KERN_WARNING PFX
  3699. "%s: Using a smaller RX jumbo ring, "
  3700. "only %d out of %d buffers were "
  3701. "allocated successfully.\n",
  3702. tp->dev->name, i, tp->rx_jumbo_pending);
  3703. if (i == 0) {
  3704. tg3_free_rings(tp);
  3705. return -ENOMEM;
  3706. }
  3707. tp->rx_jumbo_pending = i;
  3708. break;
  3709. }
  3710. }
  3711. }
  3712. return 0;
  3713. }
  3714. /*
  3715. * Must not be invoked with interrupt sources disabled and
  3716. * the hardware shutdown down.
  3717. */
  3718. static void tg3_free_consistent(struct tg3 *tp)
  3719. {
  3720. kfree(tp->rx_std_buffers);
  3721. tp->rx_std_buffers = NULL;
  3722. if (tp->rx_std) {
  3723. pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  3724. tp->rx_std, tp->rx_std_mapping);
  3725. tp->rx_std = NULL;
  3726. }
  3727. if (tp->rx_jumbo) {
  3728. pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  3729. tp->rx_jumbo, tp->rx_jumbo_mapping);
  3730. tp->rx_jumbo = NULL;
  3731. }
  3732. if (tp->rx_rcb) {
  3733. pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  3734. tp->rx_rcb, tp->rx_rcb_mapping);
  3735. tp->rx_rcb = NULL;
  3736. }
  3737. if (tp->tx_ring) {
  3738. pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  3739. tp->tx_ring, tp->tx_desc_mapping);
  3740. tp->tx_ring = NULL;
  3741. }
  3742. if (tp->hw_status) {
  3743. pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  3744. tp->hw_status, tp->status_mapping);
  3745. tp->hw_status = NULL;
  3746. }
  3747. if (tp->hw_stats) {
  3748. pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  3749. tp->hw_stats, tp->stats_mapping);
  3750. tp->hw_stats = NULL;
  3751. }
  3752. }
  3753. /*
  3754. * Must not be invoked with interrupt sources disabled and
  3755. * the hardware shutdown down. Can sleep.
  3756. */
  3757. static int tg3_alloc_consistent(struct tg3 *tp)
  3758. {
  3759. tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
  3760. (TG3_RX_RING_SIZE +
  3761. TG3_RX_JUMBO_RING_SIZE)) +
  3762. (sizeof(struct tx_ring_info) *
  3763. TG3_TX_RING_SIZE),
  3764. GFP_KERNEL);
  3765. if (!tp->rx_std_buffers)
  3766. return -ENOMEM;
  3767. tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
  3768. tp->tx_buffers = (struct tx_ring_info *)
  3769. &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
  3770. tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  3771. &tp->rx_std_mapping);
  3772. if (!tp->rx_std)
  3773. goto err_out;
  3774. tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  3775. &tp->rx_jumbo_mapping);
  3776. if (!tp->rx_jumbo)
  3777. goto err_out;
  3778. tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  3779. &tp->rx_rcb_mapping);
  3780. if (!tp->rx_rcb)
  3781. goto err_out;
  3782. tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
  3783. &tp->tx_desc_mapping);
  3784. if (!tp->tx_ring)
  3785. goto err_out;
  3786. tp->hw_status = pci_alloc_consistent(tp->pdev,
  3787. TG3_HW_STATUS_SIZE,
  3788. &tp->status_mapping);
  3789. if (!tp->hw_status)
  3790. goto err_out;
  3791. tp->hw_stats = pci_alloc_consistent(tp->pdev,
  3792. sizeof(struct tg3_hw_stats),
  3793. &tp->stats_mapping);
  3794. if (!tp->hw_stats)
  3795. goto err_out;
  3796. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  3797. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  3798. return 0;
  3799. err_out:
  3800. tg3_free_consistent(tp);
  3801. return -ENOMEM;
  3802. }
  3803. #define MAX_WAIT_CNT 1000
  3804. /* To stop a block, clear the enable bit and poll till it
  3805. * clears. tp->lock is held.
  3806. */
  3807. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  3808. {
  3809. unsigned int i;
  3810. u32 val;
  3811. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  3812. switch (ofs) {
  3813. case RCVLSC_MODE:
  3814. case DMAC_MODE:
  3815. case MBFREE_MODE:
  3816. case BUFMGR_MODE:
  3817. case MEMARB_MODE:
  3818. /* We can't enable/disable these bits of the
  3819. * 5705/5750, just say success.
  3820. */
  3821. return 0;
  3822. default:
  3823. break;
  3824. };
  3825. }
  3826. val = tr32(ofs);
  3827. val &= ~enable_bit;
  3828. tw32_f(ofs, val);
  3829. for (i = 0; i < MAX_WAIT_CNT; i++) {
  3830. udelay(100);
  3831. val = tr32(ofs);
  3832. if ((val & enable_bit) == 0)
  3833. break;
  3834. }
  3835. if (i == MAX_WAIT_CNT && !silent) {
  3836. printk(KERN_ERR PFX "tg3_stop_block timed out, "
  3837. "ofs=%lx enable_bit=%x\n",
  3838. ofs, enable_bit);
  3839. return -ENODEV;
  3840. }
  3841. return 0;
  3842. }
  3843. /* tp->lock is held. */
  3844. static int tg3_abort_hw(struct tg3 *tp, int silent)
  3845. {
  3846. int i, err;
  3847. tg3_disable_ints(tp);
  3848. tp->rx_mode &= ~RX_MODE_ENABLE;
  3849. tw32_f(MAC_RX_MODE, tp->rx_mode);
  3850. udelay(10);
  3851. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  3852. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  3853. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  3854. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  3855. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  3856. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  3857. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  3858. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  3859. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  3860. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  3861. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  3862. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  3863. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  3864. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  3865. tw32_f(MAC_MODE, tp->mac_mode);
  3866. udelay(40);
  3867. tp->tx_mode &= ~TX_MODE_ENABLE;
  3868. tw32_f(MAC_TX_MODE, tp->tx_mode);
  3869. for (i = 0; i < MAX_WAIT_CNT; i++) {
  3870. udelay(100);
  3871. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  3872. break;
  3873. }
  3874. if (i >= MAX_WAIT_CNT) {
  3875. printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
  3876. "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
  3877. tp->dev->name, tr32(MAC_TX_MODE));
  3878. err |= -ENODEV;
  3879. }
  3880. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  3881. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  3882. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  3883. tw32(FTQ_RESET, 0xffffffff);
  3884. tw32(FTQ_RESET, 0x00000000);
  3885. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  3886. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  3887. if (tp->hw_status)
  3888. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  3889. if (tp->hw_stats)
  3890. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  3891. return err;
  3892. }
  3893. /* tp->lock is held. */
  3894. static int tg3_nvram_lock(struct tg3 *tp)
  3895. {
  3896. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  3897. int i;
  3898. if (tp->nvram_lock_cnt == 0) {
  3899. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  3900. for (i = 0; i < 8000; i++) {
  3901. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  3902. break;
  3903. udelay(20);
  3904. }
  3905. if (i == 8000) {
  3906. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  3907. return -ENODEV;
  3908. }
  3909. }
  3910. tp->nvram_lock_cnt++;
  3911. }
  3912. return 0;
  3913. }
  3914. /* tp->lock is held. */
  3915. static void tg3_nvram_unlock(struct tg3 *tp)
  3916. {
  3917. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  3918. if (tp->nvram_lock_cnt > 0)
  3919. tp->nvram_lock_cnt--;
  3920. if (tp->nvram_lock_cnt == 0)
  3921. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  3922. }
  3923. }
  3924. /* tp->lock is held. */
  3925. static void tg3_enable_nvram_access(struct tg3 *tp)
  3926. {
  3927. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  3928. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  3929. u32 nvaccess = tr32(NVRAM_ACCESS);
  3930. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  3931. }
  3932. }
  3933. /* tp->lock is held. */
  3934. static void tg3_disable_nvram_access(struct tg3 *tp)
  3935. {
  3936. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  3937. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  3938. u32 nvaccess = tr32(NVRAM_ACCESS);
  3939. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  3940. }
  3941. }
  3942. /* tp->lock is held. */
  3943. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  3944. {
  3945. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  3946. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  3947. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  3948. switch (kind) {
  3949. case RESET_KIND_INIT:
  3950. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3951. DRV_STATE_START);
  3952. break;
  3953. case RESET_KIND_SHUTDOWN:
  3954. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3955. DRV_STATE_UNLOAD);
  3956. break;
  3957. case RESET_KIND_SUSPEND:
  3958. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3959. DRV_STATE_SUSPEND);
  3960. break;
  3961. default:
  3962. break;
  3963. };
  3964. }
  3965. }
  3966. /* tp->lock is held. */
  3967. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  3968. {
  3969. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  3970. switch (kind) {
  3971. case RESET_KIND_INIT:
  3972. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3973. DRV_STATE_START_DONE);
  3974. break;
  3975. case RESET_KIND_SHUTDOWN:
  3976. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3977. DRV_STATE_UNLOAD_DONE);
  3978. break;
  3979. default:
  3980. break;
  3981. };
  3982. }
  3983. }
  3984. /* tp->lock is held. */
  3985. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  3986. {
  3987. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  3988. switch (kind) {
  3989. case RESET_KIND_INIT:
  3990. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3991. DRV_STATE_START);
  3992. break;
  3993. case RESET_KIND_SHUTDOWN:
  3994. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3995. DRV_STATE_UNLOAD);
  3996. break;
  3997. case RESET_KIND_SUSPEND:
  3998. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3999. DRV_STATE_SUSPEND);
  4000. break;
  4001. default:
  4002. break;
  4003. };
  4004. }
  4005. }
  4006. static int tg3_poll_fw(struct tg3 *tp)
  4007. {
  4008. int i;
  4009. u32 val;
  4010. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4011. /* Wait up to 20ms for init done. */
  4012. for (i = 0; i < 200; i++) {
  4013. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  4014. return 0;
  4015. udelay(100);
  4016. }
  4017. return -ENODEV;
  4018. }
  4019. /* Wait for firmware initialization to complete. */
  4020. for (i = 0; i < 100000; i++) {
  4021. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  4022. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  4023. break;
  4024. udelay(10);
  4025. }
  4026. /* Chip might not be fitted with firmware. Some Sun onboard
  4027. * parts are configured like that. So don't signal the timeout
  4028. * of the above loop as an error, but do report the lack of
  4029. * running firmware once.
  4030. */
  4031. if (i >= 100000 &&
  4032. !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
  4033. tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
  4034. printk(KERN_INFO PFX "%s: No firmware running.\n",
  4035. tp->dev->name);
  4036. }
  4037. return 0;
  4038. }
  4039. static void tg3_stop_fw(struct tg3 *);
  4040. /* tp->lock is held. */
  4041. static int tg3_chip_reset(struct tg3 *tp)
  4042. {
  4043. u32 val;
  4044. void (*write_op)(struct tg3 *, u32, u32);
  4045. int err;
  4046. tg3_nvram_lock(tp);
  4047. /* No matching tg3_nvram_unlock() after this because
  4048. * chip reset below will undo the nvram lock.
  4049. */
  4050. tp->nvram_lock_cnt = 0;
  4051. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  4052. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  4053. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  4054. tw32(GRC_FASTBOOT_PC, 0);
  4055. /*
  4056. * We must avoid the readl() that normally takes place.
  4057. * It locks machines, causes machine checks, and other
  4058. * fun things. So, temporarily disable the 5701
  4059. * hardware workaround, while we do the reset.
  4060. */
  4061. write_op = tp->write32;
  4062. if (write_op == tg3_write_flush_reg32)
  4063. tp->write32 = tg3_write32;
  4064. /* Prevent the irq handler from reading or writing PCI registers
  4065. * during chip reset when the memory enable bit in the PCI command
  4066. * register may be cleared. The chip does not generate interrupt
  4067. * at this time, but the irq handler may still be called due to irq
  4068. * sharing or irqpoll.
  4069. */
  4070. tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
  4071. if (tp->hw_status) {
  4072. tp->hw_status->status = 0;
  4073. tp->hw_status->status_tag = 0;
  4074. }
  4075. tp->last_tag = 0;
  4076. smp_mb();
  4077. synchronize_irq(tp->pdev->irq);
  4078. /* do the reset */
  4079. val = GRC_MISC_CFG_CORECLK_RESET;
  4080. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4081. if (tr32(0x7e2c) == 0x60) {
  4082. tw32(0x7e2c, 0x20);
  4083. }
  4084. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4085. tw32(GRC_MISC_CFG, (1 << 29));
  4086. val |= (1 << 29);
  4087. }
  4088. }
  4089. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4090. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  4091. tw32(GRC_VCPU_EXT_CTRL,
  4092. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  4093. }
  4094. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4095. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  4096. tw32(GRC_MISC_CFG, val);
  4097. /* restore 5701 hardware bug workaround write method */
  4098. tp->write32 = write_op;
  4099. /* Unfortunately, we have to delay before the PCI read back.
  4100. * Some 575X chips even will not respond to a PCI cfg access
  4101. * when the reset command is given to the chip.
  4102. *
  4103. * How do these hardware designers expect things to work
  4104. * properly if the PCI write is posted for a long period
  4105. * of time? It is always necessary to have some method by
  4106. * which a register read back can occur to push the write
  4107. * out which does the reset.
  4108. *
  4109. * For most tg3 variants the trick below was working.
  4110. * Ho hum...
  4111. */
  4112. udelay(120);
  4113. /* Flush PCI posted writes. The normal MMIO registers
  4114. * are inaccessible at this time so this is the only
  4115. * way to make this reliably (actually, this is no longer
  4116. * the case, see above). I tried to use indirect
  4117. * register read/write but this upset some 5701 variants.
  4118. */
  4119. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  4120. udelay(120);
  4121. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4122. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  4123. int i;
  4124. u32 cfg_val;
  4125. /* Wait for link training to complete. */
  4126. for (i = 0; i < 5000; i++)
  4127. udelay(100);
  4128. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  4129. pci_write_config_dword(tp->pdev, 0xc4,
  4130. cfg_val | (1 << 15));
  4131. }
  4132. /* Set PCIE max payload size and clear error status. */
  4133. pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
  4134. }
  4135. /* Re-enable indirect register accesses. */
  4136. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  4137. tp->misc_host_ctrl);
  4138. /* Set MAX PCI retry to zero. */
  4139. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  4140. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  4141. (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  4142. val |= PCISTATE_RETRY_SAME_DMA;
  4143. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  4144. pci_restore_state(tp->pdev);
  4145. tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
  4146. /* Make sure PCI-X relaxed ordering bit is clear. */
  4147. pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
  4148. val &= ~PCIX_CAPS_RELAXED_ORDERING;
  4149. pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
  4150. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  4151. u32 val;
  4152. /* Chip reset on 5780 will reset MSI enable bit,
  4153. * so need to restore it.
  4154. */
  4155. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  4156. u16 ctrl;
  4157. pci_read_config_word(tp->pdev,
  4158. tp->msi_cap + PCI_MSI_FLAGS,
  4159. &ctrl);
  4160. pci_write_config_word(tp->pdev,
  4161. tp->msi_cap + PCI_MSI_FLAGS,
  4162. ctrl | PCI_MSI_FLAGS_ENABLE);
  4163. val = tr32(MSGINT_MODE);
  4164. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  4165. }
  4166. val = tr32(MEMARB_MODE);
  4167. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  4168. } else
  4169. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  4170. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  4171. tg3_stop_fw(tp);
  4172. tw32(0x5000, 0x400);
  4173. }
  4174. tw32(GRC_MODE, tp->grc_mode);
  4175. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  4176. u32 val = tr32(0xc4);
  4177. tw32(0xc4, val | (1 << 15));
  4178. }
  4179. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  4180. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  4181. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  4182. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  4183. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  4184. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  4185. }
  4186. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  4187. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  4188. tw32_f(MAC_MODE, tp->mac_mode);
  4189. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  4190. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  4191. tw32_f(MAC_MODE, tp->mac_mode);
  4192. } else
  4193. tw32_f(MAC_MODE, 0);
  4194. udelay(40);
  4195. err = tg3_poll_fw(tp);
  4196. if (err)
  4197. return err;
  4198. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  4199. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4200. u32 val = tr32(0x7c00);
  4201. tw32(0x7c00, val | (1 << 25));
  4202. }
  4203. /* Reprobe ASF enable state. */
  4204. tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
  4205. tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
  4206. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  4207. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  4208. u32 nic_cfg;
  4209. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  4210. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  4211. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  4212. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  4213. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  4214. }
  4215. }
  4216. return 0;
  4217. }
  4218. /* tp->lock is held. */
  4219. static void tg3_stop_fw(struct tg3 *tp)
  4220. {
  4221. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  4222. u32 val;
  4223. int i;
  4224. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  4225. val = tr32(GRC_RX_CPU_EVENT);
  4226. val |= (1 << 14);
  4227. tw32(GRC_RX_CPU_EVENT, val);
  4228. /* Wait for RX cpu to ACK the event. */
  4229. for (i = 0; i < 100; i++) {
  4230. if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
  4231. break;
  4232. udelay(1);
  4233. }
  4234. }
  4235. }
  4236. /* tp->lock is held. */
  4237. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  4238. {
  4239. int err;
  4240. tg3_stop_fw(tp);
  4241. tg3_write_sig_pre_reset(tp, kind);
  4242. tg3_abort_hw(tp, silent);
  4243. err = tg3_chip_reset(tp);
  4244. tg3_write_sig_legacy(tp, kind);
  4245. tg3_write_sig_post_reset(tp, kind);
  4246. if (err)
  4247. return err;
  4248. return 0;
  4249. }
  4250. #define TG3_FW_RELEASE_MAJOR 0x0
  4251. #define TG3_FW_RELASE_MINOR 0x0
  4252. #define TG3_FW_RELEASE_FIX 0x0
  4253. #define TG3_FW_START_ADDR 0x08000000
  4254. #define TG3_FW_TEXT_ADDR 0x08000000
  4255. #define TG3_FW_TEXT_LEN 0x9c0
  4256. #define TG3_FW_RODATA_ADDR 0x080009c0
  4257. #define TG3_FW_RODATA_LEN 0x60
  4258. #define TG3_FW_DATA_ADDR 0x08000a40
  4259. #define TG3_FW_DATA_LEN 0x20
  4260. #define TG3_FW_SBSS_ADDR 0x08000a60
  4261. #define TG3_FW_SBSS_LEN 0xc
  4262. #define TG3_FW_BSS_ADDR 0x08000a70
  4263. #define TG3_FW_BSS_LEN 0x10
  4264. static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
  4265. 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  4266. 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
  4267. 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
  4268. 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
  4269. 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
  4270. 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
  4271. 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
  4272. 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
  4273. 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
  4274. 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
  4275. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
  4276. 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
  4277. 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
  4278. 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
  4279. 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
  4280. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  4281. 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
  4282. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
  4283. 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
  4284. 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  4285. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
  4286. 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
  4287. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  4288. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4289. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4290. 0, 0, 0, 0, 0, 0,
  4291. 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
  4292. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4293. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4294. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4295. 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
  4296. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
  4297. 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
  4298. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
  4299. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4300. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4301. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
  4302. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4303. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4304. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4305. 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
  4306. 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
  4307. 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
  4308. 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
  4309. 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
  4310. 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
  4311. 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
  4312. 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
  4313. 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
  4314. 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
  4315. 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
  4316. 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
  4317. 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
  4318. 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
  4319. 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
  4320. 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
  4321. 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
  4322. 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
  4323. 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
  4324. 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
  4325. 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
  4326. 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
  4327. 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
  4328. 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
  4329. 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
  4330. 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
  4331. 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
  4332. 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
  4333. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
  4334. 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
  4335. 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
  4336. 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
  4337. 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
  4338. 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
  4339. 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
  4340. 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
  4341. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
  4342. 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
  4343. 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
  4344. 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
  4345. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
  4346. 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
  4347. 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
  4348. 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
  4349. 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
  4350. 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
  4351. 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
  4352. 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
  4353. 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
  4354. 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
  4355. 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
  4356. };
  4357. static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
  4358. 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
  4359. 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
  4360. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  4361. 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
  4362. 0x00000000
  4363. };
  4364. #if 0 /* All zeros, don't eat up space with it. */
  4365. u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
  4366. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  4367. 0x00000000, 0x00000000, 0x00000000, 0x00000000
  4368. };
  4369. #endif
  4370. #define RX_CPU_SCRATCH_BASE 0x30000
  4371. #define RX_CPU_SCRATCH_SIZE 0x04000
  4372. #define TX_CPU_SCRATCH_BASE 0x34000
  4373. #define TX_CPU_SCRATCH_SIZE 0x04000
  4374. /* tp->lock is held. */
  4375. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  4376. {
  4377. int i;
  4378. BUG_ON(offset == TX_CPU_BASE &&
  4379. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
  4380. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4381. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  4382. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  4383. return 0;
  4384. }
  4385. if (offset == RX_CPU_BASE) {
  4386. for (i = 0; i < 10000; i++) {
  4387. tw32(offset + CPU_STATE, 0xffffffff);
  4388. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4389. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4390. break;
  4391. }
  4392. tw32(offset + CPU_STATE, 0xffffffff);
  4393. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  4394. udelay(10);
  4395. } else {
  4396. for (i = 0; i < 10000; i++) {
  4397. tw32(offset + CPU_STATE, 0xffffffff);
  4398. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4399. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4400. break;
  4401. }
  4402. }
  4403. if (i >= 10000) {
  4404. printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
  4405. "and %s CPU\n",
  4406. tp->dev->name,
  4407. (offset == RX_CPU_BASE ? "RX" : "TX"));
  4408. return -ENODEV;
  4409. }
  4410. /* Clear firmware's nvram arbitration. */
  4411. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  4412. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  4413. return 0;
  4414. }
  4415. struct fw_info {
  4416. unsigned int text_base;
  4417. unsigned int text_len;
  4418. const u32 *text_data;
  4419. unsigned int rodata_base;
  4420. unsigned int rodata_len;
  4421. const u32 *rodata_data;
  4422. unsigned int data_base;
  4423. unsigned int data_len;
  4424. const u32 *data_data;
  4425. };
  4426. /* tp->lock is held. */
  4427. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  4428. int cpu_scratch_size, struct fw_info *info)
  4429. {
  4430. int err, lock_err, i;
  4431. void (*write_op)(struct tg3 *, u32, u32);
  4432. if (cpu_base == TX_CPU_BASE &&
  4433. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  4434. printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
  4435. "TX cpu firmware on %s which is 5705.\n",
  4436. tp->dev->name);
  4437. return -EINVAL;
  4438. }
  4439. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4440. write_op = tg3_write_mem;
  4441. else
  4442. write_op = tg3_write_indirect_reg32;
  4443. /* It is possible that bootcode is still loading at this point.
  4444. * Get the nvram lock first before halting the cpu.
  4445. */
  4446. lock_err = tg3_nvram_lock(tp);
  4447. err = tg3_halt_cpu(tp, cpu_base);
  4448. if (!lock_err)
  4449. tg3_nvram_unlock(tp);
  4450. if (err)
  4451. goto out;
  4452. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  4453. write_op(tp, cpu_scratch_base + i, 0);
  4454. tw32(cpu_base + CPU_STATE, 0xffffffff);
  4455. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  4456. for (i = 0; i < (info->text_len / sizeof(u32)); i++)
  4457. write_op(tp, (cpu_scratch_base +
  4458. (info->text_base & 0xffff) +
  4459. (i * sizeof(u32))),
  4460. (info->text_data ?
  4461. info->text_data[i] : 0));
  4462. for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
  4463. write_op(tp, (cpu_scratch_base +
  4464. (info->rodata_base & 0xffff) +
  4465. (i * sizeof(u32))),
  4466. (info->rodata_data ?
  4467. info->rodata_data[i] : 0));
  4468. for (i = 0; i < (info->data_len / sizeof(u32)); i++)
  4469. write_op(tp, (cpu_scratch_base +
  4470. (info->data_base & 0xffff) +
  4471. (i * sizeof(u32))),
  4472. (info->data_data ?
  4473. info->data_data[i] : 0));
  4474. err = 0;
  4475. out:
  4476. return err;
  4477. }
  4478. /* tp->lock is held. */
  4479. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  4480. {
  4481. struct fw_info info;
  4482. int err, i;
  4483. info.text_base = TG3_FW_TEXT_ADDR;
  4484. info.text_len = TG3_FW_TEXT_LEN;
  4485. info.text_data = &tg3FwText[0];
  4486. info.rodata_base = TG3_FW_RODATA_ADDR;
  4487. info.rodata_len = TG3_FW_RODATA_LEN;
  4488. info.rodata_data = &tg3FwRodata[0];
  4489. info.data_base = TG3_FW_DATA_ADDR;
  4490. info.data_len = TG3_FW_DATA_LEN;
  4491. info.data_data = NULL;
  4492. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  4493. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  4494. &info);
  4495. if (err)
  4496. return err;
  4497. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  4498. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  4499. &info);
  4500. if (err)
  4501. return err;
  4502. /* Now startup only the RX cpu. */
  4503. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4504. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4505. for (i = 0; i < 5; i++) {
  4506. if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
  4507. break;
  4508. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4509. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  4510. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4511. udelay(1000);
  4512. }
  4513. if (i >= 5) {
  4514. printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
  4515. "to set RX CPU PC, is %08x should be %08x\n",
  4516. tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
  4517. TG3_FW_TEXT_ADDR);
  4518. return -ENODEV;
  4519. }
  4520. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4521. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  4522. return 0;
  4523. }
  4524. #define TG3_TSO_FW_RELEASE_MAJOR 0x1
  4525. #define TG3_TSO_FW_RELASE_MINOR 0x6
  4526. #define TG3_TSO_FW_RELEASE_FIX 0x0
  4527. #define TG3_TSO_FW_START_ADDR 0x08000000
  4528. #define TG3_TSO_FW_TEXT_ADDR 0x08000000
  4529. #define TG3_TSO_FW_TEXT_LEN 0x1aa0
  4530. #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
  4531. #define TG3_TSO_FW_RODATA_LEN 0x60
  4532. #define TG3_TSO_FW_DATA_ADDR 0x08001b20
  4533. #define TG3_TSO_FW_DATA_LEN 0x30
  4534. #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
  4535. #define TG3_TSO_FW_SBSS_LEN 0x2c
  4536. #define TG3_TSO_FW_BSS_ADDR 0x08001b80
  4537. #define TG3_TSO_FW_BSS_LEN 0x894
  4538. static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
  4539. 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
  4540. 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
  4541. 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  4542. 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
  4543. 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
  4544. 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
  4545. 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
  4546. 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
  4547. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
  4548. 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
  4549. 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
  4550. 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
  4551. 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
  4552. 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
  4553. 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
  4554. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
  4555. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
  4556. 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
  4557. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  4558. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
  4559. 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
  4560. 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
  4561. 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
  4562. 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
  4563. 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
  4564. 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
  4565. 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
  4566. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
  4567. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
  4568. 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  4569. 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
  4570. 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
  4571. 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
  4572. 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
  4573. 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
  4574. 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
  4575. 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
  4576. 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
  4577. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  4578. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
  4579. 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
  4580. 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
  4581. 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
  4582. 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
  4583. 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
  4584. 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
  4585. 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
  4586. 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  4587. 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
  4588. 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  4589. 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
  4590. 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
  4591. 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
  4592. 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
  4593. 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
  4594. 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
  4595. 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
  4596. 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
  4597. 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
  4598. 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
  4599. 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
  4600. 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
  4601. 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
  4602. 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
  4603. 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
  4604. 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
  4605. 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
  4606. 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
  4607. 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
  4608. 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
  4609. 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
  4610. 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
  4611. 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
  4612. 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
  4613. 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
  4614. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
  4615. 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
  4616. 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
  4617. 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
  4618. 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
  4619. 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
  4620. 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
  4621. 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
  4622. 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
  4623. 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
  4624. 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
  4625. 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
  4626. 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
  4627. 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
  4628. 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
  4629. 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
  4630. 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
  4631. 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
  4632. 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
  4633. 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
  4634. 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
  4635. 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
  4636. 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
  4637. 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
  4638. 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
  4639. 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
  4640. 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
  4641. 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
  4642. 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
  4643. 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
  4644. 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
  4645. 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
  4646. 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
  4647. 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
  4648. 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
  4649. 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
  4650. 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
  4651. 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
  4652. 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
  4653. 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
  4654. 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
  4655. 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
  4656. 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
  4657. 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
  4658. 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
  4659. 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
  4660. 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
  4661. 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
  4662. 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
  4663. 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
  4664. 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
  4665. 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
  4666. 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
  4667. 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
  4668. 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
  4669. 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
  4670. 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
  4671. 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
  4672. 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
  4673. 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
  4674. 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
  4675. 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
  4676. 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
  4677. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  4678. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
  4679. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
  4680. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
  4681. 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
  4682. 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
  4683. 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
  4684. 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
  4685. 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
  4686. 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
  4687. 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
  4688. 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
  4689. 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
  4690. 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
  4691. 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
  4692. 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
  4693. 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
  4694. 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
  4695. 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
  4696. 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
  4697. 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
  4698. 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
  4699. 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
  4700. 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
  4701. 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
  4702. 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
  4703. 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
  4704. 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
  4705. 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
  4706. 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
  4707. 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
  4708. 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
  4709. 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
  4710. 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
  4711. 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
  4712. 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
  4713. 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
  4714. 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
  4715. 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
  4716. 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
  4717. 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
  4718. 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
  4719. 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
  4720. 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
  4721. 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
  4722. 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
  4723. 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
  4724. 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
  4725. 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
  4726. 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
  4727. 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
  4728. 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
  4729. 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
  4730. 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
  4731. 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
  4732. 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
  4733. 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
  4734. 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
  4735. 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
  4736. 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
  4737. 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
  4738. 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
  4739. 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
  4740. 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
  4741. 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
  4742. 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
  4743. 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
  4744. 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
  4745. 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
  4746. 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
  4747. 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
  4748. 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
  4749. 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
  4750. 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
  4751. 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
  4752. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
  4753. 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
  4754. 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
  4755. 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
  4756. 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
  4757. 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
  4758. 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
  4759. 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  4760. 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
  4761. 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
  4762. 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
  4763. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
  4764. 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
  4765. 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
  4766. 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
  4767. 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
  4768. 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
  4769. 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
  4770. 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
  4771. 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
  4772. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
  4773. 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
  4774. 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
  4775. 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
  4776. 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  4777. 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
  4778. 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
  4779. 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
  4780. 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
  4781. 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
  4782. 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
  4783. 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
  4784. 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
  4785. 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
  4786. 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
  4787. 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
  4788. 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
  4789. 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
  4790. 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
  4791. 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
  4792. 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
  4793. 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
  4794. 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
  4795. 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
  4796. 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
  4797. 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
  4798. 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
  4799. 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
  4800. 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
  4801. 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
  4802. 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
  4803. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  4804. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
  4805. 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
  4806. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
  4807. 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
  4808. 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
  4809. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
  4810. 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
  4811. 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
  4812. 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
  4813. 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
  4814. 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
  4815. 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
  4816. 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
  4817. 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
  4818. 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
  4819. 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
  4820. 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
  4821. 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
  4822. 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
  4823. };
  4824. static const u32 tg3TsoFwRodata[] = {
  4825. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  4826. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
  4827. 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
  4828. 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
  4829. 0x00000000,
  4830. };
  4831. static const u32 tg3TsoFwData[] = {
  4832. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
  4833. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  4834. 0x00000000,
  4835. };
  4836. /* 5705 needs a special version of the TSO firmware. */
  4837. #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
  4838. #define TG3_TSO5_FW_RELASE_MINOR 0x2
  4839. #define TG3_TSO5_FW_RELEASE_FIX 0x0
  4840. #define TG3_TSO5_FW_START_ADDR 0x00010000
  4841. #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
  4842. #define TG3_TSO5_FW_TEXT_LEN 0xe90
  4843. #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
  4844. #define TG3_TSO5_FW_RODATA_LEN 0x50
  4845. #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
  4846. #define TG3_TSO5_FW_DATA_LEN 0x20
  4847. #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
  4848. #define TG3_TSO5_FW_SBSS_LEN 0x28
  4849. #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
  4850. #define TG3_TSO5_FW_BSS_LEN 0x88
  4851. static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
  4852. 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
  4853. 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
  4854. 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  4855. 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
  4856. 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
  4857. 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
  4858. 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  4859. 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
  4860. 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
  4861. 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
  4862. 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
  4863. 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
  4864. 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
  4865. 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
  4866. 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
  4867. 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
  4868. 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
  4869. 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
  4870. 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
  4871. 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
  4872. 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
  4873. 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
  4874. 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
  4875. 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
  4876. 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
  4877. 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
  4878. 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
  4879. 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
  4880. 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
  4881. 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
  4882. 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  4883. 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
  4884. 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
  4885. 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
  4886. 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
  4887. 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
  4888. 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
  4889. 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
  4890. 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
  4891. 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
  4892. 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
  4893. 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
  4894. 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
  4895. 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
  4896. 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
  4897. 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
  4898. 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
  4899. 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
  4900. 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
  4901. 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
  4902. 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
  4903. 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
  4904. 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
  4905. 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
  4906. 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
  4907. 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
  4908. 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
  4909. 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
  4910. 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
  4911. 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
  4912. 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
  4913. 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
  4914. 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
  4915. 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
  4916. 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
  4917. 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
  4918. 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  4919. 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
  4920. 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
  4921. 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
  4922. 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
  4923. 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
  4924. 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
  4925. 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
  4926. 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
  4927. 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
  4928. 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
  4929. 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
  4930. 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
  4931. 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
  4932. 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
  4933. 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
  4934. 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
  4935. 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
  4936. 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
  4937. 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
  4938. 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
  4939. 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
  4940. 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
  4941. 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
  4942. 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
  4943. 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
  4944. 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
  4945. 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
  4946. 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
  4947. 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
  4948. 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
  4949. 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
  4950. 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
  4951. 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
  4952. 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
  4953. 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
  4954. 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
  4955. 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
  4956. 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
  4957. 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
  4958. 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  4959. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  4960. 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
  4961. 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
  4962. 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
  4963. 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
  4964. 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
  4965. 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
  4966. 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
  4967. 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
  4968. 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
  4969. 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  4970. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  4971. 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
  4972. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
  4973. 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  4974. 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
  4975. 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  4976. 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
  4977. 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
  4978. 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
  4979. 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
  4980. 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
  4981. 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
  4982. 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
  4983. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
  4984. 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
  4985. 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
  4986. 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
  4987. 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
  4988. 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
  4989. 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
  4990. 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
  4991. 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
  4992. 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
  4993. 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
  4994. 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
  4995. 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
  4996. 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
  4997. 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
  4998. 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
  4999. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  5000. 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
  5001. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
  5002. 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
  5003. 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  5004. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
  5005. 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  5006. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  5007. 0x00000000, 0x00000000, 0x00000000,
  5008. };
  5009. static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
  5010. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  5011. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
  5012. 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  5013. 0x00000000, 0x00000000, 0x00000000,
  5014. };
  5015. static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
  5016. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
  5017. 0x00000000, 0x00000000, 0x00000000,
  5018. };
  5019. /* tp->lock is held. */
  5020. static int tg3_load_tso_firmware(struct tg3 *tp)
  5021. {
  5022. struct fw_info info;
  5023. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  5024. int err, i;
  5025. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5026. return 0;
  5027. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5028. info.text_base = TG3_TSO5_FW_TEXT_ADDR;
  5029. info.text_len = TG3_TSO5_FW_TEXT_LEN;
  5030. info.text_data = &tg3Tso5FwText[0];
  5031. info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
  5032. info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
  5033. info.rodata_data = &tg3Tso5FwRodata[0];
  5034. info.data_base = TG3_TSO5_FW_DATA_ADDR;
  5035. info.data_len = TG3_TSO5_FW_DATA_LEN;
  5036. info.data_data = &tg3Tso5FwData[0];
  5037. cpu_base = RX_CPU_BASE;
  5038. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  5039. cpu_scratch_size = (info.text_len +
  5040. info.rodata_len +
  5041. info.data_len +
  5042. TG3_TSO5_FW_SBSS_LEN +
  5043. TG3_TSO5_FW_BSS_LEN);
  5044. } else {
  5045. info.text_base = TG3_TSO_FW_TEXT_ADDR;
  5046. info.text_len = TG3_TSO_FW_TEXT_LEN;
  5047. info.text_data = &tg3TsoFwText[0];
  5048. info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  5049. info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  5050. info.rodata_data = &tg3TsoFwRodata[0];
  5051. info.data_base = TG3_TSO_FW_DATA_ADDR;
  5052. info.data_len = TG3_TSO_FW_DATA_LEN;
  5053. info.data_data = &tg3TsoFwData[0];
  5054. cpu_base = TX_CPU_BASE;
  5055. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  5056. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  5057. }
  5058. err = tg3_load_firmware_cpu(tp, cpu_base,
  5059. cpu_scratch_base, cpu_scratch_size,
  5060. &info);
  5061. if (err)
  5062. return err;
  5063. /* Now startup the cpu. */
  5064. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5065. tw32_f(cpu_base + CPU_PC, info.text_base);
  5066. for (i = 0; i < 5; i++) {
  5067. if (tr32(cpu_base + CPU_PC) == info.text_base)
  5068. break;
  5069. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5070. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  5071. tw32_f(cpu_base + CPU_PC, info.text_base);
  5072. udelay(1000);
  5073. }
  5074. if (i >= 5) {
  5075. printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  5076. "to set CPU PC, is %08x should be %08x\n",
  5077. tp->dev->name, tr32(cpu_base + CPU_PC),
  5078. info.text_base);
  5079. return -ENODEV;
  5080. }
  5081. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5082. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  5083. return 0;
  5084. }
  5085. /* tp->lock is held. */
  5086. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  5087. {
  5088. u32 addr_high, addr_low;
  5089. int i;
  5090. addr_high = ((tp->dev->dev_addr[0] << 8) |
  5091. tp->dev->dev_addr[1]);
  5092. addr_low = ((tp->dev->dev_addr[2] << 24) |
  5093. (tp->dev->dev_addr[3] << 16) |
  5094. (tp->dev->dev_addr[4] << 8) |
  5095. (tp->dev->dev_addr[5] << 0));
  5096. for (i = 0; i < 4; i++) {
  5097. if (i == 1 && skip_mac_1)
  5098. continue;
  5099. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  5100. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  5101. }
  5102. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  5103. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5104. for (i = 0; i < 12; i++) {
  5105. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  5106. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  5107. }
  5108. }
  5109. addr_high = (tp->dev->dev_addr[0] +
  5110. tp->dev->dev_addr[1] +
  5111. tp->dev->dev_addr[2] +
  5112. tp->dev->dev_addr[3] +
  5113. tp->dev->dev_addr[4] +
  5114. tp->dev->dev_addr[5]) &
  5115. TX_BACKOFF_SEED_MASK;
  5116. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  5117. }
  5118. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  5119. {
  5120. struct tg3 *tp = netdev_priv(dev);
  5121. struct sockaddr *addr = p;
  5122. int err = 0, skip_mac_1 = 0;
  5123. if (!is_valid_ether_addr(addr->sa_data))
  5124. return -EINVAL;
  5125. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  5126. if (!netif_running(dev))
  5127. return 0;
  5128. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5129. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  5130. addr0_high = tr32(MAC_ADDR_0_HIGH);
  5131. addr0_low = tr32(MAC_ADDR_0_LOW);
  5132. addr1_high = tr32(MAC_ADDR_1_HIGH);
  5133. addr1_low = tr32(MAC_ADDR_1_LOW);
  5134. /* Skip MAC addr 1 if ASF is using it. */
  5135. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  5136. !(addr1_high == 0 && addr1_low == 0))
  5137. skip_mac_1 = 1;
  5138. }
  5139. spin_lock_bh(&tp->lock);
  5140. __tg3_set_mac_addr(tp, skip_mac_1);
  5141. spin_unlock_bh(&tp->lock);
  5142. return err;
  5143. }
  5144. /* tp->lock is held. */
  5145. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  5146. dma_addr_t mapping, u32 maxlen_flags,
  5147. u32 nic_addr)
  5148. {
  5149. tg3_write_mem(tp,
  5150. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  5151. ((u64) mapping >> 32));
  5152. tg3_write_mem(tp,
  5153. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  5154. ((u64) mapping & 0xffffffff));
  5155. tg3_write_mem(tp,
  5156. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  5157. maxlen_flags);
  5158. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5159. tg3_write_mem(tp,
  5160. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  5161. nic_addr);
  5162. }
  5163. static void __tg3_set_rx_mode(struct net_device *);
  5164. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  5165. {
  5166. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  5167. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  5168. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  5169. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  5170. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5171. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  5172. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  5173. }
  5174. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  5175. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  5176. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5177. u32 val = ec->stats_block_coalesce_usecs;
  5178. if (!netif_carrier_ok(tp->dev))
  5179. val = 0;
  5180. tw32(HOSTCC_STAT_COAL_TICKS, val);
  5181. }
  5182. }
  5183. /* tp->lock is held. */
  5184. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  5185. {
  5186. u32 val, rdmac_mode;
  5187. int i, err, limit;
  5188. tg3_disable_ints(tp);
  5189. tg3_stop_fw(tp);
  5190. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  5191. if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  5192. tg3_abort_hw(tp, 1);
  5193. }
  5194. if (reset_phy)
  5195. tg3_phy_reset(tp);
  5196. err = tg3_chip_reset(tp);
  5197. if (err)
  5198. return err;
  5199. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  5200. /* This works around an issue with Athlon chipsets on
  5201. * B3 tigon3 silicon. This bit has no effect on any
  5202. * other revision. But do not set this on PCI Express
  5203. * chips.
  5204. */
  5205. if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  5206. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  5207. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  5208. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  5209. (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  5210. val = tr32(TG3PCI_PCISTATE);
  5211. val |= PCISTATE_RETRY_SAME_DMA;
  5212. tw32(TG3PCI_PCISTATE, val);
  5213. }
  5214. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  5215. /* Enable some hw fixes. */
  5216. val = tr32(TG3PCI_MSI_DATA);
  5217. val |= (1 << 26) | (1 << 28) | (1 << 29);
  5218. tw32(TG3PCI_MSI_DATA, val);
  5219. }
  5220. /* Descriptor ring init may make accesses to the
  5221. * NIC SRAM area to setup the TX descriptors, so we
  5222. * can only do this after the hardware has been
  5223. * successfully reset.
  5224. */
  5225. err = tg3_init_rings(tp);
  5226. if (err)
  5227. return err;
  5228. /* This value is determined during the probe time DMA
  5229. * engine test, tg3_test_dma.
  5230. */
  5231. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  5232. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  5233. GRC_MODE_4X_NIC_SEND_RINGS |
  5234. GRC_MODE_NO_TX_PHDR_CSUM |
  5235. GRC_MODE_NO_RX_PHDR_CSUM);
  5236. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  5237. /* Pseudo-header checksum is done by hardware logic and not
  5238. * the offload processers, so make the chip do the pseudo-
  5239. * header checksums on receive. For transmit it is more
  5240. * convenient to do the pseudo-header checksum in software
  5241. * as Linux does that on transmit for us in all cases.
  5242. */
  5243. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  5244. tw32(GRC_MODE,
  5245. tp->grc_mode |
  5246. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  5247. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  5248. val = tr32(GRC_MISC_CFG);
  5249. val &= ~0xff;
  5250. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  5251. tw32(GRC_MISC_CFG, val);
  5252. /* Initialize MBUF/DESC pool. */
  5253. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5254. /* Do nothing. */
  5255. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  5256. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  5257. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  5258. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  5259. else
  5260. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  5261. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  5262. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  5263. }
  5264. else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  5265. int fw_len;
  5266. fw_len = (TG3_TSO5_FW_TEXT_LEN +
  5267. TG3_TSO5_FW_RODATA_LEN +
  5268. TG3_TSO5_FW_DATA_LEN +
  5269. TG3_TSO5_FW_SBSS_LEN +
  5270. TG3_TSO5_FW_BSS_LEN);
  5271. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  5272. tw32(BUFMGR_MB_POOL_ADDR,
  5273. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  5274. tw32(BUFMGR_MB_POOL_SIZE,
  5275. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  5276. }
  5277. if (tp->dev->mtu <= ETH_DATA_LEN) {
  5278. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5279. tp->bufmgr_config.mbuf_read_dma_low_water);
  5280. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5281. tp->bufmgr_config.mbuf_mac_rx_low_water);
  5282. tw32(BUFMGR_MB_HIGH_WATER,
  5283. tp->bufmgr_config.mbuf_high_water);
  5284. } else {
  5285. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5286. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  5287. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5288. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  5289. tw32(BUFMGR_MB_HIGH_WATER,
  5290. tp->bufmgr_config.mbuf_high_water_jumbo);
  5291. }
  5292. tw32(BUFMGR_DMA_LOW_WATER,
  5293. tp->bufmgr_config.dma_low_water);
  5294. tw32(BUFMGR_DMA_HIGH_WATER,
  5295. tp->bufmgr_config.dma_high_water);
  5296. tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  5297. for (i = 0; i < 2000; i++) {
  5298. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  5299. break;
  5300. udelay(10);
  5301. }
  5302. if (i >= 2000) {
  5303. printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
  5304. tp->dev->name);
  5305. return -ENODEV;
  5306. }
  5307. /* Setup replenish threshold. */
  5308. val = tp->rx_pending / 8;
  5309. if (val == 0)
  5310. val = 1;
  5311. else if (val > tp->rx_std_max_post)
  5312. val = tp->rx_std_max_post;
  5313. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5314. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  5315. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  5316. if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
  5317. val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
  5318. }
  5319. tw32(RCVBDI_STD_THRESH, val);
  5320. /* Initialize TG3_BDINFO's at:
  5321. * RCVDBDI_STD_BD: standard eth size rx ring
  5322. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  5323. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  5324. *
  5325. * like so:
  5326. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  5327. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  5328. * ring attribute flags
  5329. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  5330. *
  5331. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  5332. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  5333. *
  5334. * The size of each ring is fixed in the firmware, but the location is
  5335. * configurable.
  5336. */
  5337. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5338. ((u64) tp->rx_std_mapping >> 32));
  5339. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5340. ((u64) tp->rx_std_mapping & 0xffffffff));
  5341. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  5342. NIC_SRAM_RX_BUFFER_DESC);
  5343. /* Don't even try to program the JUMBO/MINI buffer descriptor
  5344. * configs on 5705.
  5345. */
  5346. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  5347. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5348. RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
  5349. } else {
  5350. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5351. RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5352. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5353. BDINFO_FLAGS_DISABLED);
  5354. /* Setup replenish threshold. */
  5355. tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  5356. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  5357. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5358. ((u64) tp->rx_jumbo_mapping >> 32));
  5359. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5360. ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  5361. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5362. RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5363. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  5364. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  5365. } else {
  5366. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5367. BDINFO_FLAGS_DISABLED);
  5368. }
  5369. }
  5370. /* There is only one send ring on 5705/5750, no need to explicitly
  5371. * disable the others.
  5372. */
  5373. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5374. /* Clear out send RCB ring in SRAM. */
  5375. for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  5376. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5377. BDINFO_FLAGS_DISABLED);
  5378. }
  5379. tp->tx_prod = 0;
  5380. tp->tx_cons = 0;
  5381. tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5382. tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5383. tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
  5384. tp->tx_desc_mapping,
  5385. (TG3_TX_RING_SIZE <<
  5386. BDINFO_FLAGS_MAXLEN_SHIFT),
  5387. NIC_SRAM_TX_BUFFER_DESC);
  5388. /* There is only one receive return ring on 5705/5750, no need
  5389. * to explicitly disable the others.
  5390. */
  5391. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5392. for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
  5393. i += TG3_BDINFO_SIZE) {
  5394. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5395. BDINFO_FLAGS_DISABLED);
  5396. }
  5397. }
  5398. tp->rx_rcb_ptr = 0;
  5399. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5400. tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
  5401. tp->rx_rcb_mapping,
  5402. (TG3_RX_RCB_RING_SIZE(tp) <<
  5403. BDINFO_FLAGS_MAXLEN_SHIFT),
  5404. 0);
  5405. tp->rx_std_ptr = tp->rx_pending;
  5406. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  5407. tp->rx_std_ptr);
  5408. tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
  5409. tp->rx_jumbo_pending : 0;
  5410. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  5411. tp->rx_jumbo_ptr);
  5412. /* Initialize MAC address and backoff seed. */
  5413. __tg3_set_mac_addr(tp, 0);
  5414. /* MTU + ethernet header + FCS + optional VLAN tag */
  5415. tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
  5416. /* The slot time is changed by tg3_setup_phy if we
  5417. * run at gigabit with half duplex.
  5418. */
  5419. tw32(MAC_TX_LENGTHS,
  5420. (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  5421. (6 << TX_LENGTHS_IPG_SHIFT) |
  5422. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  5423. /* Receive rules. */
  5424. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  5425. tw32(RCVLPC_CONFIG, 0x0181);
  5426. /* Calculate RDMAC_MODE setting early, we need it to determine
  5427. * the RCVLPC_STATE_ENABLE mask.
  5428. */
  5429. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  5430. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  5431. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  5432. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  5433. RDMAC_MODE_LNGREAD_ENAB);
  5434. /* If statement applies to 5705 and 5750 PCI devices only */
  5435. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  5436. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  5437. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  5438. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
  5439. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5440. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  5441. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  5442. !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  5443. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5444. }
  5445. }
  5446. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  5447. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5448. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5449. rdmac_mode |= (1 << 27);
  5450. /* Receive/send statistics. */
  5451. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5452. val = tr32(RCVLPC_STATS_ENABLE);
  5453. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  5454. tw32(RCVLPC_STATS_ENABLE, val);
  5455. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  5456. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  5457. val = tr32(RCVLPC_STATS_ENABLE);
  5458. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  5459. tw32(RCVLPC_STATS_ENABLE, val);
  5460. } else {
  5461. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  5462. }
  5463. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  5464. tw32(SNDDATAI_STATSENAB, 0xffffff);
  5465. tw32(SNDDATAI_STATSCTRL,
  5466. (SNDDATAI_SCTRL_ENABLE |
  5467. SNDDATAI_SCTRL_FASTUPD));
  5468. /* Setup host coalescing engine. */
  5469. tw32(HOSTCC_MODE, 0);
  5470. for (i = 0; i < 2000; i++) {
  5471. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  5472. break;
  5473. udelay(10);
  5474. }
  5475. __tg3_set_coalesce(tp, &tp->coal);
  5476. /* set status block DMA address */
  5477. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5478. ((u64) tp->status_mapping >> 32));
  5479. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5480. ((u64) tp->status_mapping & 0xffffffff));
  5481. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5482. /* Status/statistics block address. See tg3_timer,
  5483. * the tg3_periodic_fetch_stats call there, and
  5484. * tg3_get_stats to see how this works for 5705/5750 chips.
  5485. */
  5486. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5487. ((u64) tp->stats_mapping >> 32));
  5488. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5489. ((u64) tp->stats_mapping & 0xffffffff));
  5490. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  5491. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  5492. }
  5493. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  5494. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  5495. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  5496. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5497. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  5498. /* Clear statistics/status block in chip, and status block in ram. */
  5499. for (i = NIC_SRAM_STATS_BLK;
  5500. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  5501. i += sizeof(u32)) {
  5502. tg3_write_mem(tp, i, 0);
  5503. udelay(40);
  5504. }
  5505. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  5506. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  5507. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  5508. /* reset to prevent losing 1st rx packet intermittently */
  5509. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5510. udelay(10);
  5511. }
  5512. tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  5513. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  5514. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  5515. udelay(40);
  5516. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  5517. * If TG3_FLG2_IS_NIC is zero, we should read the
  5518. * register to preserve the GPIO settings for LOMs. The GPIOs,
  5519. * whether used as inputs or outputs, are set by boot code after
  5520. * reset.
  5521. */
  5522. if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
  5523. u32 gpio_mask;
  5524. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  5525. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  5526. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  5527. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  5528. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  5529. GRC_LCLCTRL_GPIO_OUTPUT3;
  5530. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  5531. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  5532. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  5533. /* GPIO1 must be driven high for eeprom write protect */
  5534. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
  5535. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  5536. GRC_LCLCTRL_GPIO_OUTPUT1);
  5537. }
  5538. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  5539. udelay(100);
  5540. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
  5541. tp->last_tag = 0;
  5542. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5543. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  5544. udelay(40);
  5545. }
  5546. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  5547. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  5548. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  5549. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  5550. WDMAC_MODE_LNGREAD_ENAB);
  5551. /* If statement applies to 5705 and 5750 PCI devices only */
  5552. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  5553. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  5554. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
  5555. if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
  5556. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  5557. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  5558. /* nothing */
  5559. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  5560. !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  5561. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  5562. val |= WDMAC_MODE_RX_ACCEL;
  5563. }
  5564. }
  5565. /* Enable host coalescing bug fix */
  5566. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
  5567. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
  5568. val |= (1 << 29);
  5569. tw32_f(WDMAC_MODE, val);
  5570. udelay(40);
  5571. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
  5572. val = tr32(TG3PCI_X_CAPS);
  5573. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  5574. val &= ~PCIX_CAPS_BURST_MASK;
  5575. val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
  5576. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5577. val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
  5578. val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
  5579. }
  5580. tw32(TG3PCI_X_CAPS, val);
  5581. }
  5582. tw32_f(RDMAC_MODE, rdmac_mode);
  5583. udelay(40);
  5584. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  5585. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5586. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  5587. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  5588. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  5589. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  5590. tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  5591. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  5592. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5593. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  5594. tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
  5595. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  5596. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  5597. err = tg3_load_5701_a0_firmware_fix(tp);
  5598. if (err)
  5599. return err;
  5600. }
  5601. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  5602. err = tg3_load_tso_firmware(tp);
  5603. if (err)
  5604. return err;
  5605. }
  5606. tp->tx_mode = TX_MODE_ENABLE;
  5607. tw32_f(MAC_TX_MODE, tp->tx_mode);
  5608. udelay(100);
  5609. tp->rx_mode = RX_MODE_ENABLE;
  5610. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  5611. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  5612. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5613. udelay(10);
  5614. if (tp->link_config.phy_is_low_power) {
  5615. tp->link_config.phy_is_low_power = 0;
  5616. tp->link_config.speed = tp->link_config.orig_speed;
  5617. tp->link_config.duplex = tp->link_config.orig_duplex;
  5618. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  5619. }
  5620. tp->mi_mode = MAC_MI_MODE_BASE;
  5621. tw32_f(MAC_MI_MODE, tp->mi_mode);
  5622. udelay(80);
  5623. tw32(MAC_LED_CTRL, tp->led_ctrl);
  5624. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  5625. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  5626. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5627. udelay(10);
  5628. }
  5629. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5630. udelay(10);
  5631. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  5632. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  5633. !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
  5634. /* Set drive transmission level to 1.2V */
  5635. /* only if the signal pre-emphasis bit is not set */
  5636. val = tr32(MAC_SERDES_CFG);
  5637. val &= 0xfffff000;
  5638. val |= 0x880;
  5639. tw32(MAC_SERDES_CFG, val);
  5640. }
  5641. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  5642. tw32(MAC_SERDES_CFG, 0x616000);
  5643. }
  5644. /* Prevent chip from dropping frames when flow control
  5645. * is enabled.
  5646. */
  5647. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
  5648. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  5649. (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  5650. /* Use hardware link auto-negotiation */
  5651. tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
  5652. }
  5653. if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
  5654. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  5655. u32 tmp;
  5656. tmp = tr32(SERDES_RX_CTRL);
  5657. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  5658. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  5659. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  5660. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  5661. }
  5662. err = tg3_setup_phy(tp, 0);
  5663. if (err)
  5664. return err;
  5665. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  5666. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
  5667. u32 tmp;
  5668. /* Clear CRC stats. */
  5669. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  5670. tg3_writephy(tp, MII_TG3_TEST1,
  5671. tmp | MII_TG3_TEST1_CRC_EN);
  5672. tg3_readphy(tp, 0x14, &tmp);
  5673. }
  5674. }
  5675. __tg3_set_rx_mode(tp->dev);
  5676. /* Initialize receive rules. */
  5677. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  5678. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  5679. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  5680. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  5681. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  5682. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  5683. limit = 8;
  5684. else
  5685. limit = 16;
  5686. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  5687. limit -= 4;
  5688. switch (limit) {
  5689. case 16:
  5690. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  5691. case 15:
  5692. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  5693. case 14:
  5694. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  5695. case 13:
  5696. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  5697. case 12:
  5698. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  5699. case 11:
  5700. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  5701. case 10:
  5702. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  5703. case 9:
  5704. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  5705. case 8:
  5706. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  5707. case 7:
  5708. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  5709. case 6:
  5710. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  5711. case 5:
  5712. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  5713. case 4:
  5714. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  5715. case 3:
  5716. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  5717. case 2:
  5718. case 1:
  5719. default:
  5720. break;
  5721. };
  5722. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  5723. return 0;
  5724. }
  5725. /* Called at device open time to get the chip ready for
  5726. * packet processing. Invoked with tp->lock held.
  5727. */
  5728. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  5729. {
  5730. int err;
  5731. /* Force the chip into D0. */
  5732. err = tg3_set_power_state(tp, PCI_D0);
  5733. if (err)
  5734. goto out;
  5735. tg3_switch_clocks(tp);
  5736. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  5737. err = tg3_reset_hw(tp, reset_phy);
  5738. out:
  5739. return err;
  5740. }
  5741. #define TG3_STAT_ADD32(PSTAT, REG) \
  5742. do { u32 __val = tr32(REG); \
  5743. (PSTAT)->low += __val; \
  5744. if ((PSTAT)->low < __val) \
  5745. (PSTAT)->high += 1; \
  5746. } while (0)
  5747. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  5748. {
  5749. struct tg3_hw_stats *sp = tp->hw_stats;
  5750. if (!netif_carrier_ok(tp->dev))
  5751. return;
  5752. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  5753. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  5754. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  5755. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  5756. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  5757. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  5758. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  5759. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  5760. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  5761. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  5762. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  5763. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  5764. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  5765. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  5766. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  5767. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  5768. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  5769. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  5770. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  5771. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  5772. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  5773. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  5774. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  5775. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  5776. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  5777. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  5778. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  5779. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  5780. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  5781. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  5782. }
  5783. static void tg3_timer(unsigned long __opaque)
  5784. {
  5785. struct tg3 *tp = (struct tg3 *) __opaque;
  5786. if (tp->irq_sync)
  5787. goto restart_timer;
  5788. spin_lock(&tp->lock);
  5789. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  5790. /* All of this garbage is because when using non-tagged
  5791. * IRQ status the mailbox/status_block protocol the chip
  5792. * uses with the cpu is race prone.
  5793. */
  5794. if (tp->hw_status->status & SD_STATUS_UPDATED) {
  5795. tw32(GRC_LOCAL_CTRL,
  5796. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  5797. } else {
  5798. tw32(HOSTCC_MODE, tp->coalesce_mode |
  5799. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  5800. }
  5801. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  5802. tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  5803. spin_unlock(&tp->lock);
  5804. schedule_work(&tp->reset_task);
  5805. return;
  5806. }
  5807. }
  5808. /* This part only runs once per second. */
  5809. if (!--tp->timer_counter) {
  5810. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  5811. tg3_periodic_fetch_stats(tp);
  5812. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  5813. u32 mac_stat;
  5814. int phy_event;
  5815. mac_stat = tr32(MAC_STATUS);
  5816. phy_event = 0;
  5817. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
  5818. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  5819. phy_event = 1;
  5820. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  5821. phy_event = 1;
  5822. if (phy_event)
  5823. tg3_setup_phy(tp, 0);
  5824. } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  5825. u32 mac_stat = tr32(MAC_STATUS);
  5826. int need_setup = 0;
  5827. if (netif_carrier_ok(tp->dev) &&
  5828. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  5829. need_setup = 1;
  5830. }
  5831. if (! netif_carrier_ok(tp->dev) &&
  5832. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  5833. MAC_STATUS_SIGNAL_DET))) {
  5834. need_setup = 1;
  5835. }
  5836. if (need_setup) {
  5837. if (!tp->serdes_counter) {
  5838. tw32_f(MAC_MODE,
  5839. (tp->mac_mode &
  5840. ~MAC_MODE_PORT_MODE_MASK));
  5841. udelay(40);
  5842. tw32_f(MAC_MODE, tp->mac_mode);
  5843. udelay(40);
  5844. }
  5845. tg3_setup_phy(tp, 0);
  5846. }
  5847. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  5848. tg3_serdes_parallel_detect(tp);
  5849. tp->timer_counter = tp->timer_multiplier;
  5850. }
  5851. /* Heartbeat is only sent once every 2 seconds.
  5852. *
  5853. * The heartbeat is to tell the ASF firmware that the host
  5854. * driver is still alive. In the event that the OS crashes,
  5855. * ASF needs to reset the hardware to free up the FIFO space
  5856. * that may be filled with rx packets destined for the host.
  5857. * If the FIFO is full, ASF will no longer function properly.
  5858. *
  5859. * Unintended resets have been reported on real time kernels
  5860. * where the timer doesn't run on time. Netpoll will also have
  5861. * same problem.
  5862. *
  5863. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  5864. * to check the ring condition when the heartbeat is expiring
  5865. * before doing the reset. This will prevent most unintended
  5866. * resets.
  5867. */
  5868. if (!--tp->asf_counter) {
  5869. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5870. u32 val;
  5871. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  5872. FWCMD_NICDRV_ALIVE3);
  5873. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  5874. /* 5 seconds timeout */
  5875. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
  5876. val = tr32(GRC_RX_CPU_EVENT);
  5877. val |= (1 << 14);
  5878. tw32(GRC_RX_CPU_EVENT, val);
  5879. }
  5880. tp->asf_counter = tp->asf_multiplier;
  5881. }
  5882. spin_unlock(&tp->lock);
  5883. restart_timer:
  5884. tp->timer.expires = jiffies + tp->timer_offset;
  5885. add_timer(&tp->timer);
  5886. }
  5887. static int tg3_request_irq(struct tg3 *tp)
  5888. {
  5889. irq_handler_t fn;
  5890. unsigned long flags;
  5891. struct net_device *dev = tp->dev;
  5892. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  5893. fn = tg3_msi;
  5894. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  5895. fn = tg3_msi_1shot;
  5896. flags = IRQF_SAMPLE_RANDOM;
  5897. } else {
  5898. fn = tg3_interrupt;
  5899. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  5900. fn = tg3_interrupt_tagged;
  5901. flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
  5902. }
  5903. return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
  5904. }
  5905. static int tg3_test_interrupt(struct tg3 *tp)
  5906. {
  5907. struct net_device *dev = tp->dev;
  5908. int err, i, intr_ok = 0;
  5909. if (!netif_running(dev))
  5910. return -ENODEV;
  5911. tg3_disable_ints(tp);
  5912. free_irq(tp->pdev->irq, dev);
  5913. err = request_irq(tp->pdev->irq, tg3_test_isr,
  5914. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
  5915. if (err)
  5916. return err;
  5917. tp->hw_status->status &= ~SD_STATUS_UPDATED;
  5918. tg3_enable_ints(tp);
  5919. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  5920. HOSTCC_MODE_NOW);
  5921. for (i = 0; i < 5; i++) {
  5922. u32 int_mbox, misc_host_ctrl;
  5923. int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
  5924. TG3_64BIT_REG_LOW);
  5925. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  5926. if ((int_mbox != 0) ||
  5927. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  5928. intr_ok = 1;
  5929. break;
  5930. }
  5931. msleep(10);
  5932. }
  5933. tg3_disable_ints(tp);
  5934. free_irq(tp->pdev->irq, dev);
  5935. err = tg3_request_irq(tp);
  5936. if (err)
  5937. return err;
  5938. if (intr_ok)
  5939. return 0;
  5940. return -EIO;
  5941. }
  5942. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  5943. * successfully restored
  5944. */
  5945. static int tg3_test_msi(struct tg3 *tp)
  5946. {
  5947. struct net_device *dev = tp->dev;
  5948. int err;
  5949. u16 pci_cmd;
  5950. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  5951. return 0;
  5952. /* Turn off SERR reporting in case MSI terminates with Master
  5953. * Abort.
  5954. */
  5955. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  5956. pci_write_config_word(tp->pdev, PCI_COMMAND,
  5957. pci_cmd & ~PCI_COMMAND_SERR);
  5958. err = tg3_test_interrupt(tp);
  5959. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  5960. if (!err)
  5961. return 0;
  5962. /* other failures */
  5963. if (err != -EIO)
  5964. return err;
  5965. /* MSI test failed, go back to INTx mode */
  5966. printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
  5967. "switching to INTx mode. Please report this failure to "
  5968. "the PCI maintainer and include system chipset information.\n",
  5969. tp->dev->name);
  5970. free_irq(tp->pdev->irq, dev);
  5971. pci_disable_msi(tp->pdev);
  5972. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  5973. err = tg3_request_irq(tp);
  5974. if (err)
  5975. return err;
  5976. /* Need to reset the chip because the MSI cycle may have terminated
  5977. * with Master Abort.
  5978. */
  5979. tg3_full_lock(tp, 1);
  5980. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  5981. err = tg3_init_hw(tp, 1);
  5982. tg3_full_unlock(tp);
  5983. if (err)
  5984. free_irq(tp->pdev->irq, dev);
  5985. return err;
  5986. }
  5987. static int tg3_open(struct net_device *dev)
  5988. {
  5989. struct tg3 *tp = netdev_priv(dev);
  5990. int err;
  5991. netif_carrier_off(tp->dev);
  5992. tg3_full_lock(tp, 0);
  5993. err = tg3_set_power_state(tp, PCI_D0);
  5994. if (err) {
  5995. tg3_full_unlock(tp);
  5996. return err;
  5997. }
  5998. tg3_disable_ints(tp);
  5999. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6000. tg3_full_unlock(tp);
  6001. /* The placement of this call is tied
  6002. * to the setup and use of Host TX descriptors.
  6003. */
  6004. err = tg3_alloc_consistent(tp);
  6005. if (err)
  6006. return err;
  6007. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  6008. (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
  6009. (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
  6010. !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
  6011. (tp->pdev_peer == tp->pdev))) {
  6012. /* All MSI supporting chips should support tagged
  6013. * status. Assert that this is the case.
  6014. */
  6015. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6016. printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
  6017. "Not using MSI.\n", tp->dev->name);
  6018. } else if (pci_enable_msi(tp->pdev) == 0) {
  6019. u32 msi_mode;
  6020. msi_mode = tr32(MSGINT_MODE);
  6021. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  6022. tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
  6023. }
  6024. }
  6025. err = tg3_request_irq(tp);
  6026. if (err) {
  6027. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6028. pci_disable_msi(tp->pdev);
  6029. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6030. }
  6031. tg3_free_consistent(tp);
  6032. return err;
  6033. }
  6034. tg3_full_lock(tp, 0);
  6035. err = tg3_init_hw(tp, 1);
  6036. if (err) {
  6037. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6038. tg3_free_rings(tp);
  6039. } else {
  6040. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  6041. tp->timer_offset = HZ;
  6042. else
  6043. tp->timer_offset = HZ / 10;
  6044. BUG_ON(tp->timer_offset > HZ);
  6045. tp->timer_counter = tp->timer_multiplier =
  6046. (HZ / tp->timer_offset);
  6047. tp->asf_counter = tp->asf_multiplier =
  6048. ((HZ / tp->timer_offset) * 2);
  6049. init_timer(&tp->timer);
  6050. tp->timer.expires = jiffies + tp->timer_offset;
  6051. tp->timer.data = (unsigned long) tp;
  6052. tp->timer.function = tg3_timer;
  6053. }
  6054. tg3_full_unlock(tp);
  6055. if (err) {
  6056. free_irq(tp->pdev->irq, dev);
  6057. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6058. pci_disable_msi(tp->pdev);
  6059. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6060. }
  6061. tg3_free_consistent(tp);
  6062. return err;
  6063. }
  6064. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6065. err = tg3_test_msi(tp);
  6066. if (err) {
  6067. tg3_full_lock(tp, 0);
  6068. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6069. pci_disable_msi(tp->pdev);
  6070. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6071. }
  6072. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6073. tg3_free_rings(tp);
  6074. tg3_free_consistent(tp);
  6075. tg3_full_unlock(tp);
  6076. return err;
  6077. }
  6078. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6079. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
  6080. u32 val = tr32(PCIE_TRANSACTION_CFG);
  6081. tw32(PCIE_TRANSACTION_CFG,
  6082. val | PCIE_TRANS_CFG_1SHOT_MSI);
  6083. }
  6084. }
  6085. }
  6086. tg3_full_lock(tp, 0);
  6087. add_timer(&tp->timer);
  6088. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  6089. tg3_enable_ints(tp);
  6090. tg3_full_unlock(tp);
  6091. netif_start_queue(dev);
  6092. return 0;
  6093. }
  6094. #if 0
  6095. /*static*/ void tg3_dump_state(struct tg3 *tp)
  6096. {
  6097. u32 val32, val32_2, val32_3, val32_4, val32_5;
  6098. u16 val16;
  6099. int i;
  6100. pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
  6101. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
  6102. printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
  6103. val16, val32);
  6104. /* MAC block */
  6105. printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
  6106. tr32(MAC_MODE), tr32(MAC_STATUS));
  6107. printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
  6108. tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
  6109. printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
  6110. tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
  6111. printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
  6112. tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
  6113. /* Send data initiator control block */
  6114. printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
  6115. tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
  6116. printk(" SNDDATAI_STATSCTRL[%08x]\n",
  6117. tr32(SNDDATAI_STATSCTRL));
  6118. /* Send data completion control block */
  6119. printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
  6120. /* Send BD ring selector block */
  6121. printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
  6122. tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
  6123. /* Send BD initiator control block */
  6124. printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
  6125. tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
  6126. /* Send BD completion control block */
  6127. printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
  6128. /* Receive list placement control block */
  6129. printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
  6130. tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
  6131. printk(" RCVLPC_STATSCTRL[%08x]\n",
  6132. tr32(RCVLPC_STATSCTRL));
  6133. /* Receive data and receive BD initiator control block */
  6134. printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
  6135. tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
  6136. /* Receive data completion control block */
  6137. printk("DEBUG: RCVDCC_MODE[%08x]\n",
  6138. tr32(RCVDCC_MODE));
  6139. /* Receive BD initiator control block */
  6140. printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
  6141. tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
  6142. /* Receive BD completion control block */
  6143. printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
  6144. tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
  6145. /* Receive list selector control block */
  6146. printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
  6147. tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
  6148. /* Mbuf cluster free block */
  6149. printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
  6150. tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
  6151. /* Host coalescing control block */
  6152. printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
  6153. tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
  6154. printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
  6155. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6156. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6157. printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
  6158. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6159. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6160. printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
  6161. tr32(HOSTCC_STATS_BLK_NIC_ADDR));
  6162. printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
  6163. tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
  6164. /* Memory arbiter control block */
  6165. printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
  6166. tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
  6167. /* Buffer manager control block */
  6168. printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
  6169. tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
  6170. printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
  6171. tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
  6172. printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
  6173. "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
  6174. tr32(BUFMGR_DMA_DESC_POOL_ADDR),
  6175. tr32(BUFMGR_DMA_DESC_POOL_SIZE));
  6176. /* Read DMA control block */
  6177. printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
  6178. tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
  6179. /* Write DMA control block */
  6180. printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
  6181. tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
  6182. /* DMA completion block */
  6183. printk("DEBUG: DMAC_MODE[%08x]\n",
  6184. tr32(DMAC_MODE));
  6185. /* GRC block */
  6186. printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
  6187. tr32(GRC_MODE), tr32(GRC_MISC_CFG));
  6188. printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
  6189. tr32(GRC_LOCAL_CTRL));
  6190. /* TG3_BDINFOs */
  6191. printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
  6192. tr32(RCVDBDI_JUMBO_BD + 0x0),
  6193. tr32(RCVDBDI_JUMBO_BD + 0x4),
  6194. tr32(RCVDBDI_JUMBO_BD + 0x8),
  6195. tr32(RCVDBDI_JUMBO_BD + 0xc));
  6196. printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
  6197. tr32(RCVDBDI_STD_BD + 0x0),
  6198. tr32(RCVDBDI_STD_BD + 0x4),
  6199. tr32(RCVDBDI_STD_BD + 0x8),
  6200. tr32(RCVDBDI_STD_BD + 0xc));
  6201. printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
  6202. tr32(RCVDBDI_MINI_BD + 0x0),
  6203. tr32(RCVDBDI_MINI_BD + 0x4),
  6204. tr32(RCVDBDI_MINI_BD + 0x8),
  6205. tr32(RCVDBDI_MINI_BD + 0xc));
  6206. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
  6207. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
  6208. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
  6209. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
  6210. printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
  6211. val32, val32_2, val32_3, val32_4);
  6212. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
  6213. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
  6214. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
  6215. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
  6216. printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
  6217. val32, val32_2, val32_3, val32_4);
  6218. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
  6219. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
  6220. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
  6221. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
  6222. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
  6223. printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
  6224. val32, val32_2, val32_3, val32_4, val32_5);
  6225. /* SW status block */
  6226. printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  6227. tp->hw_status->status,
  6228. tp->hw_status->status_tag,
  6229. tp->hw_status->rx_jumbo_consumer,
  6230. tp->hw_status->rx_consumer,
  6231. tp->hw_status->rx_mini_consumer,
  6232. tp->hw_status->idx[0].rx_producer,
  6233. tp->hw_status->idx[0].tx_consumer);
  6234. /* SW statistics block */
  6235. printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
  6236. ((u32 *)tp->hw_stats)[0],
  6237. ((u32 *)tp->hw_stats)[1],
  6238. ((u32 *)tp->hw_stats)[2],
  6239. ((u32 *)tp->hw_stats)[3]);
  6240. /* Mailboxes */
  6241. printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
  6242. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
  6243. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
  6244. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
  6245. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
  6246. /* NIC side send descriptors. */
  6247. for (i = 0; i < 6; i++) {
  6248. unsigned long txd;
  6249. txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
  6250. + (i * sizeof(struct tg3_tx_buffer_desc));
  6251. printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
  6252. i,
  6253. readl(txd + 0x0), readl(txd + 0x4),
  6254. readl(txd + 0x8), readl(txd + 0xc));
  6255. }
  6256. /* NIC side RX descriptors. */
  6257. for (i = 0; i < 6; i++) {
  6258. unsigned long rxd;
  6259. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
  6260. + (i * sizeof(struct tg3_rx_buffer_desc));
  6261. printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
  6262. i,
  6263. readl(rxd + 0x0), readl(rxd + 0x4),
  6264. readl(rxd + 0x8), readl(rxd + 0xc));
  6265. rxd += (4 * sizeof(u32));
  6266. printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
  6267. i,
  6268. readl(rxd + 0x0), readl(rxd + 0x4),
  6269. readl(rxd + 0x8), readl(rxd + 0xc));
  6270. }
  6271. for (i = 0; i < 6; i++) {
  6272. unsigned long rxd;
  6273. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
  6274. + (i * sizeof(struct tg3_rx_buffer_desc));
  6275. printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
  6276. i,
  6277. readl(rxd + 0x0), readl(rxd + 0x4),
  6278. readl(rxd + 0x8), readl(rxd + 0xc));
  6279. rxd += (4 * sizeof(u32));
  6280. printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
  6281. i,
  6282. readl(rxd + 0x0), readl(rxd + 0x4),
  6283. readl(rxd + 0x8), readl(rxd + 0xc));
  6284. }
  6285. }
  6286. #endif
  6287. static struct net_device_stats *tg3_get_stats(struct net_device *);
  6288. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  6289. static int tg3_close(struct net_device *dev)
  6290. {
  6291. struct tg3 *tp = netdev_priv(dev);
  6292. /* Calling flush_scheduled_work() may deadlock because
  6293. * linkwatch_event() may be on the workqueue and it will try to get
  6294. * the rtnl_lock which we are holding.
  6295. */
  6296. while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
  6297. msleep(1);
  6298. netif_stop_queue(dev);
  6299. del_timer_sync(&tp->timer);
  6300. tg3_full_lock(tp, 1);
  6301. #if 0
  6302. tg3_dump_state(tp);
  6303. #endif
  6304. tg3_disable_ints(tp);
  6305. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6306. tg3_free_rings(tp);
  6307. tp->tg3_flags &=
  6308. ~(TG3_FLAG_INIT_COMPLETE |
  6309. TG3_FLAG_GOT_SERDES_FLOWCTL);
  6310. tg3_full_unlock(tp);
  6311. free_irq(tp->pdev->irq, dev);
  6312. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6313. pci_disable_msi(tp->pdev);
  6314. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6315. }
  6316. memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
  6317. sizeof(tp->net_stats_prev));
  6318. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  6319. sizeof(tp->estats_prev));
  6320. tg3_free_consistent(tp);
  6321. tg3_set_power_state(tp, PCI_D3hot);
  6322. netif_carrier_off(tp->dev);
  6323. return 0;
  6324. }
  6325. static inline unsigned long get_stat64(tg3_stat64_t *val)
  6326. {
  6327. unsigned long ret;
  6328. #if (BITS_PER_LONG == 32)
  6329. ret = val->low;
  6330. #else
  6331. ret = ((u64)val->high << 32) | ((u64)val->low);
  6332. #endif
  6333. return ret;
  6334. }
  6335. static unsigned long calc_crc_errors(struct tg3 *tp)
  6336. {
  6337. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6338. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6339. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  6340. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  6341. u32 val;
  6342. spin_lock_bh(&tp->lock);
  6343. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  6344. tg3_writephy(tp, MII_TG3_TEST1,
  6345. val | MII_TG3_TEST1_CRC_EN);
  6346. tg3_readphy(tp, 0x14, &val);
  6347. } else
  6348. val = 0;
  6349. spin_unlock_bh(&tp->lock);
  6350. tp->phy_crc_errors += val;
  6351. return tp->phy_crc_errors;
  6352. }
  6353. return get_stat64(&hw_stats->rx_fcs_errors);
  6354. }
  6355. #define ESTAT_ADD(member) \
  6356. estats->member = old_estats->member + \
  6357. get_stat64(&hw_stats->member)
  6358. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  6359. {
  6360. struct tg3_ethtool_stats *estats = &tp->estats;
  6361. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  6362. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6363. if (!hw_stats)
  6364. return old_estats;
  6365. ESTAT_ADD(rx_octets);
  6366. ESTAT_ADD(rx_fragments);
  6367. ESTAT_ADD(rx_ucast_packets);
  6368. ESTAT_ADD(rx_mcast_packets);
  6369. ESTAT_ADD(rx_bcast_packets);
  6370. ESTAT_ADD(rx_fcs_errors);
  6371. ESTAT_ADD(rx_align_errors);
  6372. ESTAT_ADD(rx_xon_pause_rcvd);
  6373. ESTAT_ADD(rx_xoff_pause_rcvd);
  6374. ESTAT_ADD(rx_mac_ctrl_rcvd);
  6375. ESTAT_ADD(rx_xoff_entered);
  6376. ESTAT_ADD(rx_frame_too_long_errors);
  6377. ESTAT_ADD(rx_jabbers);
  6378. ESTAT_ADD(rx_undersize_packets);
  6379. ESTAT_ADD(rx_in_length_errors);
  6380. ESTAT_ADD(rx_out_length_errors);
  6381. ESTAT_ADD(rx_64_or_less_octet_packets);
  6382. ESTAT_ADD(rx_65_to_127_octet_packets);
  6383. ESTAT_ADD(rx_128_to_255_octet_packets);
  6384. ESTAT_ADD(rx_256_to_511_octet_packets);
  6385. ESTAT_ADD(rx_512_to_1023_octet_packets);
  6386. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  6387. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  6388. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  6389. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  6390. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  6391. ESTAT_ADD(tx_octets);
  6392. ESTAT_ADD(tx_collisions);
  6393. ESTAT_ADD(tx_xon_sent);
  6394. ESTAT_ADD(tx_xoff_sent);
  6395. ESTAT_ADD(tx_flow_control);
  6396. ESTAT_ADD(tx_mac_errors);
  6397. ESTAT_ADD(tx_single_collisions);
  6398. ESTAT_ADD(tx_mult_collisions);
  6399. ESTAT_ADD(tx_deferred);
  6400. ESTAT_ADD(tx_excessive_collisions);
  6401. ESTAT_ADD(tx_late_collisions);
  6402. ESTAT_ADD(tx_collide_2times);
  6403. ESTAT_ADD(tx_collide_3times);
  6404. ESTAT_ADD(tx_collide_4times);
  6405. ESTAT_ADD(tx_collide_5times);
  6406. ESTAT_ADD(tx_collide_6times);
  6407. ESTAT_ADD(tx_collide_7times);
  6408. ESTAT_ADD(tx_collide_8times);
  6409. ESTAT_ADD(tx_collide_9times);
  6410. ESTAT_ADD(tx_collide_10times);
  6411. ESTAT_ADD(tx_collide_11times);
  6412. ESTAT_ADD(tx_collide_12times);
  6413. ESTAT_ADD(tx_collide_13times);
  6414. ESTAT_ADD(tx_collide_14times);
  6415. ESTAT_ADD(tx_collide_15times);
  6416. ESTAT_ADD(tx_ucast_packets);
  6417. ESTAT_ADD(tx_mcast_packets);
  6418. ESTAT_ADD(tx_bcast_packets);
  6419. ESTAT_ADD(tx_carrier_sense_errors);
  6420. ESTAT_ADD(tx_discards);
  6421. ESTAT_ADD(tx_errors);
  6422. ESTAT_ADD(dma_writeq_full);
  6423. ESTAT_ADD(dma_write_prioq_full);
  6424. ESTAT_ADD(rxbds_empty);
  6425. ESTAT_ADD(rx_discards);
  6426. ESTAT_ADD(rx_errors);
  6427. ESTAT_ADD(rx_threshold_hit);
  6428. ESTAT_ADD(dma_readq_full);
  6429. ESTAT_ADD(dma_read_prioq_full);
  6430. ESTAT_ADD(tx_comp_queue_full);
  6431. ESTAT_ADD(ring_set_send_prod_index);
  6432. ESTAT_ADD(ring_status_update);
  6433. ESTAT_ADD(nic_irqs);
  6434. ESTAT_ADD(nic_avoided_irqs);
  6435. ESTAT_ADD(nic_tx_threshold_hit);
  6436. return estats;
  6437. }
  6438. static struct net_device_stats *tg3_get_stats(struct net_device *dev)
  6439. {
  6440. struct tg3 *tp = netdev_priv(dev);
  6441. struct net_device_stats *stats = &tp->net_stats;
  6442. struct net_device_stats *old_stats = &tp->net_stats_prev;
  6443. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6444. if (!hw_stats)
  6445. return old_stats;
  6446. stats->rx_packets = old_stats->rx_packets +
  6447. get_stat64(&hw_stats->rx_ucast_packets) +
  6448. get_stat64(&hw_stats->rx_mcast_packets) +
  6449. get_stat64(&hw_stats->rx_bcast_packets);
  6450. stats->tx_packets = old_stats->tx_packets +
  6451. get_stat64(&hw_stats->tx_ucast_packets) +
  6452. get_stat64(&hw_stats->tx_mcast_packets) +
  6453. get_stat64(&hw_stats->tx_bcast_packets);
  6454. stats->rx_bytes = old_stats->rx_bytes +
  6455. get_stat64(&hw_stats->rx_octets);
  6456. stats->tx_bytes = old_stats->tx_bytes +
  6457. get_stat64(&hw_stats->tx_octets);
  6458. stats->rx_errors = old_stats->rx_errors +
  6459. get_stat64(&hw_stats->rx_errors);
  6460. stats->tx_errors = old_stats->tx_errors +
  6461. get_stat64(&hw_stats->tx_errors) +
  6462. get_stat64(&hw_stats->tx_mac_errors) +
  6463. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  6464. get_stat64(&hw_stats->tx_discards);
  6465. stats->multicast = old_stats->multicast +
  6466. get_stat64(&hw_stats->rx_mcast_packets);
  6467. stats->collisions = old_stats->collisions +
  6468. get_stat64(&hw_stats->tx_collisions);
  6469. stats->rx_length_errors = old_stats->rx_length_errors +
  6470. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  6471. get_stat64(&hw_stats->rx_undersize_packets);
  6472. stats->rx_over_errors = old_stats->rx_over_errors +
  6473. get_stat64(&hw_stats->rxbds_empty);
  6474. stats->rx_frame_errors = old_stats->rx_frame_errors +
  6475. get_stat64(&hw_stats->rx_align_errors);
  6476. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  6477. get_stat64(&hw_stats->tx_discards);
  6478. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  6479. get_stat64(&hw_stats->tx_carrier_sense_errors);
  6480. stats->rx_crc_errors = old_stats->rx_crc_errors +
  6481. calc_crc_errors(tp);
  6482. stats->rx_missed_errors = old_stats->rx_missed_errors +
  6483. get_stat64(&hw_stats->rx_discards);
  6484. return stats;
  6485. }
  6486. static inline u32 calc_crc(unsigned char *buf, int len)
  6487. {
  6488. u32 reg;
  6489. u32 tmp;
  6490. int j, k;
  6491. reg = 0xffffffff;
  6492. for (j = 0; j < len; j++) {
  6493. reg ^= buf[j];
  6494. for (k = 0; k < 8; k++) {
  6495. tmp = reg & 0x01;
  6496. reg >>= 1;
  6497. if (tmp) {
  6498. reg ^= 0xedb88320;
  6499. }
  6500. }
  6501. }
  6502. return ~reg;
  6503. }
  6504. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  6505. {
  6506. /* accept or reject all multicast frames */
  6507. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  6508. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  6509. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  6510. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  6511. }
  6512. static void __tg3_set_rx_mode(struct net_device *dev)
  6513. {
  6514. struct tg3 *tp = netdev_priv(dev);
  6515. u32 rx_mode;
  6516. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  6517. RX_MODE_KEEP_VLAN_TAG);
  6518. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  6519. * flag clear.
  6520. */
  6521. #if TG3_VLAN_TAG_USED
  6522. if (!tp->vlgrp &&
  6523. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  6524. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  6525. #else
  6526. /* By definition, VLAN is disabled always in this
  6527. * case.
  6528. */
  6529. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  6530. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  6531. #endif
  6532. if (dev->flags & IFF_PROMISC) {
  6533. /* Promiscuous mode. */
  6534. rx_mode |= RX_MODE_PROMISC;
  6535. } else if (dev->flags & IFF_ALLMULTI) {
  6536. /* Accept all multicast. */
  6537. tg3_set_multi (tp, 1);
  6538. } else if (dev->mc_count < 1) {
  6539. /* Reject all multicast. */
  6540. tg3_set_multi (tp, 0);
  6541. } else {
  6542. /* Accept one or more multicast(s). */
  6543. struct dev_mc_list *mclist;
  6544. unsigned int i;
  6545. u32 mc_filter[4] = { 0, };
  6546. u32 regidx;
  6547. u32 bit;
  6548. u32 crc;
  6549. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  6550. i++, mclist = mclist->next) {
  6551. crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
  6552. bit = ~crc & 0x7f;
  6553. regidx = (bit & 0x60) >> 5;
  6554. bit &= 0x1f;
  6555. mc_filter[regidx] |= (1 << bit);
  6556. }
  6557. tw32(MAC_HASH_REG_0, mc_filter[0]);
  6558. tw32(MAC_HASH_REG_1, mc_filter[1]);
  6559. tw32(MAC_HASH_REG_2, mc_filter[2]);
  6560. tw32(MAC_HASH_REG_3, mc_filter[3]);
  6561. }
  6562. if (rx_mode != tp->rx_mode) {
  6563. tp->rx_mode = rx_mode;
  6564. tw32_f(MAC_RX_MODE, rx_mode);
  6565. udelay(10);
  6566. }
  6567. }
  6568. static void tg3_set_rx_mode(struct net_device *dev)
  6569. {
  6570. struct tg3 *tp = netdev_priv(dev);
  6571. if (!netif_running(dev))
  6572. return;
  6573. tg3_full_lock(tp, 0);
  6574. __tg3_set_rx_mode(dev);
  6575. tg3_full_unlock(tp);
  6576. }
  6577. #define TG3_REGDUMP_LEN (32 * 1024)
  6578. static int tg3_get_regs_len(struct net_device *dev)
  6579. {
  6580. return TG3_REGDUMP_LEN;
  6581. }
  6582. static void tg3_get_regs(struct net_device *dev,
  6583. struct ethtool_regs *regs, void *_p)
  6584. {
  6585. u32 *p = _p;
  6586. struct tg3 *tp = netdev_priv(dev);
  6587. u8 *orig_p = _p;
  6588. int i;
  6589. regs->version = 0;
  6590. memset(p, 0, TG3_REGDUMP_LEN);
  6591. if (tp->link_config.phy_is_low_power)
  6592. return;
  6593. tg3_full_lock(tp, 0);
  6594. #define __GET_REG32(reg) (*(p)++ = tr32(reg))
  6595. #define GET_REG32_LOOP(base,len) \
  6596. do { p = (u32 *)(orig_p + (base)); \
  6597. for (i = 0; i < len; i += 4) \
  6598. __GET_REG32((base) + i); \
  6599. } while (0)
  6600. #define GET_REG32_1(reg) \
  6601. do { p = (u32 *)(orig_p + (reg)); \
  6602. __GET_REG32((reg)); \
  6603. } while (0)
  6604. GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  6605. GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  6606. GET_REG32_LOOP(MAC_MODE, 0x4f0);
  6607. GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  6608. GET_REG32_1(SNDDATAC_MODE);
  6609. GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  6610. GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  6611. GET_REG32_1(SNDBDC_MODE);
  6612. GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  6613. GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  6614. GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  6615. GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  6616. GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  6617. GET_REG32_1(RCVDCC_MODE);
  6618. GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  6619. GET_REG32_LOOP(RCVCC_MODE, 0x14);
  6620. GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  6621. GET_REG32_1(MBFREE_MODE);
  6622. GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  6623. GET_REG32_LOOP(MEMARB_MODE, 0x10);
  6624. GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  6625. GET_REG32_LOOP(RDMAC_MODE, 0x08);
  6626. GET_REG32_LOOP(WDMAC_MODE, 0x08);
  6627. GET_REG32_1(RX_CPU_MODE);
  6628. GET_REG32_1(RX_CPU_STATE);
  6629. GET_REG32_1(RX_CPU_PGMCTR);
  6630. GET_REG32_1(RX_CPU_HWBKPT);
  6631. GET_REG32_1(TX_CPU_MODE);
  6632. GET_REG32_1(TX_CPU_STATE);
  6633. GET_REG32_1(TX_CPU_PGMCTR);
  6634. GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  6635. GET_REG32_LOOP(FTQ_RESET, 0x120);
  6636. GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  6637. GET_REG32_1(DMAC_MODE);
  6638. GET_REG32_LOOP(GRC_MODE, 0x4c);
  6639. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  6640. GET_REG32_LOOP(NVRAM_CMD, 0x24);
  6641. #undef __GET_REG32
  6642. #undef GET_REG32_LOOP
  6643. #undef GET_REG32_1
  6644. tg3_full_unlock(tp);
  6645. }
  6646. static int tg3_get_eeprom_len(struct net_device *dev)
  6647. {
  6648. struct tg3 *tp = netdev_priv(dev);
  6649. return tp->nvram_size;
  6650. }
  6651. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
  6652. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
  6653. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  6654. {
  6655. struct tg3 *tp = netdev_priv(dev);
  6656. int ret;
  6657. u8 *pd;
  6658. u32 i, offset, len, val, b_offset, b_count;
  6659. if (tp->link_config.phy_is_low_power)
  6660. return -EAGAIN;
  6661. offset = eeprom->offset;
  6662. len = eeprom->len;
  6663. eeprom->len = 0;
  6664. eeprom->magic = TG3_EEPROM_MAGIC;
  6665. if (offset & 3) {
  6666. /* adjustments to start on required 4 byte boundary */
  6667. b_offset = offset & 3;
  6668. b_count = 4 - b_offset;
  6669. if (b_count > len) {
  6670. /* i.e. offset=1 len=2 */
  6671. b_count = len;
  6672. }
  6673. ret = tg3_nvram_read(tp, offset-b_offset, &val);
  6674. if (ret)
  6675. return ret;
  6676. val = cpu_to_le32(val);
  6677. memcpy(data, ((char*)&val) + b_offset, b_count);
  6678. len -= b_count;
  6679. offset += b_count;
  6680. eeprom->len += b_count;
  6681. }
  6682. /* read bytes upto the last 4 byte boundary */
  6683. pd = &data[eeprom->len];
  6684. for (i = 0; i < (len - (len & 3)); i += 4) {
  6685. ret = tg3_nvram_read(tp, offset + i, &val);
  6686. if (ret) {
  6687. eeprom->len += i;
  6688. return ret;
  6689. }
  6690. val = cpu_to_le32(val);
  6691. memcpy(pd + i, &val, 4);
  6692. }
  6693. eeprom->len += i;
  6694. if (len & 3) {
  6695. /* read last bytes not ending on 4 byte boundary */
  6696. pd = &data[eeprom->len];
  6697. b_count = len & 3;
  6698. b_offset = offset + len - b_count;
  6699. ret = tg3_nvram_read(tp, b_offset, &val);
  6700. if (ret)
  6701. return ret;
  6702. val = cpu_to_le32(val);
  6703. memcpy(pd, ((char*)&val), b_count);
  6704. eeprom->len += b_count;
  6705. }
  6706. return 0;
  6707. }
  6708. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  6709. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  6710. {
  6711. struct tg3 *tp = netdev_priv(dev);
  6712. int ret;
  6713. u32 offset, len, b_offset, odd_len, start, end;
  6714. u8 *buf;
  6715. if (tp->link_config.phy_is_low_power)
  6716. return -EAGAIN;
  6717. if (eeprom->magic != TG3_EEPROM_MAGIC)
  6718. return -EINVAL;
  6719. offset = eeprom->offset;
  6720. len = eeprom->len;
  6721. if ((b_offset = (offset & 3))) {
  6722. /* adjustments to start on required 4 byte boundary */
  6723. ret = tg3_nvram_read(tp, offset-b_offset, &start);
  6724. if (ret)
  6725. return ret;
  6726. start = cpu_to_le32(start);
  6727. len += b_offset;
  6728. offset &= ~3;
  6729. if (len < 4)
  6730. len = 4;
  6731. }
  6732. odd_len = 0;
  6733. if (len & 3) {
  6734. /* adjustments to end on required 4 byte boundary */
  6735. odd_len = 1;
  6736. len = (len + 3) & ~3;
  6737. ret = tg3_nvram_read(tp, offset+len-4, &end);
  6738. if (ret)
  6739. return ret;
  6740. end = cpu_to_le32(end);
  6741. }
  6742. buf = data;
  6743. if (b_offset || odd_len) {
  6744. buf = kmalloc(len, GFP_KERNEL);
  6745. if (buf == 0)
  6746. return -ENOMEM;
  6747. if (b_offset)
  6748. memcpy(buf, &start, 4);
  6749. if (odd_len)
  6750. memcpy(buf+len-4, &end, 4);
  6751. memcpy(buf + b_offset, data, eeprom->len);
  6752. }
  6753. ret = tg3_nvram_write_block(tp, offset, len, buf);
  6754. if (buf != data)
  6755. kfree(buf);
  6756. return ret;
  6757. }
  6758. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  6759. {
  6760. struct tg3 *tp = netdev_priv(dev);
  6761. cmd->supported = (SUPPORTED_Autoneg);
  6762. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  6763. cmd->supported |= (SUPPORTED_1000baseT_Half |
  6764. SUPPORTED_1000baseT_Full);
  6765. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  6766. cmd->supported |= (SUPPORTED_100baseT_Half |
  6767. SUPPORTED_100baseT_Full |
  6768. SUPPORTED_10baseT_Half |
  6769. SUPPORTED_10baseT_Full |
  6770. SUPPORTED_MII);
  6771. cmd->port = PORT_TP;
  6772. } else {
  6773. cmd->supported |= SUPPORTED_FIBRE;
  6774. cmd->port = PORT_FIBRE;
  6775. }
  6776. cmd->advertising = tp->link_config.advertising;
  6777. if (netif_running(dev)) {
  6778. cmd->speed = tp->link_config.active_speed;
  6779. cmd->duplex = tp->link_config.active_duplex;
  6780. }
  6781. cmd->phy_address = PHY_ADDR;
  6782. cmd->transceiver = 0;
  6783. cmd->autoneg = tp->link_config.autoneg;
  6784. cmd->maxtxpkt = 0;
  6785. cmd->maxrxpkt = 0;
  6786. return 0;
  6787. }
  6788. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  6789. {
  6790. struct tg3 *tp = netdev_priv(dev);
  6791. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
  6792. /* These are the only valid advertisement bits allowed. */
  6793. if (cmd->autoneg == AUTONEG_ENABLE &&
  6794. (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
  6795. ADVERTISED_1000baseT_Full |
  6796. ADVERTISED_Autoneg |
  6797. ADVERTISED_FIBRE)))
  6798. return -EINVAL;
  6799. /* Fiber can only do SPEED_1000. */
  6800. else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  6801. (cmd->speed != SPEED_1000))
  6802. return -EINVAL;
  6803. /* Copper cannot force SPEED_1000. */
  6804. } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  6805. (cmd->speed == SPEED_1000))
  6806. return -EINVAL;
  6807. else if ((cmd->speed == SPEED_1000) &&
  6808. (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
  6809. return -EINVAL;
  6810. tg3_full_lock(tp, 0);
  6811. tp->link_config.autoneg = cmd->autoneg;
  6812. if (cmd->autoneg == AUTONEG_ENABLE) {
  6813. tp->link_config.advertising = cmd->advertising;
  6814. tp->link_config.speed = SPEED_INVALID;
  6815. tp->link_config.duplex = DUPLEX_INVALID;
  6816. } else {
  6817. tp->link_config.advertising = 0;
  6818. tp->link_config.speed = cmd->speed;
  6819. tp->link_config.duplex = cmd->duplex;
  6820. }
  6821. tp->link_config.orig_speed = tp->link_config.speed;
  6822. tp->link_config.orig_duplex = tp->link_config.duplex;
  6823. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  6824. if (netif_running(dev))
  6825. tg3_setup_phy(tp, 1);
  6826. tg3_full_unlock(tp);
  6827. return 0;
  6828. }
  6829. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  6830. {
  6831. struct tg3 *tp = netdev_priv(dev);
  6832. strcpy(info->driver, DRV_MODULE_NAME);
  6833. strcpy(info->version, DRV_MODULE_VERSION);
  6834. strcpy(info->fw_version, tp->fw_ver);
  6835. strcpy(info->bus_info, pci_name(tp->pdev));
  6836. }
  6837. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  6838. {
  6839. struct tg3 *tp = netdev_priv(dev);
  6840. wol->supported = WAKE_MAGIC;
  6841. wol->wolopts = 0;
  6842. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  6843. wol->wolopts = WAKE_MAGIC;
  6844. memset(&wol->sopass, 0, sizeof(wol->sopass));
  6845. }
  6846. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  6847. {
  6848. struct tg3 *tp = netdev_priv(dev);
  6849. if (wol->wolopts & ~WAKE_MAGIC)
  6850. return -EINVAL;
  6851. if ((wol->wolopts & WAKE_MAGIC) &&
  6852. tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
  6853. !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
  6854. return -EINVAL;
  6855. spin_lock_bh(&tp->lock);
  6856. if (wol->wolopts & WAKE_MAGIC)
  6857. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  6858. else
  6859. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  6860. spin_unlock_bh(&tp->lock);
  6861. return 0;
  6862. }
  6863. static u32 tg3_get_msglevel(struct net_device *dev)
  6864. {
  6865. struct tg3 *tp = netdev_priv(dev);
  6866. return tp->msg_enable;
  6867. }
  6868. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  6869. {
  6870. struct tg3 *tp = netdev_priv(dev);
  6871. tp->msg_enable = value;
  6872. }
  6873. static int tg3_set_tso(struct net_device *dev, u32 value)
  6874. {
  6875. struct tg3 *tp = netdev_priv(dev);
  6876. if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  6877. if (value)
  6878. return -EINVAL;
  6879. return 0;
  6880. }
  6881. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  6882. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
  6883. if (value)
  6884. dev->features |= NETIF_F_TSO6;
  6885. else
  6886. dev->features &= ~NETIF_F_TSO6;
  6887. }
  6888. return ethtool_op_set_tso(dev, value);
  6889. }
  6890. static int tg3_nway_reset(struct net_device *dev)
  6891. {
  6892. struct tg3 *tp = netdev_priv(dev);
  6893. u32 bmcr;
  6894. int r;
  6895. if (!netif_running(dev))
  6896. return -EAGAIN;
  6897. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  6898. return -EINVAL;
  6899. spin_lock_bh(&tp->lock);
  6900. r = -EINVAL;
  6901. tg3_readphy(tp, MII_BMCR, &bmcr);
  6902. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  6903. ((bmcr & BMCR_ANENABLE) ||
  6904. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
  6905. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  6906. BMCR_ANENABLE);
  6907. r = 0;
  6908. }
  6909. spin_unlock_bh(&tp->lock);
  6910. return r;
  6911. }
  6912. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  6913. {
  6914. struct tg3 *tp = netdev_priv(dev);
  6915. ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  6916. ering->rx_mini_max_pending = 0;
  6917. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  6918. ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  6919. else
  6920. ering->rx_jumbo_max_pending = 0;
  6921. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  6922. ering->rx_pending = tp->rx_pending;
  6923. ering->rx_mini_pending = 0;
  6924. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  6925. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  6926. else
  6927. ering->rx_jumbo_pending = 0;
  6928. ering->tx_pending = tp->tx_pending;
  6929. }
  6930. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  6931. {
  6932. struct tg3 *tp = netdev_priv(dev);
  6933. int irq_sync = 0, err = 0;
  6934. if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  6935. (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  6936. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  6937. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  6938. ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
  6939. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  6940. return -EINVAL;
  6941. if (netif_running(dev)) {
  6942. tg3_netif_stop(tp);
  6943. irq_sync = 1;
  6944. }
  6945. tg3_full_lock(tp, irq_sync);
  6946. tp->rx_pending = ering->rx_pending;
  6947. if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  6948. tp->rx_pending > 63)
  6949. tp->rx_pending = 63;
  6950. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  6951. tp->tx_pending = ering->tx_pending;
  6952. if (netif_running(dev)) {
  6953. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6954. err = tg3_restart_hw(tp, 1);
  6955. if (!err)
  6956. tg3_netif_start(tp);
  6957. }
  6958. tg3_full_unlock(tp);
  6959. return err;
  6960. }
  6961. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  6962. {
  6963. struct tg3 *tp = netdev_priv(dev);
  6964. epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  6965. epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
  6966. epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
  6967. }
  6968. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  6969. {
  6970. struct tg3 *tp = netdev_priv(dev);
  6971. int irq_sync = 0, err = 0;
  6972. if (netif_running(dev)) {
  6973. tg3_netif_stop(tp);
  6974. irq_sync = 1;
  6975. }
  6976. tg3_full_lock(tp, irq_sync);
  6977. if (epause->autoneg)
  6978. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  6979. else
  6980. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  6981. if (epause->rx_pause)
  6982. tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
  6983. else
  6984. tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
  6985. if (epause->tx_pause)
  6986. tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
  6987. else
  6988. tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
  6989. if (netif_running(dev)) {
  6990. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6991. err = tg3_restart_hw(tp, 1);
  6992. if (!err)
  6993. tg3_netif_start(tp);
  6994. }
  6995. tg3_full_unlock(tp);
  6996. return err;
  6997. }
  6998. static u32 tg3_get_rx_csum(struct net_device *dev)
  6999. {
  7000. struct tg3 *tp = netdev_priv(dev);
  7001. return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  7002. }
  7003. static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  7004. {
  7005. struct tg3 *tp = netdev_priv(dev);
  7006. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7007. if (data != 0)
  7008. return -EINVAL;
  7009. return 0;
  7010. }
  7011. spin_lock_bh(&tp->lock);
  7012. if (data)
  7013. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  7014. else
  7015. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  7016. spin_unlock_bh(&tp->lock);
  7017. return 0;
  7018. }
  7019. static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  7020. {
  7021. struct tg3 *tp = netdev_priv(dev);
  7022. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7023. if (data != 0)
  7024. return -EINVAL;
  7025. return 0;
  7026. }
  7027. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7028. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  7029. ethtool_op_set_tx_hw_csum(dev, data);
  7030. else
  7031. ethtool_op_set_tx_csum(dev, data);
  7032. return 0;
  7033. }
  7034. static int tg3_get_stats_count (struct net_device *dev)
  7035. {
  7036. return TG3_NUM_STATS;
  7037. }
  7038. static int tg3_get_test_count (struct net_device *dev)
  7039. {
  7040. return TG3_NUM_TEST;
  7041. }
  7042. static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
  7043. {
  7044. switch (stringset) {
  7045. case ETH_SS_STATS:
  7046. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  7047. break;
  7048. case ETH_SS_TEST:
  7049. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  7050. break;
  7051. default:
  7052. WARN_ON(1); /* we need a WARN() */
  7053. break;
  7054. }
  7055. }
  7056. static int tg3_phys_id(struct net_device *dev, u32 data)
  7057. {
  7058. struct tg3 *tp = netdev_priv(dev);
  7059. int i;
  7060. if (!netif_running(tp->dev))
  7061. return -EAGAIN;
  7062. if (data == 0)
  7063. data = 2;
  7064. for (i = 0; i < (data * 2); i++) {
  7065. if ((i % 2) == 0)
  7066. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7067. LED_CTRL_1000MBPS_ON |
  7068. LED_CTRL_100MBPS_ON |
  7069. LED_CTRL_10MBPS_ON |
  7070. LED_CTRL_TRAFFIC_OVERRIDE |
  7071. LED_CTRL_TRAFFIC_BLINK |
  7072. LED_CTRL_TRAFFIC_LED);
  7073. else
  7074. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7075. LED_CTRL_TRAFFIC_OVERRIDE);
  7076. if (msleep_interruptible(500))
  7077. break;
  7078. }
  7079. tw32(MAC_LED_CTRL, tp->led_ctrl);
  7080. return 0;
  7081. }
  7082. static void tg3_get_ethtool_stats (struct net_device *dev,
  7083. struct ethtool_stats *estats, u64 *tmp_stats)
  7084. {
  7085. struct tg3 *tp = netdev_priv(dev);
  7086. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  7087. }
  7088. #define NVRAM_TEST_SIZE 0x100
  7089. #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
  7090. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  7091. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  7092. static int tg3_test_nvram(struct tg3 *tp)
  7093. {
  7094. u32 *buf, csum, magic;
  7095. int i, j, err = 0, size;
  7096. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  7097. return -EIO;
  7098. if (magic == TG3_EEPROM_MAGIC)
  7099. size = NVRAM_TEST_SIZE;
  7100. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  7101. if ((magic & 0xe00000) == 0x200000)
  7102. size = NVRAM_SELFBOOT_FORMAT1_SIZE;
  7103. else
  7104. return 0;
  7105. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  7106. size = NVRAM_SELFBOOT_HW_SIZE;
  7107. else
  7108. return -EIO;
  7109. buf = kmalloc(size, GFP_KERNEL);
  7110. if (buf == NULL)
  7111. return -ENOMEM;
  7112. err = -EIO;
  7113. for (i = 0, j = 0; i < size; i += 4, j++) {
  7114. u32 val;
  7115. if ((err = tg3_nvram_read(tp, i, &val)) != 0)
  7116. break;
  7117. buf[j] = cpu_to_le32(val);
  7118. }
  7119. if (i < size)
  7120. goto out;
  7121. /* Selfboot format */
  7122. if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
  7123. TG3_EEPROM_MAGIC_FW) {
  7124. u8 *buf8 = (u8 *) buf, csum8 = 0;
  7125. for (i = 0; i < size; i++)
  7126. csum8 += buf8[i];
  7127. if (csum8 == 0) {
  7128. err = 0;
  7129. goto out;
  7130. }
  7131. err = -EIO;
  7132. goto out;
  7133. }
  7134. if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
  7135. TG3_EEPROM_MAGIC_HW) {
  7136. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  7137. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  7138. u8 *buf8 = (u8 *) buf;
  7139. int j, k;
  7140. /* Separate the parity bits and the data bytes. */
  7141. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  7142. if ((i == 0) || (i == 8)) {
  7143. int l;
  7144. u8 msk;
  7145. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  7146. parity[k++] = buf8[i] & msk;
  7147. i++;
  7148. }
  7149. else if (i == 16) {
  7150. int l;
  7151. u8 msk;
  7152. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  7153. parity[k++] = buf8[i] & msk;
  7154. i++;
  7155. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  7156. parity[k++] = buf8[i] & msk;
  7157. i++;
  7158. }
  7159. data[j++] = buf8[i];
  7160. }
  7161. err = -EIO;
  7162. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  7163. u8 hw8 = hweight8(data[i]);
  7164. if ((hw8 & 0x1) && parity[i])
  7165. goto out;
  7166. else if (!(hw8 & 0x1) && !parity[i])
  7167. goto out;
  7168. }
  7169. err = 0;
  7170. goto out;
  7171. }
  7172. /* Bootstrap checksum at offset 0x10 */
  7173. csum = calc_crc((unsigned char *) buf, 0x10);
  7174. if(csum != cpu_to_le32(buf[0x10/4]))
  7175. goto out;
  7176. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  7177. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  7178. if (csum != cpu_to_le32(buf[0xfc/4]))
  7179. goto out;
  7180. err = 0;
  7181. out:
  7182. kfree(buf);
  7183. return err;
  7184. }
  7185. #define TG3_SERDES_TIMEOUT_SEC 2
  7186. #define TG3_COPPER_TIMEOUT_SEC 6
  7187. static int tg3_test_link(struct tg3 *tp)
  7188. {
  7189. int i, max;
  7190. if (!netif_running(tp->dev))
  7191. return -ENODEV;
  7192. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  7193. max = TG3_SERDES_TIMEOUT_SEC;
  7194. else
  7195. max = TG3_COPPER_TIMEOUT_SEC;
  7196. for (i = 0; i < max; i++) {
  7197. if (netif_carrier_ok(tp->dev))
  7198. return 0;
  7199. if (msleep_interruptible(1000))
  7200. break;
  7201. }
  7202. return -EIO;
  7203. }
  7204. /* Only test the commonly used registers */
  7205. static int tg3_test_registers(struct tg3 *tp)
  7206. {
  7207. int i, is_5705, is_5750;
  7208. u32 offset, read_mask, write_mask, val, save_val, read_val;
  7209. static struct {
  7210. u16 offset;
  7211. u16 flags;
  7212. #define TG3_FL_5705 0x1
  7213. #define TG3_FL_NOT_5705 0x2
  7214. #define TG3_FL_NOT_5788 0x4
  7215. #define TG3_FL_NOT_5750 0x8
  7216. u32 read_mask;
  7217. u32 write_mask;
  7218. } reg_tbl[] = {
  7219. /* MAC Control Registers */
  7220. { MAC_MODE, TG3_FL_NOT_5705,
  7221. 0x00000000, 0x00ef6f8c },
  7222. { MAC_MODE, TG3_FL_5705,
  7223. 0x00000000, 0x01ef6b8c },
  7224. { MAC_STATUS, TG3_FL_NOT_5705,
  7225. 0x03800107, 0x00000000 },
  7226. { MAC_STATUS, TG3_FL_5705,
  7227. 0x03800100, 0x00000000 },
  7228. { MAC_ADDR_0_HIGH, 0x0000,
  7229. 0x00000000, 0x0000ffff },
  7230. { MAC_ADDR_0_LOW, 0x0000,
  7231. 0x00000000, 0xffffffff },
  7232. { MAC_RX_MTU_SIZE, 0x0000,
  7233. 0x00000000, 0x0000ffff },
  7234. { MAC_TX_MODE, 0x0000,
  7235. 0x00000000, 0x00000070 },
  7236. { MAC_TX_LENGTHS, 0x0000,
  7237. 0x00000000, 0x00003fff },
  7238. { MAC_RX_MODE, TG3_FL_NOT_5705,
  7239. 0x00000000, 0x000007fc },
  7240. { MAC_RX_MODE, TG3_FL_5705,
  7241. 0x00000000, 0x000007dc },
  7242. { MAC_HASH_REG_0, 0x0000,
  7243. 0x00000000, 0xffffffff },
  7244. { MAC_HASH_REG_1, 0x0000,
  7245. 0x00000000, 0xffffffff },
  7246. { MAC_HASH_REG_2, 0x0000,
  7247. 0x00000000, 0xffffffff },
  7248. { MAC_HASH_REG_3, 0x0000,
  7249. 0x00000000, 0xffffffff },
  7250. /* Receive Data and Receive BD Initiator Control Registers. */
  7251. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  7252. 0x00000000, 0xffffffff },
  7253. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  7254. 0x00000000, 0xffffffff },
  7255. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  7256. 0x00000000, 0x00000003 },
  7257. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  7258. 0x00000000, 0xffffffff },
  7259. { RCVDBDI_STD_BD+0, 0x0000,
  7260. 0x00000000, 0xffffffff },
  7261. { RCVDBDI_STD_BD+4, 0x0000,
  7262. 0x00000000, 0xffffffff },
  7263. { RCVDBDI_STD_BD+8, 0x0000,
  7264. 0x00000000, 0xffff0002 },
  7265. { RCVDBDI_STD_BD+0xc, 0x0000,
  7266. 0x00000000, 0xffffffff },
  7267. /* Receive BD Initiator Control Registers. */
  7268. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  7269. 0x00000000, 0xffffffff },
  7270. { RCVBDI_STD_THRESH, TG3_FL_5705,
  7271. 0x00000000, 0x000003ff },
  7272. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  7273. 0x00000000, 0xffffffff },
  7274. /* Host Coalescing Control Registers. */
  7275. { HOSTCC_MODE, TG3_FL_NOT_5705,
  7276. 0x00000000, 0x00000004 },
  7277. { HOSTCC_MODE, TG3_FL_5705,
  7278. 0x00000000, 0x000000f6 },
  7279. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  7280. 0x00000000, 0xffffffff },
  7281. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  7282. 0x00000000, 0x000003ff },
  7283. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  7284. 0x00000000, 0xffffffff },
  7285. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  7286. 0x00000000, 0x000003ff },
  7287. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  7288. 0x00000000, 0xffffffff },
  7289. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7290. 0x00000000, 0x000000ff },
  7291. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  7292. 0x00000000, 0xffffffff },
  7293. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7294. 0x00000000, 0x000000ff },
  7295. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7296. 0x00000000, 0xffffffff },
  7297. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7298. 0x00000000, 0xffffffff },
  7299. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7300. 0x00000000, 0xffffffff },
  7301. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7302. 0x00000000, 0x000000ff },
  7303. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7304. 0x00000000, 0xffffffff },
  7305. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7306. 0x00000000, 0x000000ff },
  7307. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  7308. 0x00000000, 0xffffffff },
  7309. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  7310. 0x00000000, 0xffffffff },
  7311. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  7312. 0x00000000, 0xffffffff },
  7313. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  7314. 0x00000000, 0xffffffff },
  7315. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  7316. 0x00000000, 0xffffffff },
  7317. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  7318. 0xffffffff, 0x00000000 },
  7319. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  7320. 0xffffffff, 0x00000000 },
  7321. /* Buffer Manager Control Registers. */
  7322. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  7323. 0x00000000, 0x007fff80 },
  7324. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  7325. 0x00000000, 0x007fffff },
  7326. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  7327. 0x00000000, 0x0000003f },
  7328. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  7329. 0x00000000, 0x000001ff },
  7330. { BUFMGR_MB_HIGH_WATER, 0x0000,
  7331. 0x00000000, 0x000001ff },
  7332. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  7333. 0xffffffff, 0x00000000 },
  7334. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  7335. 0xffffffff, 0x00000000 },
  7336. /* Mailbox Registers */
  7337. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  7338. 0x00000000, 0x000001ff },
  7339. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  7340. 0x00000000, 0x000001ff },
  7341. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  7342. 0x00000000, 0x000007ff },
  7343. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  7344. 0x00000000, 0x000001ff },
  7345. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  7346. };
  7347. is_5705 = is_5750 = 0;
  7348. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7349. is_5705 = 1;
  7350. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  7351. is_5750 = 1;
  7352. }
  7353. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  7354. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  7355. continue;
  7356. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  7357. continue;
  7358. if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  7359. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  7360. continue;
  7361. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  7362. continue;
  7363. offset = (u32) reg_tbl[i].offset;
  7364. read_mask = reg_tbl[i].read_mask;
  7365. write_mask = reg_tbl[i].write_mask;
  7366. /* Save the original register content */
  7367. save_val = tr32(offset);
  7368. /* Determine the read-only value. */
  7369. read_val = save_val & read_mask;
  7370. /* Write zero to the register, then make sure the read-only bits
  7371. * are not changed and the read/write bits are all zeros.
  7372. */
  7373. tw32(offset, 0);
  7374. val = tr32(offset);
  7375. /* Test the read-only and read/write bits. */
  7376. if (((val & read_mask) != read_val) || (val & write_mask))
  7377. goto out;
  7378. /* Write ones to all the bits defined by RdMask and WrMask, then
  7379. * make sure the read-only bits are not changed and the
  7380. * read/write bits are all ones.
  7381. */
  7382. tw32(offset, read_mask | write_mask);
  7383. val = tr32(offset);
  7384. /* Test the read-only bits. */
  7385. if ((val & read_mask) != read_val)
  7386. goto out;
  7387. /* Test the read/write bits. */
  7388. if ((val & write_mask) != write_mask)
  7389. goto out;
  7390. tw32(offset, save_val);
  7391. }
  7392. return 0;
  7393. out:
  7394. if (netif_msg_hw(tp))
  7395. printk(KERN_ERR PFX "Register test failed at offset %x\n",
  7396. offset);
  7397. tw32(offset, save_val);
  7398. return -EIO;
  7399. }
  7400. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  7401. {
  7402. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  7403. int i;
  7404. u32 j;
  7405. for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
  7406. for (j = 0; j < len; j += 4) {
  7407. u32 val;
  7408. tg3_write_mem(tp, offset + j, test_pattern[i]);
  7409. tg3_read_mem(tp, offset + j, &val);
  7410. if (val != test_pattern[i])
  7411. return -EIO;
  7412. }
  7413. }
  7414. return 0;
  7415. }
  7416. static int tg3_test_memory(struct tg3 *tp)
  7417. {
  7418. static struct mem_entry {
  7419. u32 offset;
  7420. u32 len;
  7421. } mem_tbl_570x[] = {
  7422. { 0x00000000, 0x00b50},
  7423. { 0x00002000, 0x1c000},
  7424. { 0xffffffff, 0x00000}
  7425. }, mem_tbl_5705[] = {
  7426. { 0x00000100, 0x0000c},
  7427. { 0x00000200, 0x00008},
  7428. { 0x00004000, 0x00800},
  7429. { 0x00006000, 0x01000},
  7430. { 0x00008000, 0x02000},
  7431. { 0x00010000, 0x0e000},
  7432. { 0xffffffff, 0x00000}
  7433. }, mem_tbl_5755[] = {
  7434. { 0x00000200, 0x00008},
  7435. { 0x00004000, 0x00800},
  7436. { 0x00006000, 0x00800},
  7437. { 0x00008000, 0x02000},
  7438. { 0x00010000, 0x0c000},
  7439. { 0xffffffff, 0x00000}
  7440. }, mem_tbl_5906[] = {
  7441. { 0x00000200, 0x00008},
  7442. { 0x00004000, 0x00400},
  7443. { 0x00006000, 0x00400},
  7444. { 0x00008000, 0x01000},
  7445. { 0x00010000, 0x01000},
  7446. { 0xffffffff, 0x00000}
  7447. };
  7448. struct mem_entry *mem_tbl;
  7449. int err = 0;
  7450. int i;
  7451. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7452. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7453. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  7454. mem_tbl = mem_tbl_5755;
  7455. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  7456. mem_tbl = mem_tbl_5906;
  7457. else
  7458. mem_tbl = mem_tbl_5705;
  7459. } else
  7460. mem_tbl = mem_tbl_570x;
  7461. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  7462. if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
  7463. mem_tbl[i].len)) != 0)
  7464. break;
  7465. }
  7466. return err;
  7467. }
  7468. #define TG3_MAC_LOOPBACK 0
  7469. #define TG3_PHY_LOOPBACK 1
  7470. static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
  7471. {
  7472. u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
  7473. u32 desc_idx;
  7474. struct sk_buff *skb, *rx_skb;
  7475. u8 *tx_data;
  7476. dma_addr_t map;
  7477. int num_pkts, tx_len, rx_len, i, err;
  7478. struct tg3_rx_buffer_desc *desc;
  7479. if (loopback_mode == TG3_MAC_LOOPBACK) {
  7480. /* HW errata - mac loopback fails in some cases on 5780.
  7481. * Normal traffic and PHY loopback are not affected by
  7482. * errata.
  7483. */
  7484. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
  7485. return 0;
  7486. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  7487. MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
  7488. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  7489. mac_mode |= MAC_MODE_PORT_MODE_MII;
  7490. else
  7491. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  7492. tw32(MAC_MODE, mac_mode);
  7493. } else if (loopback_mode == TG3_PHY_LOOPBACK) {
  7494. u32 val;
  7495. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  7496. u32 phytest;
  7497. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
  7498. u32 phy;
  7499. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  7500. phytest | MII_TG3_EPHY_SHADOW_EN);
  7501. if (!tg3_readphy(tp, 0x1b, &phy))
  7502. tg3_writephy(tp, 0x1b, phy & ~0x20);
  7503. if (!tg3_readphy(tp, 0x10, &phy))
  7504. tg3_writephy(tp, 0x10, phy & ~0x4000);
  7505. tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
  7506. }
  7507. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
  7508. } else
  7509. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
  7510. tg3_writephy(tp, MII_BMCR, val);
  7511. udelay(40);
  7512. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  7513. MAC_MODE_LINK_POLARITY;
  7514. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  7515. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
  7516. mac_mode |= MAC_MODE_PORT_MODE_MII;
  7517. } else
  7518. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  7519. /* reset to prevent losing 1st rx packet intermittently */
  7520. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  7521. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  7522. udelay(10);
  7523. tw32_f(MAC_RX_MODE, tp->rx_mode);
  7524. }
  7525. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  7526. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  7527. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  7528. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  7529. }
  7530. tw32(MAC_MODE, mac_mode);
  7531. }
  7532. else
  7533. return -EINVAL;
  7534. err = -EIO;
  7535. tx_len = 1514;
  7536. skb = netdev_alloc_skb(tp->dev, tx_len);
  7537. if (!skb)
  7538. return -ENOMEM;
  7539. tx_data = skb_put(skb, tx_len);
  7540. memcpy(tx_data, tp->dev->dev_addr, 6);
  7541. memset(tx_data + 6, 0x0, 8);
  7542. tw32(MAC_RX_MTU_SIZE, tx_len + 4);
  7543. for (i = 14; i < tx_len; i++)
  7544. tx_data[i] = (u8) (i & 0xff);
  7545. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  7546. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7547. HOSTCC_MODE_NOW);
  7548. udelay(10);
  7549. rx_start_idx = tp->hw_status->idx[0].rx_producer;
  7550. num_pkts = 0;
  7551. tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
  7552. tp->tx_prod++;
  7553. num_pkts++;
  7554. tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
  7555. tp->tx_prod);
  7556. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
  7557. udelay(10);
  7558. /* 250 usec to allow enough time on some 10/100 Mbps devices. */
  7559. for (i = 0; i < 25; i++) {
  7560. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7561. HOSTCC_MODE_NOW);
  7562. udelay(10);
  7563. tx_idx = tp->hw_status->idx[0].tx_consumer;
  7564. rx_idx = tp->hw_status->idx[0].rx_producer;
  7565. if ((tx_idx == tp->tx_prod) &&
  7566. (rx_idx == (rx_start_idx + num_pkts)))
  7567. break;
  7568. }
  7569. pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
  7570. dev_kfree_skb(skb);
  7571. if (tx_idx != tp->tx_prod)
  7572. goto out;
  7573. if (rx_idx != rx_start_idx + num_pkts)
  7574. goto out;
  7575. desc = &tp->rx_rcb[rx_start_idx];
  7576. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  7577. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  7578. if (opaque_key != RXD_OPAQUE_RING_STD)
  7579. goto out;
  7580. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  7581. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  7582. goto out;
  7583. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
  7584. if (rx_len != tx_len)
  7585. goto out;
  7586. rx_skb = tp->rx_std_buffers[desc_idx].skb;
  7587. map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
  7588. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
  7589. for (i = 14; i < tx_len; i++) {
  7590. if (*(rx_skb->data + i) != (u8) (i & 0xff))
  7591. goto out;
  7592. }
  7593. err = 0;
  7594. /* tg3_free_rings will unmap and free the rx_skb */
  7595. out:
  7596. return err;
  7597. }
  7598. #define TG3_MAC_LOOPBACK_FAILED 1
  7599. #define TG3_PHY_LOOPBACK_FAILED 2
  7600. #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
  7601. TG3_PHY_LOOPBACK_FAILED)
  7602. static int tg3_test_loopback(struct tg3 *tp)
  7603. {
  7604. int err = 0;
  7605. if (!netif_running(tp->dev))
  7606. return TG3_LOOPBACK_FAILED;
  7607. err = tg3_reset_hw(tp, 1);
  7608. if (err)
  7609. return TG3_LOOPBACK_FAILED;
  7610. if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
  7611. err |= TG3_MAC_LOOPBACK_FAILED;
  7612. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  7613. if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
  7614. err |= TG3_PHY_LOOPBACK_FAILED;
  7615. }
  7616. return err;
  7617. }
  7618. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  7619. u64 *data)
  7620. {
  7621. struct tg3 *tp = netdev_priv(dev);
  7622. if (tp->link_config.phy_is_low_power)
  7623. tg3_set_power_state(tp, PCI_D0);
  7624. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  7625. if (tg3_test_nvram(tp) != 0) {
  7626. etest->flags |= ETH_TEST_FL_FAILED;
  7627. data[0] = 1;
  7628. }
  7629. if (tg3_test_link(tp) != 0) {
  7630. etest->flags |= ETH_TEST_FL_FAILED;
  7631. data[1] = 1;
  7632. }
  7633. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  7634. int err, irq_sync = 0;
  7635. if (netif_running(dev)) {
  7636. tg3_netif_stop(tp);
  7637. irq_sync = 1;
  7638. }
  7639. tg3_full_lock(tp, irq_sync);
  7640. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  7641. err = tg3_nvram_lock(tp);
  7642. tg3_halt_cpu(tp, RX_CPU_BASE);
  7643. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  7644. tg3_halt_cpu(tp, TX_CPU_BASE);
  7645. if (!err)
  7646. tg3_nvram_unlock(tp);
  7647. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  7648. tg3_phy_reset(tp);
  7649. if (tg3_test_registers(tp) != 0) {
  7650. etest->flags |= ETH_TEST_FL_FAILED;
  7651. data[2] = 1;
  7652. }
  7653. if (tg3_test_memory(tp) != 0) {
  7654. etest->flags |= ETH_TEST_FL_FAILED;
  7655. data[3] = 1;
  7656. }
  7657. if ((data[4] = tg3_test_loopback(tp)) != 0)
  7658. etest->flags |= ETH_TEST_FL_FAILED;
  7659. tg3_full_unlock(tp);
  7660. if (tg3_test_interrupt(tp) != 0) {
  7661. etest->flags |= ETH_TEST_FL_FAILED;
  7662. data[5] = 1;
  7663. }
  7664. tg3_full_lock(tp, 0);
  7665. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7666. if (netif_running(dev)) {
  7667. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  7668. if (!tg3_restart_hw(tp, 1))
  7669. tg3_netif_start(tp);
  7670. }
  7671. tg3_full_unlock(tp);
  7672. }
  7673. if (tp->link_config.phy_is_low_power)
  7674. tg3_set_power_state(tp, PCI_D3hot);
  7675. }
  7676. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  7677. {
  7678. struct mii_ioctl_data *data = if_mii(ifr);
  7679. struct tg3 *tp = netdev_priv(dev);
  7680. int err;
  7681. switch(cmd) {
  7682. case SIOCGMIIPHY:
  7683. data->phy_id = PHY_ADDR;
  7684. /* fallthru */
  7685. case SIOCGMIIREG: {
  7686. u32 mii_regval;
  7687. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7688. break; /* We have no PHY */
  7689. if (tp->link_config.phy_is_low_power)
  7690. return -EAGAIN;
  7691. spin_lock_bh(&tp->lock);
  7692. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  7693. spin_unlock_bh(&tp->lock);
  7694. data->val_out = mii_regval;
  7695. return err;
  7696. }
  7697. case SIOCSMIIREG:
  7698. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7699. break; /* We have no PHY */
  7700. if (!capable(CAP_NET_ADMIN))
  7701. return -EPERM;
  7702. if (tp->link_config.phy_is_low_power)
  7703. return -EAGAIN;
  7704. spin_lock_bh(&tp->lock);
  7705. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  7706. spin_unlock_bh(&tp->lock);
  7707. return err;
  7708. default:
  7709. /* do nothing */
  7710. break;
  7711. }
  7712. return -EOPNOTSUPP;
  7713. }
  7714. #if TG3_VLAN_TAG_USED
  7715. static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  7716. {
  7717. struct tg3 *tp = netdev_priv(dev);
  7718. if (netif_running(dev))
  7719. tg3_netif_stop(tp);
  7720. tg3_full_lock(tp, 0);
  7721. tp->vlgrp = grp;
  7722. /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  7723. __tg3_set_rx_mode(dev);
  7724. tg3_full_unlock(tp);
  7725. if (netif_running(dev))
  7726. tg3_netif_start(tp);
  7727. }
  7728. static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  7729. {
  7730. struct tg3 *tp = netdev_priv(dev);
  7731. if (netif_running(dev))
  7732. tg3_netif_stop(tp);
  7733. tg3_full_lock(tp, 0);
  7734. vlan_group_set_device(tp->vlgrp, vid, NULL);
  7735. tg3_full_unlock(tp);
  7736. if (netif_running(dev))
  7737. tg3_netif_start(tp);
  7738. }
  7739. #endif
  7740. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  7741. {
  7742. struct tg3 *tp = netdev_priv(dev);
  7743. memcpy(ec, &tp->coal, sizeof(*ec));
  7744. return 0;
  7745. }
  7746. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  7747. {
  7748. struct tg3 *tp = netdev_priv(dev);
  7749. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  7750. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  7751. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  7752. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  7753. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  7754. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  7755. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  7756. }
  7757. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  7758. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  7759. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  7760. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  7761. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  7762. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  7763. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  7764. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  7765. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  7766. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  7767. return -EINVAL;
  7768. /* No rx interrupts will be generated if both are zero */
  7769. if ((ec->rx_coalesce_usecs == 0) &&
  7770. (ec->rx_max_coalesced_frames == 0))
  7771. return -EINVAL;
  7772. /* No tx interrupts will be generated if both are zero */
  7773. if ((ec->tx_coalesce_usecs == 0) &&
  7774. (ec->tx_max_coalesced_frames == 0))
  7775. return -EINVAL;
  7776. /* Only copy relevant parameters, ignore all others. */
  7777. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  7778. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  7779. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  7780. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  7781. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  7782. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  7783. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  7784. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  7785. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  7786. if (netif_running(dev)) {
  7787. tg3_full_lock(tp, 0);
  7788. __tg3_set_coalesce(tp, &tp->coal);
  7789. tg3_full_unlock(tp);
  7790. }
  7791. return 0;
  7792. }
  7793. static const struct ethtool_ops tg3_ethtool_ops = {
  7794. .get_settings = tg3_get_settings,
  7795. .set_settings = tg3_set_settings,
  7796. .get_drvinfo = tg3_get_drvinfo,
  7797. .get_regs_len = tg3_get_regs_len,
  7798. .get_regs = tg3_get_regs,
  7799. .get_wol = tg3_get_wol,
  7800. .set_wol = tg3_set_wol,
  7801. .get_msglevel = tg3_get_msglevel,
  7802. .set_msglevel = tg3_set_msglevel,
  7803. .nway_reset = tg3_nway_reset,
  7804. .get_link = ethtool_op_get_link,
  7805. .get_eeprom_len = tg3_get_eeprom_len,
  7806. .get_eeprom = tg3_get_eeprom,
  7807. .set_eeprom = tg3_set_eeprom,
  7808. .get_ringparam = tg3_get_ringparam,
  7809. .set_ringparam = tg3_set_ringparam,
  7810. .get_pauseparam = tg3_get_pauseparam,
  7811. .set_pauseparam = tg3_set_pauseparam,
  7812. .get_rx_csum = tg3_get_rx_csum,
  7813. .set_rx_csum = tg3_set_rx_csum,
  7814. .get_tx_csum = ethtool_op_get_tx_csum,
  7815. .set_tx_csum = tg3_set_tx_csum,
  7816. .get_sg = ethtool_op_get_sg,
  7817. .set_sg = ethtool_op_set_sg,
  7818. .get_tso = ethtool_op_get_tso,
  7819. .set_tso = tg3_set_tso,
  7820. .self_test_count = tg3_get_test_count,
  7821. .self_test = tg3_self_test,
  7822. .get_strings = tg3_get_strings,
  7823. .phys_id = tg3_phys_id,
  7824. .get_stats_count = tg3_get_stats_count,
  7825. .get_ethtool_stats = tg3_get_ethtool_stats,
  7826. .get_coalesce = tg3_get_coalesce,
  7827. .set_coalesce = tg3_set_coalesce,
  7828. .get_perm_addr = ethtool_op_get_perm_addr,
  7829. };
  7830. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  7831. {
  7832. u32 cursize, val, magic;
  7833. tp->nvram_size = EEPROM_CHIP_SIZE;
  7834. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  7835. return;
  7836. if ((magic != TG3_EEPROM_MAGIC) &&
  7837. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  7838. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  7839. return;
  7840. /*
  7841. * Size the chip by reading offsets at increasing powers of two.
  7842. * When we encounter our validation signature, we know the addressing
  7843. * has wrapped around, and thus have our chip size.
  7844. */
  7845. cursize = 0x10;
  7846. while (cursize < tp->nvram_size) {
  7847. if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
  7848. return;
  7849. if (val == magic)
  7850. break;
  7851. cursize <<= 1;
  7852. }
  7853. tp->nvram_size = cursize;
  7854. }
  7855. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  7856. {
  7857. u32 val;
  7858. if (tg3_nvram_read_swab(tp, 0, &val) != 0)
  7859. return;
  7860. /* Selfboot format */
  7861. if (val != TG3_EEPROM_MAGIC) {
  7862. tg3_get_eeprom_size(tp);
  7863. return;
  7864. }
  7865. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  7866. if (val != 0) {
  7867. tp->nvram_size = (val >> 16) * 1024;
  7868. return;
  7869. }
  7870. }
  7871. tp->nvram_size = 0x20000;
  7872. }
  7873. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  7874. {
  7875. u32 nvcfg1;
  7876. nvcfg1 = tr32(NVRAM_CFG1);
  7877. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  7878. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  7879. }
  7880. else {
  7881. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  7882. tw32(NVRAM_CFG1, nvcfg1);
  7883. }
  7884. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  7885. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  7886. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  7887. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  7888. tp->nvram_jedecnum = JEDEC_ATMEL;
  7889. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  7890. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7891. break;
  7892. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  7893. tp->nvram_jedecnum = JEDEC_ATMEL;
  7894. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  7895. break;
  7896. case FLASH_VENDOR_ATMEL_EEPROM:
  7897. tp->nvram_jedecnum = JEDEC_ATMEL;
  7898. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  7899. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7900. break;
  7901. case FLASH_VENDOR_ST:
  7902. tp->nvram_jedecnum = JEDEC_ST;
  7903. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  7904. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7905. break;
  7906. case FLASH_VENDOR_SAIFUN:
  7907. tp->nvram_jedecnum = JEDEC_SAIFUN;
  7908. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  7909. break;
  7910. case FLASH_VENDOR_SST_SMALL:
  7911. case FLASH_VENDOR_SST_LARGE:
  7912. tp->nvram_jedecnum = JEDEC_SST;
  7913. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  7914. break;
  7915. }
  7916. }
  7917. else {
  7918. tp->nvram_jedecnum = JEDEC_ATMEL;
  7919. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  7920. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7921. }
  7922. }
  7923. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  7924. {
  7925. u32 nvcfg1;
  7926. nvcfg1 = tr32(NVRAM_CFG1);
  7927. /* NVRAM protection for TPM */
  7928. if (nvcfg1 & (1 << 27))
  7929. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  7930. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  7931. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  7932. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  7933. tp->nvram_jedecnum = JEDEC_ATMEL;
  7934. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7935. break;
  7936. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  7937. tp->nvram_jedecnum = JEDEC_ATMEL;
  7938. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7939. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  7940. break;
  7941. case FLASH_5752VENDOR_ST_M45PE10:
  7942. case FLASH_5752VENDOR_ST_M45PE20:
  7943. case FLASH_5752VENDOR_ST_M45PE40:
  7944. tp->nvram_jedecnum = JEDEC_ST;
  7945. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7946. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  7947. break;
  7948. }
  7949. if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
  7950. switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  7951. case FLASH_5752PAGE_SIZE_256:
  7952. tp->nvram_pagesize = 256;
  7953. break;
  7954. case FLASH_5752PAGE_SIZE_512:
  7955. tp->nvram_pagesize = 512;
  7956. break;
  7957. case FLASH_5752PAGE_SIZE_1K:
  7958. tp->nvram_pagesize = 1024;
  7959. break;
  7960. case FLASH_5752PAGE_SIZE_2K:
  7961. tp->nvram_pagesize = 2048;
  7962. break;
  7963. case FLASH_5752PAGE_SIZE_4K:
  7964. tp->nvram_pagesize = 4096;
  7965. break;
  7966. case FLASH_5752PAGE_SIZE_264:
  7967. tp->nvram_pagesize = 264;
  7968. break;
  7969. }
  7970. }
  7971. else {
  7972. /* For eeprom, set pagesize to maximum eeprom size */
  7973. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  7974. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  7975. tw32(NVRAM_CFG1, nvcfg1);
  7976. }
  7977. }
  7978. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  7979. {
  7980. u32 nvcfg1;
  7981. nvcfg1 = tr32(NVRAM_CFG1);
  7982. /* NVRAM protection for TPM */
  7983. if (nvcfg1 & (1 << 27))
  7984. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  7985. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  7986. case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
  7987. case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
  7988. tp->nvram_jedecnum = JEDEC_ATMEL;
  7989. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7990. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  7991. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  7992. tw32(NVRAM_CFG1, nvcfg1);
  7993. break;
  7994. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  7995. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  7996. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  7997. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  7998. case FLASH_5755VENDOR_ATMEL_FLASH_4:
  7999. tp->nvram_jedecnum = JEDEC_ATMEL;
  8000. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8001. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8002. tp->nvram_pagesize = 264;
  8003. break;
  8004. case FLASH_5752VENDOR_ST_M45PE10:
  8005. case FLASH_5752VENDOR_ST_M45PE20:
  8006. case FLASH_5752VENDOR_ST_M45PE40:
  8007. tp->nvram_jedecnum = JEDEC_ST;
  8008. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8009. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8010. tp->nvram_pagesize = 256;
  8011. break;
  8012. }
  8013. }
  8014. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  8015. {
  8016. u32 nvcfg1;
  8017. nvcfg1 = tr32(NVRAM_CFG1);
  8018. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  8019. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  8020. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  8021. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  8022. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  8023. tp->nvram_jedecnum = JEDEC_ATMEL;
  8024. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8025. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8026. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8027. tw32(NVRAM_CFG1, nvcfg1);
  8028. break;
  8029. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  8030. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8031. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8032. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8033. tp->nvram_jedecnum = JEDEC_ATMEL;
  8034. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8035. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8036. tp->nvram_pagesize = 264;
  8037. break;
  8038. case FLASH_5752VENDOR_ST_M45PE10:
  8039. case FLASH_5752VENDOR_ST_M45PE20:
  8040. case FLASH_5752VENDOR_ST_M45PE40:
  8041. tp->nvram_jedecnum = JEDEC_ST;
  8042. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8043. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8044. tp->nvram_pagesize = 256;
  8045. break;
  8046. }
  8047. }
  8048. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  8049. {
  8050. tp->nvram_jedecnum = JEDEC_ATMEL;
  8051. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8052. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8053. }
  8054. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  8055. static void __devinit tg3_nvram_init(struct tg3 *tp)
  8056. {
  8057. tw32_f(GRC_EEPROM_ADDR,
  8058. (EEPROM_ADDR_FSM_RESET |
  8059. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  8060. EEPROM_ADDR_CLKPERD_SHIFT)));
  8061. msleep(1);
  8062. /* Enable seeprom accesses. */
  8063. tw32_f(GRC_LOCAL_CTRL,
  8064. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  8065. udelay(100);
  8066. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  8067. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  8068. tp->tg3_flags |= TG3_FLAG_NVRAM;
  8069. if (tg3_nvram_lock(tp)) {
  8070. printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
  8071. "tg3_nvram_init failed.\n", tp->dev->name);
  8072. return;
  8073. }
  8074. tg3_enable_nvram_access(tp);
  8075. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  8076. tg3_get_5752_nvram_info(tp);
  8077. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  8078. tg3_get_5755_nvram_info(tp);
  8079. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  8080. tg3_get_5787_nvram_info(tp);
  8081. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8082. tg3_get_5906_nvram_info(tp);
  8083. else
  8084. tg3_get_nvram_info(tp);
  8085. tg3_get_nvram_size(tp);
  8086. tg3_disable_nvram_access(tp);
  8087. tg3_nvram_unlock(tp);
  8088. } else {
  8089. tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  8090. tg3_get_eeprom_size(tp);
  8091. }
  8092. }
  8093. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  8094. u32 offset, u32 *val)
  8095. {
  8096. u32 tmp;
  8097. int i;
  8098. if (offset > EEPROM_ADDR_ADDR_MASK ||
  8099. (offset % 4) != 0)
  8100. return -EINVAL;
  8101. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  8102. EEPROM_ADDR_DEVID_MASK |
  8103. EEPROM_ADDR_READ);
  8104. tw32(GRC_EEPROM_ADDR,
  8105. tmp |
  8106. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8107. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  8108. EEPROM_ADDR_ADDR_MASK) |
  8109. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  8110. for (i = 0; i < 1000; i++) {
  8111. tmp = tr32(GRC_EEPROM_ADDR);
  8112. if (tmp & EEPROM_ADDR_COMPLETE)
  8113. break;
  8114. msleep(1);
  8115. }
  8116. if (!(tmp & EEPROM_ADDR_COMPLETE))
  8117. return -EBUSY;
  8118. *val = tr32(GRC_EEPROM_DATA);
  8119. return 0;
  8120. }
  8121. #define NVRAM_CMD_TIMEOUT 10000
  8122. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  8123. {
  8124. int i;
  8125. tw32(NVRAM_CMD, nvram_cmd);
  8126. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  8127. udelay(10);
  8128. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  8129. udelay(10);
  8130. break;
  8131. }
  8132. }
  8133. if (i == NVRAM_CMD_TIMEOUT) {
  8134. return -EBUSY;
  8135. }
  8136. return 0;
  8137. }
  8138. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  8139. {
  8140. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8141. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8142. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8143. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8144. addr = ((addr / tp->nvram_pagesize) <<
  8145. ATMEL_AT45DB0X1B_PAGE_POS) +
  8146. (addr % tp->nvram_pagesize);
  8147. return addr;
  8148. }
  8149. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  8150. {
  8151. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8152. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8153. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8154. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8155. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  8156. tp->nvram_pagesize) +
  8157. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  8158. return addr;
  8159. }
  8160. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  8161. {
  8162. int ret;
  8163. if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  8164. return tg3_nvram_read_using_eeprom(tp, offset, val);
  8165. offset = tg3_nvram_phys_addr(tp, offset);
  8166. if (offset > NVRAM_ADDR_MSK)
  8167. return -EINVAL;
  8168. ret = tg3_nvram_lock(tp);
  8169. if (ret)
  8170. return ret;
  8171. tg3_enable_nvram_access(tp);
  8172. tw32(NVRAM_ADDR, offset);
  8173. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  8174. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  8175. if (ret == 0)
  8176. *val = swab32(tr32(NVRAM_RDDATA));
  8177. tg3_disable_nvram_access(tp);
  8178. tg3_nvram_unlock(tp);
  8179. return ret;
  8180. }
  8181. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
  8182. {
  8183. int err;
  8184. u32 tmp;
  8185. err = tg3_nvram_read(tp, offset, &tmp);
  8186. *val = swab32(tmp);
  8187. return err;
  8188. }
  8189. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  8190. u32 offset, u32 len, u8 *buf)
  8191. {
  8192. int i, j, rc = 0;
  8193. u32 val;
  8194. for (i = 0; i < len; i += 4) {
  8195. u32 addr, data;
  8196. addr = offset + i;
  8197. memcpy(&data, buf + i, 4);
  8198. tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
  8199. val = tr32(GRC_EEPROM_ADDR);
  8200. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  8201. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  8202. EEPROM_ADDR_READ);
  8203. tw32(GRC_EEPROM_ADDR, val |
  8204. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8205. (addr & EEPROM_ADDR_ADDR_MASK) |
  8206. EEPROM_ADDR_START |
  8207. EEPROM_ADDR_WRITE);
  8208. for (j = 0; j < 1000; j++) {
  8209. val = tr32(GRC_EEPROM_ADDR);
  8210. if (val & EEPROM_ADDR_COMPLETE)
  8211. break;
  8212. msleep(1);
  8213. }
  8214. if (!(val & EEPROM_ADDR_COMPLETE)) {
  8215. rc = -EBUSY;
  8216. break;
  8217. }
  8218. }
  8219. return rc;
  8220. }
  8221. /* offset and length are dword aligned */
  8222. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  8223. u8 *buf)
  8224. {
  8225. int ret = 0;
  8226. u32 pagesize = tp->nvram_pagesize;
  8227. u32 pagemask = pagesize - 1;
  8228. u32 nvram_cmd;
  8229. u8 *tmp;
  8230. tmp = kmalloc(pagesize, GFP_KERNEL);
  8231. if (tmp == NULL)
  8232. return -ENOMEM;
  8233. while (len) {
  8234. int j;
  8235. u32 phy_addr, page_off, size;
  8236. phy_addr = offset & ~pagemask;
  8237. for (j = 0; j < pagesize; j += 4) {
  8238. if ((ret = tg3_nvram_read(tp, phy_addr + j,
  8239. (u32 *) (tmp + j))))
  8240. break;
  8241. }
  8242. if (ret)
  8243. break;
  8244. page_off = offset & pagemask;
  8245. size = pagesize;
  8246. if (len < size)
  8247. size = len;
  8248. len -= size;
  8249. memcpy(tmp + page_off, buf, size);
  8250. offset = offset + (pagesize - page_off);
  8251. tg3_enable_nvram_access(tp);
  8252. /*
  8253. * Before we can erase the flash page, we need
  8254. * to issue a special "write enable" command.
  8255. */
  8256. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8257. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8258. break;
  8259. /* Erase the target page */
  8260. tw32(NVRAM_ADDR, phy_addr);
  8261. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  8262. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  8263. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8264. break;
  8265. /* Issue another write enable to start the write. */
  8266. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8267. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8268. break;
  8269. for (j = 0; j < pagesize; j += 4) {
  8270. u32 data;
  8271. data = *((u32 *) (tmp + j));
  8272. tw32(NVRAM_WRDATA, cpu_to_be32(data));
  8273. tw32(NVRAM_ADDR, phy_addr + j);
  8274. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  8275. NVRAM_CMD_WR;
  8276. if (j == 0)
  8277. nvram_cmd |= NVRAM_CMD_FIRST;
  8278. else if (j == (pagesize - 4))
  8279. nvram_cmd |= NVRAM_CMD_LAST;
  8280. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8281. break;
  8282. }
  8283. if (ret)
  8284. break;
  8285. }
  8286. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8287. tg3_nvram_exec_cmd(tp, nvram_cmd);
  8288. kfree(tmp);
  8289. return ret;
  8290. }
  8291. /* offset and length are dword aligned */
  8292. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  8293. u8 *buf)
  8294. {
  8295. int i, ret = 0;
  8296. for (i = 0; i < len; i += 4, offset += 4) {
  8297. u32 data, page_off, phy_addr, nvram_cmd;
  8298. memcpy(&data, buf + i, 4);
  8299. tw32(NVRAM_WRDATA, cpu_to_be32(data));
  8300. page_off = offset % tp->nvram_pagesize;
  8301. phy_addr = tg3_nvram_phys_addr(tp, offset);
  8302. tw32(NVRAM_ADDR, phy_addr);
  8303. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  8304. if ((page_off == 0) || (i == 0))
  8305. nvram_cmd |= NVRAM_CMD_FIRST;
  8306. if (page_off == (tp->nvram_pagesize - 4))
  8307. nvram_cmd |= NVRAM_CMD_LAST;
  8308. if (i == (len - 4))
  8309. nvram_cmd |= NVRAM_CMD_LAST;
  8310. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
  8311. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
  8312. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
  8313. (tp->nvram_jedecnum == JEDEC_ST) &&
  8314. (nvram_cmd & NVRAM_CMD_FIRST)) {
  8315. if ((ret = tg3_nvram_exec_cmd(tp,
  8316. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  8317. NVRAM_CMD_DONE)))
  8318. break;
  8319. }
  8320. if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  8321. /* We always do complete word writes to eeprom. */
  8322. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  8323. }
  8324. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8325. break;
  8326. }
  8327. return ret;
  8328. }
  8329. /* offset and length are dword aligned */
  8330. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  8331. {
  8332. int ret;
  8333. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  8334. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  8335. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  8336. udelay(40);
  8337. }
  8338. if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
  8339. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  8340. }
  8341. else {
  8342. u32 grc_mode;
  8343. ret = tg3_nvram_lock(tp);
  8344. if (ret)
  8345. return ret;
  8346. tg3_enable_nvram_access(tp);
  8347. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  8348. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
  8349. tw32(NVRAM_WRITE1, 0x406);
  8350. grc_mode = tr32(GRC_MODE);
  8351. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  8352. if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
  8353. !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  8354. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  8355. buf);
  8356. }
  8357. else {
  8358. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  8359. buf);
  8360. }
  8361. grc_mode = tr32(GRC_MODE);
  8362. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  8363. tg3_disable_nvram_access(tp);
  8364. tg3_nvram_unlock(tp);
  8365. }
  8366. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  8367. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8368. udelay(40);
  8369. }
  8370. return ret;
  8371. }
  8372. struct subsys_tbl_ent {
  8373. u16 subsys_vendor, subsys_devid;
  8374. u32 phy_id;
  8375. };
  8376. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  8377. /* Broadcom boards. */
  8378. { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
  8379. { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
  8380. { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
  8381. { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
  8382. { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
  8383. { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
  8384. { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
  8385. { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
  8386. { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
  8387. { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
  8388. { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
  8389. /* 3com boards. */
  8390. { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
  8391. { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
  8392. { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
  8393. { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
  8394. { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
  8395. /* DELL boards. */
  8396. { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
  8397. { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  8398. { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  8399. { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
  8400. /* Compaq boards. */
  8401. { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
  8402. { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
  8403. { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
  8404. { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
  8405. { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
  8406. /* IBM boards. */
  8407. { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
  8408. };
  8409. static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
  8410. {
  8411. int i;
  8412. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  8413. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  8414. tp->pdev->subsystem_vendor) &&
  8415. (subsys_id_to_phy_id[i].subsys_devid ==
  8416. tp->pdev->subsystem_device))
  8417. return &subsys_id_to_phy_id[i];
  8418. }
  8419. return NULL;
  8420. }
  8421. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  8422. {
  8423. u32 val;
  8424. u16 pmcsr;
  8425. /* On some early chips the SRAM cannot be accessed in D3hot state,
  8426. * so need make sure we're in D0.
  8427. */
  8428. pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
  8429. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  8430. pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
  8431. msleep(1);
  8432. /* Make sure register accesses (indirect or otherwise)
  8433. * will function correctly.
  8434. */
  8435. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8436. tp->misc_host_ctrl);
  8437. /* The memory arbiter has to be enabled in order for SRAM accesses
  8438. * to succeed. Normally on powerup the tg3 chip firmware will make
  8439. * sure it is enabled, but other entities such as system netboot
  8440. * code might disable it.
  8441. */
  8442. val = tr32(MEMARB_MODE);
  8443. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  8444. tp->phy_id = PHY_ID_INVALID;
  8445. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8446. /* Assume an onboard device by default. */
  8447. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  8448. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8449. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  8450. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8451. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  8452. }
  8453. return;
  8454. }
  8455. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  8456. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  8457. u32 nic_cfg, led_cfg;
  8458. u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
  8459. int eeprom_phy_serdes = 0;
  8460. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  8461. tp->nic_sram_data_cfg = nic_cfg;
  8462. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  8463. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  8464. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
  8465. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
  8466. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
  8467. (ver > 0) && (ver < 0x100))
  8468. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  8469. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  8470. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  8471. eeprom_phy_serdes = 1;
  8472. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  8473. if (nic_phy_id != 0) {
  8474. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  8475. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  8476. eeprom_phy_id = (id1 >> 16) << 10;
  8477. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  8478. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  8479. } else
  8480. eeprom_phy_id = 0;
  8481. tp->phy_id = eeprom_phy_id;
  8482. if (eeprom_phy_serdes) {
  8483. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  8484. tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
  8485. else
  8486. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8487. }
  8488. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8489. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  8490. SHASTA_EXT_LED_MODE_MASK);
  8491. else
  8492. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  8493. switch (led_cfg) {
  8494. default:
  8495. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  8496. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8497. break;
  8498. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  8499. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  8500. break;
  8501. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  8502. tp->led_ctrl = LED_CTRL_MODE_MAC;
  8503. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  8504. * read on some older 5700/5701 bootcode.
  8505. */
  8506. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  8507. ASIC_REV_5700 ||
  8508. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  8509. ASIC_REV_5701)
  8510. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8511. break;
  8512. case SHASTA_EXT_LED_SHARED:
  8513. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  8514. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  8515. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  8516. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  8517. LED_CTRL_MODE_PHY_2);
  8518. break;
  8519. case SHASTA_EXT_LED_MAC:
  8520. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  8521. break;
  8522. case SHASTA_EXT_LED_COMBO:
  8523. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  8524. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  8525. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  8526. LED_CTRL_MODE_PHY_2);
  8527. break;
  8528. };
  8529. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  8530. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  8531. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  8532. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  8533. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  8534. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  8535. if ((tp->pdev->subsystem_vendor ==
  8536. PCI_VENDOR_ID_ARIMA) &&
  8537. (tp->pdev->subsystem_device == 0x205a ||
  8538. tp->pdev->subsystem_device == 0x2063))
  8539. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8540. } else {
  8541. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8542. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  8543. }
  8544. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  8545. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  8546. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8547. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  8548. }
  8549. if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
  8550. tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
  8551. if (cfg2 & (1 << 17))
  8552. tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
  8553. /* serdes signal pre-emphasis in register 0x590 set by */
  8554. /* bootcode if bit 18 is set */
  8555. if (cfg2 & (1 << 18))
  8556. tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
  8557. }
  8558. }
  8559. static int __devinit tg3_phy_probe(struct tg3 *tp)
  8560. {
  8561. u32 hw_phy_id_1, hw_phy_id_2;
  8562. u32 hw_phy_id, hw_phy_id_masked;
  8563. int err;
  8564. /* Reading the PHY ID register can conflict with ASF
  8565. * firwmare access to the PHY hardware.
  8566. */
  8567. err = 0;
  8568. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  8569. hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
  8570. } else {
  8571. /* Now read the physical PHY_ID from the chip and verify
  8572. * that it is sane. If it doesn't look good, we fall back
  8573. * to either the hard-coded table based PHY_ID and failing
  8574. * that the value found in the eeprom area.
  8575. */
  8576. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  8577. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  8578. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  8579. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  8580. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  8581. hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
  8582. }
  8583. if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
  8584. tp->phy_id = hw_phy_id;
  8585. if (hw_phy_id_masked == PHY_ID_BCM8002)
  8586. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8587. else
  8588. tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
  8589. } else {
  8590. if (tp->phy_id != PHY_ID_INVALID) {
  8591. /* Do nothing, phy ID already set up in
  8592. * tg3_get_eeprom_hw_cfg().
  8593. */
  8594. } else {
  8595. struct subsys_tbl_ent *p;
  8596. /* No eeprom signature? Try the hardcoded
  8597. * subsys device table.
  8598. */
  8599. p = lookup_by_subsys(tp);
  8600. if (!p)
  8601. return -ENODEV;
  8602. tp->phy_id = p->phy_id;
  8603. if (!tp->phy_id ||
  8604. tp->phy_id == PHY_ID_BCM8002)
  8605. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8606. }
  8607. }
  8608. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
  8609. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  8610. u32 bmsr, adv_reg, tg3_ctrl, mask;
  8611. tg3_readphy(tp, MII_BMSR, &bmsr);
  8612. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  8613. (bmsr & BMSR_LSTATUS))
  8614. goto skip_phy_reset;
  8615. err = tg3_phy_reset(tp);
  8616. if (err)
  8617. return err;
  8618. adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  8619. ADVERTISE_100HALF | ADVERTISE_100FULL |
  8620. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  8621. tg3_ctrl = 0;
  8622. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  8623. tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  8624. MII_TG3_CTRL_ADV_1000_FULL);
  8625. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  8626. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  8627. tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
  8628. MII_TG3_CTRL_ENABLE_AS_MASTER);
  8629. }
  8630. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  8631. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  8632. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  8633. if (!tg3_copper_is_advertising_all(tp, mask)) {
  8634. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  8635. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  8636. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  8637. tg3_writephy(tp, MII_BMCR,
  8638. BMCR_ANENABLE | BMCR_ANRESTART);
  8639. }
  8640. tg3_phy_set_wirespeed(tp);
  8641. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  8642. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  8643. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  8644. }
  8645. skip_phy_reset:
  8646. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  8647. err = tg3_init_5401phy_dsp(tp);
  8648. if (err)
  8649. return err;
  8650. }
  8651. if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  8652. err = tg3_init_5401phy_dsp(tp);
  8653. }
  8654. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  8655. tp->link_config.advertising =
  8656. (ADVERTISED_1000baseT_Half |
  8657. ADVERTISED_1000baseT_Full |
  8658. ADVERTISED_Autoneg |
  8659. ADVERTISED_FIBRE);
  8660. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  8661. tp->link_config.advertising &=
  8662. ~(ADVERTISED_1000baseT_Half |
  8663. ADVERTISED_1000baseT_Full);
  8664. return err;
  8665. }
  8666. static void __devinit tg3_read_partno(struct tg3 *tp)
  8667. {
  8668. unsigned char vpd_data[256];
  8669. unsigned int i;
  8670. u32 magic;
  8671. if (tg3_nvram_read_swab(tp, 0x0, &magic))
  8672. goto out_not_found;
  8673. if (magic == TG3_EEPROM_MAGIC) {
  8674. for (i = 0; i < 256; i += 4) {
  8675. u32 tmp;
  8676. if (tg3_nvram_read(tp, 0x100 + i, &tmp))
  8677. goto out_not_found;
  8678. vpd_data[i + 0] = ((tmp >> 0) & 0xff);
  8679. vpd_data[i + 1] = ((tmp >> 8) & 0xff);
  8680. vpd_data[i + 2] = ((tmp >> 16) & 0xff);
  8681. vpd_data[i + 3] = ((tmp >> 24) & 0xff);
  8682. }
  8683. } else {
  8684. int vpd_cap;
  8685. vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
  8686. for (i = 0; i < 256; i += 4) {
  8687. u32 tmp, j = 0;
  8688. u16 tmp16;
  8689. pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
  8690. i);
  8691. while (j++ < 100) {
  8692. pci_read_config_word(tp->pdev, vpd_cap +
  8693. PCI_VPD_ADDR, &tmp16);
  8694. if (tmp16 & 0x8000)
  8695. break;
  8696. msleep(1);
  8697. }
  8698. if (!(tmp16 & 0x8000))
  8699. goto out_not_found;
  8700. pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
  8701. &tmp);
  8702. tmp = cpu_to_le32(tmp);
  8703. memcpy(&vpd_data[i], &tmp, 4);
  8704. }
  8705. }
  8706. /* Now parse and find the part number. */
  8707. for (i = 0; i < 254; ) {
  8708. unsigned char val = vpd_data[i];
  8709. unsigned int block_end;
  8710. if (val == 0x82 || val == 0x91) {
  8711. i = (i + 3 +
  8712. (vpd_data[i + 1] +
  8713. (vpd_data[i + 2] << 8)));
  8714. continue;
  8715. }
  8716. if (val != 0x90)
  8717. goto out_not_found;
  8718. block_end = (i + 3 +
  8719. (vpd_data[i + 1] +
  8720. (vpd_data[i + 2] << 8)));
  8721. i += 3;
  8722. if (block_end > 256)
  8723. goto out_not_found;
  8724. while (i < (block_end - 2)) {
  8725. if (vpd_data[i + 0] == 'P' &&
  8726. vpd_data[i + 1] == 'N') {
  8727. int partno_len = vpd_data[i + 2];
  8728. i += 3;
  8729. if (partno_len > 24 || (partno_len + i) > 256)
  8730. goto out_not_found;
  8731. memcpy(tp->board_part_number,
  8732. &vpd_data[i], partno_len);
  8733. /* Success. */
  8734. return;
  8735. }
  8736. i += 3 + vpd_data[i + 2];
  8737. }
  8738. /* Part number not found. */
  8739. goto out_not_found;
  8740. }
  8741. out_not_found:
  8742. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8743. strcpy(tp->board_part_number, "BCM95906");
  8744. else
  8745. strcpy(tp->board_part_number, "none");
  8746. }
  8747. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  8748. {
  8749. u32 val, offset, start;
  8750. if (tg3_nvram_read_swab(tp, 0, &val))
  8751. return;
  8752. if (val != TG3_EEPROM_MAGIC)
  8753. return;
  8754. if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
  8755. tg3_nvram_read_swab(tp, 0x4, &start))
  8756. return;
  8757. offset = tg3_nvram_logical_addr(tp, offset);
  8758. if (tg3_nvram_read_swab(tp, offset, &val))
  8759. return;
  8760. if ((val & 0xfc000000) == 0x0c000000) {
  8761. u32 ver_offset, addr;
  8762. int i;
  8763. if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
  8764. tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
  8765. return;
  8766. if (val != 0)
  8767. return;
  8768. addr = offset + ver_offset - start;
  8769. for (i = 0; i < 16; i += 4) {
  8770. if (tg3_nvram_read(tp, addr + i, &val))
  8771. return;
  8772. val = cpu_to_le32(val);
  8773. memcpy(tp->fw_ver + i, &val, 4);
  8774. }
  8775. }
  8776. }
  8777. static int __devinit tg3_get_invariants(struct tg3 *tp)
  8778. {
  8779. static struct pci_device_id write_reorder_chipsets[] = {
  8780. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  8781. PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  8782. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  8783. PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  8784. { PCI_DEVICE(PCI_VENDOR_ID_VIA,
  8785. PCI_DEVICE_ID_VIA_8385_0) },
  8786. { },
  8787. };
  8788. u32 misc_ctrl_reg;
  8789. u32 cacheline_sz_reg;
  8790. u32 pci_state_reg, grc_misc_cfg;
  8791. u32 val;
  8792. u16 pci_cmd;
  8793. int err, pcie_cap;
  8794. /* Force memory write invalidate off. If we leave it on,
  8795. * then on 5700_BX chips we have to enable a workaround.
  8796. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  8797. * to match the cacheline size. The Broadcom driver have this
  8798. * workaround but turns MWI off all the times so never uses
  8799. * it. This seems to suggest that the workaround is insufficient.
  8800. */
  8801. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  8802. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  8803. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  8804. /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  8805. * has the register indirect write enable bit set before
  8806. * we try to access any of the MMIO registers. It is also
  8807. * critical that the PCI-X hw workaround situation is decided
  8808. * before that as well.
  8809. */
  8810. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8811. &misc_ctrl_reg);
  8812. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  8813. MISC_HOST_CTRL_CHIPREV_SHIFT);
  8814. /* Wrong chip ID in 5752 A0. This code can be removed later
  8815. * as A0 is not in production.
  8816. */
  8817. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  8818. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  8819. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  8820. * we need to disable memory and use config. cycles
  8821. * only to access all registers. The 5702/03 chips
  8822. * can mistakenly decode the special cycles from the
  8823. * ICH chipsets as memory write cycles, causing corruption
  8824. * of register and memory space. Only certain ICH bridges
  8825. * will drive special cycles with non-zero data during the
  8826. * address phase which can fall within the 5703's address
  8827. * range. This is not an ICH bug as the PCI spec allows
  8828. * non-zero address during special cycles. However, only
  8829. * these ICH bridges are known to drive non-zero addresses
  8830. * during special cycles.
  8831. *
  8832. * Since special cycles do not cross PCI bridges, we only
  8833. * enable this workaround if the 5703 is on the secondary
  8834. * bus of these ICH bridges.
  8835. */
  8836. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  8837. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  8838. static struct tg3_dev_id {
  8839. u32 vendor;
  8840. u32 device;
  8841. u32 rev;
  8842. } ich_chipsets[] = {
  8843. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  8844. PCI_ANY_ID },
  8845. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  8846. PCI_ANY_ID },
  8847. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  8848. 0xa },
  8849. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  8850. PCI_ANY_ID },
  8851. { },
  8852. };
  8853. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  8854. struct pci_dev *bridge = NULL;
  8855. while (pci_id->vendor != 0) {
  8856. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  8857. bridge);
  8858. if (!bridge) {
  8859. pci_id++;
  8860. continue;
  8861. }
  8862. if (pci_id->rev != PCI_ANY_ID) {
  8863. u8 rev;
  8864. pci_read_config_byte(bridge, PCI_REVISION_ID,
  8865. &rev);
  8866. if (rev > pci_id->rev)
  8867. continue;
  8868. }
  8869. if (bridge->subordinate &&
  8870. (bridge->subordinate->number ==
  8871. tp->pdev->bus->number)) {
  8872. tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
  8873. pci_dev_put(bridge);
  8874. break;
  8875. }
  8876. }
  8877. }
  8878. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  8879. * DMA addresses > 40-bit. This bridge may have other additional
  8880. * 57xx devices behind it in some 4-port NIC designs for example.
  8881. * Any tg3 device found behind the bridge will also need the 40-bit
  8882. * DMA workaround.
  8883. */
  8884. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  8885. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  8886. tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
  8887. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  8888. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  8889. }
  8890. else {
  8891. struct pci_dev *bridge = NULL;
  8892. do {
  8893. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  8894. PCI_DEVICE_ID_SERVERWORKS_EPB,
  8895. bridge);
  8896. if (bridge && bridge->subordinate &&
  8897. (bridge->subordinate->number <=
  8898. tp->pdev->bus->number) &&
  8899. (bridge->subordinate->subordinate >=
  8900. tp->pdev->bus->number)) {
  8901. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  8902. pci_dev_put(bridge);
  8903. break;
  8904. }
  8905. } while (bridge);
  8906. }
  8907. /* Initialize misc host control in PCI block. */
  8908. tp->misc_host_ctrl |= (misc_ctrl_reg &
  8909. MISC_HOST_CTRL_CHIPREV);
  8910. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8911. tp->misc_host_ctrl);
  8912. pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  8913. &cacheline_sz_reg);
  8914. tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
  8915. tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
  8916. tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
  8917. tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
  8918. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  8919. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  8920. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  8921. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  8922. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  8923. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  8924. tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
  8925. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
  8926. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  8927. tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
  8928. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  8929. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  8930. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  8931. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8932. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
  8933. tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
  8934. } else {
  8935. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
  8936. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  8937. ASIC_REV_5750 &&
  8938. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  8939. tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
  8940. }
  8941. }
  8942. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
  8943. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
  8944. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
  8945. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
  8946. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
  8947. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  8948. tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
  8949. pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
  8950. if (pcie_cap != 0) {
  8951. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  8952. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8953. u16 lnkctl;
  8954. pci_read_config_word(tp->pdev,
  8955. pcie_cap + PCI_EXP_LNKCTL,
  8956. &lnkctl);
  8957. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
  8958. tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
  8959. }
  8960. }
  8961. /* If we have an AMD 762 or VIA K8T800 chipset, write
  8962. * reordering to the mailbox registers done by the host
  8963. * controller can cause major troubles. We read back from
  8964. * every mailbox register write to force the writes to be
  8965. * posted to the chip in order.
  8966. */
  8967. if (pci_dev_present(write_reorder_chipsets) &&
  8968. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  8969. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  8970. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  8971. tp->pci_lat_timer < 64) {
  8972. tp->pci_lat_timer = 64;
  8973. cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
  8974. cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
  8975. cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
  8976. cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
  8977. pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  8978. cacheline_sz_reg);
  8979. }
  8980. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  8981. &pci_state_reg);
  8982. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
  8983. tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  8984. /* If this is a 5700 BX chipset, and we are in PCI-X
  8985. * mode, enable register write workaround.
  8986. *
  8987. * The workaround is to use indirect register accesses
  8988. * for all chip writes not to mailbox registers.
  8989. */
  8990. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  8991. u32 pm_reg;
  8992. u16 pci_cmd;
  8993. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  8994. /* The chip can have it's power management PCI config
  8995. * space registers clobbered due to this bug.
  8996. * So explicitly force the chip into D0 here.
  8997. */
  8998. pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
  8999. &pm_reg);
  9000. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  9001. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  9002. pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
  9003. pm_reg);
  9004. /* Also, force SERR#/PERR# in PCI command. */
  9005. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9006. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  9007. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9008. }
  9009. }
  9010. /* 5700 BX chips need to have their TX producer index mailboxes
  9011. * written twice to workaround a bug.
  9012. */
  9013. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
  9014. tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  9015. /* Back to back register writes can cause problems on this chip,
  9016. * the workaround is to read back all reg writes except those to
  9017. * mailbox regs. See tg3_write_indirect_reg32().
  9018. *
  9019. * PCI Express 5750_A0 rev chips need this workaround too.
  9020. */
  9021. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  9022. ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  9023. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
  9024. tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
  9025. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  9026. tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  9027. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  9028. tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  9029. /* Chip-specific fixup from Broadcom driver */
  9030. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  9031. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  9032. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  9033. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  9034. }
  9035. /* Default fast path register access methods */
  9036. tp->read32 = tg3_read32;
  9037. tp->write32 = tg3_write32;
  9038. tp->read32_mbox = tg3_read32;
  9039. tp->write32_mbox = tg3_write32;
  9040. tp->write32_tx_mbox = tg3_write32;
  9041. tp->write32_rx_mbox = tg3_write32;
  9042. /* Various workaround register access methods */
  9043. if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  9044. tp->write32 = tg3_write_indirect_reg32;
  9045. else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
  9046. tp->write32 = tg3_write_flush_reg32;
  9047. if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
  9048. (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
  9049. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  9050. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  9051. tp->write32_rx_mbox = tg3_write_flush_reg32;
  9052. }
  9053. if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
  9054. tp->read32 = tg3_read_indirect_reg32;
  9055. tp->write32 = tg3_write_indirect_reg32;
  9056. tp->read32_mbox = tg3_read_indirect_mbox;
  9057. tp->write32_mbox = tg3_write_indirect_mbox;
  9058. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  9059. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  9060. iounmap(tp->regs);
  9061. tp->regs = NULL;
  9062. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9063. pci_cmd &= ~PCI_COMMAND_MEMORY;
  9064. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9065. }
  9066. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9067. tp->read32_mbox = tg3_read32_mbox_5906;
  9068. tp->write32_mbox = tg3_write32_mbox_5906;
  9069. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  9070. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  9071. }
  9072. if (tp->write32 == tg3_write_indirect_reg32 ||
  9073. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  9074. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9075. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  9076. tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  9077. /* Get eeprom hw config before calling tg3_set_power_state().
  9078. * In particular, the TG3_FLG2_IS_NIC flag must be
  9079. * determined before calling tg3_set_power_state() so that
  9080. * we know whether or not to switch out of Vaux power.
  9081. * When the flag is set, it means that GPIO1 is used for eeprom
  9082. * write protect and also implies that it is a LOM where GPIOs
  9083. * are not used to switch power.
  9084. */
  9085. tg3_get_eeprom_hw_cfg(tp);
  9086. /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
  9087. * GPIO1 driven high will bring 5700's external PHY out of reset.
  9088. * It is also used as eeprom write protect on LOMs.
  9089. */
  9090. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  9091. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9092. (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
  9093. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  9094. GRC_LCLCTRL_GPIO_OUTPUT1);
  9095. /* Unused GPIO3 must be driven as output on 5752 because there
  9096. * are no pull-up resistors on unused GPIO pins.
  9097. */
  9098. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  9099. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  9100. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9101. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  9102. /* Force the chip into D0. */
  9103. err = tg3_set_power_state(tp, PCI_D0);
  9104. if (err) {
  9105. printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
  9106. pci_name(tp->pdev));
  9107. return err;
  9108. }
  9109. /* 5700 B0 chips do not support checksumming correctly due
  9110. * to hardware bugs.
  9111. */
  9112. if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  9113. tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  9114. /* Derive initial jumbo mode from MTU assigned in
  9115. * ether_setup() via the alloc_etherdev() call
  9116. */
  9117. if (tp->dev->mtu > ETH_DATA_LEN &&
  9118. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  9119. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  9120. /* Determine WakeOnLan speed to use. */
  9121. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9122. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  9123. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  9124. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  9125. tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  9126. } else {
  9127. tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  9128. }
  9129. /* A few boards don't want Ethernet@WireSpeed phy feature */
  9130. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9131. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  9132. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  9133. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  9134. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
  9135. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  9136. tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
  9137. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  9138. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  9139. tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
  9140. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  9141. tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
  9142. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9143. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9144. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
  9145. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  9146. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  9147. tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
  9148. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  9149. tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
  9150. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  9151. tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
  9152. }
  9153. tp->coalesce_mode = 0;
  9154. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  9155. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  9156. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  9157. /* Initialize MAC MI mode, polling disabled. */
  9158. tw32_f(MAC_MI_MODE, tp->mi_mode);
  9159. udelay(80);
  9160. /* Initialize data/descriptor byte/word swapping. */
  9161. val = tr32(GRC_MODE);
  9162. val &= GRC_MODE_HOST_STACKUP;
  9163. tw32(GRC_MODE, val | tp->grc_mode);
  9164. tg3_switch_clocks(tp);
  9165. /* Clear this out for sanity. */
  9166. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  9167. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  9168. &pci_state_reg);
  9169. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  9170. (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  9171. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  9172. if (chiprevid == CHIPREV_ID_5701_A0 ||
  9173. chiprevid == CHIPREV_ID_5701_B0 ||
  9174. chiprevid == CHIPREV_ID_5701_B2 ||
  9175. chiprevid == CHIPREV_ID_5701_B5) {
  9176. void __iomem *sram_base;
  9177. /* Write some dummy words into the SRAM status block
  9178. * area, see if it reads back correctly. If the return
  9179. * value is bad, force enable the PCIX workaround.
  9180. */
  9181. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  9182. writel(0x00000000, sram_base);
  9183. writel(0x00000000, sram_base + 4);
  9184. writel(0xffffffff, sram_base + 4);
  9185. if (readl(sram_base) != 0x00000000)
  9186. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  9187. }
  9188. }
  9189. udelay(50);
  9190. tg3_nvram_init(tp);
  9191. grc_misc_cfg = tr32(GRC_MISC_CFG);
  9192. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  9193. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  9194. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  9195. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  9196. tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  9197. if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  9198. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
  9199. tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
  9200. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  9201. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  9202. HOSTCC_MODE_CLRTICK_TXBD);
  9203. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  9204. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9205. tp->misc_host_ctrl);
  9206. }
  9207. /* these are limited to 10/100 only */
  9208. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  9209. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  9210. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  9211. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  9212. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  9213. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  9214. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  9215. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  9216. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  9217. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  9218. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  9219. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9220. tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  9221. err = tg3_phy_probe(tp);
  9222. if (err) {
  9223. printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
  9224. pci_name(tp->pdev), err);
  9225. /* ... but do not return immediately ... */
  9226. }
  9227. tg3_read_partno(tp);
  9228. tg3_read_fw_ver(tp);
  9229. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  9230. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  9231. } else {
  9232. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  9233. tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
  9234. else
  9235. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  9236. }
  9237. /* 5700 {AX,BX} chips have a broken status block link
  9238. * change bit implementation, so we must use the
  9239. * status register in those cases.
  9240. */
  9241. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  9242. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  9243. else
  9244. tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  9245. /* The led_ctrl is set during tg3_phy_probe, here we might
  9246. * have to force the link status polling mechanism based
  9247. * upon subsystem IDs.
  9248. */
  9249. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  9250. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  9251. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  9252. tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
  9253. TG3_FLAG_USE_LINKCHG_REG);
  9254. }
  9255. /* For all SERDES we poll the MAC status register. */
  9256. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  9257. tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  9258. else
  9259. tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  9260. /* All chips before 5787 can get confused if TX buffers
  9261. * straddle the 4GB address boundary in some cases.
  9262. */
  9263. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9264. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9265. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9266. tp->dev->hard_start_xmit = tg3_start_xmit;
  9267. else
  9268. tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
  9269. tp->rx_offset = 2;
  9270. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  9271. (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
  9272. tp->rx_offset = 0;
  9273. tp->rx_std_max_post = TG3_RX_RING_SIZE;
  9274. /* Increment the rx prod index on the rx std ring by at most
  9275. * 8 for these chips to workaround hw errata.
  9276. */
  9277. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  9278. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  9279. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9280. tp->rx_std_max_post = 8;
  9281. /* By default, disable wake-on-lan. User can change this
  9282. * using ETHTOOL_SWOL.
  9283. */
  9284. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  9285. return err;
  9286. }
  9287. #ifdef CONFIG_SPARC64
  9288. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  9289. {
  9290. struct net_device *dev = tp->dev;
  9291. struct pci_dev *pdev = tp->pdev;
  9292. struct pcidev_cookie *pcp = pdev->sysdata;
  9293. if (pcp != NULL) {
  9294. unsigned char *addr;
  9295. int len;
  9296. addr = of_get_property(pcp->prom_node, "local-mac-address",
  9297. &len);
  9298. if (addr && len == 6) {
  9299. memcpy(dev->dev_addr, addr, 6);
  9300. memcpy(dev->perm_addr, dev->dev_addr, 6);
  9301. return 0;
  9302. }
  9303. }
  9304. return -ENODEV;
  9305. }
  9306. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  9307. {
  9308. struct net_device *dev = tp->dev;
  9309. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  9310. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  9311. return 0;
  9312. }
  9313. #endif
  9314. static int __devinit tg3_get_device_address(struct tg3 *tp)
  9315. {
  9316. struct net_device *dev = tp->dev;
  9317. u32 hi, lo, mac_offset;
  9318. int addr_ok = 0;
  9319. #ifdef CONFIG_SPARC64
  9320. if (!tg3_get_macaddr_sparc(tp))
  9321. return 0;
  9322. #endif
  9323. mac_offset = 0x7c;
  9324. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  9325. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  9326. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  9327. mac_offset = 0xcc;
  9328. if (tg3_nvram_lock(tp))
  9329. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  9330. else
  9331. tg3_nvram_unlock(tp);
  9332. }
  9333. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9334. mac_offset = 0x10;
  9335. /* First try to get it from MAC address mailbox. */
  9336. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  9337. if ((hi >> 16) == 0x484b) {
  9338. dev->dev_addr[0] = (hi >> 8) & 0xff;
  9339. dev->dev_addr[1] = (hi >> 0) & 0xff;
  9340. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  9341. dev->dev_addr[2] = (lo >> 24) & 0xff;
  9342. dev->dev_addr[3] = (lo >> 16) & 0xff;
  9343. dev->dev_addr[4] = (lo >> 8) & 0xff;
  9344. dev->dev_addr[5] = (lo >> 0) & 0xff;
  9345. /* Some old bootcode may report a 0 MAC address in SRAM */
  9346. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  9347. }
  9348. if (!addr_ok) {
  9349. /* Next, try NVRAM. */
  9350. if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  9351. !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
  9352. dev->dev_addr[0] = ((hi >> 16) & 0xff);
  9353. dev->dev_addr[1] = ((hi >> 24) & 0xff);
  9354. dev->dev_addr[2] = ((lo >> 0) & 0xff);
  9355. dev->dev_addr[3] = ((lo >> 8) & 0xff);
  9356. dev->dev_addr[4] = ((lo >> 16) & 0xff);
  9357. dev->dev_addr[5] = ((lo >> 24) & 0xff);
  9358. }
  9359. /* Finally just fetch it out of the MAC control regs. */
  9360. else {
  9361. hi = tr32(MAC_ADDR_0_HIGH);
  9362. lo = tr32(MAC_ADDR_0_LOW);
  9363. dev->dev_addr[5] = lo & 0xff;
  9364. dev->dev_addr[4] = (lo >> 8) & 0xff;
  9365. dev->dev_addr[3] = (lo >> 16) & 0xff;
  9366. dev->dev_addr[2] = (lo >> 24) & 0xff;
  9367. dev->dev_addr[1] = hi & 0xff;
  9368. dev->dev_addr[0] = (hi >> 8) & 0xff;
  9369. }
  9370. }
  9371. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  9372. #ifdef CONFIG_SPARC64
  9373. if (!tg3_get_default_macaddr_sparc(tp))
  9374. return 0;
  9375. #endif
  9376. return -EINVAL;
  9377. }
  9378. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  9379. return 0;
  9380. }
  9381. #define BOUNDARY_SINGLE_CACHELINE 1
  9382. #define BOUNDARY_MULTI_CACHELINE 2
  9383. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  9384. {
  9385. int cacheline_size;
  9386. u8 byte;
  9387. int goal;
  9388. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  9389. if (byte == 0)
  9390. cacheline_size = 1024;
  9391. else
  9392. cacheline_size = (int) byte * 4;
  9393. /* On 5703 and later chips, the boundary bits have no
  9394. * effect.
  9395. */
  9396. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9397. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  9398. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  9399. goto out;
  9400. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  9401. goal = BOUNDARY_MULTI_CACHELINE;
  9402. #else
  9403. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  9404. goal = BOUNDARY_SINGLE_CACHELINE;
  9405. #else
  9406. goal = 0;
  9407. #endif
  9408. #endif
  9409. if (!goal)
  9410. goto out;
  9411. /* PCI controllers on most RISC systems tend to disconnect
  9412. * when a device tries to burst across a cache-line boundary.
  9413. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  9414. *
  9415. * Unfortunately, for PCI-E there are only limited
  9416. * write-side controls for this, and thus for reads
  9417. * we will still get the disconnects. We'll also waste
  9418. * these PCI cycles for both read and write for chips
  9419. * other than 5700 and 5701 which do not implement the
  9420. * boundary bits.
  9421. */
  9422. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  9423. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  9424. switch (cacheline_size) {
  9425. case 16:
  9426. case 32:
  9427. case 64:
  9428. case 128:
  9429. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9430. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  9431. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  9432. } else {
  9433. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  9434. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  9435. }
  9436. break;
  9437. case 256:
  9438. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  9439. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  9440. break;
  9441. default:
  9442. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  9443. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  9444. break;
  9445. };
  9446. } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9447. switch (cacheline_size) {
  9448. case 16:
  9449. case 32:
  9450. case 64:
  9451. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9452. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  9453. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  9454. break;
  9455. }
  9456. /* fallthrough */
  9457. case 128:
  9458. default:
  9459. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  9460. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  9461. break;
  9462. };
  9463. } else {
  9464. switch (cacheline_size) {
  9465. case 16:
  9466. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9467. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  9468. DMA_RWCTRL_WRITE_BNDRY_16);
  9469. break;
  9470. }
  9471. /* fallthrough */
  9472. case 32:
  9473. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9474. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  9475. DMA_RWCTRL_WRITE_BNDRY_32);
  9476. break;
  9477. }
  9478. /* fallthrough */
  9479. case 64:
  9480. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9481. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  9482. DMA_RWCTRL_WRITE_BNDRY_64);
  9483. break;
  9484. }
  9485. /* fallthrough */
  9486. case 128:
  9487. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9488. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  9489. DMA_RWCTRL_WRITE_BNDRY_128);
  9490. break;
  9491. }
  9492. /* fallthrough */
  9493. case 256:
  9494. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  9495. DMA_RWCTRL_WRITE_BNDRY_256);
  9496. break;
  9497. case 512:
  9498. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  9499. DMA_RWCTRL_WRITE_BNDRY_512);
  9500. break;
  9501. case 1024:
  9502. default:
  9503. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  9504. DMA_RWCTRL_WRITE_BNDRY_1024);
  9505. break;
  9506. };
  9507. }
  9508. out:
  9509. return val;
  9510. }
  9511. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  9512. {
  9513. struct tg3_internal_buffer_desc test_desc;
  9514. u32 sram_dma_descs;
  9515. int i, ret;
  9516. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  9517. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  9518. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  9519. tw32(RDMAC_STATUS, 0);
  9520. tw32(WDMAC_STATUS, 0);
  9521. tw32(BUFMGR_MODE, 0);
  9522. tw32(FTQ_RESET, 0);
  9523. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  9524. test_desc.addr_lo = buf_dma & 0xffffffff;
  9525. test_desc.nic_mbuf = 0x00002100;
  9526. test_desc.len = size;
  9527. /*
  9528. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  9529. * the *second* time the tg3 driver was getting loaded after an
  9530. * initial scan.
  9531. *
  9532. * Broadcom tells me:
  9533. * ...the DMA engine is connected to the GRC block and a DMA
  9534. * reset may affect the GRC block in some unpredictable way...
  9535. * The behavior of resets to individual blocks has not been tested.
  9536. *
  9537. * Broadcom noted the GRC reset will also reset all sub-components.
  9538. */
  9539. if (to_device) {
  9540. test_desc.cqid_sqid = (13 << 8) | 2;
  9541. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  9542. udelay(40);
  9543. } else {
  9544. test_desc.cqid_sqid = (16 << 8) | 7;
  9545. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  9546. udelay(40);
  9547. }
  9548. test_desc.flags = 0x00000005;
  9549. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  9550. u32 val;
  9551. val = *(((u32 *)&test_desc) + i);
  9552. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  9553. sram_dma_descs + (i * sizeof(u32)));
  9554. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  9555. }
  9556. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  9557. if (to_device) {
  9558. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  9559. } else {
  9560. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  9561. }
  9562. ret = -ENODEV;
  9563. for (i = 0; i < 40; i++) {
  9564. u32 val;
  9565. if (to_device)
  9566. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  9567. else
  9568. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  9569. if ((val & 0xffff) == sram_dma_descs) {
  9570. ret = 0;
  9571. break;
  9572. }
  9573. udelay(100);
  9574. }
  9575. return ret;
  9576. }
  9577. #define TEST_BUFFER_SIZE 0x2000
  9578. static int __devinit tg3_test_dma(struct tg3 *tp)
  9579. {
  9580. dma_addr_t buf_dma;
  9581. u32 *buf, saved_dma_rwctrl;
  9582. int ret;
  9583. buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  9584. if (!buf) {
  9585. ret = -ENOMEM;
  9586. goto out_nofree;
  9587. }
  9588. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  9589. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  9590. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  9591. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9592. /* DMA read watermark not used on PCIE */
  9593. tp->dma_rwctrl |= 0x00180000;
  9594. } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  9595. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  9596. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  9597. tp->dma_rwctrl |= 0x003f0000;
  9598. else
  9599. tp->dma_rwctrl |= 0x003f000f;
  9600. } else {
  9601. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  9602. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  9603. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  9604. u32 read_water = 0x7;
  9605. /* If the 5704 is behind the EPB bridge, we can
  9606. * do the less restrictive ONE_DMA workaround for
  9607. * better performance.
  9608. */
  9609. if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
  9610. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  9611. tp->dma_rwctrl |= 0x8000;
  9612. else if (ccval == 0x6 || ccval == 0x7)
  9613. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  9614. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  9615. read_water = 4;
  9616. /* Set bit 23 to enable PCIX hw bug fix */
  9617. tp->dma_rwctrl |=
  9618. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  9619. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  9620. (1 << 23);
  9621. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  9622. /* 5780 always in PCIX mode */
  9623. tp->dma_rwctrl |= 0x00144000;
  9624. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  9625. /* 5714 always in PCIX mode */
  9626. tp->dma_rwctrl |= 0x00148000;
  9627. } else {
  9628. tp->dma_rwctrl |= 0x001b000f;
  9629. }
  9630. }
  9631. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  9632. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  9633. tp->dma_rwctrl &= 0xfffffff0;
  9634. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9635. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  9636. /* Remove this if it causes problems for some boards. */
  9637. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  9638. /* On 5700/5701 chips, we need to set this bit.
  9639. * Otherwise the chip will issue cacheline transactions
  9640. * to streamable DMA memory with not all the byte
  9641. * enables turned on. This is an error on several
  9642. * RISC PCI controllers, in particular sparc64.
  9643. *
  9644. * On 5703/5704 chips, this bit has been reassigned
  9645. * a different meaning. In particular, it is used
  9646. * on those chips to enable a PCI-X workaround.
  9647. */
  9648. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  9649. }
  9650. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9651. #if 0
  9652. /* Unneeded, already done by tg3_get_invariants. */
  9653. tg3_switch_clocks(tp);
  9654. #endif
  9655. ret = 0;
  9656. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9657. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  9658. goto out;
  9659. /* It is best to perform DMA test with maximum write burst size
  9660. * to expose the 5700/5701 write DMA bug.
  9661. */
  9662. saved_dma_rwctrl = tp->dma_rwctrl;
  9663. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9664. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9665. while (1) {
  9666. u32 *p = buf, i;
  9667. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  9668. p[i] = i;
  9669. /* Send the buffer to the chip. */
  9670. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  9671. if (ret) {
  9672. printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
  9673. break;
  9674. }
  9675. #if 0
  9676. /* validate data reached card RAM correctly. */
  9677. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  9678. u32 val;
  9679. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  9680. if (le32_to_cpu(val) != p[i]) {
  9681. printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
  9682. /* ret = -ENODEV here? */
  9683. }
  9684. p[i] = 0;
  9685. }
  9686. #endif
  9687. /* Now read it back. */
  9688. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  9689. if (ret) {
  9690. printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
  9691. break;
  9692. }
  9693. /* Verify it. */
  9694. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  9695. if (p[i] == i)
  9696. continue;
  9697. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  9698. DMA_RWCTRL_WRITE_BNDRY_16) {
  9699. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9700. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  9701. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9702. break;
  9703. } else {
  9704. printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
  9705. ret = -ENODEV;
  9706. goto out;
  9707. }
  9708. }
  9709. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  9710. /* Success. */
  9711. ret = 0;
  9712. break;
  9713. }
  9714. }
  9715. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  9716. DMA_RWCTRL_WRITE_BNDRY_16) {
  9717. static struct pci_device_id dma_wait_state_chipsets[] = {
  9718. { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
  9719. PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  9720. { },
  9721. };
  9722. /* DMA test passed without adjusting DMA boundary,
  9723. * now look for chipsets that are known to expose the
  9724. * DMA bug without failing the test.
  9725. */
  9726. if (pci_dev_present(dma_wait_state_chipsets)) {
  9727. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9728. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  9729. }
  9730. else
  9731. /* Safe to use the calculated DMA boundary. */
  9732. tp->dma_rwctrl = saved_dma_rwctrl;
  9733. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9734. }
  9735. out:
  9736. pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  9737. out_nofree:
  9738. return ret;
  9739. }
  9740. static void __devinit tg3_init_link_config(struct tg3 *tp)
  9741. {
  9742. tp->link_config.advertising =
  9743. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  9744. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  9745. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  9746. ADVERTISED_Autoneg | ADVERTISED_MII);
  9747. tp->link_config.speed = SPEED_INVALID;
  9748. tp->link_config.duplex = DUPLEX_INVALID;
  9749. tp->link_config.autoneg = AUTONEG_ENABLE;
  9750. tp->link_config.active_speed = SPEED_INVALID;
  9751. tp->link_config.active_duplex = DUPLEX_INVALID;
  9752. tp->link_config.phy_is_low_power = 0;
  9753. tp->link_config.orig_speed = SPEED_INVALID;
  9754. tp->link_config.orig_duplex = DUPLEX_INVALID;
  9755. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  9756. }
  9757. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  9758. {
  9759. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9760. tp->bufmgr_config.mbuf_read_dma_low_water =
  9761. DEFAULT_MB_RDMA_LOW_WATER_5705;
  9762. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9763. DEFAULT_MB_MACRX_LOW_WATER_5705;
  9764. tp->bufmgr_config.mbuf_high_water =
  9765. DEFAULT_MB_HIGH_WATER_5705;
  9766. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9767. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9768. DEFAULT_MB_MACRX_LOW_WATER_5906;
  9769. tp->bufmgr_config.mbuf_high_water =
  9770. DEFAULT_MB_HIGH_WATER_5906;
  9771. }
  9772. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  9773. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  9774. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  9775. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  9776. tp->bufmgr_config.mbuf_high_water_jumbo =
  9777. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  9778. } else {
  9779. tp->bufmgr_config.mbuf_read_dma_low_water =
  9780. DEFAULT_MB_RDMA_LOW_WATER;
  9781. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9782. DEFAULT_MB_MACRX_LOW_WATER;
  9783. tp->bufmgr_config.mbuf_high_water =
  9784. DEFAULT_MB_HIGH_WATER;
  9785. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  9786. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  9787. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  9788. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  9789. tp->bufmgr_config.mbuf_high_water_jumbo =
  9790. DEFAULT_MB_HIGH_WATER_JUMBO;
  9791. }
  9792. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  9793. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  9794. }
  9795. static char * __devinit tg3_phy_string(struct tg3 *tp)
  9796. {
  9797. switch (tp->phy_id & PHY_ID_MASK) {
  9798. case PHY_ID_BCM5400: return "5400";
  9799. case PHY_ID_BCM5401: return "5401";
  9800. case PHY_ID_BCM5411: return "5411";
  9801. case PHY_ID_BCM5701: return "5701";
  9802. case PHY_ID_BCM5703: return "5703";
  9803. case PHY_ID_BCM5704: return "5704";
  9804. case PHY_ID_BCM5705: return "5705";
  9805. case PHY_ID_BCM5750: return "5750";
  9806. case PHY_ID_BCM5752: return "5752";
  9807. case PHY_ID_BCM5714: return "5714";
  9808. case PHY_ID_BCM5780: return "5780";
  9809. case PHY_ID_BCM5755: return "5755";
  9810. case PHY_ID_BCM5787: return "5787";
  9811. case PHY_ID_BCM5756: return "5722/5756";
  9812. case PHY_ID_BCM5906: return "5906";
  9813. case PHY_ID_BCM8002: return "8002/serdes";
  9814. case 0: return "serdes";
  9815. default: return "unknown";
  9816. };
  9817. }
  9818. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  9819. {
  9820. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9821. strcpy(str, "PCI Express");
  9822. return str;
  9823. } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  9824. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  9825. strcpy(str, "PCIX:");
  9826. if ((clock_ctrl == 7) ||
  9827. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  9828. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  9829. strcat(str, "133MHz");
  9830. else if (clock_ctrl == 0)
  9831. strcat(str, "33MHz");
  9832. else if (clock_ctrl == 2)
  9833. strcat(str, "50MHz");
  9834. else if (clock_ctrl == 4)
  9835. strcat(str, "66MHz");
  9836. else if (clock_ctrl == 6)
  9837. strcat(str, "100MHz");
  9838. } else {
  9839. strcpy(str, "PCI:");
  9840. if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
  9841. strcat(str, "66MHz");
  9842. else
  9843. strcat(str, "33MHz");
  9844. }
  9845. if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
  9846. strcat(str, ":32-bit");
  9847. else
  9848. strcat(str, ":64-bit");
  9849. return str;
  9850. }
  9851. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  9852. {
  9853. struct pci_dev *peer;
  9854. unsigned int func, devnr = tp->pdev->devfn & ~7;
  9855. for (func = 0; func < 8; func++) {
  9856. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  9857. if (peer && peer != tp->pdev)
  9858. break;
  9859. pci_dev_put(peer);
  9860. }
  9861. /* 5704 can be configured in single-port mode, set peer to
  9862. * tp->pdev in that case.
  9863. */
  9864. if (!peer) {
  9865. peer = tp->pdev;
  9866. return peer;
  9867. }
  9868. /*
  9869. * We don't need to keep the refcount elevated; there's no way
  9870. * to remove one half of this device without removing the other
  9871. */
  9872. pci_dev_put(peer);
  9873. return peer;
  9874. }
  9875. static void __devinit tg3_init_coal(struct tg3 *tp)
  9876. {
  9877. struct ethtool_coalesce *ec = &tp->coal;
  9878. memset(ec, 0, sizeof(*ec));
  9879. ec->cmd = ETHTOOL_GCOALESCE;
  9880. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  9881. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  9882. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  9883. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  9884. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  9885. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  9886. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  9887. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  9888. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  9889. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  9890. HOSTCC_MODE_CLRTICK_TXBD)) {
  9891. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  9892. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  9893. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  9894. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  9895. }
  9896. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9897. ec->rx_coalesce_usecs_irq = 0;
  9898. ec->tx_coalesce_usecs_irq = 0;
  9899. ec->stats_block_coalesce_usecs = 0;
  9900. }
  9901. }
  9902. static int __devinit tg3_init_one(struct pci_dev *pdev,
  9903. const struct pci_device_id *ent)
  9904. {
  9905. static int tg3_version_printed = 0;
  9906. unsigned long tg3reg_base, tg3reg_len;
  9907. struct net_device *dev;
  9908. struct tg3 *tp;
  9909. int i, err, pm_cap;
  9910. char str[40];
  9911. u64 dma_mask, persist_dma_mask;
  9912. if (tg3_version_printed++ == 0)
  9913. printk(KERN_INFO "%s", version);
  9914. err = pci_enable_device(pdev);
  9915. if (err) {
  9916. printk(KERN_ERR PFX "Cannot enable PCI device, "
  9917. "aborting.\n");
  9918. return err;
  9919. }
  9920. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  9921. printk(KERN_ERR PFX "Cannot find proper PCI device "
  9922. "base address, aborting.\n");
  9923. err = -ENODEV;
  9924. goto err_out_disable_pdev;
  9925. }
  9926. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  9927. if (err) {
  9928. printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  9929. "aborting.\n");
  9930. goto err_out_disable_pdev;
  9931. }
  9932. pci_set_master(pdev);
  9933. /* Find power-management capability. */
  9934. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  9935. if (pm_cap == 0) {
  9936. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  9937. "aborting.\n");
  9938. err = -EIO;
  9939. goto err_out_free_res;
  9940. }
  9941. tg3reg_base = pci_resource_start(pdev, 0);
  9942. tg3reg_len = pci_resource_len(pdev, 0);
  9943. dev = alloc_etherdev(sizeof(*tp));
  9944. if (!dev) {
  9945. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  9946. err = -ENOMEM;
  9947. goto err_out_free_res;
  9948. }
  9949. SET_MODULE_OWNER(dev);
  9950. SET_NETDEV_DEV(dev, &pdev->dev);
  9951. #if TG3_VLAN_TAG_USED
  9952. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  9953. dev->vlan_rx_register = tg3_vlan_rx_register;
  9954. dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
  9955. #endif
  9956. tp = netdev_priv(dev);
  9957. tp->pdev = pdev;
  9958. tp->dev = dev;
  9959. tp->pm_cap = pm_cap;
  9960. tp->mac_mode = TG3_DEF_MAC_MODE;
  9961. tp->rx_mode = TG3_DEF_RX_MODE;
  9962. tp->tx_mode = TG3_DEF_TX_MODE;
  9963. tp->mi_mode = MAC_MI_MODE_BASE;
  9964. if (tg3_debug > 0)
  9965. tp->msg_enable = tg3_debug;
  9966. else
  9967. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  9968. /* The word/byte swap controls here control register access byte
  9969. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  9970. * setting below.
  9971. */
  9972. tp->misc_host_ctrl =
  9973. MISC_HOST_CTRL_MASK_PCI_INT |
  9974. MISC_HOST_CTRL_WORD_SWAP |
  9975. MISC_HOST_CTRL_INDIR_ACCESS |
  9976. MISC_HOST_CTRL_PCISTATE_RW;
  9977. /* The NONFRM (non-frame) byte/word swap controls take effect
  9978. * on descriptor entries, anything which isn't packet data.
  9979. *
  9980. * The StrongARM chips on the board (one for tx, one for rx)
  9981. * are running in big-endian mode.
  9982. */
  9983. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  9984. GRC_MODE_WSWAP_NONFRM_DATA);
  9985. #ifdef __BIG_ENDIAN
  9986. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  9987. #endif
  9988. spin_lock_init(&tp->lock);
  9989. spin_lock_init(&tp->indirect_lock);
  9990. INIT_WORK(&tp->reset_task, tg3_reset_task);
  9991. tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
  9992. if (tp->regs == 0UL) {
  9993. printk(KERN_ERR PFX "Cannot map device registers, "
  9994. "aborting.\n");
  9995. err = -ENOMEM;
  9996. goto err_out_free_dev;
  9997. }
  9998. tg3_init_link_config(tp);
  9999. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  10000. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  10001. tp->tx_pending = TG3_DEF_TX_RING_PENDING;
  10002. dev->open = tg3_open;
  10003. dev->stop = tg3_close;
  10004. dev->get_stats = tg3_get_stats;
  10005. dev->set_multicast_list = tg3_set_rx_mode;
  10006. dev->set_mac_address = tg3_set_mac_addr;
  10007. dev->do_ioctl = tg3_ioctl;
  10008. dev->tx_timeout = tg3_tx_timeout;
  10009. dev->poll = tg3_poll;
  10010. dev->ethtool_ops = &tg3_ethtool_ops;
  10011. dev->weight = 64;
  10012. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  10013. dev->change_mtu = tg3_change_mtu;
  10014. dev->irq = pdev->irq;
  10015. #ifdef CONFIG_NET_POLL_CONTROLLER
  10016. dev->poll_controller = tg3_poll_controller;
  10017. #endif
  10018. err = tg3_get_invariants(tp);
  10019. if (err) {
  10020. printk(KERN_ERR PFX "Problem fetching invariants of chip, "
  10021. "aborting.\n");
  10022. goto err_out_iounmap;
  10023. }
  10024. /* The EPB bridge inside 5714, 5715, and 5780 and any
  10025. * device behind the EPB cannot support DMA addresses > 40-bit.
  10026. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  10027. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  10028. * do DMA address check in tg3_start_xmit().
  10029. */
  10030. if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  10031. persist_dma_mask = dma_mask = DMA_32BIT_MASK;
  10032. else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
  10033. persist_dma_mask = dma_mask = DMA_40BIT_MASK;
  10034. #ifdef CONFIG_HIGHMEM
  10035. dma_mask = DMA_64BIT_MASK;
  10036. #endif
  10037. } else
  10038. persist_dma_mask = dma_mask = DMA_64BIT_MASK;
  10039. /* Configure DMA attributes. */
  10040. if (dma_mask > DMA_32BIT_MASK) {
  10041. err = pci_set_dma_mask(pdev, dma_mask);
  10042. if (!err) {
  10043. dev->features |= NETIF_F_HIGHDMA;
  10044. err = pci_set_consistent_dma_mask(pdev,
  10045. persist_dma_mask);
  10046. if (err < 0) {
  10047. printk(KERN_ERR PFX "Unable to obtain 64 bit "
  10048. "DMA for consistent allocations\n");
  10049. goto err_out_iounmap;
  10050. }
  10051. }
  10052. }
  10053. if (err || dma_mask == DMA_32BIT_MASK) {
  10054. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  10055. if (err) {
  10056. printk(KERN_ERR PFX "No usable DMA configuration, "
  10057. "aborting.\n");
  10058. goto err_out_iounmap;
  10059. }
  10060. }
  10061. tg3_init_bufmgr_config(tp);
  10062. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10063. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  10064. }
  10065. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10066. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  10067. tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
  10068. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  10069. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  10070. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  10071. } else {
  10072. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
  10073. }
  10074. /* TSO is on by default on chips that support hardware TSO.
  10075. * Firmware TSO on older chips gives lower performance, so it
  10076. * is off by default, but can be enabled using ethtool.
  10077. */
  10078. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10079. dev->features |= NETIF_F_TSO;
  10080. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  10081. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
  10082. dev->features |= NETIF_F_TSO6;
  10083. }
  10084. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  10085. !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  10086. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  10087. tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  10088. tp->rx_pending = 63;
  10089. }
  10090. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  10091. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
  10092. tp->pdev_peer = tg3_find_peer(tp);
  10093. err = tg3_get_device_address(tp);
  10094. if (err) {
  10095. printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  10096. "aborting.\n");
  10097. goto err_out_iounmap;
  10098. }
  10099. /*
  10100. * Reset chip in case UNDI or EFI driver did not shutdown
  10101. * DMA self test will enable WDMAC and we'll see (spurious)
  10102. * pending DMA on the PCI bus at that point.
  10103. */
  10104. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  10105. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  10106. pci_save_state(tp->pdev);
  10107. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  10108. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10109. }
  10110. err = tg3_test_dma(tp);
  10111. if (err) {
  10112. printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
  10113. goto err_out_iounmap;
  10114. }
  10115. /* Tigon3 can do ipv4 only... and some chips have buggy
  10116. * checksumming.
  10117. */
  10118. if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
  10119. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10120. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  10121. dev->features |= NETIF_F_HW_CSUM;
  10122. else
  10123. dev->features |= NETIF_F_IP_CSUM;
  10124. dev->features |= NETIF_F_SG;
  10125. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  10126. } else
  10127. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  10128. /* flow control autonegotiation is default behavior */
  10129. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  10130. tg3_init_coal(tp);
  10131. /* Now that we have fully setup the chip, save away a snapshot
  10132. * of the PCI config space. We need to restore this after
  10133. * GRC_MISC_CFG core clock resets and some resume events.
  10134. */
  10135. pci_save_state(tp->pdev);
  10136. pci_set_drvdata(pdev, dev);
  10137. err = register_netdev(dev);
  10138. if (err) {
  10139. printk(KERN_ERR PFX "Cannot register net device, "
  10140. "aborting.\n");
  10141. goto err_out_iounmap;
  10142. }
  10143. printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
  10144. dev->name,
  10145. tp->board_part_number,
  10146. tp->pci_chip_rev_id,
  10147. tg3_phy_string(tp),
  10148. tg3_bus_string(tp, str),
  10149. ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
  10150. ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
  10151. "10/100/1000Base-T")));
  10152. for (i = 0; i < 6; i++)
  10153. printk("%2.2x%c", dev->dev_addr[i],
  10154. i == 5 ? '\n' : ':');
  10155. printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
  10156. "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
  10157. dev->name,
  10158. (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
  10159. (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
  10160. (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
  10161. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
  10162. (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
  10163. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
  10164. printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  10165. dev->name, tp->dma_rwctrl,
  10166. (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
  10167. (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
  10168. return 0;
  10169. err_out_iounmap:
  10170. if (tp->regs) {
  10171. iounmap(tp->regs);
  10172. tp->regs = NULL;
  10173. }
  10174. err_out_free_dev:
  10175. free_netdev(dev);
  10176. err_out_free_res:
  10177. pci_release_regions(pdev);
  10178. err_out_disable_pdev:
  10179. pci_disable_device(pdev);
  10180. pci_set_drvdata(pdev, NULL);
  10181. return err;
  10182. }
  10183. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  10184. {
  10185. struct net_device *dev = pci_get_drvdata(pdev);
  10186. if (dev) {
  10187. struct tg3 *tp = netdev_priv(dev);
  10188. flush_scheduled_work();
  10189. unregister_netdev(dev);
  10190. if (tp->regs) {
  10191. iounmap(tp->regs);
  10192. tp->regs = NULL;
  10193. }
  10194. free_netdev(dev);
  10195. pci_release_regions(pdev);
  10196. pci_disable_device(pdev);
  10197. pci_set_drvdata(pdev, NULL);
  10198. }
  10199. }
  10200. static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
  10201. {
  10202. struct net_device *dev = pci_get_drvdata(pdev);
  10203. struct tg3 *tp = netdev_priv(dev);
  10204. int err;
  10205. if (!netif_running(dev))
  10206. return 0;
  10207. flush_scheduled_work();
  10208. tg3_netif_stop(tp);
  10209. del_timer_sync(&tp->timer);
  10210. tg3_full_lock(tp, 1);
  10211. tg3_disable_ints(tp);
  10212. tg3_full_unlock(tp);
  10213. netif_device_detach(dev);
  10214. tg3_full_lock(tp, 0);
  10215. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10216. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  10217. tg3_full_unlock(tp);
  10218. /* Save MSI address and data for resume. */
  10219. pci_save_state(pdev);
  10220. err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
  10221. if (err) {
  10222. tg3_full_lock(tp, 0);
  10223. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  10224. if (tg3_restart_hw(tp, 1))
  10225. goto out;
  10226. tp->timer.expires = jiffies + tp->timer_offset;
  10227. add_timer(&tp->timer);
  10228. netif_device_attach(dev);
  10229. tg3_netif_start(tp);
  10230. out:
  10231. tg3_full_unlock(tp);
  10232. }
  10233. return err;
  10234. }
  10235. static int tg3_resume(struct pci_dev *pdev)
  10236. {
  10237. struct net_device *dev = pci_get_drvdata(pdev);
  10238. struct tg3 *tp = netdev_priv(dev);
  10239. int err;
  10240. if (!netif_running(dev))
  10241. return 0;
  10242. pci_restore_state(tp->pdev);
  10243. err = tg3_set_power_state(tp, PCI_D0);
  10244. if (err)
  10245. return err;
  10246. netif_device_attach(dev);
  10247. tg3_full_lock(tp, 0);
  10248. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  10249. err = tg3_restart_hw(tp, 1);
  10250. if (err)
  10251. goto out;
  10252. tp->timer.expires = jiffies + tp->timer_offset;
  10253. add_timer(&tp->timer);
  10254. tg3_netif_start(tp);
  10255. out:
  10256. tg3_full_unlock(tp);
  10257. return err;
  10258. }
  10259. static struct pci_driver tg3_driver = {
  10260. .name = DRV_MODULE_NAME,
  10261. .id_table = tg3_pci_tbl,
  10262. .probe = tg3_init_one,
  10263. .remove = __devexit_p(tg3_remove_one),
  10264. .suspend = tg3_suspend,
  10265. .resume = tg3_resume
  10266. };
  10267. static int __init tg3_init(void)
  10268. {
  10269. return pci_register_driver(&tg3_driver);
  10270. }
  10271. static void __exit tg3_cleanup(void)
  10272. {
  10273. pci_unregister_driver(&tg3_driver);
  10274. }
  10275. module_init(tg3_init);
  10276. module_exit(tg3_cleanup);