tc35815.c 53 KB

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  1. /* tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
  2. *
  3. * Copyright 2001 MontaVista Software Inc.
  4. * Author: MontaVista Software, Inc.
  5. * ahennessy@mvista.com
  6. *
  7. * Based on skelton.c by Donald Becker.
  8. * Copyright (C) 2000-2001 Toshiba Corporation
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  21. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. *
  26. * You should have received a copy of the GNU General Public License along
  27. * with this program; if not, write to the Free Software Foundation, Inc.,
  28. * 675 Mass Ave, Cambridge, MA 02139, USA.
  29. */
  30. static const char *version =
  31. "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/types.h>
  35. #include <linux/fcntl.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/ioport.h>
  38. #include <linux/in.h>
  39. #include <linux/slab.h>
  40. #include <linux/string.h>
  41. #include <linux/errno.h>
  42. #include <linux/init.h>
  43. #include <linux/netdevice.h>
  44. #include <linux/etherdevice.h>
  45. #include <linux/skbuff.h>
  46. #include <linux/delay.h>
  47. #include <linux/pci.h>
  48. #include <linux/proc_fs.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/bitops.h>
  51. #include <asm/system.h>
  52. #include <asm/io.h>
  53. #include <asm/dma.h>
  54. #include <asm/byteorder.h>
  55. /*
  56. * The name of the card. Is used for messages and in the requests for
  57. * io regions, irqs and dma channels
  58. */
  59. static const char* cardname = "TC35815CF";
  60. #define TC35815_PROC_ENTRY "net/tc35815"
  61. #define TC35815_MODULE_NAME "TC35815CF"
  62. #define TX_TIMEOUT (4*HZ)
  63. /* First, a few definitions that the brave might change. */
  64. /* use 0 for production, 1 for verification, >2 for debug */
  65. #ifndef TC35815_DEBUG
  66. #define TC35815_DEBUG 1
  67. #endif
  68. static unsigned int tc35815_debug = TC35815_DEBUG;
  69. #define GATHER_TXINT /* On-Demand Tx Interrupt */
  70. #define vtonocache(p) KSEG1ADDR(virt_to_phys(p))
  71. /*
  72. * Registers
  73. */
  74. struct tc35815_regs {
  75. volatile __u32 DMA_Ctl; /* 0x00 */
  76. volatile __u32 TxFrmPtr;
  77. volatile __u32 TxThrsh;
  78. volatile __u32 TxPollCtr;
  79. volatile __u32 BLFrmPtr;
  80. volatile __u32 RxFragSize;
  81. volatile __u32 Int_En;
  82. volatile __u32 FDA_Bas;
  83. volatile __u32 FDA_Lim; /* 0x20 */
  84. volatile __u32 Int_Src;
  85. volatile __u32 unused0[2];
  86. volatile __u32 PauseCnt;
  87. volatile __u32 RemPauCnt;
  88. volatile __u32 TxCtlFrmStat;
  89. volatile __u32 unused1;
  90. volatile __u32 MAC_Ctl; /* 0x40 */
  91. volatile __u32 CAM_Ctl;
  92. volatile __u32 Tx_Ctl;
  93. volatile __u32 Tx_Stat;
  94. volatile __u32 Rx_Ctl;
  95. volatile __u32 Rx_Stat;
  96. volatile __u32 MD_Data;
  97. volatile __u32 MD_CA;
  98. volatile __u32 CAM_Adr; /* 0x60 */
  99. volatile __u32 CAM_Data;
  100. volatile __u32 CAM_Ena;
  101. volatile __u32 PROM_Ctl;
  102. volatile __u32 PROM_Data;
  103. volatile __u32 Algn_Cnt;
  104. volatile __u32 CRC_Cnt;
  105. volatile __u32 Miss_Cnt;
  106. };
  107. /*
  108. * Bit assignments
  109. */
  110. /* DMA_Ctl bit asign ------------------------------------------------------- */
  111. #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
  112. #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
  113. #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
  114. #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
  115. #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
  116. #define DMA_TestMode 0x00002000 /* 1:Test Mode */
  117. #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
  118. #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
  119. /* RxFragSize bit asign ---------------------------------------------------- */
  120. #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
  121. #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
  122. /* MAC_Ctl bit asign ------------------------------------------------------- */
  123. #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
  124. #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
  125. #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
  126. #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
  127. #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
  128. #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
  129. #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
  130. #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
  131. #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
  132. #define MAC_Reset 0x00000004 /* 1:Software Reset */
  133. #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
  134. #define MAC_HaltReq 0x00000001 /* 1:Halt request */
  135. /* PROM_Ctl bit asign ------------------------------------------------------ */
  136. #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
  137. #define PROM_Read 0x00004000 /*10:Read operation */
  138. #define PROM_Write 0x00002000 /*01:Write operation */
  139. #define PROM_Erase 0x00006000 /*11:Erase operation */
  140. /*00:Enable or Disable Writting, */
  141. /* as specified in PROM_Addr. */
  142. #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
  143. /*00xxxx: disable */
  144. /* CAM_Ctl bit asign ------------------------------------------------------- */
  145. #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
  146. #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
  147. /* accept other */
  148. #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
  149. #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
  150. #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
  151. /* CAM_Ena bit asign ------------------------------------------------------- */
  152. #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
  153. #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
  154. #define CAM_Ena_Bit(index) (1<<(index))
  155. #define CAM_ENTRY_DESTINATION 0
  156. #define CAM_ENTRY_SOURCE 1
  157. #define CAM_ENTRY_MACCTL 20
  158. /* Tx_Ctl bit asign -------------------------------------------------------- */
  159. #define Tx_En 0x00000001 /* 1:Transmit enable */
  160. #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
  161. #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
  162. #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
  163. #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
  164. #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
  165. #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
  166. #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
  167. #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
  168. #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
  169. #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
  170. #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
  171. /* Tx_Stat bit asign ------------------------------------------------------- */
  172. #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
  173. #define Tx_ExColl 0x00000010 /* Excessive Collision */
  174. #define Tx_TXDefer 0x00000020 /* Transmit Defered */
  175. #define Tx_Paused 0x00000040 /* Transmit Paused */
  176. #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
  177. #define Tx_Under 0x00000100 /* Underrun */
  178. #define Tx_Defer 0x00000200 /* Deferral */
  179. #define Tx_NCarr 0x00000400 /* No Carrier */
  180. #define Tx_10Stat 0x00000800 /* 10Mbps Status */
  181. #define Tx_LateColl 0x00001000 /* Late Collision */
  182. #define Tx_TxPar 0x00002000 /* Tx Parity Error */
  183. #define Tx_Comp 0x00004000 /* Completion */
  184. #define Tx_Halted 0x00008000 /* Tx Halted */
  185. #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
  186. /* Rx_Ctl bit asign -------------------------------------------------------- */
  187. #define Rx_EnGood 0x00004000 /* 1:Enable Good */
  188. #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
  189. #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
  190. #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
  191. #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
  192. #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
  193. #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
  194. #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
  195. #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
  196. #define Rx_LongEn 0x00000004 /* 1:Long Enable */
  197. #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
  198. #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
  199. /* Rx_Stat bit asign ------------------------------------------------------- */
  200. #define Rx_Halted 0x00008000 /* Rx Halted */
  201. #define Rx_Good 0x00004000 /* Rx Good */
  202. #define Rx_RxPar 0x00002000 /* Rx Parity Error */
  203. /* 0x00001000 not use */
  204. #define Rx_LongErr 0x00000800 /* Rx Long Error */
  205. #define Rx_Over 0x00000400 /* Rx Overflow */
  206. #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
  207. #define Rx_Align 0x00000100 /* Rx Alignment Error */
  208. #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
  209. #define Rx_IntRx 0x00000040 /* Rx Interrupt */
  210. #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
  211. #define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
  212. /* Int_En bit asign -------------------------------------------------------- */
  213. #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
  214. #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Control Complete Enable */
  215. #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
  216. #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
  217. #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
  218. #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
  219. #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
  220. #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
  221. #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
  222. #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
  223. #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
  224. #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
  225. /* Exhausted Enable */
  226. /* Int_Src bit asign ------------------------------------------------------- */
  227. #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
  228. #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
  229. #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
  230. #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
  231. #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
  232. #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
  233. #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
  234. #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
  235. #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
  236. #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
  237. #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
  238. #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
  239. #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
  240. #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
  241. #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
  242. /* MD_CA bit asign --------------------------------------------------------- */
  243. #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
  244. #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
  245. #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
  246. /* MII register offsets */
  247. #define MII_CONTROL 0x0000
  248. #define MII_STATUS 0x0001
  249. #define MII_PHY_ID0 0x0002
  250. #define MII_PHY_ID1 0x0003
  251. #define MII_ANAR 0x0004
  252. #define MII_ANLPAR 0x0005
  253. #define MII_ANER 0x0006
  254. /* MII Control register bit definitions. */
  255. #define MIICNTL_FDX 0x0100
  256. #define MIICNTL_RST_AUTO 0x0200
  257. #define MIICNTL_ISOLATE 0x0400
  258. #define MIICNTL_PWRDWN 0x0800
  259. #define MIICNTL_AUTO 0x1000
  260. #define MIICNTL_SPEED 0x2000
  261. #define MIICNTL_LPBK 0x4000
  262. #define MIICNTL_RESET 0x8000
  263. /* MII Status register bit significance. */
  264. #define MIISTAT_EXT 0x0001
  265. #define MIISTAT_JAB 0x0002
  266. #define MIISTAT_LINK 0x0004
  267. #define MIISTAT_CAN_AUTO 0x0008
  268. #define MIISTAT_FAULT 0x0010
  269. #define MIISTAT_AUTO_DONE 0x0020
  270. #define MIISTAT_CAN_T 0x0800
  271. #define MIISTAT_CAN_T_FDX 0x1000
  272. #define MIISTAT_CAN_TX 0x2000
  273. #define MIISTAT_CAN_TX_FDX 0x4000
  274. #define MIISTAT_CAN_T4 0x8000
  275. /* MII Auto-Negotiation Expansion/RemoteEnd Register Bits */
  276. #define MII_AN_TX_FDX 0x0100
  277. #define MII_AN_TX_HDX 0x0080
  278. #define MII_AN_10_FDX 0x0040
  279. #define MII_AN_10_HDX 0x0020
  280. /*
  281. * Descriptors
  282. */
  283. /* Frame descripter */
  284. struct FDesc {
  285. volatile __u32 FDNext;
  286. volatile __u32 FDSystem;
  287. volatile __u32 FDStat;
  288. volatile __u32 FDCtl;
  289. };
  290. /* Buffer descripter */
  291. struct BDesc {
  292. volatile __u32 BuffData;
  293. volatile __u32 BDCtl;
  294. };
  295. #define FD_ALIGN 16
  296. /* Frame Descripter bit asign ---------------------------------------------- */
  297. #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
  298. #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
  299. #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
  300. #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
  301. #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
  302. #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
  303. #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
  304. #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
  305. #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
  306. #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
  307. #define FD_BDCnt_SHIFT 16
  308. /* Buffer Descripter bit asign --------------------------------------------- */
  309. #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
  310. #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
  311. #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
  312. #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
  313. #define BD_RxBDID_SHIFT 16
  314. #define BD_RxBDSeqN_SHIFT 24
  315. /* Some useful constants. */
  316. #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
  317. #ifdef NO_CHECK_CARRIER
  318. #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
  319. Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
  320. Tx_En) /* maybe 0x7d01 */
  321. #else
  322. #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
  323. Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
  324. Tx_En) /* maybe 0x7f01 */
  325. #endif
  326. #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
  327. | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
  328. #define INT_EN_CMD (Int_NRAbtEn | \
  329. Int_DParDEn | Int_DParErrEn | \
  330. Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
  331. Int_STargAbtEn | \
  332. Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
  333. /* Tuning parameters */
  334. #define DMA_BURST_SIZE 32
  335. #define TX_THRESHOLD 1024
  336. #define FD_PAGE_NUM 2
  337. #define FD_PAGE_ORDER 1
  338. /* 16 + RX_BUF_PAGES * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*2 */
  339. #define RX_BUF_PAGES 8 /* >= 2 */
  340. #define RX_FD_NUM 250 /* >= 32 */
  341. #define TX_FD_NUM 128
  342. struct TxFD {
  343. struct FDesc fd;
  344. struct BDesc bd;
  345. struct BDesc unused;
  346. };
  347. struct RxFD {
  348. struct FDesc fd;
  349. struct BDesc bd[0]; /* variable length */
  350. };
  351. struct FrFD {
  352. struct FDesc fd;
  353. struct BDesc bd[RX_BUF_PAGES];
  354. };
  355. extern unsigned long tc_readl(volatile __u32 *addr);
  356. extern void tc_writel(unsigned long data, volatile __u32 *addr);
  357. dma_addr_t priv_dma_handle;
  358. /* Information that need to be kept for each board. */
  359. struct tc35815_local {
  360. struct net_device *next_module;
  361. /* statistics */
  362. struct net_device_stats stats;
  363. struct {
  364. int max_tx_qlen;
  365. int tx_ints;
  366. int rx_ints;
  367. } lstats;
  368. int tbusy;
  369. int option;
  370. #define TC35815_OPT_AUTO 0x00
  371. #define TC35815_OPT_10M 0x01
  372. #define TC35815_OPT_100M 0x02
  373. #define TC35815_OPT_FULLDUP 0x04
  374. int linkspeed; /* 10 or 100 */
  375. int fullduplex;
  376. /*
  377. * Transmitting: Batch Mode.
  378. * 1 BD in 1 TxFD.
  379. * Receiving: Packing Mode.
  380. * 1 circular FD for Free Buffer List.
  381. * RX_BUG_PAGES BD in Free Buffer FD.
  382. * One Free Buffer BD has PAGE_SIZE data buffer.
  383. */
  384. struct pci_dev *pdev;
  385. dma_addr_t fd_buf_dma_handle;
  386. void * fd_buf; /* for TxFD, TxFD, FrFD */
  387. struct TxFD *tfd_base;
  388. int tfd_start;
  389. int tfd_end;
  390. struct RxFD *rfd_base;
  391. struct RxFD *rfd_limit;
  392. struct RxFD *rfd_cur;
  393. struct FrFD *fbl_ptr;
  394. unsigned char fbl_curid;
  395. dma_addr_t data_buf_dma_handle[RX_BUF_PAGES];
  396. void * data_buf[RX_BUF_PAGES]; /* packing */
  397. spinlock_t lock;
  398. };
  399. /* Index to functions, as function prototypes. */
  400. static int __devinit tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq);
  401. static int tc35815_open(struct net_device *dev);
  402. static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
  403. static void tc35815_tx_timeout(struct net_device *dev);
  404. static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
  405. static void tc35815_rx(struct net_device *dev);
  406. static void tc35815_txdone(struct net_device *dev);
  407. static int tc35815_close(struct net_device *dev);
  408. static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
  409. static void tc35815_set_multicast_list(struct net_device *dev);
  410. static void tc35815_chip_reset(struct net_device *dev);
  411. static void tc35815_chip_init(struct net_device *dev);
  412. static void tc35815_phy_chip_init(struct net_device *dev);
  413. /* A list of all installed tc35815 devices. */
  414. static struct net_device *root_tc35815_dev = NULL;
  415. /*
  416. * PCI device identifiers for "new style" Linux PCI Device Drivers
  417. */
  418. static struct pci_device_id tc35815_pci_tbl[] = {
  419. { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  420. { 0, }
  421. };
  422. MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl);
  423. int
  424. tc35815_probe(struct pci_dev *pdev,
  425. const struct pci_device_id *ent)
  426. {
  427. int err = 0;
  428. int ret;
  429. unsigned long pci_memaddr;
  430. unsigned int pci_irq_line;
  431. printk(KERN_INFO "tc35815_probe: found device %#08x.%#08x\n", ent->vendor, ent->device);
  432. err = pci_enable_device(pdev);
  433. if (err)
  434. return err;
  435. pci_memaddr = pci_resource_start (pdev, 1);
  436. printk(KERN_INFO " pci_memaddr=%#08lx resource_flags=%#08lx\n", pci_memaddr, pci_resource_flags (pdev, 0));
  437. if (!pci_memaddr) {
  438. printk(KERN_WARNING "no PCI MEM resources, aborting\n");
  439. ret = -ENODEV;
  440. goto err_out;
  441. }
  442. pci_irq_line = pdev->irq;
  443. /* irq disabled. */
  444. if (pci_irq_line == 0) {
  445. printk(KERN_WARNING "no PCI irq, aborting\n");
  446. ret = -ENODEV;
  447. goto err_out;
  448. }
  449. ret = tc35815_probe1(pdev, pci_memaddr, pci_irq_line);
  450. if (ret)
  451. goto err_out;
  452. pci_set_master(pdev);
  453. return 0;
  454. err_out:
  455. pci_disable_device(pdev);
  456. return ret;
  457. }
  458. static int __devinit tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq)
  459. {
  460. static unsigned version_printed = 0;
  461. int i, ret;
  462. struct tc35815_local *lp;
  463. struct tc35815_regs *tr;
  464. struct net_device *dev;
  465. /* Allocate a new 'dev' if needed. */
  466. dev = alloc_etherdev(sizeof(struct tc35815_local));
  467. if (dev == NULL)
  468. return -ENOMEM;
  469. /*
  470. * alloc_etherdev allocs and zeros dev->priv
  471. */
  472. lp = dev->priv;
  473. if (tc35815_debug && version_printed++ == 0)
  474. printk(KERN_DEBUG "%s", version);
  475. /* Fill in the 'dev' fields. */
  476. dev->irq = irq;
  477. dev->base_addr = (unsigned long)ioremap(base_addr,
  478. sizeof(struct tc35815_regs));
  479. if (!dev->base_addr) {
  480. ret = -ENOMEM;
  481. goto err_out;
  482. }
  483. tr = (struct tc35815_regs*)dev->base_addr;
  484. tc35815_chip_reset(dev);
  485. /* Retrieve and print the ethernet address. */
  486. while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
  487. ;
  488. for (i = 0; i < 6; i += 2) {
  489. unsigned short data;
  490. tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
  491. while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
  492. ;
  493. data = tc_readl(&tr->PROM_Data);
  494. dev->dev_addr[i] = data & 0xff;
  495. dev->dev_addr[i+1] = data >> 8;
  496. }
  497. /* Initialize the device structure. */
  498. lp->pdev = pdev;
  499. lp->next_module = root_tc35815_dev;
  500. root_tc35815_dev = dev;
  501. spin_lock_init(&lp->lock);
  502. if (dev->mem_start > 0) {
  503. lp->option = dev->mem_start;
  504. if ((lp->option & TC35815_OPT_10M) &&
  505. (lp->option & TC35815_OPT_100M)) {
  506. /* if both speed speficied, auto select. */
  507. lp->option &= ~(TC35815_OPT_10M | TC35815_OPT_100M);
  508. }
  509. }
  510. //XXX fixme
  511. lp->option |= TC35815_OPT_10M;
  512. /* do auto negotiation */
  513. tc35815_phy_chip_init(dev);
  514. dev->open = tc35815_open;
  515. dev->stop = tc35815_close;
  516. dev->tx_timeout = tc35815_tx_timeout;
  517. dev->watchdog_timeo = TX_TIMEOUT;
  518. dev->hard_start_xmit = tc35815_send_packet;
  519. dev->get_stats = tc35815_get_stats;
  520. dev->set_multicast_list = tc35815_set_multicast_list;
  521. SET_MODULE_OWNER(dev);
  522. SET_NETDEV_DEV(dev, &pdev->dev);
  523. ret = register_netdev(dev);
  524. if (ret)
  525. goto err_out_iounmap;
  526. printk(KERN_INFO "%s: %s found at %#x, irq %d, MAC",
  527. dev->name, cardname, base_addr, irq);
  528. for (i = 0; i < 6; i++)
  529. printk(" %2.2x", dev->dev_addr[i]);
  530. printk("\n");
  531. printk(KERN_INFO "%s: linkspeed %dMbps, %s Duplex\n",
  532. dev->name, lp->linkspeed, lp->fullduplex ? "Full" : "Half");
  533. return 0;
  534. err_out_iounmap:
  535. iounmap((void *) dev->base_addr);
  536. err_out:
  537. free_netdev(dev);
  538. return ret;
  539. }
  540. static int
  541. tc35815_init_queues(struct net_device *dev)
  542. {
  543. struct tc35815_local *lp = dev->priv;
  544. int i;
  545. unsigned long fd_addr;
  546. if (!lp->fd_buf) {
  547. if (sizeof(struct FDesc) +
  548. sizeof(struct BDesc) * RX_BUF_PAGES +
  549. sizeof(struct FDesc) * RX_FD_NUM +
  550. sizeof(struct TxFD) * TX_FD_NUM > PAGE_SIZE * FD_PAGE_NUM) {
  551. printk(KERN_WARNING "%s: Invalid Queue Size.\n", dev->name);
  552. return -ENOMEM;
  553. }
  554. if ((lp->fd_buf = (void *)__get_free_pages(GFP_KERNEL, FD_PAGE_ORDER)) == 0)
  555. return -ENOMEM;
  556. for (i = 0; i < RX_BUF_PAGES; i++) {
  557. if ((lp->data_buf[i] = (void *)get_zeroed_page(GFP_KERNEL)) == 0) {
  558. while (--i >= 0) {
  559. free_page((unsigned long)lp->data_buf[i]);
  560. lp->data_buf[i] = 0;
  561. }
  562. free_page((unsigned long)lp->fd_buf);
  563. lp->fd_buf = 0;
  564. return -ENOMEM;
  565. }
  566. #ifdef __mips__
  567. dma_cache_wback_inv((unsigned long)lp->data_buf[i], PAGE_SIZE * FD_PAGE_NUM);
  568. #endif
  569. }
  570. #ifdef __mips__
  571. dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
  572. #endif
  573. } else {
  574. memset(lp->fd_buf, 0, PAGE_SIZE * FD_PAGE_NUM);
  575. #ifdef __mips__
  576. dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
  577. #endif
  578. }
  579. #ifdef __mips__
  580. fd_addr = (unsigned long)vtonocache(lp->fd_buf);
  581. #else
  582. fd_addr = (unsigned long)lp->fd_buf;
  583. #endif
  584. /* Free Descriptors (for Receive) */
  585. lp->rfd_base = (struct RxFD *)fd_addr;
  586. fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
  587. for (i = 0; i < RX_FD_NUM; i++) {
  588. lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
  589. }
  590. lp->rfd_cur = lp->rfd_base;
  591. lp->rfd_limit = (struct RxFD *)(fd_addr -
  592. sizeof(struct FDesc) -
  593. sizeof(struct BDesc) * 30);
  594. /* Transmit Descriptors */
  595. lp->tfd_base = (struct TxFD *)fd_addr;
  596. fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
  597. for (i = 0; i < TX_FD_NUM; i++) {
  598. lp->tfd_base[i].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[i+1]));
  599. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
  600. lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
  601. }
  602. lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[0]));
  603. lp->tfd_start = 0;
  604. lp->tfd_end = 0;
  605. /* Buffer List (for Receive) */
  606. lp->fbl_ptr = (struct FrFD *)fd_addr;
  607. lp->fbl_ptr->fd.FDNext = cpu_to_le32(virt_to_bus(lp->fbl_ptr));
  608. lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_PAGES | FD_CownsFD);
  609. for (i = 0; i < RX_BUF_PAGES; i++) {
  610. lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(virt_to_bus(lp->data_buf[i]));
  611. /* BDID is index of FrFD.bd[] */
  612. lp->fbl_ptr->bd[i].BDCtl =
  613. cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | PAGE_SIZE);
  614. }
  615. lp->fbl_curid = 0;
  616. return 0;
  617. }
  618. static void
  619. tc35815_clear_queues(struct net_device *dev)
  620. {
  621. struct tc35815_local *lp = dev->priv;
  622. int i;
  623. for (i = 0; i < TX_FD_NUM; i++) {
  624. struct sk_buff *skb = (struct sk_buff *)
  625. le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
  626. if (skb)
  627. dev_kfree_skb_any(skb);
  628. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
  629. }
  630. tc35815_init_queues(dev);
  631. }
  632. static void
  633. tc35815_free_queues(struct net_device *dev)
  634. {
  635. struct tc35815_local *lp = dev->priv;
  636. int i;
  637. if (lp->tfd_base) {
  638. for (i = 0; i < TX_FD_NUM; i++) {
  639. struct sk_buff *skb = (struct sk_buff *)
  640. le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
  641. if (skb)
  642. dev_kfree_skb_any(skb);
  643. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
  644. }
  645. }
  646. lp->rfd_base = NULL;
  647. lp->rfd_base = NULL;
  648. lp->rfd_limit = NULL;
  649. lp->rfd_cur = NULL;
  650. lp->fbl_ptr = NULL;
  651. for (i = 0; i < RX_BUF_PAGES; i++) {
  652. if (lp->data_buf[i])
  653. free_page((unsigned long)lp->data_buf[i]);
  654. lp->data_buf[i] = 0;
  655. }
  656. if (lp->fd_buf)
  657. __free_pages(lp->fd_buf, FD_PAGE_ORDER);
  658. lp->fd_buf = NULL;
  659. }
  660. static void
  661. dump_txfd(struct TxFD *fd)
  662. {
  663. printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
  664. le32_to_cpu(fd->fd.FDNext),
  665. le32_to_cpu(fd->fd.FDSystem),
  666. le32_to_cpu(fd->fd.FDStat),
  667. le32_to_cpu(fd->fd.FDCtl));
  668. printk("BD: ");
  669. printk(" %08x %08x",
  670. le32_to_cpu(fd->bd.BuffData),
  671. le32_to_cpu(fd->bd.BDCtl));
  672. printk("\n");
  673. }
  674. static int
  675. dump_rxfd(struct RxFD *fd)
  676. {
  677. int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
  678. if (bd_count > 8)
  679. bd_count = 8;
  680. printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
  681. le32_to_cpu(fd->fd.FDNext),
  682. le32_to_cpu(fd->fd.FDSystem),
  683. le32_to_cpu(fd->fd.FDStat),
  684. le32_to_cpu(fd->fd.FDCtl));
  685. if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
  686. return 0;
  687. printk("BD: ");
  688. for (i = 0; i < bd_count; i++)
  689. printk(" %08x %08x",
  690. le32_to_cpu(fd->bd[i].BuffData),
  691. le32_to_cpu(fd->bd[i].BDCtl));
  692. printk("\n");
  693. return bd_count;
  694. }
  695. static void
  696. dump_frfd(struct FrFD *fd)
  697. {
  698. int i;
  699. printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
  700. le32_to_cpu(fd->fd.FDNext),
  701. le32_to_cpu(fd->fd.FDSystem),
  702. le32_to_cpu(fd->fd.FDStat),
  703. le32_to_cpu(fd->fd.FDCtl));
  704. printk("BD: ");
  705. for (i = 0; i < RX_BUF_PAGES; i++)
  706. printk(" %08x %08x",
  707. le32_to_cpu(fd->bd[i].BuffData),
  708. le32_to_cpu(fd->bd[i].BDCtl));
  709. printk("\n");
  710. }
  711. static void
  712. panic_queues(struct net_device *dev)
  713. {
  714. struct tc35815_local *lp = dev->priv;
  715. int i;
  716. printk("TxFD base %p, start %d, end %d\n",
  717. lp->tfd_base, lp->tfd_start, lp->tfd_end);
  718. printk("RxFD base %p limit %p cur %p\n",
  719. lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
  720. printk("FrFD %p\n", lp->fbl_ptr);
  721. for (i = 0; i < TX_FD_NUM; i++)
  722. dump_txfd(&lp->tfd_base[i]);
  723. for (i = 0; i < RX_FD_NUM; i++) {
  724. int bd_count = dump_rxfd(&lp->rfd_base[i]);
  725. i += (bd_count + 1) / 2; /* skip BDs */
  726. }
  727. dump_frfd(lp->fbl_ptr);
  728. panic("%s: Illegal queue state.", dev->name);
  729. }
  730. #if 0
  731. static void print_buf(char *add, int length)
  732. {
  733. int i;
  734. int len = length;
  735. printk("print_buf(%08x)(%x)\n", (unsigned int) add,length);
  736. if (len > 100)
  737. len = 100;
  738. for (i = 0; i < len; i++) {
  739. printk(" %2.2X", (unsigned char) add[i]);
  740. if (!(i % 16))
  741. printk("\n");
  742. }
  743. printk("\n");
  744. }
  745. #endif
  746. static void print_eth(char *add)
  747. {
  748. int i;
  749. printk("print_eth(%08x)\n", (unsigned int) add);
  750. for (i = 0; i < 6; i++)
  751. printk(" %2.2X", (unsigned char) add[i + 6]);
  752. printk(" =>");
  753. for (i = 0; i < 6; i++)
  754. printk(" %2.2X", (unsigned char) add[i]);
  755. printk(" : %2.2X%2.2X\n", (unsigned char) add[12], (unsigned char) add[13]);
  756. }
  757. /*
  758. * Open/initialize the board. This is called (in the current kernel)
  759. * sometime after booting when the 'ifconfig' program is run.
  760. *
  761. * This routine should set everything up anew at each open, even
  762. * registers that "should" only need to be set once at boot, so that
  763. * there is non-reboot way to recover if something goes wrong.
  764. */
  765. static int
  766. tc35815_open(struct net_device *dev)
  767. {
  768. struct tc35815_local *lp = dev->priv;
  769. /*
  770. * This is used if the interrupt line can turned off (shared).
  771. * See 3c503.c for an example of selecting the IRQ at config-time.
  772. */
  773. if (dev->irq == 0 ||
  774. request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED, cardname, dev)) {
  775. return -EAGAIN;
  776. }
  777. tc35815_chip_reset(dev);
  778. if (tc35815_init_queues(dev) != 0) {
  779. free_irq(dev->irq, dev);
  780. return -EAGAIN;
  781. }
  782. /* Reset the hardware here. Don't forget to set the station address. */
  783. tc35815_chip_init(dev);
  784. lp->tbusy = 0;
  785. netif_start_queue(dev);
  786. return 0;
  787. }
  788. static void tc35815_tx_timeout(struct net_device *dev)
  789. {
  790. struct tc35815_local *lp = dev->priv;
  791. struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
  792. unsigned long flags;
  793. spin_lock_irqsave(&lp->lock, flags);
  794. printk(KERN_WARNING "%s: transmit timed out, status %#lx\n",
  795. dev->name, tc_readl(&tr->Tx_Stat));
  796. /* Try to restart the adaptor. */
  797. tc35815_chip_reset(dev);
  798. tc35815_clear_queues(dev);
  799. tc35815_chip_init(dev);
  800. lp->tbusy=0;
  801. spin_unlock_irqrestore(&lp->lock, flags);
  802. dev->trans_start = jiffies;
  803. netif_wake_queue(dev);
  804. }
  805. static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
  806. {
  807. struct tc35815_local *lp = dev->priv;
  808. struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
  809. if (netif_queue_stopped(dev)) {
  810. /*
  811. * If we get here, some higher level has decided we are broken.
  812. * There should really be a "kick me" function call instead.
  813. */
  814. int tickssofar = jiffies - dev->trans_start;
  815. if (tickssofar < 5)
  816. return 1;
  817. printk(KERN_WARNING "%s: transmit timed out, status %#lx\n",
  818. dev->name, tc_readl(&tr->Tx_Stat));
  819. /* Try to restart the adaptor. */
  820. tc35815_chip_reset(dev);
  821. tc35815_clear_queues(dev);
  822. tc35815_chip_init(dev);
  823. lp->tbusy=0;
  824. dev->trans_start = jiffies;
  825. netif_wake_queue(dev);
  826. }
  827. /*
  828. * Block a timer-based transmit from overlapping. This could better be
  829. * done with atomic_swap(1, lp->tbusy), but set_bit() works as well.
  830. */
  831. if (test_and_set_bit(0, (void*)&lp->tbusy) != 0) {
  832. printk(KERN_WARNING "%s: Transmitter access conflict.\n", dev->name);
  833. dev_kfree_skb_any(skb);
  834. } else {
  835. short length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
  836. unsigned char *buf = skb->data;
  837. struct TxFD *txfd = &lp->tfd_base[lp->tfd_start];
  838. unsigned long flags;
  839. lp->stats.tx_bytes += skb->len;
  840. #ifdef __mips__
  841. dma_cache_wback_inv((unsigned long)buf, length);
  842. #endif
  843. spin_lock_irqsave(&lp->lock, flags);
  844. /* failsafe... */
  845. if (lp->tfd_start != lp->tfd_end)
  846. tc35815_txdone(dev);
  847. txfd->bd.BuffData = cpu_to_le32(virt_to_bus(buf));
  848. txfd->bd.BDCtl = cpu_to_le32(length);
  849. txfd->fd.FDSystem = cpu_to_le32((__u32)skb);
  850. txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
  851. if (lp->tfd_start == lp->tfd_end) {
  852. /* Start DMA Transmitter. */
  853. txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
  854. #ifdef GATHER_TXINT
  855. txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
  856. #endif
  857. if (tc35815_debug > 2) {
  858. printk("%s: starting TxFD.\n", dev->name);
  859. dump_txfd(txfd);
  860. if (tc35815_debug > 3)
  861. print_eth(buf);
  862. }
  863. tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
  864. } else {
  865. txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
  866. if (tc35815_debug > 2) {
  867. printk("%s: queueing TxFD.\n", dev->name);
  868. dump_txfd(txfd);
  869. if (tc35815_debug > 3)
  870. print_eth(buf);
  871. }
  872. }
  873. lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
  874. dev->trans_start = jiffies;
  875. if ((lp->tfd_start + 1) % TX_FD_NUM != lp->tfd_end) {
  876. /* we can send another packet */
  877. lp->tbusy = 0;
  878. netif_start_queue(dev);
  879. } else {
  880. netif_stop_queue(dev);
  881. if (tc35815_debug > 1)
  882. printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
  883. }
  884. spin_unlock_irqrestore(&lp->lock, flags);
  885. }
  886. return 0;
  887. }
  888. #define FATAL_ERROR_INT \
  889. (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
  890. static void tc35815_fatal_error_interrupt(struct net_device *dev, int status)
  891. {
  892. static int count;
  893. printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
  894. dev->name, status);
  895. if (status & Int_IntPCI)
  896. printk(" IntPCI");
  897. if (status & Int_DmParErr)
  898. printk(" DmParErr");
  899. if (status & Int_IntNRAbt)
  900. printk(" IntNRAbt");
  901. printk("\n");
  902. if (count++ > 100)
  903. panic("%s: Too many fatal errors.", dev->name);
  904. printk(KERN_WARNING "%s: Resetting %s...\n", dev->name, cardname);
  905. /* Try to restart the adaptor. */
  906. tc35815_chip_reset(dev);
  907. tc35815_clear_queues(dev);
  908. tc35815_chip_init(dev);
  909. }
  910. /*
  911. * The typical workload of the driver:
  912. * Handle the network interface interrupts.
  913. */
  914. static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
  915. {
  916. struct net_device *dev = dev_id;
  917. struct tc35815_regs *tr;
  918. struct tc35815_local *lp;
  919. int status, boguscount = 0;
  920. int handled = 0;
  921. if (dev == NULL) {
  922. printk(KERN_WARNING "%s: irq %d for unknown device.\n", cardname, irq);
  923. return IRQ_NONE;
  924. }
  925. tr = (struct tc35815_regs*)dev->base_addr;
  926. lp = dev->priv;
  927. do {
  928. status = tc_readl(&tr->Int_Src);
  929. if (status == 0)
  930. break;
  931. handled = 1;
  932. tc_writel(status, &tr->Int_Src); /* write to clear */
  933. /* Fatal errors... */
  934. if (status & FATAL_ERROR_INT) {
  935. tc35815_fatal_error_interrupt(dev, status);
  936. break;
  937. }
  938. /* recoverable errors */
  939. if (status & Int_IntFDAEx) {
  940. /* disable FDAEx int. (until we make rooms...) */
  941. tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
  942. printk(KERN_WARNING
  943. "%s: Free Descriptor Area Exhausted (%#x).\n",
  944. dev->name, status);
  945. lp->stats.rx_dropped++;
  946. }
  947. if (status & Int_IntBLEx) {
  948. /* disable BLEx int. (until we make rooms...) */
  949. tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
  950. printk(KERN_WARNING
  951. "%s: Buffer List Exhausted (%#x).\n",
  952. dev->name, status);
  953. lp->stats.rx_dropped++;
  954. }
  955. if (status & Int_IntExBD) {
  956. printk(KERN_WARNING
  957. "%s: Excessive Buffer Descriptiors (%#x).\n",
  958. dev->name, status);
  959. lp->stats.rx_length_errors++;
  960. }
  961. /* normal notification */
  962. if (status & Int_IntMacRx) {
  963. /* Got a packet(s). */
  964. lp->lstats.rx_ints++;
  965. tc35815_rx(dev);
  966. }
  967. if (status & Int_IntMacTx) {
  968. lp->lstats.tx_ints++;
  969. tc35815_txdone(dev);
  970. }
  971. } while (++boguscount < 20) ;
  972. return IRQ_RETVAL(handled);
  973. }
  974. /* We have a good packet(s), get it/them out of the buffers. */
  975. static void
  976. tc35815_rx(struct net_device *dev)
  977. {
  978. struct tc35815_local *lp = dev->priv;
  979. struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
  980. unsigned int fdctl;
  981. int i;
  982. int buf_free_count = 0;
  983. int fd_free_count = 0;
  984. while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
  985. int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
  986. int pkt_len = fdctl & FD_FDLength_MASK;
  987. struct RxFD *next_rfd;
  988. int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
  989. if (tc35815_debug > 2)
  990. dump_rxfd(lp->rfd_cur);
  991. if (status & Rx_Good) {
  992. /* Malloc up new buffer. */
  993. struct sk_buff *skb;
  994. unsigned char *data;
  995. int cur_bd, offset;
  996. lp->stats.rx_bytes += pkt_len;
  997. skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
  998. if (skb == NULL) {
  999. printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
  1000. dev->name);
  1001. lp->stats.rx_dropped++;
  1002. break;
  1003. }
  1004. skb_reserve(skb, 2); /* 16 bit alignment */
  1005. skb->dev = dev;
  1006. data = skb_put(skb, pkt_len);
  1007. /* copy from receive buffer */
  1008. cur_bd = 0;
  1009. offset = 0;
  1010. while (offset < pkt_len && cur_bd < bd_count) {
  1011. int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
  1012. BD_BuffLength_MASK;
  1013. void *rxbuf =
  1014. bus_to_virt(le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData));
  1015. #ifdef __mips__
  1016. dma_cache_inv((unsigned long)rxbuf, len);
  1017. #endif
  1018. memcpy(data + offset, rxbuf, len);
  1019. offset += len;
  1020. cur_bd++;
  1021. }
  1022. #if 0
  1023. print_buf(data,pkt_len);
  1024. #endif
  1025. if (tc35815_debug > 3)
  1026. print_eth(data);
  1027. skb->protocol = eth_type_trans(skb, dev);
  1028. netif_rx(skb);
  1029. lp->stats.rx_packets++;
  1030. } else {
  1031. lp->stats.rx_errors++;
  1032. /* WORKAROUND: LongErr and CRCErr means Overflow. */
  1033. if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
  1034. status &= ~(Rx_LongErr|Rx_CRCErr);
  1035. status |= Rx_Over;
  1036. }
  1037. if (status & Rx_LongErr) lp->stats.rx_length_errors++;
  1038. if (status & Rx_Over) lp->stats.rx_fifo_errors++;
  1039. if (status & Rx_CRCErr) lp->stats.rx_crc_errors++;
  1040. if (status & Rx_Align) lp->stats.rx_frame_errors++;
  1041. }
  1042. if (bd_count > 0) {
  1043. /* put Free Buffer back to controller */
  1044. int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
  1045. unsigned char id =
  1046. (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
  1047. if (id >= RX_BUF_PAGES) {
  1048. printk("%s: invalid BDID.\n", dev->name);
  1049. panic_queues(dev);
  1050. }
  1051. /* free old buffers */
  1052. while (lp->fbl_curid != id) {
  1053. bdctl = le32_to_cpu(lp->fbl_ptr->bd[lp->fbl_curid].BDCtl);
  1054. if (bdctl & BD_CownsBD) {
  1055. printk("%s: Freeing invalid BD.\n",
  1056. dev->name);
  1057. panic_queues(dev);
  1058. }
  1059. /* pass BD to controler */
  1060. /* Note: BDLength was modified by chip. */
  1061. lp->fbl_ptr->bd[lp->fbl_curid].BDCtl =
  1062. cpu_to_le32(BD_CownsBD |
  1063. (lp->fbl_curid << BD_RxBDID_SHIFT) |
  1064. PAGE_SIZE);
  1065. lp->fbl_curid =
  1066. (lp->fbl_curid + 1) % RX_BUF_PAGES;
  1067. if (tc35815_debug > 2) {
  1068. printk("%s: Entering new FBD %d\n",
  1069. dev->name, lp->fbl_curid);
  1070. dump_frfd(lp->fbl_ptr);
  1071. }
  1072. buf_free_count++;
  1073. }
  1074. }
  1075. /* put RxFD back to controller */
  1076. next_rfd = bus_to_virt(le32_to_cpu(lp->rfd_cur->fd.FDNext));
  1077. #ifdef __mips__
  1078. next_rfd = (struct RxFD *)vtonocache(next_rfd);
  1079. #endif
  1080. if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
  1081. printk("%s: RxFD FDNext invalid.\n", dev->name);
  1082. panic_queues(dev);
  1083. }
  1084. for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
  1085. /* pass FD to controler */
  1086. lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); /* for debug */
  1087. lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
  1088. lp->rfd_cur++;
  1089. fd_free_count++;
  1090. }
  1091. lp->rfd_cur = next_rfd;
  1092. }
  1093. /* re-enable BL/FDA Exhaust interrupts. */
  1094. if (fd_free_count) {
  1095. tc_writel(tc_readl(&tr->Int_En) | Int_FDAExEn, &tr->Int_En);
  1096. if (buf_free_count)
  1097. tc_writel(tc_readl(&tr->Int_En) | Int_BLExEn, &tr->Int_En);
  1098. }
  1099. }
  1100. #ifdef NO_CHECK_CARRIER
  1101. #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
  1102. #else
  1103. #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
  1104. #endif
  1105. static void
  1106. tc35815_check_tx_stat(struct net_device *dev, int status)
  1107. {
  1108. struct tc35815_local *lp = dev->priv;
  1109. const char *msg = NULL;
  1110. /* count collisions */
  1111. if (status & Tx_ExColl)
  1112. lp->stats.collisions += 16;
  1113. if (status & Tx_TxColl_MASK)
  1114. lp->stats.collisions += status & Tx_TxColl_MASK;
  1115. /* WORKAROUND: ignore LostCrS in full duplex operation */
  1116. if (lp->fullduplex)
  1117. status &= ~Tx_NCarr;
  1118. if (!(status & TX_STA_ERR)) {
  1119. /* no error. */
  1120. lp->stats.tx_packets++;
  1121. return;
  1122. }
  1123. lp->stats.tx_errors++;
  1124. if (status & Tx_ExColl) {
  1125. lp->stats.tx_aborted_errors++;
  1126. msg = "Excessive Collision.";
  1127. }
  1128. if (status & Tx_Under) {
  1129. lp->stats.tx_fifo_errors++;
  1130. msg = "Tx FIFO Underrun.";
  1131. }
  1132. if (status & Tx_Defer) {
  1133. lp->stats.tx_fifo_errors++;
  1134. msg = "Excessive Deferral.";
  1135. }
  1136. #ifndef NO_CHECK_CARRIER
  1137. if (status & Tx_NCarr) {
  1138. lp->stats.tx_carrier_errors++;
  1139. msg = "Lost Carrier Sense.";
  1140. }
  1141. #endif
  1142. if (status & Tx_LateColl) {
  1143. lp->stats.tx_aborted_errors++;
  1144. msg = "Late Collision.";
  1145. }
  1146. if (status & Tx_TxPar) {
  1147. lp->stats.tx_fifo_errors++;
  1148. msg = "Transmit Parity Error.";
  1149. }
  1150. if (status & Tx_SQErr) {
  1151. lp->stats.tx_heartbeat_errors++;
  1152. msg = "Signal Quality Error.";
  1153. }
  1154. if (msg)
  1155. printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
  1156. }
  1157. static void
  1158. tc35815_txdone(struct net_device *dev)
  1159. {
  1160. struct tc35815_local *lp = dev->priv;
  1161. struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
  1162. struct TxFD *txfd;
  1163. unsigned int fdctl;
  1164. int num_done = 0;
  1165. txfd = &lp->tfd_base[lp->tfd_end];
  1166. while (lp->tfd_start != lp->tfd_end &&
  1167. !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
  1168. int status = le32_to_cpu(txfd->fd.FDStat);
  1169. struct sk_buff *skb;
  1170. unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
  1171. if (tc35815_debug > 2) {
  1172. printk("%s: complete TxFD.\n", dev->name);
  1173. dump_txfd(txfd);
  1174. }
  1175. tc35815_check_tx_stat(dev, status);
  1176. skb = (struct sk_buff *)le32_to_cpu(txfd->fd.FDSystem);
  1177. if (skb) {
  1178. dev_kfree_skb_any(skb);
  1179. }
  1180. txfd->fd.FDSystem = cpu_to_le32(0);
  1181. num_done++;
  1182. lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
  1183. txfd = &lp->tfd_base[lp->tfd_end];
  1184. if ((fdnext & ~FD_Next_EOL) != virt_to_bus(txfd)) {
  1185. printk("%s: TxFD FDNext invalid.\n", dev->name);
  1186. panic_queues(dev);
  1187. }
  1188. if (fdnext & FD_Next_EOL) {
  1189. /* DMA Transmitter has been stopping... */
  1190. if (lp->tfd_end != lp->tfd_start) {
  1191. int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
  1192. struct TxFD* txhead = &lp->tfd_base[head];
  1193. int qlen = (lp->tfd_start + TX_FD_NUM
  1194. - lp->tfd_end) % TX_FD_NUM;
  1195. if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
  1196. printk("%s: TxFD FDCtl invalid.\n", dev->name);
  1197. panic_queues(dev);
  1198. }
  1199. /* log max queue length */
  1200. if (lp->lstats.max_tx_qlen < qlen)
  1201. lp->lstats.max_tx_qlen = qlen;
  1202. /* start DMA Transmitter again */
  1203. txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
  1204. #ifdef GATHER_TXINT
  1205. txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
  1206. #endif
  1207. if (tc35815_debug > 2) {
  1208. printk("%s: start TxFD on queue.\n",
  1209. dev->name);
  1210. dump_txfd(txfd);
  1211. }
  1212. tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
  1213. }
  1214. break;
  1215. }
  1216. }
  1217. if (num_done > 0 && lp->tbusy) {
  1218. lp->tbusy = 0;
  1219. netif_start_queue(dev);
  1220. }
  1221. }
  1222. /* The inverse routine to tc35815_open(). */
  1223. static int
  1224. tc35815_close(struct net_device *dev)
  1225. {
  1226. struct tc35815_local *lp = dev->priv;
  1227. lp->tbusy = 1;
  1228. netif_stop_queue(dev);
  1229. /* Flush the Tx and disable Rx here. */
  1230. tc35815_chip_reset(dev);
  1231. free_irq(dev->irq, dev);
  1232. tc35815_free_queues(dev);
  1233. return 0;
  1234. }
  1235. /*
  1236. * Get the current statistics.
  1237. * This may be called with the card open or closed.
  1238. */
  1239. static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
  1240. {
  1241. struct tc35815_local *lp = dev->priv;
  1242. struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
  1243. unsigned long flags;
  1244. if (netif_running(dev)) {
  1245. spin_lock_irqsave(&lp->lock, flags);
  1246. /* Update the statistics from the device registers. */
  1247. lp->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
  1248. spin_unlock_irqrestore(&lp->lock, flags);
  1249. }
  1250. return &lp->stats;
  1251. }
  1252. static void tc35815_set_cam_entry(struct tc35815_regs *tr, int index, unsigned char *addr)
  1253. {
  1254. int cam_index = index * 6;
  1255. unsigned long cam_data;
  1256. unsigned long saved_addr;
  1257. saved_addr = tc_readl(&tr->CAM_Adr);
  1258. if (tc35815_debug > 1) {
  1259. int i;
  1260. printk(KERN_DEBUG "%s: CAM %d:", cardname, index);
  1261. for (i = 0; i < 6; i++)
  1262. printk(" %02x", addr[i]);
  1263. printk("\n");
  1264. }
  1265. if (index & 1) {
  1266. /* read modify write */
  1267. tc_writel(cam_index - 2, &tr->CAM_Adr);
  1268. cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
  1269. cam_data |= addr[0] << 8 | addr[1];
  1270. tc_writel(cam_data, &tr->CAM_Data);
  1271. /* write whole word */
  1272. tc_writel(cam_index + 2, &tr->CAM_Adr);
  1273. cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
  1274. tc_writel(cam_data, &tr->CAM_Data);
  1275. } else {
  1276. /* write whole word */
  1277. tc_writel(cam_index, &tr->CAM_Adr);
  1278. cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
  1279. tc_writel(cam_data, &tr->CAM_Data);
  1280. /* read modify write */
  1281. tc_writel(cam_index + 4, &tr->CAM_Adr);
  1282. cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
  1283. cam_data |= addr[4] << 24 | (addr[5] << 16);
  1284. tc_writel(cam_data, &tr->CAM_Data);
  1285. }
  1286. if (tc35815_debug > 2) {
  1287. int i;
  1288. for (i = cam_index / 4; i < cam_index / 4 + 2; i++) {
  1289. tc_writel(i * 4, &tr->CAM_Adr);
  1290. printk("CAM 0x%x: %08lx",
  1291. i * 4, tc_readl(&tr->CAM_Data));
  1292. }
  1293. }
  1294. tc_writel(saved_addr, &tr->CAM_Adr);
  1295. }
  1296. /*
  1297. * Set or clear the multicast filter for this adaptor.
  1298. * num_addrs == -1 Promiscuous mode, receive all packets
  1299. * num_addrs == 0 Normal mode, clear multicast list
  1300. * num_addrs > 0 Multicast mode, receive normal and MC packets,
  1301. * and do best-effort filtering.
  1302. */
  1303. static void
  1304. tc35815_set_multicast_list(struct net_device *dev)
  1305. {
  1306. struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
  1307. if (dev->flags&IFF_PROMISC)
  1308. {
  1309. /* Enable promiscuous mode */
  1310. tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
  1311. }
  1312. else if((dev->flags&IFF_ALLMULTI) || dev->mc_count > CAM_ENTRY_MAX - 3)
  1313. {
  1314. /* CAM 0, 1, 20 are reserved. */
  1315. /* Disable promiscuous mode, use normal mode. */
  1316. tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
  1317. }
  1318. else if(dev->mc_count)
  1319. {
  1320. struct dev_mc_list* cur_addr = dev->mc_list;
  1321. int i;
  1322. int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
  1323. tc_writel(0, &tr->CAM_Ctl);
  1324. /* Walk the address list, and load the filter */
  1325. for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
  1326. if (!cur_addr)
  1327. break;
  1328. /* entry 0,1 is reserved. */
  1329. tc35815_set_cam_entry(tr, i + 2, cur_addr->dmi_addr);
  1330. ena_bits |= CAM_Ena_Bit(i + 2);
  1331. }
  1332. tc_writel(ena_bits, &tr->CAM_Ena);
  1333. tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
  1334. }
  1335. else {
  1336. tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
  1337. tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
  1338. }
  1339. }
  1340. static unsigned long tc_phy_read(struct net_device *dev, struct tc35815_regs *tr, int phy, int phy_reg)
  1341. {
  1342. struct tc35815_local *lp = dev->priv;
  1343. unsigned long data;
  1344. unsigned long flags;
  1345. spin_lock_irqsave(&lp->lock, flags);
  1346. tc_writel(MD_CA_Busy | (phy << 5) | phy_reg, &tr->MD_CA);
  1347. while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
  1348. ;
  1349. data = tc_readl(&tr->MD_Data);
  1350. spin_unlock_irqrestore(&lp->lock, flags);
  1351. return data;
  1352. }
  1353. static void tc_phy_write(struct net_device *dev, unsigned long d, struct tc35815_regs *tr, int phy, int phy_reg)
  1354. {
  1355. struct tc35815_local *lp = dev->priv;
  1356. unsigned long flags;
  1357. spin_lock_irqsave(&lp->lock, flags);
  1358. tc_writel(d, &tr->MD_Data);
  1359. tc_writel(MD_CA_Busy | MD_CA_Wr | (phy << 5) | phy_reg, &tr->MD_CA);
  1360. while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
  1361. ;
  1362. spin_unlock_irqrestore(&lp->lock, flags);
  1363. }
  1364. static void tc35815_phy_chip_init(struct net_device *dev)
  1365. {
  1366. struct tc35815_local *lp = dev->priv;
  1367. struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
  1368. static int first = 1;
  1369. unsigned short ctl;
  1370. if (first) {
  1371. unsigned short id0, id1;
  1372. int count;
  1373. first = 0;
  1374. /* first data written to the PHY will be an ID number */
  1375. tc_phy_write(dev, 0, tr, 0, MII_CONTROL); /* ID:0 */
  1376. #if 0
  1377. tc_phy_write(dev, MIICNTL_RESET, tr, 0, MII_CONTROL);
  1378. printk(KERN_INFO "%s: Resetting PHY...", dev->name);
  1379. while (tc_phy_read(dev, tr, 0, MII_CONTROL) & MIICNTL_RESET)
  1380. ;
  1381. printk("\n");
  1382. tc_phy_write(dev, MIICNTL_AUTO|MIICNTL_SPEED|MIICNTL_FDX, tr, 0,
  1383. MII_CONTROL);
  1384. #endif
  1385. id0 = tc_phy_read(dev, tr, 0, MII_PHY_ID0);
  1386. id1 = tc_phy_read(dev, tr, 0, MII_PHY_ID1);
  1387. printk(KERN_DEBUG "%s: PHY ID %04x %04x\n", dev->name,
  1388. id0, id1);
  1389. if (lp->option & TC35815_OPT_10M) {
  1390. lp->linkspeed = 10;
  1391. lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
  1392. } else if (lp->option & TC35815_OPT_100M) {
  1393. lp->linkspeed = 100;
  1394. lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
  1395. } else {
  1396. /* auto negotiation */
  1397. unsigned long neg_result;
  1398. tc_phy_write(dev, MIICNTL_AUTO | MIICNTL_RST_AUTO, tr, 0, MII_CONTROL);
  1399. printk(KERN_INFO "%s: Auto Negotiation...", dev->name);
  1400. count = 0;
  1401. while (!(tc_phy_read(dev, tr, 0, MII_STATUS) & MIISTAT_AUTO_DONE)) {
  1402. if (count++ > 5000) {
  1403. printk(" failed. Assume 10Mbps\n");
  1404. lp->linkspeed = 10;
  1405. lp->fullduplex = 0;
  1406. goto done;
  1407. }
  1408. if (count % 512 == 0)
  1409. printk(".");
  1410. mdelay(1);
  1411. }
  1412. printk(" done.\n");
  1413. neg_result = tc_phy_read(dev, tr, 0, MII_ANLPAR);
  1414. if (neg_result & (MII_AN_TX_FDX | MII_AN_TX_HDX))
  1415. lp->linkspeed = 100;
  1416. else
  1417. lp->linkspeed = 10;
  1418. if (neg_result & (MII_AN_TX_FDX | MII_AN_10_FDX))
  1419. lp->fullduplex = 1;
  1420. else
  1421. lp->fullduplex = 0;
  1422. done:
  1423. ;
  1424. }
  1425. }
  1426. ctl = 0;
  1427. if (lp->linkspeed == 100)
  1428. ctl |= MIICNTL_SPEED;
  1429. if (lp->fullduplex)
  1430. ctl |= MIICNTL_FDX;
  1431. tc_phy_write(dev, ctl, tr, 0, MII_CONTROL);
  1432. if (lp->fullduplex) {
  1433. tc_writel(tc_readl(&tr->MAC_Ctl) | MAC_FullDup, &tr->MAC_Ctl);
  1434. }
  1435. }
  1436. static void tc35815_chip_reset(struct net_device *dev)
  1437. {
  1438. struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
  1439. /* reset the controller */
  1440. tc_writel(MAC_Reset, &tr->MAC_Ctl);
  1441. while (tc_readl(&tr->MAC_Ctl) & MAC_Reset)
  1442. ;
  1443. tc_writel(0, &tr->MAC_Ctl);
  1444. /* initialize registers to default value */
  1445. tc_writel(0, &tr->DMA_Ctl);
  1446. tc_writel(0, &tr->TxThrsh);
  1447. tc_writel(0, &tr->TxPollCtr);
  1448. tc_writel(0, &tr->RxFragSize);
  1449. tc_writel(0, &tr->Int_En);
  1450. tc_writel(0, &tr->FDA_Bas);
  1451. tc_writel(0, &tr->FDA_Lim);
  1452. tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
  1453. tc_writel(0, &tr->CAM_Ctl);
  1454. tc_writel(0, &tr->Tx_Ctl);
  1455. tc_writel(0, &tr->Rx_Ctl);
  1456. tc_writel(0, &tr->CAM_Ena);
  1457. (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
  1458. }
  1459. static void tc35815_chip_init(struct net_device *dev)
  1460. {
  1461. struct tc35815_local *lp = dev->priv;
  1462. struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
  1463. unsigned long flags;
  1464. unsigned long txctl = TX_CTL_CMD;
  1465. tc35815_phy_chip_init(dev);
  1466. /* load station address to CAM */
  1467. tc35815_set_cam_entry(tr, CAM_ENTRY_SOURCE, dev->dev_addr);
  1468. /* Enable CAM (broadcast and unicast) */
  1469. tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
  1470. tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
  1471. spin_lock_irqsave(&lp->lock, flags);
  1472. tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
  1473. tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
  1474. tc_writel(0, &tr->TxPollCtr); /* Batch mode */
  1475. tc_writel(TX_THRESHOLD, &tr->TxThrsh);
  1476. tc_writel(INT_EN_CMD, &tr->Int_En);
  1477. /* set queues */
  1478. tc_writel(virt_to_bus(lp->rfd_base), &tr->FDA_Bas);
  1479. tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
  1480. &tr->FDA_Lim);
  1481. /*
  1482. * Activation method:
  1483. * First, enable eht MAC Transmitter and the DMA Receive circuits.
  1484. * Then enable the DMA Transmitter and the MAC Receive circuits.
  1485. */
  1486. tc_writel(virt_to_bus(lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
  1487. tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
  1488. /* start MAC transmitter */
  1489. /* WORKAROUND: ignore LostCrS in full duplex operation */
  1490. if (lp->fullduplex)
  1491. txctl = TX_CTL_CMD & ~Tx_EnLCarr;
  1492. #ifdef GATHER_TXINT
  1493. txctl &= ~Tx_EnComp; /* disable global tx completion int. */
  1494. #endif
  1495. tc_writel(txctl, &tr->Tx_Ctl);
  1496. #if 0 /* No need to polling */
  1497. tc_writel(virt_to_bus(lp->tfd_base), &tr->TxFrmPtr); /* start DMA transmitter */
  1498. #endif
  1499. spin_unlock_irqrestore(&lp->lock, flags);
  1500. }
  1501. static struct pci_driver tc35815_driver = {
  1502. .name = TC35815_MODULE_NAME,
  1503. .probe = tc35815_probe,
  1504. .remove = NULL,
  1505. .id_table = tc35815_pci_tbl,
  1506. };
  1507. static int __init tc35815_init_module(void)
  1508. {
  1509. return pci_register_driver(&tc35815_driver);
  1510. }
  1511. static void __exit tc35815_cleanup_module(void)
  1512. {
  1513. struct net_device *next_dev;
  1514. /*
  1515. * TODO: implement a tc35815_driver.remove hook, and
  1516. * move this code into that function. Then, delete
  1517. * all root_tc35815_dev list handling code.
  1518. */
  1519. while (root_tc35815_dev) {
  1520. struct net_device *dev = root_tc35815_dev;
  1521. next_dev = ((struct tc35815_local *)dev->priv)->next_module;
  1522. iounmap((void *)(dev->base_addr));
  1523. unregister_netdev(dev);
  1524. free_netdev(dev);
  1525. root_tc35815_dev = next_dev;
  1526. }
  1527. pci_unregister_driver(&tc35815_driver);
  1528. }
  1529. module_init(tc35815_init_module);
  1530. module_exit(tc35815_cleanup_module);