sunqe.c 26 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024
  1. /* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
  2. * Once again I am out to prove that every ethernet
  3. * controller out there can be most efficiently programmed
  4. * if you make it look like a LANCE.
  5. *
  6. * Copyright (C) 1996, 1999, 2003, 2006 David S. Miller (davem@davemloft.net)
  7. */
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/types.h>
  11. #include <linux/errno.h>
  12. #include <linux/fcntl.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ioport.h>
  15. #include <linux/in.h>
  16. #include <linux/slab.h>
  17. #include <linux/string.h>
  18. #include <linux/delay.h>
  19. #include <linux/init.h>
  20. #include <linux/crc32.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/skbuff.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/bitops.h>
  26. #include <asm/system.h>
  27. #include <asm/io.h>
  28. #include <asm/dma.h>
  29. #include <asm/byteorder.h>
  30. #include <asm/idprom.h>
  31. #include <asm/sbus.h>
  32. #include <asm/openprom.h>
  33. #include <asm/oplib.h>
  34. #include <asm/auxio.h>
  35. #include <asm/pgtable.h>
  36. #include <asm/irq.h>
  37. #include "sunqe.h"
  38. #define DRV_NAME "sunqe"
  39. #define DRV_VERSION "4.0"
  40. #define DRV_RELDATE "June 23, 2006"
  41. #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
  42. static char version[] =
  43. DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
  44. MODULE_VERSION(DRV_VERSION);
  45. MODULE_AUTHOR(DRV_AUTHOR);
  46. MODULE_DESCRIPTION("Sun QuadEthernet 10baseT SBUS card driver");
  47. MODULE_LICENSE("GPL");
  48. static struct sunqec *root_qec_dev;
  49. static void qe_set_multicast(struct net_device *dev);
  50. #define QEC_RESET_TRIES 200
  51. static inline int qec_global_reset(void __iomem *gregs)
  52. {
  53. int tries = QEC_RESET_TRIES;
  54. sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
  55. while (--tries) {
  56. u32 tmp = sbus_readl(gregs + GLOB_CTRL);
  57. if (tmp & GLOB_CTRL_RESET) {
  58. udelay(20);
  59. continue;
  60. }
  61. break;
  62. }
  63. if (tries)
  64. return 0;
  65. printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n");
  66. return -1;
  67. }
  68. #define MACE_RESET_RETRIES 200
  69. #define QE_RESET_RETRIES 200
  70. static inline int qe_stop(struct sunqe *qep)
  71. {
  72. void __iomem *cregs = qep->qcregs;
  73. void __iomem *mregs = qep->mregs;
  74. int tries;
  75. /* Reset the MACE, then the QEC channel. */
  76. sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
  77. tries = MACE_RESET_RETRIES;
  78. while (--tries) {
  79. u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
  80. if (tmp & MREGS_BCONFIG_RESET) {
  81. udelay(20);
  82. continue;
  83. }
  84. break;
  85. }
  86. if (!tries) {
  87. printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n");
  88. return -1;
  89. }
  90. sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL);
  91. tries = QE_RESET_RETRIES;
  92. while (--tries) {
  93. u32 tmp = sbus_readl(cregs + CREG_CTRL);
  94. if (tmp & CREG_CTRL_RESET) {
  95. udelay(20);
  96. continue;
  97. }
  98. break;
  99. }
  100. if (!tries) {
  101. printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n");
  102. return -1;
  103. }
  104. return 0;
  105. }
  106. static void qe_init_rings(struct sunqe *qep)
  107. {
  108. struct qe_init_block *qb = qep->qe_block;
  109. struct sunqe_buffers *qbufs = qep->buffers;
  110. __u32 qbufs_dvma = qep->buffers_dvma;
  111. int i;
  112. qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
  113. memset(qb, 0, sizeof(struct qe_init_block));
  114. memset(qbufs, 0, sizeof(struct sunqe_buffers));
  115. for (i = 0; i < RX_RING_SIZE; i++) {
  116. qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
  117. qb->qe_rxd[i].rx_flags =
  118. (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
  119. }
  120. }
  121. static int qe_init(struct sunqe *qep, int from_irq)
  122. {
  123. struct sunqec *qecp = qep->parent;
  124. void __iomem *cregs = qep->qcregs;
  125. void __iomem *mregs = qep->mregs;
  126. void __iomem *gregs = qecp->gregs;
  127. unsigned char *e = &qep->dev->dev_addr[0];
  128. u32 tmp;
  129. int i;
  130. /* Shut it up. */
  131. if (qe_stop(qep))
  132. return -EAGAIN;
  133. /* Setup initial rx/tx init block pointers. */
  134. sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
  135. sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
  136. /* Enable/mask the various irq's. */
  137. sbus_writel(0, cregs + CREG_RIMASK);
  138. sbus_writel(1, cregs + CREG_TIMASK);
  139. sbus_writel(0, cregs + CREG_QMASK);
  140. sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK);
  141. /* Setup the FIFO pointers into QEC local memory. */
  142. tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
  143. sbus_writel(tmp, cregs + CREG_RXRBUFPTR);
  144. sbus_writel(tmp, cregs + CREG_RXWBUFPTR);
  145. tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
  146. sbus_readl(gregs + GLOB_RSIZE);
  147. sbus_writel(tmp, cregs + CREG_TXRBUFPTR);
  148. sbus_writel(tmp, cregs + CREG_TXWBUFPTR);
  149. /* Clear the channel collision counter. */
  150. sbus_writel(0, cregs + CREG_CCNT);
  151. /* For 10baseT, inter frame space nor throttle seems to be necessary. */
  152. sbus_writel(0, cregs + CREG_PIPG);
  153. /* Now dork with the AMD MACE. */
  154. sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
  155. sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
  156. sbus_writeb(0, mregs + MREGS_RXFCNTL);
  157. /* The QEC dma's the rx'd packets from local memory out to main memory,
  158. * and therefore it interrupts when the packet reception is "complete".
  159. * So don't listen for the MACE talking about it.
  160. */
  161. sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
  162. sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
  163. sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
  164. MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU),
  165. mregs + MREGS_FCONFIG);
  166. /* Only usable interface on QuadEther is twisted pair. */
  167. sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
  168. /* Tell MACE we are changing the ether address. */
  169. sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
  170. mregs + MREGS_IACONFIG);
  171. while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
  172. barrier();
  173. sbus_writeb(e[0], mregs + MREGS_ETHADDR);
  174. sbus_writeb(e[1], mregs + MREGS_ETHADDR);
  175. sbus_writeb(e[2], mregs + MREGS_ETHADDR);
  176. sbus_writeb(e[3], mregs + MREGS_ETHADDR);
  177. sbus_writeb(e[4], mregs + MREGS_ETHADDR);
  178. sbus_writeb(e[5], mregs + MREGS_ETHADDR);
  179. /* Clear out the address filter. */
  180. sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
  181. mregs + MREGS_IACONFIG);
  182. while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
  183. barrier();
  184. for (i = 0; i < 8; i++)
  185. sbus_writeb(0, mregs + MREGS_FILTER);
  186. /* Address changes are now complete. */
  187. sbus_writeb(0, mregs + MREGS_IACONFIG);
  188. qe_init_rings(qep);
  189. /* Wait a little bit for the link to come up... */
  190. mdelay(5);
  191. if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
  192. int tries = 50;
  193. while (tries--) {
  194. u8 tmp;
  195. mdelay(5);
  196. barrier();
  197. tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
  198. if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0)
  199. break;
  200. }
  201. if (tries == 0)
  202. printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name);
  203. }
  204. /* Missed packet counter is cleared on a read. */
  205. sbus_readb(mregs + MREGS_MPCNT);
  206. /* Reload multicast information, this will enable the receiver
  207. * and transmitter.
  208. */
  209. qe_set_multicast(qep->dev);
  210. /* QEC should now start to show interrupts. */
  211. return 0;
  212. }
  213. /* Grrr, certain error conditions completely lock up the AMD MACE,
  214. * so when we get these we _must_ reset the chip.
  215. */
  216. static int qe_is_bolixed(struct sunqe *qep, u32 qe_status)
  217. {
  218. struct net_device *dev = qep->dev;
  219. int mace_hwbug_workaround = 0;
  220. if (qe_status & CREG_STAT_EDEFER) {
  221. printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name);
  222. qep->net_stats.tx_errors++;
  223. }
  224. if (qe_status & CREG_STAT_CLOSS) {
  225. printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name);
  226. qep->net_stats.tx_errors++;
  227. qep->net_stats.tx_carrier_errors++;
  228. }
  229. if (qe_status & CREG_STAT_ERETRIES) {
  230. printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name);
  231. qep->net_stats.tx_errors++;
  232. mace_hwbug_workaround = 1;
  233. }
  234. if (qe_status & CREG_STAT_LCOLL) {
  235. printk(KERN_ERR "%s: Late transmit collision.\n", dev->name);
  236. qep->net_stats.tx_errors++;
  237. qep->net_stats.collisions++;
  238. mace_hwbug_workaround = 1;
  239. }
  240. if (qe_status & CREG_STAT_FUFLOW) {
  241. printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name);
  242. qep->net_stats.tx_errors++;
  243. mace_hwbug_workaround = 1;
  244. }
  245. if (qe_status & CREG_STAT_JERROR) {
  246. printk(KERN_ERR "%s: Jabber error.\n", dev->name);
  247. }
  248. if (qe_status & CREG_STAT_BERROR) {
  249. printk(KERN_ERR "%s: Babble error.\n", dev->name);
  250. }
  251. if (qe_status & CREG_STAT_CCOFLOW) {
  252. qep->net_stats.tx_errors += 256;
  253. qep->net_stats.collisions += 256;
  254. }
  255. if (qe_status & CREG_STAT_TXDERROR) {
  256. printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
  257. qep->net_stats.tx_errors++;
  258. qep->net_stats.tx_aborted_errors++;
  259. mace_hwbug_workaround = 1;
  260. }
  261. if (qe_status & CREG_STAT_TXLERR) {
  262. printk(KERN_ERR "%s: Transmit late error.\n", dev->name);
  263. qep->net_stats.tx_errors++;
  264. mace_hwbug_workaround = 1;
  265. }
  266. if (qe_status & CREG_STAT_TXPERR) {
  267. printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name);
  268. qep->net_stats.tx_errors++;
  269. qep->net_stats.tx_aborted_errors++;
  270. mace_hwbug_workaround = 1;
  271. }
  272. if (qe_status & CREG_STAT_TXSERR) {
  273. printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name);
  274. qep->net_stats.tx_errors++;
  275. qep->net_stats.tx_aborted_errors++;
  276. mace_hwbug_workaround = 1;
  277. }
  278. if (qe_status & CREG_STAT_RCCOFLOW) {
  279. qep->net_stats.rx_errors += 256;
  280. qep->net_stats.collisions += 256;
  281. }
  282. if (qe_status & CREG_STAT_RUOFLOW) {
  283. qep->net_stats.rx_errors += 256;
  284. qep->net_stats.rx_over_errors += 256;
  285. }
  286. if (qe_status & CREG_STAT_MCOFLOW) {
  287. qep->net_stats.rx_errors += 256;
  288. qep->net_stats.rx_missed_errors += 256;
  289. }
  290. if (qe_status & CREG_STAT_RXFOFLOW) {
  291. printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name);
  292. qep->net_stats.rx_errors++;
  293. qep->net_stats.rx_over_errors++;
  294. }
  295. if (qe_status & CREG_STAT_RLCOLL) {
  296. printk(KERN_ERR "%s: Late receive collision.\n", dev->name);
  297. qep->net_stats.rx_errors++;
  298. qep->net_stats.collisions++;
  299. }
  300. if (qe_status & CREG_STAT_FCOFLOW) {
  301. qep->net_stats.rx_errors += 256;
  302. qep->net_stats.rx_frame_errors += 256;
  303. }
  304. if (qe_status & CREG_STAT_CECOFLOW) {
  305. qep->net_stats.rx_errors += 256;
  306. qep->net_stats.rx_crc_errors += 256;
  307. }
  308. if (qe_status & CREG_STAT_RXDROP) {
  309. printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name);
  310. qep->net_stats.rx_errors++;
  311. qep->net_stats.rx_dropped++;
  312. qep->net_stats.rx_missed_errors++;
  313. }
  314. if (qe_status & CREG_STAT_RXSMALL) {
  315. printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name);
  316. qep->net_stats.rx_errors++;
  317. qep->net_stats.rx_length_errors++;
  318. }
  319. if (qe_status & CREG_STAT_RXLERR) {
  320. printk(KERN_ERR "%s: Receive late error.\n", dev->name);
  321. qep->net_stats.rx_errors++;
  322. mace_hwbug_workaround = 1;
  323. }
  324. if (qe_status & CREG_STAT_RXPERR) {
  325. printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name);
  326. qep->net_stats.rx_errors++;
  327. qep->net_stats.rx_missed_errors++;
  328. mace_hwbug_workaround = 1;
  329. }
  330. if (qe_status & CREG_STAT_RXSERR) {
  331. printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name);
  332. qep->net_stats.rx_errors++;
  333. qep->net_stats.rx_missed_errors++;
  334. mace_hwbug_workaround = 1;
  335. }
  336. if (mace_hwbug_workaround)
  337. qe_init(qep, 1);
  338. return mace_hwbug_workaround;
  339. }
  340. /* Per-QE receive interrupt service routine. Just like on the happy meal
  341. * we receive directly into skb's with a small packet copy water mark.
  342. */
  343. static void qe_rx(struct sunqe *qep)
  344. {
  345. struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
  346. struct qe_rxd *this;
  347. struct sunqe_buffers *qbufs = qep->buffers;
  348. __u32 qbufs_dvma = qep->buffers_dvma;
  349. int elem = qep->rx_new, drops = 0;
  350. u32 flags;
  351. this = &rxbase[elem];
  352. while (!((flags = this->rx_flags) & RXD_OWN)) {
  353. struct sk_buff *skb;
  354. unsigned char *this_qbuf =
  355. &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
  356. __u32 this_qbuf_dvma = qbufs_dvma +
  357. qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
  358. struct qe_rxd *end_rxd =
  359. &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
  360. int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
  361. /* Check for errors. */
  362. if (len < ETH_ZLEN) {
  363. qep->net_stats.rx_errors++;
  364. qep->net_stats.rx_length_errors++;
  365. qep->net_stats.rx_dropped++;
  366. } else {
  367. skb = dev_alloc_skb(len + 2);
  368. if (skb == NULL) {
  369. drops++;
  370. qep->net_stats.rx_dropped++;
  371. } else {
  372. skb->dev = qep->dev;
  373. skb_reserve(skb, 2);
  374. skb_put(skb, len);
  375. eth_copy_and_sum(skb, (unsigned char *) this_qbuf,
  376. len, 0);
  377. skb->protocol = eth_type_trans(skb, qep->dev);
  378. netif_rx(skb);
  379. qep->dev->last_rx = jiffies;
  380. qep->net_stats.rx_packets++;
  381. qep->net_stats.rx_bytes += len;
  382. }
  383. }
  384. end_rxd->rx_addr = this_qbuf_dvma;
  385. end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
  386. elem = NEXT_RX(elem);
  387. this = &rxbase[elem];
  388. }
  389. qep->rx_new = elem;
  390. if (drops)
  391. printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", qep->dev->name);
  392. }
  393. static void qe_tx_reclaim(struct sunqe *qep);
  394. /* Interrupts for all QE's get filtered out via the QEC master controller,
  395. * so we just run through each qe and check to see who is signaling
  396. * and thus needs to be serviced.
  397. */
  398. static irqreturn_t qec_interrupt(int irq, void *dev_id)
  399. {
  400. struct sunqec *qecp = dev_id;
  401. u32 qec_status;
  402. int channel = 0;
  403. /* Latch the status now. */
  404. qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
  405. while (channel < 4) {
  406. if (qec_status & 0xf) {
  407. struct sunqe *qep = qecp->qes[channel];
  408. u32 qe_status;
  409. qe_status = sbus_readl(qep->qcregs + CREG_STAT);
  410. if (qe_status & CREG_STAT_ERRORS) {
  411. if (qe_is_bolixed(qep, qe_status))
  412. goto next;
  413. }
  414. if (qe_status & CREG_STAT_RXIRQ)
  415. qe_rx(qep);
  416. if (netif_queue_stopped(qep->dev) &&
  417. (qe_status & CREG_STAT_TXIRQ)) {
  418. spin_lock(&qep->lock);
  419. qe_tx_reclaim(qep);
  420. if (TX_BUFFS_AVAIL(qep) > 0) {
  421. /* Wake net queue and return to
  422. * lazy tx reclaim.
  423. */
  424. netif_wake_queue(qep->dev);
  425. sbus_writel(1, qep->qcregs + CREG_TIMASK);
  426. }
  427. spin_unlock(&qep->lock);
  428. }
  429. next:
  430. ;
  431. }
  432. qec_status >>= 4;
  433. channel++;
  434. }
  435. return IRQ_HANDLED;
  436. }
  437. static int qe_open(struct net_device *dev)
  438. {
  439. struct sunqe *qep = (struct sunqe *) dev->priv;
  440. qep->mconfig = (MREGS_MCONFIG_TXENAB |
  441. MREGS_MCONFIG_RXENAB |
  442. MREGS_MCONFIG_MBAENAB);
  443. return qe_init(qep, 0);
  444. }
  445. static int qe_close(struct net_device *dev)
  446. {
  447. struct sunqe *qep = (struct sunqe *) dev->priv;
  448. qe_stop(qep);
  449. return 0;
  450. }
  451. /* Reclaim TX'd frames from the ring. This must always run under
  452. * the IRQ protected qep->lock.
  453. */
  454. static void qe_tx_reclaim(struct sunqe *qep)
  455. {
  456. struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
  457. int elem = qep->tx_old;
  458. while (elem != qep->tx_new) {
  459. u32 flags = txbase[elem].tx_flags;
  460. if (flags & TXD_OWN)
  461. break;
  462. elem = NEXT_TX(elem);
  463. }
  464. qep->tx_old = elem;
  465. }
  466. static void qe_tx_timeout(struct net_device *dev)
  467. {
  468. struct sunqe *qep = (struct sunqe *) dev->priv;
  469. int tx_full;
  470. spin_lock_irq(&qep->lock);
  471. /* Try to reclaim, if that frees up some tx
  472. * entries, we're fine.
  473. */
  474. qe_tx_reclaim(qep);
  475. tx_full = TX_BUFFS_AVAIL(qep) <= 0;
  476. spin_unlock_irq(&qep->lock);
  477. if (! tx_full)
  478. goto out;
  479. printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
  480. qe_init(qep, 1);
  481. out:
  482. netif_wake_queue(dev);
  483. }
  484. /* Get a packet queued to go onto the wire. */
  485. static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
  486. {
  487. struct sunqe *qep = (struct sunqe *) dev->priv;
  488. struct sunqe_buffers *qbufs = qep->buffers;
  489. __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
  490. unsigned char *txbuf;
  491. int len, entry;
  492. spin_lock_irq(&qep->lock);
  493. qe_tx_reclaim(qep);
  494. len = skb->len;
  495. entry = qep->tx_new;
  496. txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
  497. txbuf_dvma = qbufs_dvma +
  498. qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
  499. /* Avoid a race... */
  500. qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
  501. memcpy(txbuf, skb->data, len);
  502. qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
  503. qep->qe_block->qe_txd[entry].tx_flags =
  504. (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
  505. qep->tx_new = NEXT_TX(entry);
  506. /* Get it going. */
  507. dev->trans_start = jiffies;
  508. sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);
  509. qep->net_stats.tx_packets++;
  510. qep->net_stats.tx_bytes += len;
  511. if (TX_BUFFS_AVAIL(qep) <= 0) {
  512. /* Halt the net queue and enable tx interrupts.
  513. * When the tx queue empties the tx irq handler
  514. * will wake up the queue and return us back to
  515. * the lazy tx reclaim scheme.
  516. */
  517. netif_stop_queue(dev);
  518. sbus_writel(0, qep->qcregs + CREG_TIMASK);
  519. }
  520. spin_unlock_irq(&qep->lock);
  521. dev_kfree_skb(skb);
  522. return 0;
  523. }
  524. static struct net_device_stats *qe_get_stats(struct net_device *dev)
  525. {
  526. struct sunqe *qep = (struct sunqe *) dev->priv;
  527. return &qep->net_stats;
  528. }
  529. static void qe_set_multicast(struct net_device *dev)
  530. {
  531. struct sunqe *qep = (struct sunqe *) dev->priv;
  532. struct dev_mc_list *dmi = dev->mc_list;
  533. u8 new_mconfig = qep->mconfig;
  534. char *addrs;
  535. int i;
  536. u32 crc;
  537. /* Lock out others. */
  538. netif_stop_queue(dev);
  539. if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
  540. sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
  541. qep->mregs + MREGS_IACONFIG);
  542. while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
  543. barrier();
  544. for (i = 0; i < 8; i++)
  545. sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
  546. sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
  547. } else if (dev->flags & IFF_PROMISC) {
  548. new_mconfig |= MREGS_MCONFIG_PROMISC;
  549. } else {
  550. u16 hash_table[4];
  551. u8 *hbytes = (unsigned char *) &hash_table[0];
  552. for (i = 0; i < 4; i++)
  553. hash_table[i] = 0;
  554. for (i = 0; i < dev->mc_count; i++) {
  555. addrs = dmi->dmi_addr;
  556. dmi = dmi->next;
  557. if (!(*addrs & 1))
  558. continue;
  559. crc = ether_crc_le(6, addrs);
  560. crc >>= 26;
  561. hash_table[crc >> 4] |= 1 << (crc & 0xf);
  562. }
  563. /* Program the qe with the new filter value. */
  564. sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
  565. qep->mregs + MREGS_IACONFIG);
  566. while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
  567. barrier();
  568. for (i = 0; i < 8; i++) {
  569. u8 tmp = *hbytes++;
  570. sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
  571. }
  572. sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
  573. }
  574. /* Any change of the logical address filter, the physical address,
  575. * or enabling/disabling promiscuous mode causes the MACE to disable
  576. * the receiver. So we must re-enable them here or else the MACE
  577. * refuses to listen to anything on the network. Sheesh, took
  578. * me a day or two to find this bug.
  579. */
  580. qep->mconfig = new_mconfig;
  581. sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
  582. /* Let us get going again. */
  583. netif_wake_queue(dev);
  584. }
  585. /* Ethtool support... */
  586. static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  587. {
  588. struct sunqe *qep = dev->priv;
  589. strcpy(info->driver, "sunqe");
  590. strcpy(info->version, "3.0");
  591. sprintf(info->bus_info, "SBUS:%d",
  592. qep->qe_sdev->slot);
  593. }
  594. static u32 qe_get_link(struct net_device *dev)
  595. {
  596. struct sunqe *qep = dev->priv;
  597. void __iomem *mregs = qep->mregs;
  598. u8 phyconfig;
  599. spin_lock_irq(&qep->lock);
  600. phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
  601. spin_unlock_irq(&qep->lock);
  602. return (phyconfig & MREGS_PHYCONFIG_LSTAT);
  603. }
  604. static const struct ethtool_ops qe_ethtool_ops = {
  605. .get_drvinfo = qe_get_drvinfo,
  606. .get_link = qe_get_link,
  607. };
  608. /* This is only called once at boot time for each card probed. */
  609. static inline void qec_init_once(struct sunqec *qecp, struct sbus_dev *qsdev)
  610. {
  611. u8 bsizes = qecp->qec_bursts;
  612. if (sbus_can_burst64(qsdev) && (bsizes & DMA_BURST64)) {
  613. sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
  614. } else if (bsizes & DMA_BURST32) {
  615. sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
  616. } else {
  617. sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
  618. }
  619. /* Packetsize only used in 100baseT BigMAC configurations,
  620. * set it to zero just to be on the safe side.
  621. */
  622. sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);
  623. /* Set the local memsize register, divided up to one piece per QE channel. */
  624. sbus_writel((qsdev->reg_addrs[1].reg_size >> 2),
  625. qecp->gregs + GLOB_MSIZE);
  626. /* Divide up the local QEC memory amongst the 4 QE receiver and
  627. * transmitter FIFOs. Basically it is (total / 2 / num_channels).
  628. */
  629. sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
  630. qecp->gregs + GLOB_TSIZE);
  631. sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
  632. qecp->gregs + GLOB_RSIZE);
  633. }
  634. static u8 __init qec_get_burst(struct device_node *dp)
  635. {
  636. u8 bsizes, bsizes_more;
  637. /* Find and set the burst sizes for the QEC, since it
  638. * does the actual dma for all 4 channels.
  639. */
  640. bsizes = of_getintprop_default(dp, "burst-sizes", 0xff);
  641. bsizes &= 0xff;
  642. bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff);
  643. if (bsizes_more != 0xff)
  644. bsizes &= bsizes_more;
  645. if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
  646. (bsizes & DMA_BURST32)==0)
  647. bsizes = (DMA_BURST32 - 1);
  648. return bsizes;
  649. }
  650. static struct sunqec * __init get_qec(struct sbus_dev *child_sdev)
  651. {
  652. struct sbus_dev *qec_sdev = child_sdev->parent;
  653. struct sunqec *qecp;
  654. for (qecp = root_qec_dev; qecp; qecp = qecp->next_module) {
  655. if (qecp->qec_sdev == qec_sdev)
  656. break;
  657. }
  658. if (!qecp) {
  659. qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL);
  660. if (qecp) {
  661. u32 ctrl;
  662. qecp->qec_sdev = qec_sdev;
  663. qecp->gregs = sbus_ioremap(&qec_sdev->resource[0], 0,
  664. GLOB_REG_SIZE,
  665. "QEC Global Registers");
  666. if (!qecp->gregs)
  667. goto fail;
  668. /* Make sure the QEC is in MACE mode. */
  669. ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
  670. ctrl &= 0xf0000000;
  671. if (ctrl != GLOB_CTRL_MMODE) {
  672. printk(KERN_ERR "qec: Not in MACE mode!\n");
  673. goto fail;
  674. }
  675. if (qec_global_reset(qecp->gregs))
  676. goto fail;
  677. qecp->qec_bursts = qec_get_burst(qec_sdev->ofdev.node);
  678. qec_init_once(qecp, qec_sdev);
  679. if (request_irq(qec_sdev->irqs[0], &qec_interrupt,
  680. IRQF_SHARED, "qec", (void *) qecp)) {
  681. printk(KERN_ERR "qec: Can't register irq.\n");
  682. goto fail;
  683. }
  684. qecp->next_module = root_qec_dev;
  685. root_qec_dev = qecp;
  686. }
  687. }
  688. return qecp;
  689. fail:
  690. if (qecp->gregs)
  691. sbus_iounmap(qecp->gregs, GLOB_REG_SIZE);
  692. kfree(qecp);
  693. return NULL;
  694. }
  695. static int __init qec_ether_init(struct sbus_dev *sdev)
  696. {
  697. static unsigned version_printed;
  698. struct net_device *dev;
  699. struct sunqe *qe;
  700. struct sunqec *qecp;
  701. int i, res;
  702. if (version_printed++ == 0)
  703. printk(KERN_INFO "%s", version);
  704. dev = alloc_etherdev(sizeof(struct sunqe));
  705. if (!dev)
  706. return -ENOMEM;
  707. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  708. qe = netdev_priv(dev);
  709. i = of_getintprop_default(sdev->ofdev.node, "channel#", -1);
  710. if (i == -1) {
  711. struct sbus_dev *td = sdev->parent->child;
  712. i = 0;
  713. while (td != sdev) {
  714. td = td->next;
  715. i++;
  716. }
  717. }
  718. qe->channel = i;
  719. spin_lock_init(&qe->lock);
  720. res = -ENODEV;
  721. qecp = get_qec(sdev);
  722. if (!qecp)
  723. goto fail;
  724. qecp->qes[qe->channel] = qe;
  725. qe->dev = dev;
  726. qe->parent = qecp;
  727. qe->qe_sdev = sdev;
  728. res = -ENOMEM;
  729. qe->qcregs = sbus_ioremap(&qe->qe_sdev->resource[0], 0,
  730. CREG_REG_SIZE, "QEC Channel Registers");
  731. if (!qe->qcregs) {
  732. printk(KERN_ERR "qe: Cannot map channel registers.\n");
  733. goto fail;
  734. }
  735. qe->mregs = sbus_ioremap(&qe->qe_sdev->resource[1], 0,
  736. MREGS_REG_SIZE, "QE MACE Registers");
  737. if (!qe->mregs) {
  738. printk(KERN_ERR "qe: Cannot map MACE registers.\n");
  739. goto fail;
  740. }
  741. qe->qe_block = sbus_alloc_consistent(qe->qe_sdev,
  742. PAGE_SIZE,
  743. &qe->qblock_dvma);
  744. qe->buffers = sbus_alloc_consistent(qe->qe_sdev,
  745. sizeof(struct sunqe_buffers),
  746. &qe->buffers_dvma);
  747. if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
  748. qe->buffers == NULL || qe->buffers_dvma == 0)
  749. goto fail;
  750. /* Stop this QE. */
  751. qe_stop(qe);
  752. SET_MODULE_OWNER(dev);
  753. SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
  754. dev->open = qe_open;
  755. dev->stop = qe_close;
  756. dev->hard_start_xmit = qe_start_xmit;
  757. dev->get_stats = qe_get_stats;
  758. dev->set_multicast_list = qe_set_multicast;
  759. dev->tx_timeout = qe_tx_timeout;
  760. dev->watchdog_timeo = 5*HZ;
  761. dev->irq = sdev->irqs[0];
  762. dev->dma = 0;
  763. dev->ethtool_ops = &qe_ethtool_ops;
  764. res = register_netdev(dev);
  765. if (res)
  766. goto fail;
  767. dev_set_drvdata(&sdev->ofdev.dev, qe);
  768. printk(KERN_INFO "%s: qe channel[%d] ", dev->name, qe->channel);
  769. for (i = 0; i < 6; i++)
  770. printk ("%2.2x%c",
  771. dev->dev_addr[i],
  772. i == 5 ? ' ': ':');
  773. printk("\n");
  774. return 0;
  775. fail:
  776. if (qe->qcregs)
  777. sbus_iounmap(qe->qcregs, CREG_REG_SIZE);
  778. if (qe->mregs)
  779. sbus_iounmap(qe->mregs, MREGS_REG_SIZE);
  780. if (qe->qe_block)
  781. sbus_free_consistent(qe->qe_sdev,
  782. PAGE_SIZE,
  783. qe->qe_block,
  784. qe->qblock_dvma);
  785. if (qe->buffers)
  786. sbus_free_consistent(qe->qe_sdev,
  787. sizeof(struct sunqe_buffers),
  788. qe->buffers,
  789. qe->buffers_dvma);
  790. free_netdev(dev);
  791. return res;
  792. }
  793. static int __devinit qec_sbus_probe(struct of_device *dev, const struct of_device_id *match)
  794. {
  795. struct sbus_dev *sdev = to_sbus_device(&dev->dev);
  796. return qec_ether_init(sdev);
  797. }
  798. static int __devexit qec_sbus_remove(struct of_device *dev)
  799. {
  800. struct sunqe *qp = dev_get_drvdata(&dev->dev);
  801. struct net_device *net_dev = qp->dev;
  802. unregister_netdev(net_dev);
  803. sbus_iounmap(qp->qcregs, CREG_REG_SIZE);
  804. sbus_iounmap(qp->mregs, MREGS_REG_SIZE);
  805. sbus_free_consistent(qp->qe_sdev,
  806. PAGE_SIZE,
  807. qp->qe_block,
  808. qp->qblock_dvma);
  809. sbus_free_consistent(qp->qe_sdev,
  810. sizeof(struct sunqe_buffers),
  811. qp->buffers,
  812. qp->buffers_dvma);
  813. free_netdev(net_dev);
  814. dev_set_drvdata(&dev->dev, NULL);
  815. return 0;
  816. }
  817. static struct of_device_id qec_sbus_match[] = {
  818. {
  819. .name = "qe",
  820. },
  821. {},
  822. };
  823. MODULE_DEVICE_TABLE(of, qec_sbus_match);
  824. static struct of_platform_driver qec_sbus_driver = {
  825. .name = "qec",
  826. .match_table = qec_sbus_match,
  827. .probe = qec_sbus_probe,
  828. .remove = __devexit_p(qec_sbus_remove),
  829. };
  830. static int __init qec_init(void)
  831. {
  832. return of_register_driver(&qec_sbus_driver, &sbus_bus_type);
  833. }
  834. static void __exit qec_exit(void)
  835. {
  836. of_unregister_driver(&qec_sbus_driver);
  837. while (root_qec_dev) {
  838. struct sunqec *next = root_qec_dev->next_module;
  839. free_irq(root_qec_dev->qec_sdev->irqs[0],
  840. (void *) root_qec_dev);
  841. sbus_iounmap(root_qec_dev->gregs, GLOB_REG_SIZE);
  842. kfree(root_qec_dev);
  843. root_qec_dev = next;
  844. }
  845. }
  846. module_init(qec_init);
  847. module_exit(qec_exit);