sunhme.h 27 KB

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  1. /* $Id: sunhme.h,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  2. * sunhme.h: Definitions for Sparc HME/BigMac 10/100baseT ethernet driver.
  3. * Also known as the "Happy Meal".
  4. *
  5. * Copyright (C) 1996, 1999 David S. Miller (davem@redhat.com)
  6. */
  7. #ifndef _SUNHME_H
  8. #define _SUNHME_H
  9. #include <linux/pci.h>
  10. /* Happy Meal global registers. */
  11. #define GREG_SWRESET 0x000UL /* Software Reset */
  12. #define GREG_CFG 0x004UL /* Config Register */
  13. #define GREG_STAT 0x108UL /* Status */
  14. #define GREG_IMASK 0x10cUL /* Interrupt Mask */
  15. #define GREG_REG_SIZE 0x110UL
  16. /* Global reset register. */
  17. #define GREG_RESET_ETX 0x01
  18. #define GREG_RESET_ERX 0x02
  19. #define GREG_RESET_ALL 0x03
  20. /* Global config register. */
  21. #define GREG_CFG_BURSTMSK 0x03
  22. #define GREG_CFG_BURST16 0x00
  23. #define GREG_CFG_BURST32 0x01
  24. #define GREG_CFG_BURST64 0x02
  25. #define GREG_CFG_64BIT 0x04
  26. #define GREG_CFG_PARITY 0x08
  27. #define GREG_CFG_RESV 0x10
  28. /* Global status register. */
  29. #define GREG_STAT_GOTFRAME 0x00000001 /* Received a frame */
  30. #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
  31. #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
  32. #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
  33. #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
  34. #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
  35. #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
  36. #define GREG_STAT_STSTERR 0x00000080 /* Test error in XIF for SQE */
  37. #define GREG_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
  38. #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
  39. #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
  40. #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
  41. #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
  42. #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
  43. #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
  44. #define GREG_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
  45. #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
  46. #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
  47. #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
  48. #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
  49. #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
  50. #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
  51. #define GREG_STAT_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
  52. #define GREG_STAT_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
  53. #define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
  54. #define GREG_STAT_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
  55. #define GREG_STAT_TXEACK 0x04000000 /* Error during transmit dma */
  56. #define GREG_STAT_TXLERR 0x08000000 /* Late error during transmit dma */
  57. #define GREG_STAT_TXPERR 0x10000000 /* Parity error during transmit dma */
  58. #define GREG_STAT_TXTERR 0x20000000 /* Tag error during transmit dma */
  59. #define GREG_STAT_SLVERR 0x40000000 /* PIO access got an error */
  60. #define GREG_STAT_SLVPERR 0x80000000 /* PIO access got a parity error */
  61. /* All interesting error conditions. */
  62. #define GREG_STAT_ERRORS 0xfc7efefc
  63. /* Global interrupt mask register. */
  64. #define GREG_IMASK_GOTFRAME 0x00000001 /* Received a frame */
  65. #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
  66. #define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
  67. #define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
  68. #define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
  69. #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
  70. #define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
  71. #define GREG_IMASK_STSTERR 0x00000080 /* Test error in XIF for SQE */
  72. #define GREG_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
  73. #define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
  74. #define GREG_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
  75. #define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
  76. #define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
  77. #define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
  78. #define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
  79. #define GREG_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
  80. #define GREG_IMASK_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
  81. #define GREG_IMASK_NORXD 0x00020000 /* No more receive descriptors */
  82. #define GREG_IMASK_RXERR 0x00040000 /* Error during receive dma */
  83. #define GREG_IMASK_RXLATERR 0x00080000 /* Late error during receive dma */
  84. #define GREG_IMASK_RXPERR 0x00100000 /* Parity error during receive dma */
  85. #define GREG_IMASK_RXTERR 0x00200000 /* Tag error during receive dma */
  86. #define GREG_IMASK_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
  87. #define GREG_IMASK_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
  88. #define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
  89. #define GREG_IMASK_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
  90. #define GREG_IMASK_TXEACK 0x04000000 /* Error during transmit dma */
  91. #define GREG_IMASK_TXLERR 0x08000000 /* Late error during transmit dma */
  92. #define GREG_IMASK_TXPERR 0x10000000 /* Parity error during transmit dma */
  93. #define GREG_IMASK_TXTERR 0x20000000 /* Tag error during transmit dma */
  94. #define GREG_IMASK_SLVERR 0x40000000 /* PIO access got an error */
  95. #define GREG_IMASK_SLVPERR 0x80000000 /* PIO access got a parity error */
  96. /* Happy Meal external transmitter registers. */
  97. #define ETX_PENDING 0x00UL /* Transmit pending/wakeup register */
  98. #define ETX_CFG 0x04UL /* Transmit config register */
  99. #define ETX_RING 0x08UL /* Transmit ring pointer */
  100. #define ETX_BBASE 0x0cUL /* Transmit buffer base */
  101. #define ETX_BDISP 0x10UL /* Transmit buffer displacement */
  102. #define ETX_FIFOWPTR 0x14UL /* FIFO write ptr */
  103. #define ETX_FIFOSWPTR 0x18UL /* FIFO write ptr (shadow register) */
  104. #define ETX_FIFORPTR 0x1cUL /* FIFO read ptr */
  105. #define ETX_FIFOSRPTR 0x20UL /* FIFO read ptr (shadow register) */
  106. #define ETX_FIFOPCNT 0x24UL /* FIFO packet counter */
  107. #define ETX_SMACHINE 0x28UL /* Transmitter state machine */
  108. #define ETX_RSIZE 0x2cUL /* Ring descriptor size */
  109. #define ETX_BPTR 0x30UL /* Transmit data buffer ptr */
  110. #define ETX_REG_SIZE 0x34UL
  111. /* ETX transmit pending register. */
  112. #define ETX_TP_DMAWAKEUP 0x00000001 /* Restart transmit dma */
  113. /* ETX config register. */
  114. #define ETX_CFG_DMAENABLE 0x00000001 /* Enable transmit dma */
  115. #define ETX_CFG_FIFOTHRESH 0x000003fe /* Transmit FIFO threshold */
  116. #define ETX_CFG_IRQDAFTER 0x00000400 /* Interrupt after TX-FIFO drained */
  117. #define ETX_CFG_IRQDBEFORE 0x00000000 /* Interrupt before TX-FIFO drained */
  118. #define ETX_RSIZE_SHIFT 4
  119. /* Happy Meal external receiver registers. */
  120. #define ERX_CFG 0x00UL /* Receiver config register */
  121. #define ERX_RING 0x04UL /* Receiver ring ptr */
  122. #define ERX_BPTR 0x08UL /* Receiver buffer ptr */
  123. #define ERX_FIFOWPTR 0x0cUL /* FIFO write ptr */
  124. #define ERX_FIFOSWPTR 0x10UL /* FIFO write ptr (shadow register) */
  125. #define ERX_FIFORPTR 0x14UL /* FIFO read ptr */
  126. #define ERX_FIFOSRPTR 0x18UL /* FIFO read ptr (shadow register) */
  127. #define ERX_SMACHINE 0x1cUL /* Receiver state machine */
  128. #define ERX_REG_SIZE 0x20UL
  129. /* ERX config register. */
  130. #define ERX_CFG_DMAENABLE 0x00000001 /* Enable receive DMA */
  131. #define ERX_CFG_RESV1 0x00000006 /* Unused... */
  132. #define ERX_CFG_BYTEOFFSET 0x00000038 /* Receive first byte offset */
  133. #define ERX_CFG_RESV2 0x000001c0 /* Unused... */
  134. #define ERX_CFG_SIZE32 0x00000000 /* Receive ring size == 32 */
  135. #define ERX_CFG_SIZE64 0x00000200 /* Receive ring size == 64 */
  136. #define ERX_CFG_SIZE128 0x00000400 /* Receive ring size == 128 */
  137. #define ERX_CFG_SIZE256 0x00000600 /* Receive ring size == 256 */
  138. #define ERX_CFG_RESV3 0x0000f800 /* Unused... */
  139. #define ERX_CFG_CSUMSTART 0x007f0000 /* Offset of checksum start,
  140. * in halfwords. */
  141. /* I'd like a Big Mac, small fries, small coke, and SparcLinux please. */
  142. #define BMAC_XIFCFG 0x0000UL /* XIF config register */
  143. /* 0x4-->0x204, reserved */
  144. #define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */
  145. #define BMAC_TXCFG 0x20cUL /* Transmitter config register */
  146. #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
  147. #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
  148. #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
  149. #define BMAC_STIME 0x21cUL /* Transmit slot time */
  150. #define BMAC_PLEN 0x220UL /* Size of transmit preamble */
  151. #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
  152. #define BMAC_TXSDELIM 0x228UL /* Transmit delimiter */
  153. #define BMAC_JSIZE 0x22cUL /* Jam size */
  154. #define BMAC_TXMAX 0x230UL /* Transmit max pkt size */
  155. #define BMAC_TXMIN 0x234UL /* Transmit min pkt size */
  156. #define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */
  157. #define BMAC_DTCTR 0x23cUL /* Transmit defer timer */
  158. #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
  159. #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
  160. #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
  161. #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
  162. #define BMAC_RSEED 0x250UL /* Transmit random number seed */
  163. #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */
  164. /* 0x258-->0x304, reserved */
  165. #define BMAC_RXSWRESET 0x308UL /* Receiver software reset */
  166. #define BMAC_RXCFG 0x30cUL /* Receiver config register */
  167. #define BMAC_RXMAX 0x310UL /* Receive max pkt size */
  168. #define BMAC_RXMIN 0x314UL /* Receive min pkt size */
  169. #define BMAC_MACADDR2 0x318UL /* Ether address register 2 */
  170. #define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */
  171. #define BMAC_MACADDR0 0x320UL /* Ether address register 0 */
  172. #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
  173. #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
  174. #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
  175. #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
  176. #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */
  177. #define BMAC_RXCVALID 0x338UL /* Receiver code violation */
  178. /* 0x33c, reserved */
  179. #define BMAC_HTABLE3 0x340UL /* Hash table 3 */
  180. #define BMAC_HTABLE2 0x344UL /* Hash table 2 */
  181. #define BMAC_HTABLE1 0x348UL /* Hash table 1 */
  182. #define BMAC_HTABLE0 0x34cUL /* Hash table 0 */
  183. #define BMAC_AFILTER2 0x350UL /* Address filter 2 */
  184. #define BMAC_AFILTER1 0x354UL /* Address filter 1 */
  185. #define BMAC_AFILTER0 0x358UL /* Address filter 0 */
  186. #define BMAC_AFMASK 0x35cUL /* Address filter mask */
  187. #define BMAC_REG_SIZE 0x360UL
  188. /* BigMac XIF config register. */
  189. #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
  190. #define BIGMAC_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */
  191. #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
  192. #define BIGMAC_XCFG_MIIDISAB 0x00000008 /* MII receive buffer disable */
  193. #define BIGMAC_XCFG_SQENABLE 0x00000010 /* SQE test enable */
  194. #define BIGMAC_XCFG_SQETWIN 0x000003e0 /* SQE time window */
  195. #define BIGMAC_XCFG_LANCE 0x00000010 /* Lance mode enable */
  196. #define BIGMAC_XCFG_LIPG0 0x000003e0 /* Lance mode IPG0 */
  197. /* BigMac transmit config register. */
  198. #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
  199. #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
  200. #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
  201. #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
  202. #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
  203. #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
  204. #define BIGMAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
  205. /* BigMac receive config register. */
  206. #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
  207. #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
  208. #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
  209. #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
  210. #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
  211. #define BIGMAC_RXCFG_REJME 0x00000200 /* Reject packets addressed to me */
  212. #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
  213. #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
  214. #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
  215. /* These are the "Management Interface" (ie. MIF) registers of the transceiver. */
  216. #define TCVR_BBCLOCK 0x00UL /* Bit bang clock register */
  217. #define TCVR_BBDATA 0x04UL /* Bit bang data register */
  218. #define TCVR_BBOENAB 0x08UL /* Bit bang output enable */
  219. #define TCVR_FRAME 0x0cUL /* Frame control/data register */
  220. #define TCVR_CFG 0x10UL /* MIF config register */
  221. #define TCVR_IMASK 0x14UL /* MIF interrupt mask */
  222. #define TCVR_STATUS 0x18UL /* MIF status */
  223. #define TCVR_SMACHINE 0x1cUL /* MIF state machine */
  224. #define TCVR_REG_SIZE 0x20UL
  225. /* Frame commands. */
  226. #define FRAME_WRITE 0x50020000
  227. #define FRAME_READ 0x60020000
  228. /* Transceiver config register */
  229. #define TCV_CFG_PSELECT 0x00000001 /* Select PHY */
  230. #define TCV_CFG_PENABLE 0x00000002 /* Enable MIF polling */
  231. #define TCV_CFG_BENABLE 0x00000004 /* Enable the "bit banger" oh baby */
  232. #define TCV_CFG_PREGADDR 0x000000f8 /* Address of poll register */
  233. #define TCV_CFG_MDIO0 0x00000100 /* MDIO zero, data/attached */
  234. #define TCV_CFG_MDIO1 0x00000200 /* MDIO one, data/attached */
  235. #define TCV_CFG_PDADDR 0x00007c00 /* Device PHY address polling */
  236. /* Here are some PHY addresses. */
  237. #define TCV_PADDR_ETX 0 /* Internal transceiver */
  238. #define TCV_PADDR_ITX 1 /* External transceiver */
  239. /* Transceiver status register */
  240. #define TCV_STAT_BASIC 0xffff0000 /* The "basic" part */
  241. #define TCV_STAT_NORMAL 0x0000ffff /* The "non-basic" part */
  242. /* Inside the Happy Meal transceiver is the physical layer, they use an
  243. * implementations for National Semiconductor, part number DP83840VCE.
  244. * You can retrieve the data sheets and programming docs for this beast
  245. * from http://www.national.com/
  246. *
  247. * The DP83840 is capable of both 10 and 100Mbps ethernet, in both
  248. * half and full duplex mode. It also supports auto negotiation.
  249. *
  250. * But.... THIS THING IS A PAIN IN THE ASS TO PROGRAM!
  251. * Debugging eeprom burnt code is more fun than programming this chip!
  252. */
  253. /* Generic MII registers defined in linux/mii.h, these below
  254. * are DP83840 specific.
  255. */
  256. #define DP83840_CSCONFIG 0x17 /* CS configuration */
  257. /* The Carrier Sense config register. */
  258. #define CSCONFIG_RESV1 0x0001 /* Unused... */
  259. #define CSCONFIG_LED4 0x0002 /* Pin for full-dplx LED4 */
  260. #define CSCONFIG_LED1 0x0004 /* Pin for conn-status LED1 */
  261. #define CSCONFIG_RESV2 0x0008 /* Unused... */
  262. #define CSCONFIG_TCVDISAB 0x0010 /* Turns off the transceiver */
  263. #define CSCONFIG_DFBYPASS 0x0020 /* Bypass disconnect function */
  264. #define CSCONFIG_GLFORCE 0x0040 /* Good link force for 100mbps */
  265. #define CSCONFIG_CLKTRISTATE 0x0080 /* Tristate 25m clock */
  266. #define CSCONFIG_RESV3 0x0700 /* Unused... */
  267. #define CSCONFIG_ENCODE 0x0800 /* 1=MLT-3, 0=binary */
  268. #define CSCONFIG_RENABLE 0x1000 /* Repeater mode enable */
  269. #define CSCONFIG_TCDISABLE 0x2000 /* Disable timeout counter */
  270. #define CSCONFIG_RESV4 0x4000 /* Unused... */
  271. #define CSCONFIG_NDISABLE 0x8000 /* Disable NRZI */
  272. /* Happy Meal descriptor rings and such.
  273. * All descriptor rings must be aligned on a 2K boundary.
  274. * All receive buffers must be 64 byte aligned.
  275. * Always write the address first before setting the ownership
  276. * bits to avoid races with the hardware scanning the ring.
  277. */
  278. struct happy_meal_rxd {
  279. u32 rx_flags;
  280. u32 rx_addr;
  281. };
  282. #define RXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
  283. #define RXFLAG_OVERFLOW 0x40000000 /* 1 = buffer overflow */
  284. #define RXFLAG_SIZE 0x3fff0000 /* Size of the buffer */
  285. #define RXFLAG_CSUM 0x0000ffff /* HW computed checksum */
  286. struct happy_meal_txd {
  287. u32 tx_flags;
  288. u32 tx_addr;
  289. };
  290. #define TXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
  291. #define TXFLAG_SOP 0x40000000 /* 1 = start of packet */
  292. #define TXFLAG_EOP 0x20000000 /* 1 = end of packet */
  293. #define TXFLAG_CSENABLE 0x10000000 /* 1 = enable hw-checksums */
  294. #define TXFLAG_CSLOCATION 0x0ff00000 /* Where to stick the csum */
  295. #define TXFLAG_CSBUFBEGIN 0x000fc000 /* Where to begin checksum */
  296. #define TXFLAG_SIZE 0x00003fff /* Size of the packet */
  297. #define TX_RING_SIZE 32 /* Must be >16 and <255, multiple of 16 */
  298. #define RX_RING_SIZE 32 /* see ERX_CFG_SIZE* for possible values */
  299. #if (TX_RING_SIZE < 16 || TX_RING_SIZE > 256 || (TX_RING_SIZE % 16) != 0)
  300. #error TX_RING_SIZE holds illegal value
  301. #endif
  302. #define TX_RING_MAXSIZE 256
  303. #define RX_RING_MAXSIZE 256
  304. /* We use a 14 byte offset for checksum computation. */
  305. #if (RX_RING_SIZE == 32)
  306. #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|((14/2)<<16))
  307. #else
  308. #if (RX_RING_SIZE == 64)
  309. #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE64|((14/2)<<16))
  310. #else
  311. #if (RX_RING_SIZE == 128)
  312. #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE128|((14/2)<<16))
  313. #else
  314. #if (RX_RING_SIZE == 256)
  315. #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE256|((14/2)<<16))
  316. #else
  317. #error RX_RING_SIZE holds illegal value
  318. #endif
  319. #endif
  320. #endif
  321. #endif
  322. #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
  323. #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
  324. #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
  325. #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
  326. #define TX_BUFFS_AVAIL(hp) \
  327. (((hp)->tx_old <= (hp)->tx_new) ? \
  328. (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \
  329. (hp)->tx_old - (hp)->tx_new - 1)
  330. #define RX_OFFSET 2
  331. #define RX_BUF_ALLOC_SIZE (1546 + RX_OFFSET + 64)
  332. #define RX_COPY_THRESHOLD 256
  333. struct hmeal_init_block {
  334. struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];
  335. struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];
  336. };
  337. #define hblock_offset(mem, elem) \
  338. ((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
  339. /* Now software state stuff. */
  340. enum happy_transceiver {
  341. external = 0,
  342. internal = 1,
  343. none = 2,
  344. };
  345. /* Timer state engine. */
  346. enum happy_timer_state {
  347. arbwait = 0, /* Waiting for auto negotiation to complete. */
  348. lupwait = 1, /* Auto-neg complete, awaiting link-up status. */
  349. ltrywait = 2, /* Forcing try of all modes, from fastest to slowest. */
  350. asleep = 3, /* Time inactive. */
  351. };
  352. struct quattro;
  353. /* Happy happy, joy joy! */
  354. struct happy_meal {
  355. void __iomem *gregs; /* Happy meal global registers */
  356. struct hmeal_init_block *happy_block; /* RX and TX descriptors (CPU addr) */
  357. #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
  358. u32 (*read_desc32)(u32 *);
  359. void (*write_txd)(struct happy_meal_txd *, u32, u32);
  360. void (*write_rxd)(struct happy_meal_rxd *, u32, u32);
  361. u32 (*dma_map)(void *, void *, long, int);
  362. void (*dma_unmap)(void *, u32, long, int);
  363. void (*dma_sync_for_cpu)(void *, u32, long, int);
  364. void (*dma_sync_for_device)(void *, u32, long, int);
  365. #endif
  366. /* This is either a sbus_dev or a pci_dev. */
  367. void *happy_dev;
  368. spinlock_t happy_lock;
  369. struct sk_buff *rx_skbs[RX_RING_SIZE];
  370. struct sk_buff *tx_skbs[TX_RING_SIZE];
  371. int rx_new, tx_new, rx_old, tx_old;
  372. struct net_device_stats net_stats; /* Statistical counters */
  373. #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
  374. u32 (*read32)(void __iomem *);
  375. void (*write32)(void __iomem *, u32);
  376. #endif
  377. void __iomem *etxregs; /* External transmitter regs */
  378. void __iomem *erxregs; /* External receiver regs */
  379. void __iomem *bigmacregs; /* BIGMAC core regs */
  380. void __iomem *tcvregs; /* MIF transceiver regs */
  381. dma_addr_t hblock_dvma; /* DVMA visible address happy block */
  382. unsigned int happy_flags; /* Driver state flags */
  383. enum happy_transceiver tcvr_type; /* Kind of transceiver in use */
  384. unsigned int happy_bursts; /* Get your mind out of the gutter */
  385. unsigned int paddr; /* PHY address for transceiver */
  386. unsigned short hm_revision; /* Happy meal revision */
  387. unsigned short sw_bmcr; /* SW copy of BMCR */
  388. unsigned short sw_bmsr; /* SW copy of BMSR */
  389. unsigned short sw_physid1; /* SW copy of PHYSID1 */
  390. unsigned short sw_physid2; /* SW copy of PHYSID2 */
  391. unsigned short sw_advertise; /* SW copy of ADVERTISE */
  392. unsigned short sw_lpa; /* SW copy of LPA */
  393. unsigned short sw_expansion; /* SW copy of EXPANSION */
  394. unsigned short sw_csconfig; /* SW copy of CSCONFIG */
  395. unsigned int auto_speed; /* Auto-nego link speed */
  396. unsigned int forced_speed; /* Force mode link speed */
  397. unsigned int poll_data; /* MIF poll data */
  398. unsigned int poll_flag; /* MIF poll flag */
  399. unsigned int linkcheck; /* Have we checked the link yet? */
  400. unsigned int lnkup; /* Is the link up as far as we know? */
  401. unsigned int lnkdown; /* Trying to force the link down? */
  402. unsigned int lnkcnt; /* Counter for link-up attempts. */
  403. struct timer_list happy_timer; /* To watch the link when coming up. */
  404. enum happy_timer_state timer_state; /* State of the auto-neg timer. */
  405. unsigned int timer_ticks; /* Number of clicks at each state. */
  406. struct net_device *dev; /* Backpointer */
  407. struct quattro *qfe_parent; /* For Quattro cards */
  408. int qfe_ent; /* Which instance on quattro */
  409. };
  410. /* Here are the happy flags. */
  411. #define HFLAG_POLL 0x00000001 /* We are doing MIF polling */
  412. #define HFLAG_FENABLE 0x00000002 /* The MII frame is enabled */
  413. #define HFLAG_LANCE 0x00000004 /* We are using lance-mode */
  414. #define HFLAG_RXENABLE 0x00000008 /* Receiver is enabled */
  415. #define HFLAG_AUTO 0x00000010 /* Using auto-negotiation, 0 = force */
  416. #define HFLAG_FULL 0x00000020 /* Full duplex enable */
  417. #define HFLAG_MACFULL 0x00000040 /* Using full duplex in the MAC */
  418. #define HFLAG_POLLENABLE 0x00000080 /* Actually try MIF polling */
  419. #define HFLAG_RXCV 0x00000100 /* XXX RXCV ENABLE */
  420. #define HFLAG_INIT 0x00000200 /* Init called at least once */
  421. #define HFLAG_LINKUP 0x00000400 /* 1 = Link is up */
  422. #define HFLAG_PCI 0x00000800 /* PCI based Happy Meal */
  423. #define HFLAG_QUATTRO 0x00001000 /* On QFE/Quattro card */
  424. #define HFLAG_20_21 (HFLAG_POLLENABLE | HFLAG_FENABLE)
  425. #define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)
  426. /* Support for QFE/Quattro cards. */
  427. struct quattro {
  428. struct net_device *happy_meals[4];
  429. /* This is either a sbus_dev or a pci_dev. */
  430. void *quattro_dev;
  431. struct quattro *next;
  432. /* PROM ranges, if any. */
  433. #ifdef CONFIG_SBUS
  434. struct linux_prom_ranges ranges[8];
  435. #endif
  436. int nranges;
  437. };
  438. /* We use this to acquire receive skb's that we can DMA directly into. */
  439. #define ALIGNED_RX_SKB_ADDR(addr) \
  440. ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
  441. #define happy_meal_alloc_skb(__length, __gfp_flags) \
  442. ({ struct sk_buff *__skb; \
  443. __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
  444. if(__skb) { \
  445. int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
  446. if(__offset) \
  447. skb_reserve(__skb, __offset); \
  448. } \
  449. __skb; \
  450. })
  451. #endif /* !(_SUNHME_H) */