sunhme.c 92 KB

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  1. /* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
  2. * auto carrier detecting ethernet driver. Also known as the
  3. * "Happy Meal Ethernet" found on SunSwift SBUS cards.
  4. *
  5. * Copyright (C) 1996, 1998, 1999, 2002, 2003,
  6. 2006 David S. Miller (davem@davemloft.net)
  7. *
  8. * Changes :
  9. * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
  10. * - port to non-sparc architectures. Tested only on x86 and
  11. * only currently works with QFE PCI cards.
  12. * - ability to specify the MAC address at module load time by passing this
  13. * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
  14. */
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/types.h>
  18. #include <linux/fcntl.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ioport.h>
  21. #include <linux/in.h>
  22. #include <linux/slab.h>
  23. #include <linux/string.h>
  24. #include <linux/delay.h>
  25. #include <linux/init.h>
  26. #include <linux/ethtool.h>
  27. #include <linux/mii.h>
  28. #include <linux/crc32.h>
  29. #include <linux/random.h>
  30. #include <linux/errno.h>
  31. #include <linux/netdevice.h>
  32. #include <linux/etherdevice.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/mm.h>
  35. #include <linux/bitops.h>
  36. #include <asm/system.h>
  37. #include <asm/io.h>
  38. #include <asm/dma.h>
  39. #include <asm/byteorder.h>
  40. #ifdef CONFIG_SPARC
  41. #include <asm/idprom.h>
  42. #include <asm/sbus.h>
  43. #include <asm/openprom.h>
  44. #include <asm/oplib.h>
  45. #include <asm/prom.h>
  46. #include <asm/auxio.h>
  47. #endif
  48. #include <asm/uaccess.h>
  49. #include <asm/pgtable.h>
  50. #include <asm/irq.h>
  51. #ifdef CONFIG_PCI
  52. #include <linux/pci.h>
  53. #ifdef CONFIG_SPARC
  54. #include <asm/pbm.h>
  55. #endif
  56. #endif
  57. #include "sunhme.h"
  58. #define DRV_NAME "sunhme"
  59. #define DRV_VERSION "3.00"
  60. #define DRV_RELDATE "June 23, 2006"
  61. #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
  62. static char version[] =
  63. DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
  64. MODULE_VERSION(DRV_VERSION);
  65. MODULE_AUTHOR(DRV_AUTHOR);
  66. MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
  67. MODULE_LICENSE("GPL");
  68. static int macaddr[6];
  69. /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
  70. module_param_array(macaddr, int, NULL, 0);
  71. MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
  72. #ifdef CONFIG_SBUS
  73. static struct quattro *qfe_sbus_list;
  74. #endif
  75. #ifdef CONFIG_PCI
  76. static struct quattro *qfe_pci_list;
  77. #endif
  78. #undef HMEDEBUG
  79. #undef SXDEBUG
  80. #undef RXDEBUG
  81. #undef TXDEBUG
  82. #undef TXLOGGING
  83. #ifdef TXLOGGING
  84. struct hme_tx_logent {
  85. unsigned int tstamp;
  86. int tx_new, tx_old;
  87. unsigned int action;
  88. #define TXLOG_ACTION_IRQ 0x01
  89. #define TXLOG_ACTION_TXMIT 0x02
  90. #define TXLOG_ACTION_TBUSY 0x04
  91. #define TXLOG_ACTION_NBUFS 0x08
  92. unsigned int status;
  93. };
  94. #define TX_LOG_LEN 128
  95. static struct hme_tx_logent tx_log[TX_LOG_LEN];
  96. static int txlog_cur_entry;
  97. static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
  98. {
  99. struct hme_tx_logent *tlp;
  100. unsigned long flags;
  101. save_and_cli(flags);
  102. tlp = &tx_log[txlog_cur_entry];
  103. tlp->tstamp = (unsigned int)jiffies;
  104. tlp->tx_new = hp->tx_new;
  105. tlp->tx_old = hp->tx_old;
  106. tlp->action = a;
  107. tlp->status = s;
  108. txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
  109. restore_flags(flags);
  110. }
  111. static __inline__ void tx_dump_log(void)
  112. {
  113. int i, this;
  114. this = txlog_cur_entry;
  115. for (i = 0; i < TX_LOG_LEN; i++) {
  116. printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
  117. tx_log[this].tstamp,
  118. tx_log[this].tx_new, tx_log[this].tx_old,
  119. tx_log[this].action, tx_log[this].status);
  120. this = (this + 1) & (TX_LOG_LEN - 1);
  121. }
  122. }
  123. static __inline__ void tx_dump_ring(struct happy_meal *hp)
  124. {
  125. struct hmeal_init_block *hb = hp->happy_block;
  126. struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
  127. int i;
  128. for (i = 0; i < TX_RING_SIZE; i+=4) {
  129. printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
  130. i, i + 4,
  131. le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
  132. le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
  133. le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
  134. le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
  135. }
  136. }
  137. #else
  138. #define tx_add_log(hp, a, s) do { } while(0)
  139. #define tx_dump_log() do { } while(0)
  140. #define tx_dump_ring(hp) do { } while(0)
  141. #endif
  142. #ifdef HMEDEBUG
  143. #define HMD(x) printk x
  144. #else
  145. #define HMD(x)
  146. #endif
  147. /* #define AUTO_SWITCH_DEBUG */
  148. #ifdef AUTO_SWITCH_DEBUG
  149. #define ASD(x) printk x
  150. #else
  151. #define ASD(x)
  152. #endif
  153. #define DEFAULT_IPG0 16 /* For lance-mode only */
  154. #define DEFAULT_IPG1 8 /* For all modes */
  155. #define DEFAULT_IPG2 4 /* For all modes */
  156. #define DEFAULT_JAMSIZE 4 /* Toe jam */
  157. /* NOTE: In the descriptor writes one _must_ write the address
  158. * member _first_. The card must not be allowed to see
  159. * the updated descriptor flags until the address is
  160. * correct. I've added a write memory barrier between
  161. * the two stores so that I can sleep well at night... -DaveM
  162. */
  163. #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
  164. static void sbus_hme_write32(void __iomem *reg, u32 val)
  165. {
  166. sbus_writel(val, reg);
  167. }
  168. static u32 sbus_hme_read32(void __iomem *reg)
  169. {
  170. return sbus_readl(reg);
  171. }
  172. static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
  173. {
  174. rxd->rx_addr = addr;
  175. wmb();
  176. rxd->rx_flags = flags;
  177. }
  178. static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
  179. {
  180. txd->tx_addr = addr;
  181. wmb();
  182. txd->tx_flags = flags;
  183. }
  184. static u32 sbus_hme_read_desc32(u32 *p)
  185. {
  186. return *p;
  187. }
  188. static void pci_hme_write32(void __iomem *reg, u32 val)
  189. {
  190. writel(val, reg);
  191. }
  192. static u32 pci_hme_read32(void __iomem *reg)
  193. {
  194. return readl(reg);
  195. }
  196. static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
  197. {
  198. rxd->rx_addr = cpu_to_le32(addr);
  199. wmb();
  200. rxd->rx_flags = cpu_to_le32(flags);
  201. }
  202. static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
  203. {
  204. txd->tx_addr = cpu_to_le32(addr);
  205. wmb();
  206. txd->tx_flags = cpu_to_le32(flags);
  207. }
  208. static u32 pci_hme_read_desc32(u32 *p)
  209. {
  210. return cpu_to_le32p(p);
  211. }
  212. #define hme_write32(__hp, __reg, __val) \
  213. ((__hp)->write32((__reg), (__val)))
  214. #define hme_read32(__hp, __reg) \
  215. ((__hp)->read32(__reg))
  216. #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
  217. ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
  218. #define hme_write_txd(__hp, __txd, __flags, __addr) \
  219. ((__hp)->write_txd((__txd), (__flags), (__addr)))
  220. #define hme_read_desc32(__hp, __p) \
  221. ((__hp)->read_desc32(__p))
  222. #define hme_dma_map(__hp, __ptr, __size, __dir) \
  223. ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
  224. #define hme_dma_unmap(__hp, __addr, __size, __dir) \
  225. ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
  226. #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
  227. ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
  228. #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
  229. ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
  230. #else
  231. #ifdef CONFIG_SBUS
  232. /* SBUS only compilation */
  233. #define hme_write32(__hp, __reg, __val) \
  234. sbus_writel((__val), (__reg))
  235. #define hme_read32(__hp, __reg) \
  236. sbus_readl(__reg)
  237. #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
  238. do { (__rxd)->rx_addr = (__addr); \
  239. wmb(); \
  240. (__rxd)->rx_flags = (__flags); \
  241. } while(0)
  242. #define hme_write_txd(__hp, __txd, __flags, __addr) \
  243. do { (__txd)->tx_addr = (__addr); \
  244. wmb(); \
  245. (__txd)->tx_flags = (__flags); \
  246. } while(0)
  247. #define hme_read_desc32(__hp, __p) (*(__p))
  248. #define hme_dma_map(__hp, __ptr, __size, __dir) \
  249. sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
  250. #define hme_dma_unmap(__hp, __addr, __size, __dir) \
  251. sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
  252. #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
  253. sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
  254. #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
  255. sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
  256. #else
  257. /* PCI only compilation */
  258. #define hme_write32(__hp, __reg, __val) \
  259. writel((__val), (__reg))
  260. #define hme_read32(__hp, __reg) \
  261. readl(__reg)
  262. #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
  263. do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
  264. wmb(); \
  265. (__rxd)->rx_flags = cpu_to_le32(__flags); \
  266. } while(0)
  267. #define hme_write_txd(__hp, __txd, __flags, __addr) \
  268. do { (__txd)->tx_addr = cpu_to_le32(__addr); \
  269. wmb(); \
  270. (__txd)->tx_flags = cpu_to_le32(__flags); \
  271. } while(0)
  272. #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
  273. #define hme_dma_map(__hp, __ptr, __size, __dir) \
  274. pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
  275. #define hme_dma_unmap(__hp, __addr, __size, __dir) \
  276. pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
  277. #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
  278. pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
  279. #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
  280. pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
  281. #endif
  282. #endif
  283. #ifdef SBUS_DMA_BIDIRECTIONAL
  284. # define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
  285. #else
  286. # define DMA_BIDIRECTIONAL 0
  287. #endif
  288. #ifdef SBUS_DMA_FROMDEVICE
  289. # define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
  290. #else
  291. # define DMA_TODEVICE 1
  292. #endif
  293. #ifdef SBUS_DMA_TODEVICE
  294. # define DMA_TODEVICE SBUS_DMA_TODEVICE
  295. #else
  296. # define DMA_FROMDEVICE 2
  297. #endif
  298. /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
  299. static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
  300. {
  301. hme_write32(hp, tregs + TCVR_BBDATA, bit);
  302. hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
  303. hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
  304. }
  305. #if 0
  306. static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
  307. {
  308. u32 ret;
  309. hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
  310. hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
  311. ret = hme_read32(hp, tregs + TCVR_CFG);
  312. if (internal)
  313. ret &= TCV_CFG_MDIO0;
  314. else
  315. ret &= TCV_CFG_MDIO1;
  316. return ret;
  317. }
  318. #endif
  319. static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
  320. {
  321. u32 retval;
  322. hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
  323. udelay(1);
  324. retval = hme_read32(hp, tregs + TCVR_CFG);
  325. if (internal)
  326. retval &= TCV_CFG_MDIO0;
  327. else
  328. retval &= TCV_CFG_MDIO1;
  329. hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
  330. return retval;
  331. }
  332. #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
  333. static int happy_meal_bb_read(struct happy_meal *hp,
  334. void __iomem *tregs, int reg)
  335. {
  336. u32 tmp;
  337. int retval = 0;
  338. int i;
  339. ASD(("happy_meal_bb_read: reg=%d ", reg));
  340. /* Enable the MIF BitBang outputs. */
  341. hme_write32(hp, tregs + TCVR_BBOENAB, 1);
  342. /* Force BitBang into the idle state. */
  343. for (i = 0; i < 32; i++)
  344. BB_PUT_BIT(hp, tregs, 1);
  345. /* Give it the read sequence. */
  346. BB_PUT_BIT(hp, tregs, 0);
  347. BB_PUT_BIT(hp, tregs, 1);
  348. BB_PUT_BIT(hp, tregs, 1);
  349. BB_PUT_BIT(hp, tregs, 0);
  350. /* Give it the PHY address. */
  351. tmp = hp->paddr & 0xff;
  352. for (i = 4; i >= 0; i--)
  353. BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
  354. /* Tell it what register we want to read. */
  355. tmp = (reg & 0xff);
  356. for (i = 4; i >= 0; i--)
  357. BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
  358. /* Close down the MIF BitBang outputs. */
  359. hme_write32(hp, tregs + TCVR_BBOENAB, 0);
  360. /* Now read in the value. */
  361. (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
  362. for (i = 15; i >= 0; i--)
  363. retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
  364. (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
  365. (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
  366. (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
  367. ASD(("value=%x\n", retval));
  368. return retval;
  369. }
  370. static void happy_meal_bb_write(struct happy_meal *hp,
  371. void __iomem *tregs, int reg,
  372. unsigned short value)
  373. {
  374. u32 tmp;
  375. int i;
  376. ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
  377. /* Enable the MIF BitBang outputs. */
  378. hme_write32(hp, tregs + TCVR_BBOENAB, 1);
  379. /* Force BitBang into the idle state. */
  380. for (i = 0; i < 32; i++)
  381. BB_PUT_BIT(hp, tregs, 1);
  382. /* Give it write sequence. */
  383. BB_PUT_BIT(hp, tregs, 0);
  384. BB_PUT_BIT(hp, tregs, 1);
  385. BB_PUT_BIT(hp, tregs, 0);
  386. BB_PUT_BIT(hp, tregs, 1);
  387. /* Give it the PHY address. */
  388. tmp = (hp->paddr & 0xff);
  389. for (i = 4; i >= 0; i--)
  390. BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
  391. /* Tell it what register we will be writing. */
  392. tmp = (reg & 0xff);
  393. for (i = 4; i >= 0; i--)
  394. BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
  395. /* Tell it to become ready for the bits. */
  396. BB_PUT_BIT(hp, tregs, 1);
  397. BB_PUT_BIT(hp, tregs, 0);
  398. for (i = 15; i >= 0; i--)
  399. BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
  400. /* Close down the MIF BitBang outputs. */
  401. hme_write32(hp, tregs + TCVR_BBOENAB, 0);
  402. }
  403. #define TCVR_READ_TRIES 16
  404. static int happy_meal_tcvr_read(struct happy_meal *hp,
  405. void __iomem *tregs, int reg)
  406. {
  407. int tries = TCVR_READ_TRIES;
  408. int retval;
  409. ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
  410. if (hp->tcvr_type == none) {
  411. ASD(("no transceiver, value=TCVR_FAILURE\n"));
  412. return TCVR_FAILURE;
  413. }
  414. if (!(hp->happy_flags & HFLAG_FENABLE)) {
  415. ASD(("doing bit bang\n"));
  416. return happy_meal_bb_read(hp, tregs, reg);
  417. }
  418. hme_write32(hp, tregs + TCVR_FRAME,
  419. (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
  420. while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
  421. udelay(20);
  422. if (!tries) {
  423. printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
  424. return TCVR_FAILURE;
  425. }
  426. retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
  427. ASD(("value=%04x\n", retval));
  428. return retval;
  429. }
  430. #define TCVR_WRITE_TRIES 16
  431. static void happy_meal_tcvr_write(struct happy_meal *hp,
  432. void __iomem *tregs, int reg,
  433. unsigned short value)
  434. {
  435. int tries = TCVR_WRITE_TRIES;
  436. ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
  437. /* Welcome to Sun Microsystems, can I take your order please? */
  438. if (!(hp->happy_flags & HFLAG_FENABLE)) {
  439. happy_meal_bb_write(hp, tregs, reg, value);
  440. return;
  441. }
  442. /* Would you like fries with that? */
  443. hme_write32(hp, tregs + TCVR_FRAME,
  444. (FRAME_WRITE | (hp->paddr << 23) |
  445. ((reg & 0xff) << 18) | (value & 0xffff)));
  446. while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
  447. udelay(20);
  448. /* Anything else? */
  449. if (!tries)
  450. printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
  451. /* Fifty-two cents is your change, have a nice day. */
  452. }
  453. /* Auto negotiation. The scheme is very simple. We have a timer routine
  454. * that keeps watching the auto negotiation process as it progresses.
  455. * The DP83840 is first told to start doing it's thing, we set up the time
  456. * and place the timer state machine in it's initial state.
  457. *
  458. * Here the timer peeks at the DP83840 status registers at each click to see
  459. * if the auto negotiation has completed, we assume here that the DP83840 PHY
  460. * will time out at some point and just tell us what (didn't) happen. For
  461. * complete coverage we only allow so many of the ticks at this level to run,
  462. * when this has expired we print a warning message and try another strategy.
  463. * This "other" strategy is to force the interface into various speed/duplex
  464. * configurations and we stop when we see a link-up condition before the
  465. * maximum number of "peek" ticks have occurred.
  466. *
  467. * Once a valid link status has been detected we configure the BigMAC and
  468. * the rest of the Happy Meal to speak the most efficient protocol we could
  469. * get a clean link for. The priority for link configurations, highest first
  470. * is:
  471. * 100 Base-T Full Duplex
  472. * 100 Base-T Half Duplex
  473. * 10 Base-T Full Duplex
  474. * 10 Base-T Half Duplex
  475. *
  476. * We start a new timer now, after a successful auto negotiation status has
  477. * been detected. This timer just waits for the link-up bit to get set in
  478. * the BMCR of the DP83840. When this occurs we print a kernel log message
  479. * describing the link type in use and the fact that it is up.
  480. *
  481. * If a fatal error of some sort is signalled and detected in the interrupt
  482. * service routine, and the chip is reset, or the link is ifconfig'd down
  483. * and then back up, this entire process repeats itself all over again.
  484. */
  485. static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
  486. {
  487. hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  488. /* Downgrade from full to half duplex. Only possible
  489. * via ethtool.
  490. */
  491. if (hp->sw_bmcr & BMCR_FULLDPLX) {
  492. hp->sw_bmcr &= ~(BMCR_FULLDPLX);
  493. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  494. return 0;
  495. }
  496. /* Downgrade from 100 to 10. */
  497. if (hp->sw_bmcr & BMCR_SPEED100) {
  498. hp->sw_bmcr &= ~(BMCR_SPEED100);
  499. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  500. return 0;
  501. }
  502. /* We've tried everything. */
  503. return -1;
  504. }
  505. static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
  506. {
  507. printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
  508. if (hp->tcvr_type == external)
  509. printk("external ");
  510. else
  511. printk("internal ");
  512. printk("transceiver at ");
  513. hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
  514. if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
  515. if (hp->sw_lpa & LPA_100FULL)
  516. printk("100Mb/s, Full Duplex.\n");
  517. else
  518. printk("100Mb/s, Half Duplex.\n");
  519. } else {
  520. if (hp->sw_lpa & LPA_10FULL)
  521. printk("10Mb/s, Full Duplex.\n");
  522. else
  523. printk("10Mb/s, Half Duplex.\n");
  524. }
  525. }
  526. static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
  527. {
  528. printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
  529. if (hp->tcvr_type == external)
  530. printk("external ");
  531. else
  532. printk("internal ");
  533. printk("transceiver at ");
  534. hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  535. if (hp->sw_bmcr & BMCR_SPEED100)
  536. printk("100Mb/s, ");
  537. else
  538. printk("10Mb/s, ");
  539. if (hp->sw_bmcr & BMCR_FULLDPLX)
  540. printk("Full Duplex.\n");
  541. else
  542. printk("Half Duplex.\n");
  543. }
  544. static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
  545. {
  546. int full;
  547. /* All we care about is making sure the bigmac tx_cfg has a
  548. * proper duplex setting.
  549. */
  550. if (hp->timer_state == arbwait) {
  551. hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
  552. if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
  553. goto no_response;
  554. if (hp->sw_lpa & LPA_100FULL)
  555. full = 1;
  556. else if (hp->sw_lpa & LPA_100HALF)
  557. full = 0;
  558. else if (hp->sw_lpa & LPA_10FULL)
  559. full = 1;
  560. else
  561. full = 0;
  562. } else {
  563. /* Forcing a link mode. */
  564. hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  565. if (hp->sw_bmcr & BMCR_FULLDPLX)
  566. full = 1;
  567. else
  568. full = 0;
  569. }
  570. /* Before changing other bits in the tx_cfg register, and in
  571. * general any of other the TX config registers too, you
  572. * must:
  573. * 1) Clear Enable
  574. * 2) Poll with reads until that bit reads back as zero
  575. * 3) Make TX configuration changes
  576. * 4) Set Enable once more
  577. */
  578. hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
  579. hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
  580. ~(BIGMAC_TXCFG_ENABLE));
  581. while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
  582. barrier();
  583. if (full) {
  584. hp->happy_flags |= HFLAG_FULL;
  585. hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
  586. hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
  587. BIGMAC_TXCFG_FULLDPLX);
  588. } else {
  589. hp->happy_flags &= ~(HFLAG_FULL);
  590. hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
  591. hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
  592. ~(BIGMAC_TXCFG_FULLDPLX));
  593. }
  594. hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
  595. hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
  596. BIGMAC_TXCFG_ENABLE);
  597. return 0;
  598. no_response:
  599. return 1;
  600. }
  601. static int happy_meal_init(struct happy_meal *hp);
  602. static int is_lucent_phy(struct happy_meal *hp)
  603. {
  604. void __iomem *tregs = hp->tcvregs;
  605. unsigned short mr2, mr3;
  606. int ret = 0;
  607. mr2 = happy_meal_tcvr_read(hp, tregs, 2);
  608. mr3 = happy_meal_tcvr_read(hp, tregs, 3);
  609. if ((mr2 & 0xffff) == 0x0180 &&
  610. ((mr3 & 0xffff) >> 10) == 0x1d)
  611. ret = 1;
  612. return ret;
  613. }
  614. static void happy_meal_timer(unsigned long data)
  615. {
  616. struct happy_meal *hp = (struct happy_meal *) data;
  617. void __iomem *tregs = hp->tcvregs;
  618. int restart_timer = 0;
  619. spin_lock_irq(&hp->happy_lock);
  620. hp->timer_ticks++;
  621. switch(hp->timer_state) {
  622. case arbwait:
  623. /* Only allow for 5 ticks, thats 10 seconds and much too
  624. * long to wait for arbitration to complete.
  625. */
  626. if (hp->timer_ticks >= 10) {
  627. /* Enter force mode. */
  628. do_force_mode:
  629. hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  630. printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
  631. hp->dev->name);
  632. hp->sw_bmcr = BMCR_SPEED100;
  633. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  634. if (!is_lucent_phy(hp)) {
  635. /* OK, seems we need do disable the transceiver for the first
  636. * tick to make sure we get an accurate link state at the
  637. * second tick.
  638. */
  639. hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
  640. hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
  641. happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
  642. }
  643. hp->timer_state = ltrywait;
  644. hp->timer_ticks = 0;
  645. restart_timer = 1;
  646. } else {
  647. /* Anything interesting happen? */
  648. hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
  649. if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
  650. int ret;
  651. /* Just what we've been waiting for... */
  652. ret = set_happy_link_modes(hp, tregs);
  653. if (ret) {
  654. /* Ooops, something bad happened, go to force
  655. * mode.
  656. *
  657. * XXX Broken hubs which don't support 802.3u
  658. * XXX auto-negotiation make this happen as well.
  659. */
  660. goto do_force_mode;
  661. }
  662. /* Success, at least so far, advance our state engine. */
  663. hp->timer_state = lupwait;
  664. restart_timer = 1;
  665. } else {
  666. restart_timer = 1;
  667. }
  668. }
  669. break;
  670. case lupwait:
  671. /* Auto negotiation was successful and we are awaiting a
  672. * link up status. I have decided to let this timer run
  673. * forever until some sort of error is signalled, reporting
  674. * a message to the user at 10 second intervals.
  675. */
  676. hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
  677. if (hp->sw_bmsr & BMSR_LSTATUS) {
  678. /* Wheee, it's up, display the link mode in use and put
  679. * the timer to sleep.
  680. */
  681. display_link_mode(hp, tregs);
  682. hp->timer_state = asleep;
  683. restart_timer = 0;
  684. } else {
  685. if (hp->timer_ticks >= 10) {
  686. printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
  687. "not completely up.\n", hp->dev->name);
  688. hp->timer_ticks = 0;
  689. restart_timer = 1;
  690. } else {
  691. restart_timer = 1;
  692. }
  693. }
  694. break;
  695. case ltrywait:
  696. /* Making the timeout here too long can make it take
  697. * annoyingly long to attempt all of the link mode
  698. * permutations, but then again this is essentially
  699. * error recovery code for the most part.
  700. */
  701. hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
  702. hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
  703. if (hp->timer_ticks == 1) {
  704. if (!is_lucent_phy(hp)) {
  705. /* Re-enable transceiver, we'll re-enable the transceiver next
  706. * tick, then check link state on the following tick.
  707. */
  708. hp->sw_csconfig |= CSCONFIG_TCVDISAB;
  709. happy_meal_tcvr_write(hp, tregs,
  710. DP83840_CSCONFIG, hp->sw_csconfig);
  711. }
  712. restart_timer = 1;
  713. break;
  714. }
  715. if (hp->timer_ticks == 2) {
  716. if (!is_lucent_phy(hp)) {
  717. hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
  718. happy_meal_tcvr_write(hp, tregs,
  719. DP83840_CSCONFIG, hp->sw_csconfig);
  720. }
  721. restart_timer = 1;
  722. break;
  723. }
  724. if (hp->sw_bmsr & BMSR_LSTATUS) {
  725. /* Force mode selection success. */
  726. display_forced_link_mode(hp, tregs);
  727. set_happy_link_modes(hp, tregs); /* XXX error? then what? */
  728. hp->timer_state = asleep;
  729. restart_timer = 0;
  730. } else {
  731. if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
  732. int ret;
  733. ret = try_next_permutation(hp, tregs);
  734. if (ret == -1) {
  735. /* Aieee, tried them all, reset the
  736. * chip and try all over again.
  737. */
  738. /* Let the user know... */
  739. printk(KERN_NOTICE "%s: Link down, cable problem?\n",
  740. hp->dev->name);
  741. ret = happy_meal_init(hp);
  742. if (ret) {
  743. /* ho hum... */
  744. printk(KERN_ERR "%s: Error, cannot re-init the "
  745. "Happy Meal.\n", hp->dev->name);
  746. }
  747. goto out;
  748. }
  749. if (!is_lucent_phy(hp)) {
  750. hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
  751. DP83840_CSCONFIG);
  752. hp->sw_csconfig |= CSCONFIG_TCVDISAB;
  753. happy_meal_tcvr_write(hp, tregs,
  754. DP83840_CSCONFIG, hp->sw_csconfig);
  755. }
  756. hp->timer_ticks = 0;
  757. restart_timer = 1;
  758. } else {
  759. restart_timer = 1;
  760. }
  761. }
  762. break;
  763. case asleep:
  764. default:
  765. /* Can't happens.... */
  766. printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
  767. hp->dev->name);
  768. restart_timer = 0;
  769. hp->timer_ticks = 0;
  770. hp->timer_state = asleep; /* foo on you */
  771. break;
  772. };
  773. if (restart_timer) {
  774. hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
  775. add_timer(&hp->happy_timer);
  776. }
  777. out:
  778. spin_unlock_irq(&hp->happy_lock);
  779. }
  780. #define TX_RESET_TRIES 32
  781. #define RX_RESET_TRIES 32
  782. /* hp->happy_lock must be held */
  783. static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
  784. {
  785. int tries = TX_RESET_TRIES;
  786. HMD(("happy_meal_tx_reset: reset, "));
  787. /* Would you like to try our SMCC Delux? */
  788. hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
  789. while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
  790. udelay(20);
  791. /* Lettuce, tomato, buggy hardware (no extra charge)? */
  792. if (!tries)
  793. printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
  794. /* Take care. */
  795. HMD(("done\n"));
  796. }
  797. /* hp->happy_lock must be held */
  798. static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
  799. {
  800. int tries = RX_RESET_TRIES;
  801. HMD(("happy_meal_rx_reset: reset, "));
  802. /* We have a special on GNU/Viking hardware bugs today. */
  803. hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
  804. while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
  805. udelay(20);
  806. /* Will that be all? */
  807. if (!tries)
  808. printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
  809. /* Don't forget your vik_1137125_wa. Have a nice day. */
  810. HMD(("done\n"));
  811. }
  812. #define STOP_TRIES 16
  813. /* hp->happy_lock must be held */
  814. static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
  815. {
  816. int tries = STOP_TRIES;
  817. HMD(("happy_meal_stop: reset, "));
  818. /* We're consolidating our STB products, it's your lucky day. */
  819. hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
  820. while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
  821. udelay(20);
  822. /* Come back next week when we are "Sun Microelectronics". */
  823. if (!tries)
  824. printk(KERN_ERR "happy meal: Fry guys.");
  825. /* Remember: "Different name, same old buggy as shit hardware." */
  826. HMD(("done\n"));
  827. }
  828. /* hp->happy_lock must be held */
  829. static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
  830. {
  831. struct net_device_stats *stats = &hp->net_stats;
  832. stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
  833. hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
  834. stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
  835. hme_write32(hp, bregs + BMAC_UNALECTR, 0);
  836. stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
  837. hme_write32(hp, bregs + BMAC_GLECTR, 0);
  838. stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
  839. stats->collisions +=
  840. (hme_read32(hp, bregs + BMAC_EXCTR) +
  841. hme_read32(hp, bregs + BMAC_LTCTR));
  842. hme_write32(hp, bregs + BMAC_EXCTR, 0);
  843. hme_write32(hp, bregs + BMAC_LTCTR, 0);
  844. }
  845. /* hp->happy_lock must be held */
  846. static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
  847. {
  848. ASD(("happy_meal_poll_stop: "));
  849. /* If polling disabled or not polling already, nothing to do. */
  850. if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
  851. (HFLAG_POLLENABLE | HFLAG_POLL)) {
  852. HMD(("not polling, return\n"));
  853. return;
  854. }
  855. /* Shut up the MIF. */
  856. ASD(("were polling, mif ints off, "));
  857. hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
  858. /* Turn off polling. */
  859. ASD(("polling off, "));
  860. hme_write32(hp, tregs + TCVR_CFG,
  861. hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
  862. /* We are no longer polling. */
  863. hp->happy_flags &= ~(HFLAG_POLL);
  864. /* Let the bits set. */
  865. udelay(200);
  866. ASD(("done\n"));
  867. }
  868. /* Only Sun can take such nice parts and fuck up the programming interface
  869. * like this. Good job guys...
  870. */
  871. #define TCVR_RESET_TRIES 16 /* It should reset quickly */
  872. #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
  873. /* hp->happy_lock must be held */
  874. static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
  875. {
  876. u32 tconfig;
  877. int result, tries = TCVR_RESET_TRIES;
  878. tconfig = hme_read32(hp, tregs + TCVR_CFG);
  879. ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
  880. if (hp->tcvr_type == external) {
  881. ASD(("external<"));
  882. hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
  883. hp->tcvr_type = internal;
  884. hp->paddr = TCV_PADDR_ITX;
  885. ASD(("ISOLATE,"));
  886. happy_meal_tcvr_write(hp, tregs, MII_BMCR,
  887. (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
  888. result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  889. if (result == TCVR_FAILURE) {
  890. ASD(("phyread_fail>\n"));
  891. return -1;
  892. }
  893. ASD(("phyread_ok,PSELECT>"));
  894. hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
  895. hp->tcvr_type = external;
  896. hp->paddr = TCV_PADDR_ETX;
  897. } else {
  898. if (tconfig & TCV_CFG_MDIO1) {
  899. ASD(("internal<PSELECT,"));
  900. hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
  901. ASD(("ISOLATE,"));
  902. happy_meal_tcvr_write(hp, tregs, MII_BMCR,
  903. (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
  904. result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  905. if (result == TCVR_FAILURE) {
  906. ASD(("phyread_fail>\n"));
  907. return -1;
  908. }
  909. ASD(("phyread_ok,~PSELECT>"));
  910. hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
  911. hp->tcvr_type = internal;
  912. hp->paddr = TCV_PADDR_ITX;
  913. }
  914. }
  915. ASD(("BMCR_RESET "));
  916. happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
  917. while (--tries) {
  918. result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  919. if (result == TCVR_FAILURE)
  920. return -1;
  921. hp->sw_bmcr = result;
  922. if (!(result & BMCR_RESET))
  923. break;
  924. udelay(20);
  925. }
  926. if (!tries) {
  927. ASD(("BMCR RESET FAILED!\n"));
  928. return -1;
  929. }
  930. ASD(("RESET_OK\n"));
  931. /* Get fresh copies of the PHY registers. */
  932. hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
  933. hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
  934. hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
  935. hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
  936. ASD(("UNISOLATE"));
  937. hp->sw_bmcr &= ~(BMCR_ISOLATE);
  938. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  939. tries = TCVR_UNISOLATE_TRIES;
  940. while (--tries) {
  941. result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  942. if (result == TCVR_FAILURE)
  943. return -1;
  944. if (!(result & BMCR_ISOLATE))
  945. break;
  946. udelay(20);
  947. }
  948. if (!tries) {
  949. ASD((" FAILED!\n"));
  950. return -1;
  951. }
  952. ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
  953. if (!is_lucent_phy(hp)) {
  954. result = happy_meal_tcvr_read(hp, tregs,
  955. DP83840_CSCONFIG);
  956. happy_meal_tcvr_write(hp, tregs,
  957. DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
  958. }
  959. return 0;
  960. }
  961. /* Figure out whether we have an internal or external transceiver.
  962. *
  963. * hp->happy_lock must be held
  964. */
  965. static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
  966. {
  967. unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
  968. ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
  969. if (hp->happy_flags & HFLAG_POLL) {
  970. /* If we are polling, we must stop to get the transceiver type. */
  971. ASD(("<polling> "));
  972. if (hp->tcvr_type == internal) {
  973. if (tconfig & TCV_CFG_MDIO1) {
  974. ASD(("<internal> <poll stop> "));
  975. happy_meal_poll_stop(hp, tregs);
  976. hp->paddr = TCV_PADDR_ETX;
  977. hp->tcvr_type = external;
  978. ASD(("<external>\n"));
  979. tconfig &= ~(TCV_CFG_PENABLE);
  980. tconfig |= TCV_CFG_PSELECT;
  981. hme_write32(hp, tregs + TCVR_CFG, tconfig);
  982. }
  983. } else {
  984. if (hp->tcvr_type == external) {
  985. ASD(("<external> "));
  986. if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
  987. ASD(("<poll stop> "));
  988. happy_meal_poll_stop(hp, tregs);
  989. hp->paddr = TCV_PADDR_ITX;
  990. hp->tcvr_type = internal;
  991. ASD(("<internal>\n"));
  992. hme_write32(hp, tregs + TCVR_CFG,
  993. hme_read32(hp, tregs + TCVR_CFG) &
  994. ~(TCV_CFG_PSELECT));
  995. }
  996. ASD(("\n"));
  997. } else {
  998. ASD(("<none>\n"));
  999. }
  1000. }
  1001. } else {
  1002. u32 reread = hme_read32(hp, tregs + TCVR_CFG);
  1003. /* Else we can just work off of the MDIO bits. */
  1004. ASD(("<not polling> "));
  1005. if (reread & TCV_CFG_MDIO1) {
  1006. hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
  1007. hp->paddr = TCV_PADDR_ETX;
  1008. hp->tcvr_type = external;
  1009. ASD(("<external>\n"));
  1010. } else {
  1011. if (reread & TCV_CFG_MDIO0) {
  1012. hme_write32(hp, tregs + TCVR_CFG,
  1013. tconfig & ~(TCV_CFG_PSELECT));
  1014. hp->paddr = TCV_PADDR_ITX;
  1015. hp->tcvr_type = internal;
  1016. ASD(("<internal>\n"));
  1017. } else {
  1018. printk(KERN_ERR "happy meal: Transceiver and a coke please.");
  1019. hp->tcvr_type = none; /* Grrr... */
  1020. ASD(("<none>\n"));
  1021. }
  1022. }
  1023. }
  1024. }
  1025. /* The receive ring buffers are a bit tricky to get right. Here goes...
  1026. *
  1027. * The buffers we dma into must be 64 byte aligned. So we use a special
  1028. * alloc_skb() routine for the happy meal to allocate 64 bytes more than
  1029. * we really need.
  1030. *
  1031. * We use skb_reserve() to align the data block we get in the skb. We
  1032. * also program the etxregs->cfg register to use an offset of 2. This
  1033. * imperical constant plus the ethernet header size will always leave
  1034. * us with a nicely aligned ip header once we pass things up to the
  1035. * protocol layers.
  1036. *
  1037. * The numbers work out to:
  1038. *
  1039. * Max ethernet frame size 1518
  1040. * Ethernet header size 14
  1041. * Happy Meal base offset 2
  1042. *
  1043. * Say a skb data area is at 0xf001b010, and its size alloced is
  1044. * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
  1045. *
  1046. * First our alloc_skb() routine aligns the data base to a 64 byte
  1047. * boundary. We now have 0xf001b040 as our skb data address. We
  1048. * plug this into the receive descriptor address.
  1049. *
  1050. * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
  1051. * So now the data we will end up looking at starts at 0xf001b042. When
  1052. * the packet arrives, we will check out the size received and subtract
  1053. * this from the skb->length. Then we just pass the packet up to the
  1054. * protocols as is, and allocate a new skb to replace this slot we have
  1055. * just received from.
  1056. *
  1057. * The ethernet layer will strip the ether header from the front of the
  1058. * skb we just sent to it, this leaves us with the ip header sitting
  1059. * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
  1060. * Happy Meal has even checksummed the tcp/udp data for us. The 16
  1061. * bit checksum is obtained from the low bits of the receive descriptor
  1062. * flags, thus:
  1063. *
  1064. * skb->csum = rxd->rx_flags & 0xffff;
  1065. * skb->ip_summed = CHECKSUM_COMPLETE;
  1066. *
  1067. * before sending off the skb to the protocols, and we are good as gold.
  1068. */
  1069. static void happy_meal_clean_rings(struct happy_meal *hp)
  1070. {
  1071. int i;
  1072. for (i = 0; i < RX_RING_SIZE; i++) {
  1073. if (hp->rx_skbs[i] != NULL) {
  1074. struct sk_buff *skb = hp->rx_skbs[i];
  1075. struct happy_meal_rxd *rxd;
  1076. u32 dma_addr;
  1077. rxd = &hp->happy_block->happy_meal_rxd[i];
  1078. dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
  1079. hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
  1080. dev_kfree_skb_any(skb);
  1081. hp->rx_skbs[i] = NULL;
  1082. }
  1083. }
  1084. for (i = 0; i < TX_RING_SIZE; i++) {
  1085. if (hp->tx_skbs[i] != NULL) {
  1086. struct sk_buff *skb = hp->tx_skbs[i];
  1087. struct happy_meal_txd *txd;
  1088. u32 dma_addr;
  1089. int frag;
  1090. hp->tx_skbs[i] = NULL;
  1091. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  1092. txd = &hp->happy_block->happy_meal_txd[i];
  1093. dma_addr = hme_read_desc32(hp, &txd->tx_addr);
  1094. hme_dma_unmap(hp, dma_addr,
  1095. (hme_read_desc32(hp, &txd->tx_flags)
  1096. & TXFLAG_SIZE),
  1097. DMA_TODEVICE);
  1098. if (frag != skb_shinfo(skb)->nr_frags)
  1099. i++;
  1100. }
  1101. dev_kfree_skb_any(skb);
  1102. }
  1103. }
  1104. }
  1105. /* hp->happy_lock must be held */
  1106. static void happy_meal_init_rings(struct happy_meal *hp)
  1107. {
  1108. struct hmeal_init_block *hb = hp->happy_block;
  1109. struct net_device *dev = hp->dev;
  1110. int i;
  1111. HMD(("happy_meal_init_rings: counters to zero, "));
  1112. hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
  1113. /* Free any skippy bufs left around in the rings. */
  1114. HMD(("clean, "));
  1115. happy_meal_clean_rings(hp);
  1116. /* Now get new skippy bufs for the receive ring. */
  1117. HMD(("init rxring, "));
  1118. for (i = 0; i < RX_RING_SIZE; i++) {
  1119. struct sk_buff *skb;
  1120. skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
  1121. if (!skb) {
  1122. hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
  1123. continue;
  1124. }
  1125. hp->rx_skbs[i] = skb;
  1126. skb->dev = dev;
  1127. /* Because we reserve afterwards. */
  1128. skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
  1129. hme_write_rxd(hp, &hb->happy_meal_rxd[i],
  1130. (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
  1131. hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
  1132. skb_reserve(skb, RX_OFFSET);
  1133. }
  1134. HMD(("init txring, "));
  1135. for (i = 0; i < TX_RING_SIZE; i++)
  1136. hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
  1137. HMD(("done\n"));
  1138. }
  1139. /* hp->happy_lock must be held */
  1140. static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
  1141. void __iomem *tregs,
  1142. struct ethtool_cmd *ep)
  1143. {
  1144. int timeout;
  1145. /* Read all of the registers we are interested in now. */
  1146. hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
  1147. hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  1148. hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
  1149. hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
  1150. /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
  1151. hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
  1152. if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
  1153. /* Advertise everything we can support. */
  1154. if (hp->sw_bmsr & BMSR_10HALF)
  1155. hp->sw_advertise |= (ADVERTISE_10HALF);
  1156. else
  1157. hp->sw_advertise &= ~(ADVERTISE_10HALF);
  1158. if (hp->sw_bmsr & BMSR_10FULL)
  1159. hp->sw_advertise |= (ADVERTISE_10FULL);
  1160. else
  1161. hp->sw_advertise &= ~(ADVERTISE_10FULL);
  1162. if (hp->sw_bmsr & BMSR_100HALF)
  1163. hp->sw_advertise |= (ADVERTISE_100HALF);
  1164. else
  1165. hp->sw_advertise &= ~(ADVERTISE_100HALF);
  1166. if (hp->sw_bmsr & BMSR_100FULL)
  1167. hp->sw_advertise |= (ADVERTISE_100FULL);
  1168. else
  1169. hp->sw_advertise &= ~(ADVERTISE_100FULL);
  1170. happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
  1171. /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
  1172. * XXX and this is because the DP83840 does not support it, changes
  1173. * XXX would need to be made to the tx/rx logic in the driver as well
  1174. * XXX so I completely skip checking for it in the BMSR for now.
  1175. */
  1176. #ifdef AUTO_SWITCH_DEBUG
  1177. ASD(("%s: Advertising [ ", hp->dev->name));
  1178. if (hp->sw_advertise & ADVERTISE_10HALF)
  1179. ASD(("10H "));
  1180. if (hp->sw_advertise & ADVERTISE_10FULL)
  1181. ASD(("10F "));
  1182. if (hp->sw_advertise & ADVERTISE_100HALF)
  1183. ASD(("100H "));
  1184. if (hp->sw_advertise & ADVERTISE_100FULL)
  1185. ASD(("100F "));
  1186. #endif
  1187. /* Enable Auto-Negotiation, this is usually on already... */
  1188. hp->sw_bmcr |= BMCR_ANENABLE;
  1189. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  1190. /* Restart it to make sure it is going. */
  1191. hp->sw_bmcr |= BMCR_ANRESTART;
  1192. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  1193. /* BMCR_ANRESTART self clears when the process has begun. */
  1194. timeout = 64; /* More than enough. */
  1195. while (--timeout) {
  1196. hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  1197. if (!(hp->sw_bmcr & BMCR_ANRESTART))
  1198. break; /* got it. */
  1199. udelay(10);
  1200. }
  1201. if (!timeout) {
  1202. printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
  1203. "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
  1204. printk(KERN_NOTICE "%s: Performing force link detection.\n",
  1205. hp->dev->name);
  1206. goto force_link;
  1207. } else {
  1208. hp->timer_state = arbwait;
  1209. }
  1210. } else {
  1211. force_link:
  1212. /* Force the link up, trying first a particular mode.
  1213. * Either we are here at the request of ethtool or
  1214. * because the Happy Meal would not start to autoneg.
  1215. */
  1216. /* Disable auto-negotiation in BMCR, enable the duplex and
  1217. * speed setting, init the timer state machine, and fire it off.
  1218. */
  1219. if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
  1220. hp->sw_bmcr = BMCR_SPEED100;
  1221. } else {
  1222. if (ep->speed == SPEED_100)
  1223. hp->sw_bmcr = BMCR_SPEED100;
  1224. else
  1225. hp->sw_bmcr = 0;
  1226. if (ep->duplex == DUPLEX_FULL)
  1227. hp->sw_bmcr |= BMCR_FULLDPLX;
  1228. }
  1229. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  1230. if (!is_lucent_phy(hp)) {
  1231. /* OK, seems we need do disable the transceiver for the first
  1232. * tick to make sure we get an accurate link state at the
  1233. * second tick.
  1234. */
  1235. hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
  1236. DP83840_CSCONFIG);
  1237. hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
  1238. happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
  1239. hp->sw_csconfig);
  1240. }
  1241. hp->timer_state = ltrywait;
  1242. }
  1243. hp->timer_ticks = 0;
  1244. hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
  1245. hp->happy_timer.data = (unsigned long) hp;
  1246. hp->happy_timer.function = &happy_meal_timer;
  1247. add_timer(&hp->happy_timer);
  1248. }
  1249. /* hp->happy_lock must be held */
  1250. static int happy_meal_init(struct happy_meal *hp)
  1251. {
  1252. void __iomem *gregs = hp->gregs;
  1253. void __iomem *etxregs = hp->etxregs;
  1254. void __iomem *erxregs = hp->erxregs;
  1255. void __iomem *bregs = hp->bigmacregs;
  1256. void __iomem *tregs = hp->tcvregs;
  1257. u32 regtmp, rxcfg;
  1258. unsigned char *e = &hp->dev->dev_addr[0];
  1259. /* If auto-negotiation timer is running, kill it. */
  1260. del_timer(&hp->happy_timer);
  1261. HMD(("happy_meal_init: happy_flags[%08x] ",
  1262. hp->happy_flags));
  1263. if (!(hp->happy_flags & HFLAG_INIT)) {
  1264. HMD(("set HFLAG_INIT, "));
  1265. hp->happy_flags |= HFLAG_INIT;
  1266. happy_meal_get_counters(hp, bregs);
  1267. }
  1268. /* Stop polling. */
  1269. HMD(("to happy_meal_poll_stop\n"));
  1270. happy_meal_poll_stop(hp, tregs);
  1271. /* Stop transmitter and receiver. */
  1272. HMD(("happy_meal_init: to happy_meal_stop\n"));
  1273. happy_meal_stop(hp, gregs);
  1274. /* Alloc and reset the tx/rx descriptor chains. */
  1275. HMD(("happy_meal_init: to happy_meal_init_rings\n"));
  1276. happy_meal_init_rings(hp);
  1277. /* Shut up the MIF. */
  1278. HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
  1279. hme_read32(hp, tregs + TCVR_IMASK)));
  1280. hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
  1281. /* See if we can enable the MIF frame on this card to speak to the DP83840. */
  1282. if (hp->happy_flags & HFLAG_FENABLE) {
  1283. HMD(("use frame old[%08x], ",
  1284. hme_read32(hp, tregs + TCVR_CFG)));
  1285. hme_write32(hp, tregs + TCVR_CFG,
  1286. hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
  1287. } else {
  1288. HMD(("use bitbang old[%08x], ",
  1289. hme_read32(hp, tregs + TCVR_CFG)));
  1290. hme_write32(hp, tregs + TCVR_CFG,
  1291. hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
  1292. }
  1293. /* Check the state of the transceiver. */
  1294. HMD(("to happy_meal_transceiver_check\n"));
  1295. happy_meal_transceiver_check(hp, tregs);
  1296. /* Put the Big Mac into a sane state. */
  1297. HMD(("happy_meal_init: "));
  1298. switch(hp->tcvr_type) {
  1299. case none:
  1300. /* Cannot operate if we don't know the transceiver type! */
  1301. HMD(("AAIEEE no transceiver type, EAGAIN"));
  1302. return -EAGAIN;
  1303. case internal:
  1304. /* Using the MII buffers. */
  1305. HMD(("internal, using MII, "));
  1306. hme_write32(hp, bregs + BMAC_XIFCFG, 0);
  1307. break;
  1308. case external:
  1309. /* Not using the MII, disable it. */
  1310. HMD(("external, disable MII, "));
  1311. hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
  1312. break;
  1313. };
  1314. if (happy_meal_tcvr_reset(hp, tregs))
  1315. return -EAGAIN;
  1316. /* Reset the Happy Meal Big Mac transceiver and the receiver. */
  1317. HMD(("tx/rx reset, "));
  1318. happy_meal_tx_reset(hp, bregs);
  1319. happy_meal_rx_reset(hp, bregs);
  1320. /* Set jam size and inter-packet gaps to reasonable defaults. */
  1321. HMD(("jsize/ipg1/ipg2, "));
  1322. hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
  1323. hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
  1324. hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
  1325. /* Load up the MAC address and random seed. */
  1326. HMD(("rseed/macaddr, "));
  1327. /* The docs recommend to use the 10LSB of our MAC here. */
  1328. hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
  1329. hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
  1330. hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
  1331. hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
  1332. HMD(("htable, "));
  1333. if ((hp->dev->flags & IFF_ALLMULTI) ||
  1334. (hp->dev->mc_count > 64)) {
  1335. hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
  1336. hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
  1337. hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
  1338. hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
  1339. } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
  1340. u16 hash_table[4];
  1341. struct dev_mc_list *dmi = hp->dev->mc_list;
  1342. char *addrs;
  1343. int i;
  1344. u32 crc;
  1345. for (i = 0; i < 4; i++)
  1346. hash_table[i] = 0;
  1347. for (i = 0; i < hp->dev->mc_count; i++) {
  1348. addrs = dmi->dmi_addr;
  1349. dmi = dmi->next;
  1350. if (!(*addrs & 1))
  1351. continue;
  1352. crc = ether_crc_le(6, addrs);
  1353. crc >>= 26;
  1354. hash_table[crc >> 4] |= 1 << (crc & 0xf);
  1355. }
  1356. hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
  1357. hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
  1358. hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
  1359. hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
  1360. } else {
  1361. hme_write32(hp, bregs + BMAC_HTABLE3, 0);
  1362. hme_write32(hp, bregs + BMAC_HTABLE2, 0);
  1363. hme_write32(hp, bregs + BMAC_HTABLE1, 0);
  1364. hme_write32(hp, bregs + BMAC_HTABLE0, 0);
  1365. }
  1366. /* Set the RX and TX ring ptrs. */
  1367. HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
  1368. ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
  1369. ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
  1370. hme_write32(hp, erxregs + ERX_RING,
  1371. ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
  1372. hme_write32(hp, etxregs + ETX_RING,
  1373. ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
  1374. /* Parity issues in the ERX unit of some HME revisions can cause some
  1375. * registers to not be written unless their parity is even. Detect such
  1376. * lost writes and simply rewrite with a low bit set (which will be ignored
  1377. * since the rxring needs to be 2K aligned).
  1378. */
  1379. if (hme_read32(hp, erxregs + ERX_RING) !=
  1380. ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
  1381. hme_write32(hp, erxregs + ERX_RING,
  1382. ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
  1383. | 0x4);
  1384. /* Set the supported burst sizes. */
  1385. HMD(("happy_meal_init: old[%08x] bursts<",
  1386. hme_read32(hp, gregs + GREG_CFG)));
  1387. #ifndef CONFIG_SPARC
  1388. /* It is always PCI and can handle 64byte bursts. */
  1389. hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
  1390. #else
  1391. if ((hp->happy_bursts & DMA_BURST64) &&
  1392. ((hp->happy_flags & HFLAG_PCI) != 0
  1393. #ifdef CONFIG_SBUS
  1394. || sbus_can_burst64(hp->happy_dev)
  1395. #endif
  1396. || 0)) {
  1397. u32 gcfg = GREG_CFG_BURST64;
  1398. /* I have no idea if I should set the extended
  1399. * transfer mode bit for Cheerio, so for now I
  1400. * do not. -DaveM
  1401. */
  1402. #ifdef CONFIG_SBUS
  1403. if ((hp->happy_flags & HFLAG_PCI) == 0 &&
  1404. sbus_can_dma_64bit(hp->happy_dev)) {
  1405. sbus_set_sbus64(hp->happy_dev,
  1406. hp->happy_bursts);
  1407. gcfg |= GREG_CFG_64BIT;
  1408. }
  1409. #endif
  1410. HMD(("64>"));
  1411. hme_write32(hp, gregs + GREG_CFG, gcfg);
  1412. } else if (hp->happy_bursts & DMA_BURST32) {
  1413. HMD(("32>"));
  1414. hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
  1415. } else if (hp->happy_bursts & DMA_BURST16) {
  1416. HMD(("16>"));
  1417. hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
  1418. } else {
  1419. HMD(("XXX>"));
  1420. hme_write32(hp, gregs + GREG_CFG, 0);
  1421. }
  1422. #endif /* CONFIG_SPARC */
  1423. /* Turn off interrupts we do not want to hear. */
  1424. HMD((", enable global interrupts, "));
  1425. hme_write32(hp, gregs + GREG_IMASK,
  1426. (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
  1427. GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
  1428. /* Set the transmit ring buffer size. */
  1429. HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
  1430. hme_read32(hp, etxregs + ETX_RSIZE)));
  1431. hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
  1432. /* Enable transmitter DVMA. */
  1433. HMD(("tx dma enable old[%08x], ",
  1434. hme_read32(hp, etxregs + ETX_CFG)));
  1435. hme_write32(hp, etxregs + ETX_CFG,
  1436. hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
  1437. /* This chip really rots, for the receiver sometimes when you
  1438. * write to its control registers not all the bits get there
  1439. * properly. I cannot think of a sane way to provide complete
  1440. * coverage for this hardware bug yet.
  1441. */
  1442. HMD(("erx regs bug old[%08x]\n",
  1443. hme_read32(hp, erxregs + ERX_CFG)));
  1444. hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
  1445. regtmp = hme_read32(hp, erxregs + ERX_CFG);
  1446. hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
  1447. if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
  1448. printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
  1449. printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
  1450. ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
  1451. /* XXX Should return failure here... */
  1452. }
  1453. /* Enable Big Mac hash table filter. */
  1454. HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
  1455. hme_read32(hp, bregs + BMAC_RXCFG)));
  1456. rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
  1457. if (hp->dev->flags & IFF_PROMISC)
  1458. rxcfg |= BIGMAC_RXCFG_PMISC;
  1459. hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
  1460. /* Let the bits settle in the chip. */
  1461. udelay(10);
  1462. /* Ok, configure the Big Mac transmitter. */
  1463. HMD(("BIGMAC init, "));
  1464. regtmp = 0;
  1465. if (hp->happy_flags & HFLAG_FULL)
  1466. regtmp |= BIGMAC_TXCFG_FULLDPLX;
  1467. /* Don't turn on the "don't give up" bit for now. It could cause hme
  1468. * to deadlock with the PHY if a Jabber occurs.
  1469. */
  1470. hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
  1471. /* Give up after 16 TX attempts. */
  1472. hme_write32(hp, bregs + BMAC_ALIMIT, 16);
  1473. /* Enable the output drivers no matter what. */
  1474. regtmp = BIGMAC_XCFG_ODENABLE;
  1475. /* If card can do lance mode, enable it. */
  1476. if (hp->happy_flags & HFLAG_LANCE)
  1477. regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
  1478. /* Disable the MII buffers if using external transceiver. */
  1479. if (hp->tcvr_type == external)
  1480. regtmp |= BIGMAC_XCFG_MIIDISAB;
  1481. HMD(("XIF config old[%08x], ",
  1482. hme_read32(hp, bregs + BMAC_XIFCFG)));
  1483. hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
  1484. /* Start things up. */
  1485. HMD(("tx old[%08x] and rx [%08x] ON!\n",
  1486. hme_read32(hp, bregs + BMAC_TXCFG),
  1487. hme_read32(hp, bregs + BMAC_RXCFG)));
  1488. hme_write32(hp, bregs + BMAC_TXCFG,
  1489. hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
  1490. hme_write32(hp, bregs + BMAC_RXCFG,
  1491. hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
  1492. /* Get the autonegotiation started, and the watch timer ticking. */
  1493. happy_meal_begin_auto_negotiation(hp, tregs, NULL);
  1494. /* Success. */
  1495. return 0;
  1496. }
  1497. /* hp->happy_lock must be held */
  1498. static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
  1499. {
  1500. void __iomem *tregs = hp->tcvregs;
  1501. void __iomem *bregs = hp->bigmacregs;
  1502. void __iomem *gregs = hp->gregs;
  1503. happy_meal_stop(hp, gregs);
  1504. hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
  1505. if (hp->happy_flags & HFLAG_FENABLE)
  1506. hme_write32(hp, tregs + TCVR_CFG,
  1507. hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
  1508. else
  1509. hme_write32(hp, tregs + TCVR_CFG,
  1510. hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
  1511. happy_meal_transceiver_check(hp, tregs);
  1512. switch(hp->tcvr_type) {
  1513. case none:
  1514. return;
  1515. case internal:
  1516. hme_write32(hp, bregs + BMAC_XIFCFG, 0);
  1517. break;
  1518. case external:
  1519. hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
  1520. break;
  1521. };
  1522. if (happy_meal_tcvr_reset(hp, tregs))
  1523. return;
  1524. /* Latch PHY registers as of now. */
  1525. hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
  1526. hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
  1527. /* Advertise everything we can support. */
  1528. if (hp->sw_bmsr & BMSR_10HALF)
  1529. hp->sw_advertise |= (ADVERTISE_10HALF);
  1530. else
  1531. hp->sw_advertise &= ~(ADVERTISE_10HALF);
  1532. if (hp->sw_bmsr & BMSR_10FULL)
  1533. hp->sw_advertise |= (ADVERTISE_10FULL);
  1534. else
  1535. hp->sw_advertise &= ~(ADVERTISE_10FULL);
  1536. if (hp->sw_bmsr & BMSR_100HALF)
  1537. hp->sw_advertise |= (ADVERTISE_100HALF);
  1538. else
  1539. hp->sw_advertise &= ~(ADVERTISE_100HALF);
  1540. if (hp->sw_bmsr & BMSR_100FULL)
  1541. hp->sw_advertise |= (ADVERTISE_100FULL);
  1542. else
  1543. hp->sw_advertise &= ~(ADVERTISE_100FULL);
  1544. /* Update the PHY advertisement register. */
  1545. happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
  1546. }
  1547. /* Once status is latched (by happy_meal_interrupt) it is cleared by
  1548. * the hardware, so we cannot re-read it and get a correct value.
  1549. *
  1550. * hp->happy_lock must be held
  1551. */
  1552. static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
  1553. {
  1554. int reset = 0;
  1555. /* Only print messages for non-counter related interrupts. */
  1556. if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
  1557. GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
  1558. GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
  1559. GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
  1560. GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
  1561. GREG_STAT_SLVPERR))
  1562. printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
  1563. hp->dev->name, status);
  1564. if (status & GREG_STAT_RFIFOVF) {
  1565. /* Receive FIFO overflow is harmless and the hardware will take
  1566. care of it, just some packets are lost. Who cares. */
  1567. printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
  1568. }
  1569. if (status & GREG_STAT_STSTERR) {
  1570. /* BigMAC SQE link test failed. */
  1571. printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
  1572. reset = 1;
  1573. }
  1574. if (status & GREG_STAT_TFIFO_UND) {
  1575. /* Transmit FIFO underrun, again DMA error likely. */
  1576. printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
  1577. hp->dev->name);
  1578. reset = 1;
  1579. }
  1580. if (status & GREG_STAT_MAXPKTERR) {
  1581. /* Driver error, tried to transmit something larger
  1582. * than ethernet max mtu.
  1583. */
  1584. printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
  1585. reset = 1;
  1586. }
  1587. if (status & GREG_STAT_NORXD) {
  1588. /* This is harmless, it just means the system is
  1589. * quite loaded and the incoming packet rate was
  1590. * faster than the interrupt handler could keep up
  1591. * with.
  1592. */
  1593. printk(KERN_INFO "%s: Happy Meal out of receive "
  1594. "descriptors, packet dropped.\n",
  1595. hp->dev->name);
  1596. }
  1597. if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
  1598. /* All sorts of DMA receive errors. */
  1599. printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
  1600. if (status & GREG_STAT_RXERR)
  1601. printk("GenericError ");
  1602. if (status & GREG_STAT_RXPERR)
  1603. printk("ParityError ");
  1604. if (status & GREG_STAT_RXTERR)
  1605. printk("RxTagBotch ");
  1606. printk("]\n");
  1607. reset = 1;
  1608. }
  1609. if (status & GREG_STAT_EOPERR) {
  1610. /* Driver bug, didn't set EOP bit in tx descriptor given
  1611. * to the happy meal.
  1612. */
  1613. printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
  1614. hp->dev->name);
  1615. reset = 1;
  1616. }
  1617. if (status & GREG_STAT_MIFIRQ) {
  1618. /* MIF signalled an interrupt, were we polling it? */
  1619. printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
  1620. }
  1621. if (status &
  1622. (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
  1623. /* All sorts of transmit DMA errors. */
  1624. printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
  1625. if (status & GREG_STAT_TXEACK)
  1626. printk("GenericError ");
  1627. if (status & GREG_STAT_TXLERR)
  1628. printk("LateError ");
  1629. if (status & GREG_STAT_TXPERR)
  1630. printk("ParityErro ");
  1631. if (status & GREG_STAT_TXTERR)
  1632. printk("TagBotch ");
  1633. printk("]\n");
  1634. reset = 1;
  1635. }
  1636. if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
  1637. /* Bus or parity error when cpu accessed happy meal registers
  1638. * or it's internal FIFO's. Should never see this.
  1639. */
  1640. printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
  1641. hp->dev->name,
  1642. (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
  1643. reset = 1;
  1644. }
  1645. if (reset) {
  1646. printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
  1647. happy_meal_init(hp);
  1648. return 1;
  1649. }
  1650. return 0;
  1651. }
  1652. /* hp->happy_lock must be held */
  1653. static void happy_meal_mif_interrupt(struct happy_meal *hp)
  1654. {
  1655. void __iomem *tregs = hp->tcvregs;
  1656. printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
  1657. hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
  1658. hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
  1659. /* Use the fastest transmission protocol possible. */
  1660. if (hp->sw_lpa & LPA_100FULL) {
  1661. printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
  1662. hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
  1663. } else if (hp->sw_lpa & LPA_100HALF) {
  1664. printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
  1665. hp->sw_bmcr |= BMCR_SPEED100;
  1666. } else if (hp->sw_lpa & LPA_10FULL) {
  1667. printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
  1668. hp->sw_bmcr |= BMCR_FULLDPLX;
  1669. } else {
  1670. printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
  1671. }
  1672. happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
  1673. /* Finally stop polling and shut up the MIF. */
  1674. happy_meal_poll_stop(hp, tregs);
  1675. }
  1676. #ifdef TXDEBUG
  1677. #define TXD(x) printk x
  1678. #else
  1679. #define TXD(x)
  1680. #endif
  1681. /* hp->happy_lock must be held */
  1682. static void happy_meal_tx(struct happy_meal *hp)
  1683. {
  1684. struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
  1685. struct happy_meal_txd *this;
  1686. struct net_device *dev = hp->dev;
  1687. int elem;
  1688. elem = hp->tx_old;
  1689. TXD(("TX<"));
  1690. while (elem != hp->tx_new) {
  1691. struct sk_buff *skb;
  1692. u32 flags, dma_addr, dma_len;
  1693. int frag;
  1694. TXD(("[%d]", elem));
  1695. this = &txbase[elem];
  1696. flags = hme_read_desc32(hp, &this->tx_flags);
  1697. if (flags & TXFLAG_OWN)
  1698. break;
  1699. skb = hp->tx_skbs[elem];
  1700. if (skb_shinfo(skb)->nr_frags) {
  1701. int last;
  1702. last = elem + skb_shinfo(skb)->nr_frags;
  1703. last &= (TX_RING_SIZE - 1);
  1704. flags = hme_read_desc32(hp, &txbase[last].tx_flags);
  1705. if (flags & TXFLAG_OWN)
  1706. break;
  1707. }
  1708. hp->tx_skbs[elem] = NULL;
  1709. hp->net_stats.tx_bytes += skb->len;
  1710. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  1711. dma_addr = hme_read_desc32(hp, &this->tx_addr);
  1712. dma_len = hme_read_desc32(hp, &this->tx_flags);
  1713. dma_len &= TXFLAG_SIZE;
  1714. hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
  1715. elem = NEXT_TX(elem);
  1716. this = &txbase[elem];
  1717. }
  1718. dev_kfree_skb_irq(skb);
  1719. hp->net_stats.tx_packets++;
  1720. }
  1721. hp->tx_old = elem;
  1722. TXD((">"));
  1723. if (netif_queue_stopped(dev) &&
  1724. TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
  1725. netif_wake_queue(dev);
  1726. }
  1727. #ifdef RXDEBUG
  1728. #define RXD(x) printk x
  1729. #else
  1730. #define RXD(x)
  1731. #endif
  1732. /* Originally I used to handle the allocation failure by just giving back just
  1733. * that one ring buffer to the happy meal. Problem is that usually when that
  1734. * condition is triggered, the happy meal expects you to do something reasonable
  1735. * with all of the packets it has DMA'd in. So now I just drop the entire
  1736. * ring when we cannot get a new skb and give them all back to the happy meal,
  1737. * maybe things will be "happier" now.
  1738. *
  1739. * hp->happy_lock must be held
  1740. */
  1741. static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
  1742. {
  1743. struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
  1744. struct happy_meal_rxd *this;
  1745. int elem = hp->rx_new, drops = 0;
  1746. u32 flags;
  1747. RXD(("RX<"));
  1748. this = &rxbase[elem];
  1749. while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
  1750. struct sk_buff *skb;
  1751. int len = flags >> 16;
  1752. u16 csum = flags & RXFLAG_CSUM;
  1753. u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
  1754. RXD(("[%d ", elem));
  1755. /* Check for errors. */
  1756. if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
  1757. RXD(("ERR(%08x)]", flags));
  1758. hp->net_stats.rx_errors++;
  1759. if (len < ETH_ZLEN)
  1760. hp->net_stats.rx_length_errors++;
  1761. if (len & (RXFLAG_OVERFLOW >> 16)) {
  1762. hp->net_stats.rx_over_errors++;
  1763. hp->net_stats.rx_fifo_errors++;
  1764. }
  1765. /* Return it to the Happy meal. */
  1766. drop_it:
  1767. hp->net_stats.rx_dropped++;
  1768. hme_write_rxd(hp, this,
  1769. (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
  1770. dma_addr);
  1771. goto next;
  1772. }
  1773. skb = hp->rx_skbs[elem];
  1774. if (len > RX_COPY_THRESHOLD) {
  1775. struct sk_buff *new_skb;
  1776. /* Now refill the entry, if we can. */
  1777. new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
  1778. if (new_skb == NULL) {
  1779. drops++;
  1780. goto drop_it;
  1781. }
  1782. hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
  1783. hp->rx_skbs[elem] = new_skb;
  1784. new_skb->dev = dev;
  1785. skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
  1786. hme_write_rxd(hp, this,
  1787. (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
  1788. hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
  1789. skb_reserve(new_skb, RX_OFFSET);
  1790. /* Trim the original skb for the netif. */
  1791. skb_trim(skb, len);
  1792. } else {
  1793. struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
  1794. if (copy_skb == NULL) {
  1795. drops++;
  1796. goto drop_it;
  1797. }
  1798. copy_skb->dev = dev;
  1799. skb_reserve(copy_skb, 2);
  1800. skb_put(copy_skb, len);
  1801. hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
  1802. memcpy(copy_skb->data, skb->data, len);
  1803. hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
  1804. /* Reuse original ring buffer. */
  1805. hme_write_rxd(hp, this,
  1806. (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
  1807. dma_addr);
  1808. skb = copy_skb;
  1809. }
  1810. /* This card is _fucking_ hot... */
  1811. skb->csum = ntohs(csum ^ 0xffff);
  1812. skb->ip_summed = CHECKSUM_COMPLETE;
  1813. RXD(("len=%d csum=%4x]", len, csum));
  1814. skb->protocol = eth_type_trans(skb, dev);
  1815. netif_rx(skb);
  1816. dev->last_rx = jiffies;
  1817. hp->net_stats.rx_packets++;
  1818. hp->net_stats.rx_bytes += len;
  1819. next:
  1820. elem = NEXT_RX(elem);
  1821. this = &rxbase[elem];
  1822. }
  1823. hp->rx_new = elem;
  1824. if (drops)
  1825. printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
  1826. RXD((">"));
  1827. }
  1828. static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
  1829. {
  1830. struct net_device *dev = dev_id;
  1831. struct happy_meal *hp = netdev_priv(dev);
  1832. u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
  1833. HMD(("happy_meal_interrupt: status=%08x ", happy_status));
  1834. spin_lock(&hp->happy_lock);
  1835. if (happy_status & GREG_STAT_ERRORS) {
  1836. HMD(("ERRORS "));
  1837. if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
  1838. goto out;
  1839. }
  1840. if (happy_status & GREG_STAT_MIFIRQ) {
  1841. HMD(("MIFIRQ "));
  1842. happy_meal_mif_interrupt(hp);
  1843. }
  1844. if (happy_status & GREG_STAT_TXALL) {
  1845. HMD(("TXALL "));
  1846. happy_meal_tx(hp);
  1847. }
  1848. if (happy_status & GREG_STAT_RXTOHOST) {
  1849. HMD(("RXTOHOST "));
  1850. happy_meal_rx(hp, dev);
  1851. }
  1852. HMD(("done\n"));
  1853. out:
  1854. spin_unlock(&hp->happy_lock);
  1855. return IRQ_HANDLED;
  1856. }
  1857. #ifdef CONFIG_SBUS
  1858. static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
  1859. {
  1860. struct quattro *qp = (struct quattro *) cookie;
  1861. int i;
  1862. for (i = 0; i < 4; i++) {
  1863. struct net_device *dev = qp->happy_meals[i];
  1864. struct happy_meal *hp = dev->priv;
  1865. u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
  1866. HMD(("quattro_interrupt: status=%08x ", happy_status));
  1867. if (!(happy_status & (GREG_STAT_ERRORS |
  1868. GREG_STAT_MIFIRQ |
  1869. GREG_STAT_TXALL |
  1870. GREG_STAT_RXTOHOST)))
  1871. continue;
  1872. spin_lock(&hp->happy_lock);
  1873. if (happy_status & GREG_STAT_ERRORS) {
  1874. HMD(("ERRORS "));
  1875. if (happy_meal_is_not_so_happy(hp, happy_status))
  1876. goto next;
  1877. }
  1878. if (happy_status & GREG_STAT_MIFIRQ) {
  1879. HMD(("MIFIRQ "));
  1880. happy_meal_mif_interrupt(hp);
  1881. }
  1882. if (happy_status & GREG_STAT_TXALL) {
  1883. HMD(("TXALL "));
  1884. happy_meal_tx(hp);
  1885. }
  1886. if (happy_status & GREG_STAT_RXTOHOST) {
  1887. HMD(("RXTOHOST "));
  1888. happy_meal_rx(hp, dev);
  1889. }
  1890. next:
  1891. spin_unlock(&hp->happy_lock);
  1892. }
  1893. HMD(("done\n"));
  1894. return IRQ_HANDLED;
  1895. }
  1896. #endif
  1897. static int happy_meal_open(struct net_device *dev)
  1898. {
  1899. struct happy_meal *hp = dev->priv;
  1900. int res;
  1901. HMD(("happy_meal_open: "));
  1902. /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
  1903. * into a single source which we register handling at probe time.
  1904. */
  1905. if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
  1906. if (request_irq(dev->irq, &happy_meal_interrupt,
  1907. IRQF_SHARED, dev->name, (void *)dev)) {
  1908. HMD(("EAGAIN\n"));
  1909. printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
  1910. dev->irq);
  1911. return -EAGAIN;
  1912. }
  1913. }
  1914. HMD(("to happy_meal_init\n"));
  1915. spin_lock_irq(&hp->happy_lock);
  1916. res = happy_meal_init(hp);
  1917. spin_unlock_irq(&hp->happy_lock);
  1918. if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
  1919. free_irq(dev->irq, dev);
  1920. return res;
  1921. }
  1922. static int happy_meal_close(struct net_device *dev)
  1923. {
  1924. struct happy_meal *hp = dev->priv;
  1925. spin_lock_irq(&hp->happy_lock);
  1926. happy_meal_stop(hp, hp->gregs);
  1927. happy_meal_clean_rings(hp);
  1928. /* If auto-negotiation timer is running, kill it. */
  1929. del_timer(&hp->happy_timer);
  1930. spin_unlock_irq(&hp->happy_lock);
  1931. /* On Quattro QFE cards, all hme interrupts are concentrated
  1932. * into a single source which we register handling at probe
  1933. * time and never unregister.
  1934. */
  1935. if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
  1936. free_irq(dev->irq, dev);
  1937. return 0;
  1938. }
  1939. #ifdef SXDEBUG
  1940. #define SXD(x) printk x
  1941. #else
  1942. #define SXD(x)
  1943. #endif
  1944. static void happy_meal_tx_timeout(struct net_device *dev)
  1945. {
  1946. struct happy_meal *hp = dev->priv;
  1947. printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
  1948. tx_dump_log();
  1949. printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
  1950. hme_read32(hp, hp->gregs + GREG_STAT),
  1951. hme_read32(hp, hp->etxregs + ETX_CFG),
  1952. hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
  1953. spin_lock_irq(&hp->happy_lock);
  1954. happy_meal_init(hp);
  1955. spin_unlock_irq(&hp->happy_lock);
  1956. netif_wake_queue(dev);
  1957. }
  1958. static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1959. {
  1960. struct happy_meal *hp = dev->priv;
  1961. int entry;
  1962. u32 tx_flags;
  1963. tx_flags = TXFLAG_OWN;
  1964. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1965. u32 csum_start_off, csum_stuff_off;
  1966. csum_start_off = (u32) (skb->h.raw - skb->data);
  1967. csum_stuff_off = csum_start_off + skb->csum_offset;
  1968. tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
  1969. ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
  1970. ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
  1971. }
  1972. spin_lock_irq(&hp->happy_lock);
  1973. if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
  1974. netif_stop_queue(dev);
  1975. spin_unlock_irq(&hp->happy_lock);
  1976. printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
  1977. dev->name);
  1978. return 1;
  1979. }
  1980. entry = hp->tx_new;
  1981. SXD(("SX<l[%d]e[%d]>", len, entry));
  1982. hp->tx_skbs[entry] = skb;
  1983. if (skb_shinfo(skb)->nr_frags == 0) {
  1984. u32 mapping, len;
  1985. len = skb->len;
  1986. mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
  1987. tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
  1988. hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
  1989. (tx_flags | (len & TXFLAG_SIZE)),
  1990. mapping);
  1991. entry = NEXT_TX(entry);
  1992. } else {
  1993. u32 first_len, first_mapping;
  1994. int frag, first_entry = entry;
  1995. /* We must give this initial chunk to the device last.
  1996. * Otherwise we could race with the device.
  1997. */
  1998. first_len = skb_headlen(skb);
  1999. first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
  2000. entry = NEXT_TX(entry);
  2001. for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
  2002. skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
  2003. u32 len, mapping, this_txflags;
  2004. len = this_frag->size;
  2005. mapping = hme_dma_map(hp,
  2006. ((void *) page_address(this_frag->page) +
  2007. this_frag->page_offset),
  2008. len, DMA_TODEVICE);
  2009. this_txflags = tx_flags;
  2010. if (frag == skb_shinfo(skb)->nr_frags - 1)
  2011. this_txflags |= TXFLAG_EOP;
  2012. hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
  2013. (this_txflags | (len & TXFLAG_SIZE)),
  2014. mapping);
  2015. entry = NEXT_TX(entry);
  2016. }
  2017. hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
  2018. (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
  2019. first_mapping);
  2020. }
  2021. hp->tx_new = entry;
  2022. if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
  2023. netif_stop_queue(dev);
  2024. /* Get it going. */
  2025. hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
  2026. spin_unlock_irq(&hp->happy_lock);
  2027. dev->trans_start = jiffies;
  2028. tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
  2029. return 0;
  2030. }
  2031. static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
  2032. {
  2033. struct happy_meal *hp = dev->priv;
  2034. spin_lock_irq(&hp->happy_lock);
  2035. happy_meal_get_counters(hp, hp->bigmacregs);
  2036. spin_unlock_irq(&hp->happy_lock);
  2037. return &hp->net_stats;
  2038. }
  2039. static void happy_meal_set_multicast(struct net_device *dev)
  2040. {
  2041. struct happy_meal *hp = dev->priv;
  2042. void __iomem *bregs = hp->bigmacregs;
  2043. struct dev_mc_list *dmi = dev->mc_list;
  2044. char *addrs;
  2045. int i;
  2046. u32 crc;
  2047. spin_lock_irq(&hp->happy_lock);
  2048. netif_stop_queue(dev);
  2049. if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
  2050. hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
  2051. hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
  2052. hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
  2053. hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
  2054. } else if (dev->flags & IFF_PROMISC) {
  2055. hme_write32(hp, bregs + BMAC_RXCFG,
  2056. hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
  2057. } else {
  2058. u16 hash_table[4];
  2059. for (i = 0; i < 4; i++)
  2060. hash_table[i] = 0;
  2061. for (i = 0; i < dev->mc_count; i++) {
  2062. addrs = dmi->dmi_addr;
  2063. dmi = dmi->next;
  2064. if (!(*addrs & 1))
  2065. continue;
  2066. crc = ether_crc_le(6, addrs);
  2067. crc >>= 26;
  2068. hash_table[crc >> 4] |= 1 << (crc & 0xf);
  2069. }
  2070. hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
  2071. hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
  2072. hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
  2073. hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
  2074. }
  2075. netif_wake_queue(dev);
  2076. spin_unlock_irq(&hp->happy_lock);
  2077. }
  2078. /* Ethtool support... */
  2079. static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2080. {
  2081. struct happy_meal *hp = dev->priv;
  2082. cmd->supported =
  2083. (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  2084. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  2085. SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
  2086. /* XXX hardcoded stuff for now */
  2087. cmd->port = PORT_TP; /* XXX no MII support */
  2088. cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
  2089. cmd->phy_address = 0; /* XXX fixed PHYAD */
  2090. /* Record PHY settings. */
  2091. spin_lock_irq(&hp->happy_lock);
  2092. hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
  2093. hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
  2094. spin_unlock_irq(&hp->happy_lock);
  2095. if (hp->sw_bmcr & BMCR_ANENABLE) {
  2096. cmd->autoneg = AUTONEG_ENABLE;
  2097. cmd->speed =
  2098. (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
  2099. SPEED_100 : SPEED_10;
  2100. if (cmd->speed == SPEED_100)
  2101. cmd->duplex =
  2102. (hp->sw_lpa & (LPA_100FULL)) ?
  2103. DUPLEX_FULL : DUPLEX_HALF;
  2104. else
  2105. cmd->duplex =
  2106. (hp->sw_lpa & (LPA_10FULL)) ?
  2107. DUPLEX_FULL : DUPLEX_HALF;
  2108. } else {
  2109. cmd->autoneg = AUTONEG_DISABLE;
  2110. cmd->speed =
  2111. (hp->sw_bmcr & BMCR_SPEED100) ?
  2112. SPEED_100 : SPEED_10;
  2113. cmd->duplex =
  2114. (hp->sw_bmcr & BMCR_FULLDPLX) ?
  2115. DUPLEX_FULL : DUPLEX_HALF;
  2116. }
  2117. return 0;
  2118. }
  2119. static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2120. {
  2121. struct happy_meal *hp = dev->priv;
  2122. /* Verify the settings we care about. */
  2123. if (cmd->autoneg != AUTONEG_ENABLE &&
  2124. cmd->autoneg != AUTONEG_DISABLE)
  2125. return -EINVAL;
  2126. if (cmd->autoneg == AUTONEG_DISABLE &&
  2127. ((cmd->speed != SPEED_100 &&
  2128. cmd->speed != SPEED_10) ||
  2129. (cmd->duplex != DUPLEX_HALF &&
  2130. cmd->duplex != DUPLEX_FULL)))
  2131. return -EINVAL;
  2132. /* Ok, do it to it. */
  2133. spin_lock_irq(&hp->happy_lock);
  2134. del_timer(&hp->happy_timer);
  2135. happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
  2136. spin_unlock_irq(&hp->happy_lock);
  2137. return 0;
  2138. }
  2139. static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  2140. {
  2141. struct happy_meal *hp = dev->priv;
  2142. strcpy(info->driver, "sunhme");
  2143. strcpy(info->version, "2.02");
  2144. if (hp->happy_flags & HFLAG_PCI) {
  2145. struct pci_dev *pdev = hp->happy_dev;
  2146. strcpy(info->bus_info, pci_name(pdev));
  2147. }
  2148. #ifdef CONFIG_SBUS
  2149. else {
  2150. struct sbus_dev *sdev = hp->happy_dev;
  2151. sprintf(info->bus_info, "SBUS:%d",
  2152. sdev->slot);
  2153. }
  2154. #endif
  2155. }
  2156. static u32 hme_get_link(struct net_device *dev)
  2157. {
  2158. struct happy_meal *hp = dev->priv;
  2159. spin_lock_irq(&hp->happy_lock);
  2160. hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
  2161. spin_unlock_irq(&hp->happy_lock);
  2162. return (hp->sw_bmsr & BMSR_LSTATUS);
  2163. }
  2164. static const struct ethtool_ops hme_ethtool_ops = {
  2165. .get_settings = hme_get_settings,
  2166. .set_settings = hme_set_settings,
  2167. .get_drvinfo = hme_get_drvinfo,
  2168. .get_link = hme_get_link,
  2169. };
  2170. static int hme_version_printed;
  2171. #ifdef CONFIG_SBUS
  2172. void __devinit quattro_get_ranges(struct quattro *qp)
  2173. {
  2174. struct sbus_dev *sdev = qp->quattro_dev;
  2175. int err;
  2176. err = prom_getproperty(sdev->prom_node,
  2177. "ranges",
  2178. (char *)&qp->ranges[0],
  2179. sizeof(qp->ranges));
  2180. if (err == 0 || err == -1) {
  2181. qp->nranges = 0;
  2182. return;
  2183. }
  2184. qp->nranges = (err / sizeof(struct linux_prom_ranges));
  2185. }
  2186. static void __devinit quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
  2187. {
  2188. struct sbus_dev *sdev = hp->happy_dev;
  2189. int rng;
  2190. for (rng = 0; rng < qp->nranges; rng++) {
  2191. struct linux_prom_ranges *rngp = &qp->ranges[rng];
  2192. int reg;
  2193. for (reg = 0; reg < 5; reg++) {
  2194. if (sdev->reg_addrs[reg].which_io ==
  2195. rngp->ot_child_space)
  2196. break;
  2197. }
  2198. if (reg == 5)
  2199. continue;
  2200. sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
  2201. sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
  2202. }
  2203. }
  2204. /* Given a happy meal sbus device, find it's quattro parent.
  2205. * If none exist, allocate and return a new one.
  2206. *
  2207. * Return NULL on failure.
  2208. */
  2209. static struct quattro * __devinit quattro_sbus_find(struct sbus_dev *goal_sdev)
  2210. {
  2211. struct sbus_dev *sdev;
  2212. struct quattro *qp;
  2213. int i;
  2214. for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
  2215. for (i = 0, sdev = qp->quattro_dev;
  2216. (sdev != NULL) && (i < 4);
  2217. sdev = sdev->next, i++) {
  2218. if (sdev == goal_sdev)
  2219. return qp;
  2220. }
  2221. }
  2222. qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
  2223. if (qp != NULL) {
  2224. int i;
  2225. for (i = 0; i < 4; i++)
  2226. qp->happy_meals[i] = NULL;
  2227. qp->quattro_dev = goal_sdev;
  2228. qp->next = qfe_sbus_list;
  2229. qfe_sbus_list = qp;
  2230. quattro_get_ranges(qp);
  2231. }
  2232. return qp;
  2233. }
  2234. /* After all quattro cards have been probed, we call these functions
  2235. * to register the IRQ handlers.
  2236. */
  2237. static void __init quattro_sbus_register_irqs(void)
  2238. {
  2239. struct quattro *qp;
  2240. for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
  2241. struct sbus_dev *sdev = qp->quattro_dev;
  2242. int err;
  2243. err = request_irq(sdev->irqs[0],
  2244. quattro_sbus_interrupt,
  2245. IRQF_SHARED, "Quattro",
  2246. qp);
  2247. if (err != 0) {
  2248. printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
  2249. panic("QFE request irq");
  2250. }
  2251. }
  2252. }
  2253. static void quattro_sbus_free_irqs(void)
  2254. {
  2255. struct quattro *qp;
  2256. for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
  2257. struct sbus_dev *sdev = qp->quattro_dev;
  2258. free_irq(sdev->irqs[0], qp);
  2259. }
  2260. }
  2261. #endif /* CONFIG_SBUS */
  2262. #ifdef CONFIG_PCI
  2263. static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
  2264. {
  2265. struct pci_dev *bdev = pdev->bus->self;
  2266. struct quattro *qp;
  2267. if (!bdev) return NULL;
  2268. for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
  2269. struct pci_dev *qpdev = qp->quattro_dev;
  2270. if (qpdev == bdev)
  2271. return qp;
  2272. }
  2273. qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
  2274. if (qp != NULL) {
  2275. int i;
  2276. for (i = 0; i < 4; i++)
  2277. qp->happy_meals[i] = NULL;
  2278. qp->quattro_dev = bdev;
  2279. qp->next = qfe_pci_list;
  2280. qfe_pci_list = qp;
  2281. /* No range tricks necessary on PCI. */
  2282. qp->nranges = 0;
  2283. }
  2284. return qp;
  2285. }
  2286. #endif /* CONFIG_PCI */
  2287. #ifdef CONFIG_SBUS
  2288. static int __devinit happy_meal_sbus_probe_one(struct sbus_dev *sdev, int is_qfe)
  2289. {
  2290. struct device_node *dp = sdev->ofdev.node;
  2291. struct quattro *qp = NULL;
  2292. struct happy_meal *hp;
  2293. struct net_device *dev;
  2294. int i, qfe_slot = -1;
  2295. int err = -ENODEV;
  2296. if (is_qfe) {
  2297. qp = quattro_sbus_find(sdev);
  2298. if (qp == NULL)
  2299. goto err_out;
  2300. for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
  2301. if (qp->happy_meals[qfe_slot] == NULL)
  2302. break;
  2303. if (qfe_slot == 4)
  2304. goto err_out;
  2305. }
  2306. err = -ENOMEM;
  2307. dev = alloc_etherdev(sizeof(struct happy_meal));
  2308. if (!dev)
  2309. goto err_out;
  2310. SET_MODULE_OWNER(dev);
  2311. SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
  2312. if (hme_version_printed++ == 0)
  2313. printk(KERN_INFO "%s", version);
  2314. /* If user did not specify a MAC address specifically, use
  2315. * the Quattro local-mac-address property...
  2316. */
  2317. for (i = 0; i < 6; i++) {
  2318. if (macaddr[i] != 0)
  2319. break;
  2320. }
  2321. if (i < 6) { /* a mac address was given */
  2322. for (i = 0; i < 6; i++)
  2323. dev->dev_addr[i] = macaddr[i];
  2324. macaddr[5]++;
  2325. } else {
  2326. unsigned char *addr;
  2327. int len;
  2328. addr = of_get_property(dp, "local-mac-address", &len);
  2329. if (qfe_slot != -1 && addr && len == 6)
  2330. memcpy(dev->dev_addr, addr, 6);
  2331. else
  2332. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  2333. }
  2334. hp = dev->priv;
  2335. hp->happy_dev = sdev;
  2336. spin_lock_init(&hp->happy_lock);
  2337. err = -ENODEV;
  2338. if (sdev->num_registers != 5) {
  2339. printk(KERN_ERR "happymeal: Device needs 5 regs, has %d.\n",
  2340. sdev->num_registers);
  2341. goto err_out_free_netdev;
  2342. }
  2343. if (qp != NULL) {
  2344. hp->qfe_parent = qp;
  2345. hp->qfe_ent = qfe_slot;
  2346. qp->happy_meals[qfe_slot] = dev;
  2347. quattro_apply_ranges(qp, hp);
  2348. }
  2349. hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
  2350. GREG_REG_SIZE, "HME Global Regs");
  2351. if (!hp->gregs) {
  2352. printk(KERN_ERR "happymeal: Cannot map global registers.\n");
  2353. goto err_out_free_netdev;
  2354. }
  2355. hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
  2356. ETX_REG_SIZE, "HME TX Regs");
  2357. if (!hp->etxregs) {
  2358. printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
  2359. goto err_out_iounmap;
  2360. }
  2361. hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
  2362. ERX_REG_SIZE, "HME RX Regs");
  2363. if (!hp->erxregs) {
  2364. printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
  2365. goto err_out_iounmap;
  2366. }
  2367. hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
  2368. BMAC_REG_SIZE, "HME BIGMAC Regs");
  2369. if (!hp->bigmacregs) {
  2370. printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
  2371. goto err_out_iounmap;
  2372. }
  2373. hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
  2374. TCVR_REG_SIZE, "HME Tranceiver Regs");
  2375. if (!hp->tcvregs) {
  2376. printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
  2377. goto err_out_iounmap;
  2378. }
  2379. hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
  2380. if (hp->hm_revision == 0xff)
  2381. hp->hm_revision = 0xa0;
  2382. /* Now enable the feature flags we can. */
  2383. if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
  2384. hp->happy_flags = HFLAG_20_21;
  2385. else if (hp->hm_revision != 0xa0)
  2386. hp->happy_flags = HFLAG_NOT_A0;
  2387. if (qp != NULL)
  2388. hp->happy_flags |= HFLAG_QUATTRO;
  2389. /* Get the supported DVMA burst sizes from our Happy SBUS. */
  2390. hp->happy_bursts = of_getintprop_default(sdev->bus->ofdev.node,
  2391. "burst-sizes", 0x00);
  2392. hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
  2393. PAGE_SIZE,
  2394. &hp->hblock_dvma);
  2395. err = -ENOMEM;
  2396. if (!hp->happy_block) {
  2397. printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
  2398. goto err_out_iounmap;
  2399. }
  2400. /* Force check of the link first time we are brought up. */
  2401. hp->linkcheck = 0;
  2402. /* Force timer state to 'asleep' with count of zero. */
  2403. hp->timer_state = asleep;
  2404. hp->timer_ticks = 0;
  2405. init_timer(&hp->happy_timer);
  2406. hp->dev = dev;
  2407. dev->open = &happy_meal_open;
  2408. dev->stop = &happy_meal_close;
  2409. dev->hard_start_xmit = &happy_meal_start_xmit;
  2410. dev->get_stats = &happy_meal_get_stats;
  2411. dev->set_multicast_list = &happy_meal_set_multicast;
  2412. dev->tx_timeout = &happy_meal_tx_timeout;
  2413. dev->watchdog_timeo = 5*HZ;
  2414. dev->ethtool_ops = &hme_ethtool_ops;
  2415. /* Happy Meal can do it all... except VLAN. */
  2416. dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED;
  2417. dev->irq = sdev->irqs[0];
  2418. #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
  2419. /* Hook up PCI register/dma accessors. */
  2420. hp->read_desc32 = sbus_hme_read_desc32;
  2421. hp->write_txd = sbus_hme_write_txd;
  2422. hp->write_rxd = sbus_hme_write_rxd;
  2423. hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
  2424. hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
  2425. hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
  2426. sbus_dma_sync_single_for_cpu;
  2427. hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
  2428. sbus_dma_sync_single_for_device;
  2429. hp->read32 = sbus_hme_read32;
  2430. hp->write32 = sbus_hme_write32;
  2431. #endif
  2432. /* Grrr, Happy Meal comes up by default not advertising
  2433. * full duplex 100baseT capabilities, fix this.
  2434. */
  2435. spin_lock_irq(&hp->happy_lock);
  2436. happy_meal_set_initial_advertisement(hp);
  2437. spin_unlock_irq(&hp->happy_lock);
  2438. if (register_netdev(hp->dev)) {
  2439. printk(KERN_ERR "happymeal: Cannot register net device, "
  2440. "aborting.\n");
  2441. goto err_out_free_consistent;
  2442. }
  2443. dev_set_drvdata(&sdev->ofdev.dev, hp);
  2444. if (qfe_slot != -1)
  2445. printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
  2446. dev->name, qfe_slot);
  2447. else
  2448. printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
  2449. dev->name);
  2450. for (i = 0; i < 6; i++)
  2451. printk("%2.2x%c",
  2452. dev->dev_addr[i], i == 5 ? ' ' : ':');
  2453. printk("\n");
  2454. return 0;
  2455. err_out_free_consistent:
  2456. sbus_free_consistent(hp->happy_dev,
  2457. PAGE_SIZE,
  2458. hp->happy_block,
  2459. hp->hblock_dvma);
  2460. err_out_iounmap:
  2461. if (hp->gregs)
  2462. sbus_iounmap(hp->gregs, GREG_REG_SIZE);
  2463. if (hp->etxregs)
  2464. sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
  2465. if (hp->erxregs)
  2466. sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
  2467. if (hp->bigmacregs)
  2468. sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
  2469. if (hp->tcvregs)
  2470. sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
  2471. err_out_free_netdev:
  2472. free_netdev(dev);
  2473. err_out:
  2474. return err;
  2475. }
  2476. #endif
  2477. #ifdef CONFIG_PCI
  2478. #ifndef CONFIG_SPARC
  2479. static int is_quattro_p(struct pci_dev *pdev)
  2480. {
  2481. struct pci_dev *busdev = pdev->bus->self;
  2482. struct list_head *tmp;
  2483. int n_hmes;
  2484. if (busdev == NULL ||
  2485. busdev->vendor != PCI_VENDOR_ID_DEC ||
  2486. busdev->device != PCI_DEVICE_ID_DEC_21153)
  2487. return 0;
  2488. n_hmes = 0;
  2489. tmp = pdev->bus->devices.next;
  2490. while (tmp != &pdev->bus->devices) {
  2491. struct pci_dev *this_pdev = pci_dev_b(tmp);
  2492. if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
  2493. this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
  2494. n_hmes++;
  2495. tmp = tmp->next;
  2496. }
  2497. if (n_hmes != 4)
  2498. return 0;
  2499. return 1;
  2500. }
  2501. /* Fetch MAC address from vital product data of PCI ROM. */
  2502. static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
  2503. {
  2504. int this_offset;
  2505. for (this_offset = 0x20; this_offset < len; this_offset++) {
  2506. void __iomem *p = rom_base + this_offset;
  2507. if (readb(p + 0) != 0x90 ||
  2508. readb(p + 1) != 0x00 ||
  2509. readb(p + 2) != 0x09 ||
  2510. readb(p + 3) != 0x4e ||
  2511. readb(p + 4) != 0x41 ||
  2512. readb(p + 5) != 0x06)
  2513. continue;
  2514. this_offset += 6;
  2515. p += 6;
  2516. if (index == 0) {
  2517. int i;
  2518. for (i = 0; i < 6; i++)
  2519. dev_addr[i] = readb(p + i);
  2520. return 1;
  2521. }
  2522. index--;
  2523. }
  2524. return 0;
  2525. }
  2526. static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
  2527. {
  2528. size_t size;
  2529. void __iomem *p = pci_map_rom(pdev, &size);
  2530. if (p) {
  2531. int index = 0;
  2532. int found;
  2533. if (is_quattro_p(pdev))
  2534. index = PCI_SLOT(pdev->devfn);
  2535. found = readb(p) == 0x55 &&
  2536. readb(p + 1) == 0xaa &&
  2537. find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
  2538. pci_unmap_rom(pdev, p);
  2539. if (found)
  2540. return;
  2541. }
  2542. /* Sun MAC prefix then 3 random bytes. */
  2543. dev_addr[0] = 0x08;
  2544. dev_addr[1] = 0x00;
  2545. dev_addr[2] = 0x20;
  2546. get_random_bytes(&dev_addr[3], 3);
  2547. return;
  2548. }
  2549. #endif /* !(CONFIG_SPARC) */
  2550. static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
  2551. const struct pci_device_id *ent)
  2552. {
  2553. struct quattro *qp = NULL;
  2554. #ifdef CONFIG_SPARC
  2555. struct pcidev_cookie *pcp;
  2556. #endif
  2557. struct happy_meal *hp;
  2558. struct net_device *dev;
  2559. void __iomem *hpreg_base;
  2560. unsigned long hpreg_res;
  2561. int i, qfe_slot = -1;
  2562. char prom_name[64];
  2563. int err;
  2564. /* Now make sure pci_dev cookie is there. */
  2565. #ifdef CONFIG_SPARC
  2566. pcp = pdev->sysdata;
  2567. if (pcp == NULL) {
  2568. printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
  2569. return -ENODEV;
  2570. }
  2571. strcpy(prom_name, pcp->prom_node->name);
  2572. #else
  2573. if (is_quattro_p(pdev))
  2574. strcpy(prom_name, "SUNW,qfe");
  2575. else
  2576. strcpy(prom_name, "SUNW,hme");
  2577. #endif
  2578. err = -ENODEV;
  2579. if (pci_enable_device(pdev))
  2580. goto err_out;
  2581. pci_set_master(pdev);
  2582. if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
  2583. qp = quattro_pci_find(pdev);
  2584. if (qp == NULL)
  2585. goto err_out;
  2586. for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
  2587. if (qp->happy_meals[qfe_slot] == NULL)
  2588. break;
  2589. if (qfe_slot == 4)
  2590. goto err_out;
  2591. }
  2592. dev = alloc_etherdev(sizeof(struct happy_meal));
  2593. err = -ENOMEM;
  2594. if (!dev)
  2595. goto err_out;
  2596. SET_MODULE_OWNER(dev);
  2597. SET_NETDEV_DEV(dev, &pdev->dev);
  2598. if (hme_version_printed++ == 0)
  2599. printk(KERN_INFO "%s", version);
  2600. dev->base_addr = (long) pdev;
  2601. hp = (struct happy_meal *)dev->priv;
  2602. memset(hp, 0, sizeof(*hp));
  2603. hp->happy_dev = pdev;
  2604. spin_lock_init(&hp->happy_lock);
  2605. if (qp != NULL) {
  2606. hp->qfe_parent = qp;
  2607. hp->qfe_ent = qfe_slot;
  2608. qp->happy_meals[qfe_slot] = dev;
  2609. }
  2610. hpreg_res = pci_resource_start(pdev, 0);
  2611. err = -ENODEV;
  2612. if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
  2613. printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
  2614. goto err_out_clear_quattro;
  2615. }
  2616. if (pci_request_regions(pdev, DRV_NAME)) {
  2617. printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
  2618. "aborting.\n");
  2619. goto err_out_clear_quattro;
  2620. }
  2621. if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
  2622. printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
  2623. goto err_out_free_res;
  2624. }
  2625. for (i = 0; i < 6; i++) {
  2626. if (macaddr[i] != 0)
  2627. break;
  2628. }
  2629. if (i < 6) { /* a mac address was given */
  2630. for (i = 0; i < 6; i++)
  2631. dev->dev_addr[i] = macaddr[i];
  2632. macaddr[5]++;
  2633. } else {
  2634. #ifdef CONFIG_SPARC
  2635. unsigned char *addr;
  2636. int len;
  2637. if (qfe_slot != -1 &&
  2638. (addr = of_get_property(pcp->prom_node,
  2639. "local-mac-address", &len)) != NULL
  2640. && len == 6) {
  2641. memcpy(dev->dev_addr, addr, 6);
  2642. } else {
  2643. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  2644. }
  2645. #else
  2646. get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
  2647. #endif
  2648. }
  2649. /* Layout registers. */
  2650. hp->gregs = (hpreg_base + 0x0000UL);
  2651. hp->etxregs = (hpreg_base + 0x2000UL);
  2652. hp->erxregs = (hpreg_base + 0x4000UL);
  2653. hp->bigmacregs = (hpreg_base + 0x6000UL);
  2654. hp->tcvregs = (hpreg_base + 0x7000UL);
  2655. #ifdef CONFIG_SPARC
  2656. hp->hm_revision = of_getintprop_default(pcp->prom_node, "hm-rev", 0xff);
  2657. if (hp->hm_revision == 0xff) {
  2658. unsigned char prev;
  2659. pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
  2660. hp->hm_revision = 0xc0 | (prev & 0x0f);
  2661. }
  2662. #else
  2663. /* works with this on non-sparc hosts */
  2664. hp->hm_revision = 0x20;
  2665. #endif
  2666. /* Now enable the feature flags we can. */
  2667. if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
  2668. hp->happy_flags = HFLAG_20_21;
  2669. else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
  2670. hp->happy_flags = HFLAG_NOT_A0;
  2671. if (qp != NULL)
  2672. hp->happy_flags |= HFLAG_QUATTRO;
  2673. /* And of course, indicate this is PCI. */
  2674. hp->happy_flags |= HFLAG_PCI;
  2675. #ifdef CONFIG_SPARC
  2676. /* Assume PCI happy meals can handle all burst sizes. */
  2677. hp->happy_bursts = DMA_BURSTBITS;
  2678. #endif
  2679. hp->happy_block = (struct hmeal_init_block *)
  2680. pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
  2681. err = -ENODEV;
  2682. if (!hp->happy_block) {
  2683. printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
  2684. goto err_out_iounmap;
  2685. }
  2686. hp->linkcheck = 0;
  2687. hp->timer_state = asleep;
  2688. hp->timer_ticks = 0;
  2689. init_timer(&hp->happy_timer);
  2690. hp->dev = dev;
  2691. dev->open = &happy_meal_open;
  2692. dev->stop = &happy_meal_close;
  2693. dev->hard_start_xmit = &happy_meal_start_xmit;
  2694. dev->get_stats = &happy_meal_get_stats;
  2695. dev->set_multicast_list = &happy_meal_set_multicast;
  2696. dev->tx_timeout = &happy_meal_tx_timeout;
  2697. dev->watchdog_timeo = 5*HZ;
  2698. dev->ethtool_ops = &hme_ethtool_ops;
  2699. dev->irq = pdev->irq;
  2700. dev->dma = 0;
  2701. /* Happy Meal can do it all... */
  2702. dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
  2703. #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
  2704. /* Hook up PCI register/dma accessors. */
  2705. hp->read_desc32 = pci_hme_read_desc32;
  2706. hp->write_txd = pci_hme_write_txd;
  2707. hp->write_rxd = pci_hme_write_rxd;
  2708. hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
  2709. hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
  2710. hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
  2711. pci_dma_sync_single_for_cpu;
  2712. hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
  2713. pci_dma_sync_single_for_device;
  2714. hp->read32 = pci_hme_read32;
  2715. hp->write32 = pci_hme_write32;
  2716. #endif
  2717. /* Grrr, Happy Meal comes up by default not advertising
  2718. * full duplex 100baseT capabilities, fix this.
  2719. */
  2720. spin_lock_irq(&hp->happy_lock);
  2721. happy_meal_set_initial_advertisement(hp);
  2722. spin_unlock_irq(&hp->happy_lock);
  2723. if (register_netdev(hp->dev)) {
  2724. printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
  2725. "aborting.\n");
  2726. goto err_out_iounmap;
  2727. }
  2728. dev_set_drvdata(&pdev->dev, hp);
  2729. if (!qfe_slot) {
  2730. struct pci_dev *qpdev = qp->quattro_dev;
  2731. prom_name[0] = 0;
  2732. if (!strncmp(dev->name, "eth", 3)) {
  2733. int i = simple_strtoul(dev->name + 3, NULL, 10);
  2734. sprintf(prom_name, "-%d", i + 3);
  2735. }
  2736. printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
  2737. if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
  2738. qpdev->device == PCI_DEVICE_ID_DEC_21153)
  2739. printk("DEC 21153 PCI Bridge\n");
  2740. else
  2741. printk("unknown bridge %04x.%04x\n",
  2742. qpdev->vendor, qpdev->device);
  2743. }
  2744. if (qfe_slot != -1)
  2745. printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
  2746. dev->name, qfe_slot);
  2747. else
  2748. printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
  2749. dev->name);
  2750. for (i = 0; i < 6; i++)
  2751. printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
  2752. printk("\n");
  2753. return 0;
  2754. err_out_iounmap:
  2755. iounmap(hp->gregs);
  2756. err_out_free_res:
  2757. pci_release_regions(pdev);
  2758. err_out_clear_quattro:
  2759. if (qp != NULL)
  2760. qp->happy_meals[qfe_slot] = NULL;
  2761. free_netdev(dev);
  2762. err_out:
  2763. return err;
  2764. }
  2765. static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
  2766. {
  2767. struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
  2768. struct net_device *net_dev = hp->dev;
  2769. unregister_netdev(net_dev);
  2770. pci_free_consistent(hp->happy_dev,
  2771. PAGE_SIZE,
  2772. hp->happy_block,
  2773. hp->hblock_dvma);
  2774. iounmap(hp->gregs);
  2775. pci_release_regions(hp->happy_dev);
  2776. free_netdev(net_dev);
  2777. dev_set_drvdata(&pdev->dev, NULL);
  2778. }
  2779. static struct pci_device_id happymeal_pci_ids[] = {
  2780. { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
  2781. { } /* Terminating entry */
  2782. };
  2783. MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
  2784. static struct pci_driver hme_pci_driver = {
  2785. .name = "hme",
  2786. .id_table = happymeal_pci_ids,
  2787. .probe = happy_meal_pci_probe,
  2788. .remove = __devexit_p(happy_meal_pci_remove),
  2789. };
  2790. static int __init happy_meal_pci_init(void)
  2791. {
  2792. return pci_register_driver(&hme_pci_driver);
  2793. }
  2794. static void happy_meal_pci_exit(void)
  2795. {
  2796. pci_unregister_driver(&hme_pci_driver);
  2797. while (qfe_pci_list) {
  2798. struct quattro *qfe = qfe_pci_list;
  2799. struct quattro *next = qfe->next;
  2800. kfree(qfe);
  2801. qfe_pci_list = next;
  2802. }
  2803. }
  2804. #endif
  2805. #ifdef CONFIG_SBUS
  2806. static int __devinit hme_sbus_probe(struct of_device *dev, const struct of_device_id *match)
  2807. {
  2808. struct sbus_dev *sdev = to_sbus_device(&dev->dev);
  2809. struct device_node *dp = dev->node;
  2810. char *model = of_get_property(dp, "model", NULL);
  2811. int is_qfe = (match->data != NULL);
  2812. if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
  2813. is_qfe = 1;
  2814. return happy_meal_sbus_probe_one(sdev, is_qfe);
  2815. }
  2816. static int __devexit hme_sbus_remove(struct of_device *dev)
  2817. {
  2818. struct happy_meal *hp = dev_get_drvdata(&dev->dev);
  2819. struct net_device *net_dev = hp->dev;
  2820. unregister_netdev(net_dev);
  2821. /* XXX qfe parent interrupt... */
  2822. sbus_iounmap(hp->gregs, GREG_REG_SIZE);
  2823. sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
  2824. sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
  2825. sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
  2826. sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
  2827. sbus_free_consistent(hp->happy_dev,
  2828. PAGE_SIZE,
  2829. hp->happy_block,
  2830. hp->hblock_dvma);
  2831. free_netdev(net_dev);
  2832. dev_set_drvdata(&dev->dev, NULL);
  2833. return 0;
  2834. }
  2835. static struct of_device_id hme_sbus_match[] = {
  2836. {
  2837. .name = "SUNW,hme",
  2838. },
  2839. {
  2840. .name = "SUNW,qfe",
  2841. .data = (void *) 1,
  2842. },
  2843. {
  2844. .name = "qfe",
  2845. .data = (void *) 1,
  2846. },
  2847. {},
  2848. };
  2849. MODULE_DEVICE_TABLE(of, hme_sbus_match);
  2850. static struct of_platform_driver hme_sbus_driver = {
  2851. .name = "hme",
  2852. .match_table = hme_sbus_match,
  2853. .probe = hme_sbus_probe,
  2854. .remove = __devexit_p(hme_sbus_remove),
  2855. };
  2856. static int __init happy_meal_sbus_init(void)
  2857. {
  2858. int err;
  2859. err = of_register_driver(&hme_sbus_driver, &sbus_bus_type);
  2860. if (!err)
  2861. quattro_sbus_register_irqs();
  2862. return err;
  2863. }
  2864. static void happy_meal_sbus_exit(void)
  2865. {
  2866. of_unregister_driver(&hme_sbus_driver);
  2867. quattro_sbus_free_irqs();
  2868. while (qfe_sbus_list) {
  2869. struct quattro *qfe = qfe_sbus_list;
  2870. struct quattro *next = qfe->next;
  2871. kfree(qfe);
  2872. qfe_sbus_list = next;
  2873. }
  2874. }
  2875. #endif
  2876. static int __init happy_meal_probe(void)
  2877. {
  2878. int err = 0;
  2879. #ifdef CONFIG_SBUS
  2880. err = happy_meal_sbus_init();
  2881. #endif
  2882. #ifdef CONFIG_PCI
  2883. if (!err) {
  2884. err = happy_meal_pci_init();
  2885. #ifdef CONFIG_SBUS
  2886. if (err)
  2887. happy_meal_sbus_exit();
  2888. #endif
  2889. }
  2890. #endif
  2891. return err;
  2892. }
  2893. static void __exit happy_meal_exit(void)
  2894. {
  2895. #ifdef CONFIG_SBUS
  2896. happy_meal_sbus_exit();
  2897. #endif
  2898. #ifdef CONFIG_PCI
  2899. happy_meal_pci_exit();
  2900. #endif
  2901. }
  2902. module_init(happy_meal_probe);
  2903. module_exit(happy_meal_exit);