sungem_phy.h 3.9 KB

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  1. #ifndef __SUNGEM_PHY_H__
  2. #define __SUNGEM_PHY_H__
  3. struct mii_phy;
  4. /* Operations supported by any kind of PHY */
  5. struct mii_phy_ops
  6. {
  7. int (*init)(struct mii_phy *phy);
  8. int (*suspend)(struct mii_phy *phy);
  9. int (*setup_aneg)(struct mii_phy *phy, u32 advertise);
  10. int (*setup_forced)(struct mii_phy *phy, int speed, int fd);
  11. int (*poll_link)(struct mii_phy *phy);
  12. int (*read_link)(struct mii_phy *phy);
  13. int (*enable_fiber)(struct mii_phy *phy, int autoneg);
  14. };
  15. /* Structure used to statically define an mii/gii based PHY */
  16. struct mii_phy_def
  17. {
  18. u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
  19. u32 phy_id_mask; /* Significant bits */
  20. u32 features; /* Ethtool SUPPORTED_* defines */
  21. int magic_aneg; /* Autoneg does all speed test for us */
  22. const char* name;
  23. const struct mii_phy_ops* ops;
  24. };
  25. enum {
  26. BCM54XX_COPPER,
  27. BCM54XX_FIBER,
  28. BCM54XX_GBIC,
  29. BCM54XX_SGMII,
  30. BCM54XX_UNKNOWN,
  31. };
  32. /* An instance of a PHY, partially borrowed from mii_if_info */
  33. struct mii_phy
  34. {
  35. struct mii_phy_def* def;
  36. u32 advertising;
  37. int mii_id;
  38. /* 1: autoneg enabled, 0: disabled */
  39. int autoneg;
  40. /* forced speed & duplex (no autoneg)
  41. * partner speed & duplex & pause (autoneg)
  42. */
  43. int speed;
  44. int duplex;
  45. int pause;
  46. /* Provided by host chip */
  47. struct net_device *dev;
  48. int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
  49. void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
  50. void *platform_data;
  51. };
  52. /* Pass in a struct mii_phy with dev, mdio_read and mdio_write
  53. * filled, the remaining fields will be filled on return
  54. */
  55. extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
  56. /* MII definitions missing from mii.h */
  57. #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
  58. #define LPA_PAUSE 0x0400
  59. /* More PHY registers (model specific) */
  60. /* MII BCM5201 MULTIPHY interrupt register */
  61. #define MII_BCM5201_INTERRUPT 0x1A
  62. #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
  63. #define MII_BCM5201_AUXMODE2 0x1B
  64. #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
  65. #define MII_BCM5201_MULTIPHY 0x1E
  66. /* MII BCM5201 MULTIPHY register bits */
  67. #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
  68. #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
  69. /* MII BCM5221 Additional registers */
  70. #define MII_BCM5221_TEST 0x1f
  71. #define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080
  72. #define MII_BCM5221_SHDOW_AUX_STAT2 0x1b
  73. #define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020
  74. #define MII_BCM5221_SHDOW_AUX_MODE4 0x1a
  75. #define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001
  76. #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
  77. /* MII BCM5241 Additional registers */
  78. #define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR 0x0008
  79. /* MII BCM5400 1000-BASET Control register */
  80. #define MII_BCM5400_GB_CONTROL 0x09
  81. #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
  82. /* MII BCM5400 AUXCONTROL register */
  83. #define MII_BCM5400_AUXCONTROL 0x18
  84. #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
  85. /* MII BCM5400 AUXSTATUS register */
  86. #define MII_BCM5400_AUXSTATUS 0x19
  87. #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
  88. #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
  89. /* 1000BT control (Marvell & BCM54xx at least) */
  90. #define MII_1000BASETCONTROL 0x09
  91. #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
  92. #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
  93. /* Marvell 88E1011 PHY control */
  94. #define MII_M1011_PHY_SPEC_CONTROL 0x10
  95. #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
  96. #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
  97. /* Marvell 88E1011 PHY status */
  98. #define MII_M1011_PHY_SPEC_STATUS 0x11
  99. #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
  100. #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
  101. #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
  102. #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
  103. #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
  104. #define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008
  105. #define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004
  106. #endif /* __SUNGEM_PHY_H__ */