sungem.c 80 KB

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  1. /* $Id: sungem.c,v 1.1.1.1 2007/06/12 07:27:11 eyryu Exp $
  2. * sungem.c: Sun GEM ethernet driver.
  3. *
  4. * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
  5. *
  6. * Support for Apple GMAC and assorted PHYs, WOL, Power Management
  7. * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
  8. * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
  9. *
  10. * NAPI and NETPOLL support
  11. * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
  12. *
  13. * TODO:
  14. * - Now that the driver was significantly simplified, I need to rework
  15. * the locking. I'm sure we don't need _2_ spinlocks, and we probably
  16. * can avoid taking most of them for so long period of time (and schedule
  17. * instead). The main issues at this point are caused by the netdev layer
  18. * though:
  19. *
  20. * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
  21. * help by net/core/dev.c, thus they can't schedule. That means they can't
  22. * call netif_poll_disable() neither, thus force gem_poll() to keep a spinlock
  23. * where it could have been dropped. change_mtu especially would love also to
  24. * be able to msleep instead of horrid locked delays when resetting the HW,
  25. * but that read_lock() makes it impossible, unless I defer it's action to
  26. * the reset task, which means it'll be asynchronous (won't take effect until
  27. * the system schedules a bit).
  28. *
  29. * Also, it would probably be possible to also remove most of the long-life
  30. * locking in open/resume code path (gem_reinit_chip) by beeing more careful
  31. * about when we can start taking interrupts or get xmit() called...
  32. */
  33. #include <linux/module.h>
  34. #include <linux/kernel.h>
  35. #include <linux/types.h>
  36. #include <linux/fcntl.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/ioport.h>
  39. #include <linux/in.h>
  40. #include <linux/slab.h>
  41. #include <linux/string.h>
  42. #include <linux/delay.h>
  43. #include <linux/init.h>
  44. #include <linux/errno.h>
  45. #include <linux/pci.h>
  46. #include <linux/dma-mapping.h>
  47. #include <linux/netdevice.h>
  48. #include <linux/etherdevice.h>
  49. #include <linux/skbuff.h>
  50. #include <linux/mii.h>
  51. #include <linux/ethtool.h>
  52. #include <linux/crc32.h>
  53. #include <linux/random.h>
  54. #include <linux/workqueue.h>
  55. #include <linux/if_vlan.h>
  56. #include <linux/bitops.h>
  57. #include <linux/mutex.h>
  58. #include <linux/mm.h>
  59. #include <asm/system.h>
  60. #include <asm/io.h>
  61. #include <asm/byteorder.h>
  62. #include <asm/uaccess.h>
  63. #include <asm/irq.h>
  64. #ifdef __sparc__
  65. #include <asm/idprom.h>
  66. #include <asm/openprom.h>
  67. #include <asm/oplib.h>
  68. #include <asm/pbm.h>
  69. #endif
  70. #ifdef CONFIG_PPC_PMAC
  71. #include <asm/pci-bridge.h>
  72. #include <asm/prom.h>
  73. #include <asm/machdep.h>
  74. #include <asm/pmac_feature.h>
  75. #endif
  76. #include "sungem_phy.h"
  77. #include "sungem.h"
  78. /* Stripping FCS is causing problems, disabled for now */
  79. #undef STRIP_FCS
  80. #define DEFAULT_MSG (NETIF_MSG_DRV | \
  81. NETIF_MSG_PROBE | \
  82. NETIF_MSG_LINK)
  83. #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
  84. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
  85. SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
  86. SUPPORTED_Pause | SUPPORTED_Autoneg)
  87. #define DRV_NAME "sungem"
  88. #define DRV_VERSION "0.98"
  89. #define DRV_RELDATE "8/24/03"
  90. #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
  91. static char version[] __devinitdata =
  92. DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
  93. MODULE_AUTHOR(DRV_AUTHOR);
  94. MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
  95. MODULE_LICENSE("GPL");
  96. #define GEM_MODULE_NAME "gem"
  97. #define PFX GEM_MODULE_NAME ": "
  98. static struct pci_device_id gem_pci_tbl[] = {
  99. { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
  100. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  101. /* These models only differ from the original GEM in
  102. * that their tx/rx fifos are of a different size and
  103. * they only support 10/100 speeds. -DaveM
  104. *
  105. * Apple's GMAC does support gigabit on machines with
  106. * the BCM54xx PHYs. -BenH
  107. */
  108. { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
  109. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  110. { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
  111. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  112. { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
  113. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  114. { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
  115. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  116. { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
  117. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  118. { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
  119. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  120. { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
  121. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  122. {0, }
  123. };
  124. MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
  125. static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
  126. {
  127. u32 cmd;
  128. int limit = 10000;
  129. cmd = (1 << 30);
  130. cmd |= (2 << 28);
  131. cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
  132. cmd |= (reg << 18) & MIF_FRAME_REGAD;
  133. cmd |= (MIF_FRAME_TAMSB);
  134. writel(cmd, gp->regs + MIF_FRAME);
  135. while (limit--) {
  136. cmd = readl(gp->regs + MIF_FRAME);
  137. if (cmd & MIF_FRAME_TALSB)
  138. break;
  139. udelay(10);
  140. }
  141. if (!limit)
  142. cmd = 0xffff;
  143. return cmd & MIF_FRAME_DATA;
  144. }
  145. static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
  146. {
  147. struct gem *gp = dev->priv;
  148. return __phy_read(gp, mii_id, reg);
  149. }
  150. static inline u16 phy_read(struct gem *gp, int reg)
  151. {
  152. return __phy_read(gp, gp->mii_phy_addr, reg);
  153. }
  154. static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
  155. {
  156. u32 cmd;
  157. int limit = 10000;
  158. cmd = (1 << 30);
  159. cmd |= (1 << 28);
  160. cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
  161. cmd |= (reg << 18) & MIF_FRAME_REGAD;
  162. cmd |= (MIF_FRAME_TAMSB);
  163. cmd |= (val & MIF_FRAME_DATA);
  164. writel(cmd, gp->regs + MIF_FRAME);
  165. while (limit--) {
  166. cmd = readl(gp->regs + MIF_FRAME);
  167. if (cmd & MIF_FRAME_TALSB)
  168. break;
  169. udelay(10);
  170. }
  171. }
  172. static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
  173. {
  174. struct gem *gp = dev->priv;
  175. __phy_write(gp, mii_id, reg, val & 0xffff);
  176. }
  177. static inline void phy_write(struct gem *gp, int reg, u16 val)
  178. {
  179. __phy_write(gp, gp->mii_phy_addr, reg, val);
  180. }
  181. static inline void gem_enable_ints(struct gem *gp)
  182. {
  183. /* Enable all interrupts but TXDONE */
  184. writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
  185. }
  186. static inline void gem_disable_ints(struct gem *gp)
  187. {
  188. /* Disable all interrupts, including TXDONE */
  189. writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
  190. }
  191. static void gem_get_cell(struct gem *gp)
  192. {
  193. BUG_ON(gp->cell_enabled < 0);
  194. gp->cell_enabled++;
  195. #ifdef CONFIG_PPC_PMAC
  196. if (gp->cell_enabled == 1) {
  197. mb();
  198. pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
  199. udelay(10);
  200. }
  201. #endif /* CONFIG_PPC_PMAC */
  202. }
  203. /* Turn off the chip's clock */
  204. static void gem_put_cell(struct gem *gp)
  205. {
  206. BUG_ON(gp->cell_enabled <= 0);
  207. gp->cell_enabled--;
  208. #ifdef CONFIG_PPC_PMAC
  209. if (gp->cell_enabled == 0) {
  210. mb();
  211. pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
  212. udelay(10);
  213. }
  214. #endif /* CONFIG_PPC_PMAC */
  215. }
  216. static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
  217. {
  218. if (netif_msg_intr(gp))
  219. printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
  220. }
  221. static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
  222. {
  223. u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
  224. u32 pcs_miistat;
  225. if (netif_msg_intr(gp))
  226. printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
  227. gp->dev->name, pcs_istat);
  228. if (!(pcs_istat & PCS_ISTAT_LSC)) {
  229. printk(KERN_ERR "%s: PCS irq but no link status change???\n",
  230. dev->name);
  231. return 0;
  232. }
  233. /* The link status bit latches on zero, so you must
  234. * read it twice in such a case to see a transition
  235. * to the link being up.
  236. */
  237. pcs_miistat = readl(gp->regs + PCS_MIISTAT);
  238. if (!(pcs_miistat & PCS_MIISTAT_LS))
  239. pcs_miistat |=
  240. (readl(gp->regs + PCS_MIISTAT) &
  241. PCS_MIISTAT_LS);
  242. if (pcs_miistat & PCS_MIISTAT_ANC) {
  243. /* The remote-fault indication is only valid
  244. * when autoneg has completed.
  245. */
  246. if (pcs_miistat & PCS_MIISTAT_RF)
  247. printk(KERN_INFO "%s: PCS AutoNEG complete, "
  248. "RemoteFault\n", dev->name);
  249. else
  250. printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
  251. dev->name);
  252. }
  253. if (pcs_miistat & PCS_MIISTAT_LS) {
  254. printk(KERN_INFO "%s: PCS link is now up.\n",
  255. dev->name);
  256. netif_carrier_on(gp->dev);
  257. } else {
  258. printk(KERN_INFO "%s: PCS link is now down.\n",
  259. dev->name);
  260. netif_carrier_off(gp->dev);
  261. /* If this happens and the link timer is not running,
  262. * reset so we re-negotiate.
  263. */
  264. if (!timer_pending(&gp->link_timer))
  265. return 1;
  266. }
  267. return 0;
  268. }
  269. static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
  270. {
  271. u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
  272. if (netif_msg_intr(gp))
  273. printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
  274. gp->dev->name, txmac_stat);
  275. /* Defer timer expiration is quite normal,
  276. * don't even log the event.
  277. */
  278. if ((txmac_stat & MAC_TXSTAT_DTE) &&
  279. !(txmac_stat & ~MAC_TXSTAT_DTE))
  280. return 0;
  281. if (txmac_stat & MAC_TXSTAT_URUN) {
  282. printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
  283. dev->name);
  284. gp->net_stats.tx_fifo_errors++;
  285. }
  286. if (txmac_stat & MAC_TXSTAT_MPE) {
  287. printk(KERN_ERR "%s: TX MAC max packet size error.\n",
  288. dev->name);
  289. gp->net_stats.tx_errors++;
  290. }
  291. /* The rest are all cases of one of the 16-bit TX
  292. * counters expiring.
  293. */
  294. if (txmac_stat & MAC_TXSTAT_NCE)
  295. gp->net_stats.collisions += 0x10000;
  296. if (txmac_stat & MAC_TXSTAT_ECE) {
  297. gp->net_stats.tx_aborted_errors += 0x10000;
  298. gp->net_stats.collisions += 0x10000;
  299. }
  300. if (txmac_stat & MAC_TXSTAT_LCE) {
  301. gp->net_stats.tx_aborted_errors += 0x10000;
  302. gp->net_stats.collisions += 0x10000;
  303. }
  304. /* We do not keep track of MAC_TXSTAT_FCE and
  305. * MAC_TXSTAT_PCE events.
  306. */
  307. return 0;
  308. }
  309. /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
  310. * so we do the following.
  311. *
  312. * If any part of the reset goes wrong, we return 1 and that causes the
  313. * whole chip to be reset.
  314. */
  315. static int gem_rxmac_reset(struct gem *gp)
  316. {
  317. struct net_device *dev = gp->dev;
  318. int limit, i;
  319. u64 desc_dma;
  320. u32 val;
  321. /* First, reset & disable MAC RX. */
  322. writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
  323. for (limit = 0; limit < 5000; limit++) {
  324. if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
  325. break;
  326. udelay(10);
  327. }
  328. if (limit == 5000) {
  329. printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
  330. "chip.\n", dev->name);
  331. return 1;
  332. }
  333. writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
  334. gp->regs + MAC_RXCFG);
  335. for (limit = 0; limit < 5000; limit++) {
  336. if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
  337. break;
  338. udelay(10);
  339. }
  340. if (limit == 5000) {
  341. printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
  342. "chip.\n", dev->name);
  343. return 1;
  344. }
  345. /* Second, disable RX DMA. */
  346. writel(0, gp->regs + RXDMA_CFG);
  347. for (limit = 0; limit < 5000; limit++) {
  348. if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
  349. break;
  350. udelay(10);
  351. }
  352. if (limit == 5000) {
  353. printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
  354. "chip.\n", dev->name);
  355. return 1;
  356. }
  357. udelay(5000);
  358. /* Execute RX reset command. */
  359. writel(gp->swrst_base | GREG_SWRST_RXRST,
  360. gp->regs + GREG_SWRST);
  361. for (limit = 0; limit < 5000; limit++) {
  362. if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
  363. break;
  364. udelay(10);
  365. }
  366. if (limit == 5000) {
  367. printk(KERN_ERR "%s: RX reset command will not execute, resetting "
  368. "whole chip.\n", dev->name);
  369. return 1;
  370. }
  371. /* Refresh the RX ring. */
  372. for (i = 0; i < RX_RING_SIZE; i++) {
  373. struct gem_rxd *rxd = &gp->init_block->rxd[i];
  374. if (gp->rx_skbs[i] == NULL) {
  375. printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
  376. "whole chip.\n", dev->name);
  377. return 1;
  378. }
  379. rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
  380. }
  381. gp->rx_new = gp->rx_old = 0;
  382. /* Now we must reprogram the rest of RX unit. */
  383. desc_dma = (u64) gp->gblock_dvma;
  384. desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
  385. writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
  386. writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
  387. writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
  388. val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
  389. ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
  390. writel(val, gp->regs + RXDMA_CFG);
  391. if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
  392. writel(((5 & RXDMA_BLANK_IPKTS) |
  393. ((8 << 12) & RXDMA_BLANK_ITIME)),
  394. gp->regs + RXDMA_BLANK);
  395. else
  396. writel(((5 & RXDMA_BLANK_IPKTS) |
  397. ((4 << 12) & RXDMA_BLANK_ITIME)),
  398. gp->regs + RXDMA_BLANK);
  399. val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
  400. val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
  401. writel(val, gp->regs + RXDMA_PTHRESH);
  402. val = readl(gp->regs + RXDMA_CFG);
  403. writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
  404. writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
  405. val = readl(gp->regs + MAC_RXCFG);
  406. writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
  407. return 0;
  408. }
  409. static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
  410. {
  411. u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
  412. int ret = 0;
  413. if (netif_msg_intr(gp))
  414. printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
  415. gp->dev->name, rxmac_stat);
  416. if (rxmac_stat & MAC_RXSTAT_OFLW) {
  417. u32 smac = readl(gp->regs + MAC_SMACHINE);
  418. printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
  419. dev->name, smac);
  420. gp->net_stats.rx_over_errors++;
  421. gp->net_stats.rx_fifo_errors++;
  422. ret = gem_rxmac_reset(gp);
  423. }
  424. if (rxmac_stat & MAC_RXSTAT_ACE)
  425. gp->net_stats.rx_frame_errors += 0x10000;
  426. if (rxmac_stat & MAC_RXSTAT_CCE)
  427. gp->net_stats.rx_crc_errors += 0x10000;
  428. if (rxmac_stat & MAC_RXSTAT_LCE)
  429. gp->net_stats.rx_length_errors += 0x10000;
  430. /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
  431. * events.
  432. */
  433. return ret;
  434. }
  435. static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
  436. {
  437. u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
  438. if (netif_msg_intr(gp))
  439. printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
  440. gp->dev->name, mac_cstat);
  441. /* This interrupt is just for pause frame and pause
  442. * tracking. It is useful for diagnostics and debug
  443. * but probably by default we will mask these events.
  444. */
  445. if (mac_cstat & MAC_CSTAT_PS)
  446. gp->pause_entered++;
  447. if (mac_cstat & MAC_CSTAT_PRCV)
  448. gp->pause_last_time_recvd = (mac_cstat >> 16);
  449. return 0;
  450. }
  451. static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
  452. {
  453. u32 mif_status = readl(gp->regs + MIF_STATUS);
  454. u32 reg_val, changed_bits;
  455. reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
  456. changed_bits = (mif_status & MIF_STATUS_STAT);
  457. gem_handle_mif_event(gp, reg_val, changed_bits);
  458. return 0;
  459. }
  460. static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
  461. {
  462. u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
  463. if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
  464. gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
  465. printk(KERN_ERR "%s: PCI error [%04x] ",
  466. dev->name, pci_estat);
  467. if (pci_estat & GREG_PCIESTAT_BADACK)
  468. printk("<No ACK64# during ABS64 cycle> ");
  469. if (pci_estat & GREG_PCIESTAT_DTRTO)
  470. printk("<Delayed transaction timeout> ");
  471. if (pci_estat & GREG_PCIESTAT_OTHER)
  472. printk("<other>");
  473. printk("\n");
  474. } else {
  475. pci_estat |= GREG_PCIESTAT_OTHER;
  476. printk(KERN_ERR "%s: PCI error\n", dev->name);
  477. }
  478. if (pci_estat & GREG_PCIESTAT_OTHER) {
  479. u16 pci_cfg_stat;
  480. /* Interrogate PCI config space for the
  481. * true cause.
  482. */
  483. pci_read_config_word(gp->pdev, PCI_STATUS,
  484. &pci_cfg_stat);
  485. printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
  486. dev->name, pci_cfg_stat);
  487. if (pci_cfg_stat & PCI_STATUS_PARITY)
  488. printk(KERN_ERR "%s: PCI parity error detected.\n",
  489. dev->name);
  490. if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
  491. printk(KERN_ERR "%s: PCI target abort.\n",
  492. dev->name);
  493. if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
  494. printk(KERN_ERR "%s: PCI master acks target abort.\n",
  495. dev->name);
  496. if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
  497. printk(KERN_ERR "%s: PCI master abort.\n",
  498. dev->name);
  499. if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
  500. printk(KERN_ERR "%s: PCI system error SERR#.\n",
  501. dev->name);
  502. if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
  503. printk(KERN_ERR "%s: PCI parity error.\n",
  504. dev->name);
  505. /* Write the error bits back to clear them. */
  506. pci_cfg_stat &= (PCI_STATUS_PARITY |
  507. PCI_STATUS_SIG_TARGET_ABORT |
  508. PCI_STATUS_REC_TARGET_ABORT |
  509. PCI_STATUS_REC_MASTER_ABORT |
  510. PCI_STATUS_SIG_SYSTEM_ERROR |
  511. PCI_STATUS_DETECTED_PARITY);
  512. pci_write_config_word(gp->pdev,
  513. PCI_STATUS, pci_cfg_stat);
  514. }
  515. /* For all PCI errors, we should reset the chip. */
  516. return 1;
  517. }
  518. /* All non-normal interrupt conditions get serviced here.
  519. * Returns non-zero if we should just exit the interrupt
  520. * handler right now (ie. if we reset the card which invalidates
  521. * all of the other original irq status bits).
  522. */
  523. static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
  524. {
  525. if (gem_status & GREG_STAT_RXNOBUF) {
  526. /* Frame arrived, no free RX buffers available. */
  527. if (netif_msg_rx_err(gp))
  528. printk(KERN_DEBUG "%s: no buffer for rx frame\n",
  529. gp->dev->name);
  530. gp->net_stats.rx_dropped++;
  531. }
  532. if (gem_status & GREG_STAT_RXTAGERR) {
  533. /* corrupt RX tag framing */
  534. if (netif_msg_rx_err(gp))
  535. printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
  536. gp->dev->name);
  537. gp->net_stats.rx_errors++;
  538. goto do_reset;
  539. }
  540. if (gem_status & GREG_STAT_PCS) {
  541. if (gem_pcs_interrupt(dev, gp, gem_status))
  542. goto do_reset;
  543. }
  544. if (gem_status & GREG_STAT_TXMAC) {
  545. if (gem_txmac_interrupt(dev, gp, gem_status))
  546. goto do_reset;
  547. }
  548. if (gem_status & GREG_STAT_RXMAC) {
  549. if (gem_rxmac_interrupt(dev, gp, gem_status))
  550. goto do_reset;
  551. }
  552. if (gem_status & GREG_STAT_MAC) {
  553. if (gem_mac_interrupt(dev, gp, gem_status))
  554. goto do_reset;
  555. }
  556. if (gem_status & GREG_STAT_MIF) {
  557. if (gem_mif_interrupt(dev, gp, gem_status))
  558. goto do_reset;
  559. }
  560. if (gem_status & GREG_STAT_PCIERR) {
  561. if (gem_pci_interrupt(dev, gp, gem_status))
  562. goto do_reset;
  563. }
  564. return 0;
  565. do_reset:
  566. gp->reset_task_pending = 1;
  567. schedule_work(&gp->reset_task);
  568. return 1;
  569. }
  570. static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
  571. {
  572. int entry, limit;
  573. if (netif_msg_intr(gp))
  574. printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
  575. gp->dev->name, gem_status);
  576. entry = gp->tx_old;
  577. limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
  578. while (entry != limit) {
  579. struct sk_buff *skb;
  580. struct gem_txd *txd;
  581. dma_addr_t dma_addr;
  582. u32 dma_len;
  583. int frag;
  584. if (netif_msg_tx_done(gp))
  585. printk(KERN_DEBUG "%s: tx done, slot %d\n",
  586. gp->dev->name, entry);
  587. skb = gp->tx_skbs[entry];
  588. if (skb_shinfo(skb)->nr_frags) {
  589. int last = entry + skb_shinfo(skb)->nr_frags;
  590. int walk = entry;
  591. int incomplete = 0;
  592. last &= (TX_RING_SIZE - 1);
  593. for (;;) {
  594. walk = NEXT_TX(walk);
  595. if (walk == limit)
  596. incomplete = 1;
  597. if (walk == last)
  598. break;
  599. }
  600. if (incomplete)
  601. break;
  602. }
  603. gp->tx_skbs[entry] = NULL;
  604. gp->net_stats.tx_bytes += skb->len;
  605. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  606. txd = &gp->init_block->txd[entry];
  607. dma_addr = le64_to_cpu(txd->buffer);
  608. dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
  609. pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
  610. entry = NEXT_TX(entry);
  611. }
  612. gp->net_stats.tx_packets++;
  613. dev_kfree_skb_irq(skb);
  614. }
  615. gp->tx_old = entry;
  616. if (netif_queue_stopped(dev) &&
  617. TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
  618. netif_wake_queue(dev);
  619. }
  620. static __inline__ void gem_post_rxds(struct gem *gp, int limit)
  621. {
  622. int cluster_start, curr, count, kick;
  623. cluster_start = curr = (gp->rx_new & ~(4 - 1));
  624. count = 0;
  625. kick = -1;
  626. wmb();
  627. while (curr != limit) {
  628. curr = NEXT_RX(curr);
  629. if (++count == 4) {
  630. struct gem_rxd *rxd =
  631. &gp->init_block->rxd[cluster_start];
  632. for (;;) {
  633. rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
  634. rxd++;
  635. cluster_start = NEXT_RX(cluster_start);
  636. if (cluster_start == curr)
  637. break;
  638. }
  639. kick = curr;
  640. count = 0;
  641. }
  642. }
  643. if (kick >= 0) {
  644. mb();
  645. writel(kick, gp->regs + RXDMA_KICK);
  646. }
  647. }
  648. static int gem_rx(struct gem *gp, int work_to_do)
  649. {
  650. int entry, drops, work_done = 0;
  651. u32 done;
  652. if (netif_msg_rx_status(gp))
  653. printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
  654. gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
  655. entry = gp->rx_new;
  656. drops = 0;
  657. done = readl(gp->regs + RXDMA_DONE);
  658. for (;;) {
  659. struct gem_rxd *rxd = &gp->init_block->rxd[entry];
  660. struct sk_buff *skb;
  661. u64 status = cpu_to_le64(rxd->status_word);
  662. dma_addr_t dma_addr;
  663. int len;
  664. if ((status & RXDCTRL_OWN) != 0)
  665. break;
  666. if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
  667. break;
  668. /* When writing back RX descriptor, GEM writes status
  669. * then buffer address, possibly in seperate transactions.
  670. * If we don't wait for the chip to write both, we could
  671. * post a new buffer to this descriptor then have GEM spam
  672. * on the buffer address. We sync on the RX completion
  673. * register to prevent this from happening.
  674. */
  675. if (entry == done) {
  676. done = readl(gp->regs + RXDMA_DONE);
  677. if (entry == done)
  678. break;
  679. }
  680. /* We can now account for the work we're about to do */
  681. work_done++;
  682. skb = gp->rx_skbs[entry];
  683. len = (status & RXDCTRL_BUFSZ) >> 16;
  684. if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
  685. gp->net_stats.rx_errors++;
  686. if (len < ETH_ZLEN)
  687. gp->net_stats.rx_length_errors++;
  688. if (len & RXDCTRL_BAD)
  689. gp->net_stats.rx_crc_errors++;
  690. /* We'll just return it to GEM. */
  691. drop_it:
  692. gp->net_stats.rx_dropped++;
  693. goto next;
  694. }
  695. dma_addr = cpu_to_le64(rxd->buffer);
  696. if (len > RX_COPY_THRESHOLD) {
  697. struct sk_buff *new_skb;
  698. new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
  699. if (new_skb == NULL) {
  700. drops++;
  701. goto drop_it;
  702. }
  703. pci_unmap_page(gp->pdev, dma_addr,
  704. RX_BUF_ALLOC_SIZE(gp),
  705. PCI_DMA_FROMDEVICE);
  706. gp->rx_skbs[entry] = new_skb;
  707. new_skb->dev = gp->dev;
  708. skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
  709. rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
  710. virt_to_page(new_skb->data),
  711. offset_in_page(new_skb->data),
  712. RX_BUF_ALLOC_SIZE(gp),
  713. PCI_DMA_FROMDEVICE));
  714. skb_reserve(new_skb, RX_OFFSET);
  715. /* Trim the original skb for the netif. */
  716. skb_trim(skb, len);
  717. } else {
  718. struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
  719. if (copy_skb == NULL) {
  720. drops++;
  721. goto drop_it;
  722. }
  723. copy_skb->dev = gp->dev;
  724. skb_reserve(copy_skb, 2);
  725. skb_put(copy_skb, len);
  726. pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  727. memcpy(copy_skb->data, skb->data, len);
  728. pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  729. /* We'll reuse the original ring buffer. */
  730. skb = copy_skb;
  731. }
  732. skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
  733. skb->ip_summed = CHECKSUM_COMPLETE;
  734. skb->protocol = eth_type_trans(skb, gp->dev);
  735. netif_receive_skb(skb);
  736. gp->net_stats.rx_packets++;
  737. gp->net_stats.rx_bytes += len;
  738. gp->dev->last_rx = jiffies;
  739. next:
  740. entry = NEXT_RX(entry);
  741. }
  742. gem_post_rxds(gp, entry);
  743. gp->rx_new = entry;
  744. if (drops)
  745. printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
  746. gp->dev->name);
  747. return work_done;
  748. }
  749. static int gem_poll(struct net_device *dev, int *budget)
  750. {
  751. struct gem *gp = dev->priv;
  752. unsigned long flags;
  753. /*
  754. * NAPI locking nightmare: See comment at head of driver
  755. */
  756. spin_lock_irqsave(&gp->lock, flags);
  757. do {
  758. int work_to_do, work_done;
  759. /* Handle anomalies */
  760. if (gp->status & GREG_STAT_ABNORMAL) {
  761. if (gem_abnormal_irq(dev, gp, gp->status))
  762. break;
  763. }
  764. /* Run TX completion thread */
  765. spin_lock(&gp->tx_lock);
  766. gem_tx(dev, gp, gp->status);
  767. spin_unlock(&gp->tx_lock);
  768. spin_unlock_irqrestore(&gp->lock, flags);
  769. /* Run RX thread. We don't use any locking here,
  770. * code willing to do bad things - like cleaning the
  771. * rx ring - must call netif_poll_disable(), which
  772. * schedule_timeout()'s if polling is already disabled.
  773. */
  774. work_to_do = min(*budget, dev->quota);
  775. work_done = gem_rx(gp, work_to_do);
  776. *budget -= work_done;
  777. dev->quota -= work_done;
  778. if (work_done >= work_to_do)
  779. return 1;
  780. spin_lock_irqsave(&gp->lock, flags);
  781. gp->status = readl(gp->regs + GREG_STAT);
  782. } while (gp->status & GREG_STAT_NAPI);
  783. __netif_rx_complete(dev);
  784. gem_enable_ints(gp);
  785. spin_unlock_irqrestore(&gp->lock, flags);
  786. return 0;
  787. }
  788. static irqreturn_t gem_interrupt(int irq, void *dev_id)
  789. {
  790. struct net_device *dev = dev_id;
  791. struct gem *gp = dev->priv;
  792. unsigned long flags;
  793. /* Swallow interrupts when shutting the chip down, though
  794. * that shouldn't happen, we should have done free_irq() at
  795. * this point...
  796. */
  797. if (!gp->running)
  798. return IRQ_HANDLED;
  799. spin_lock_irqsave(&gp->lock, flags);
  800. if (netif_rx_schedule_prep(dev)) {
  801. u32 gem_status = readl(gp->regs + GREG_STAT);
  802. if (gem_status == 0) {
  803. netif_poll_enable(dev);
  804. spin_unlock_irqrestore(&gp->lock, flags);
  805. return IRQ_NONE;
  806. }
  807. gp->status = gem_status;
  808. gem_disable_ints(gp);
  809. __netif_rx_schedule(dev);
  810. }
  811. spin_unlock_irqrestore(&gp->lock, flags);
  812. /* If polling was disabled at the time we received that
  813. * interrupt, we may return IRQ_HANDLED here while we
  814. * should return IRQ_NONE. No big deal...
  815. */
  816. return IRQ_HANDLED;
  817. }
  818. #ifdef CONFIG_NET_POLL_CONTROLLER
  819. static void gem_poll_controller(struct net_device *dev)
  820. {
  821. /* gem_interrupt is safe to reentrance so no need
  822. * to disable_irq here.
  823. */
  824. gem_interrupt(dev->irq, dev);
  825. }
  826. #endif
  827. static void gem_tx_timeout(struct net_device *dev)
  828. {
  829. struct gem *gp = dev->priv;
  830. printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
  831. if (!gp->running) {
  832. printk("%s: hrm.. hw not running !\n", dev->name);
  833. return;
  834. }
  835. printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
  836. dev->name,
  837. readl(gp->regs + TXDMA_CFG),
  838. readl(gp->regs + MAC_TXSTAT),
  839. readl(gp->regs + MAC_TXCFG));
  840. printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
  841. dev->name,
  842. readl(gp->regs + RXDMA_CFG),
  843. readl(gp->regs + MAC_RXSTAT),
  844. readl(gp->regs + MAC_RXCFG));
  845. spin_lock_irq(&gp->lock);
  846. spin_lock(&gp->tx_lock);
  847. gp->reset_task_pending = 1;
  848. schedule_work(&gp->reset_task);
  849. spin_unlock(&gp->tx_lock);
  850. spin_unlock_irq(&gp->lock);
  851. }
  852. static __inline__ int gem_intme(int entry)
  853. {
  854. /* Algorithm: IRQ every 1/2 of descriptors. */
  855. if (!(entry & ((TX_RING_SIZE>>1)-1)))
  856. return 1;
  857. return 0;
  858. }
  859. static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
  860. {
  861. struct gem *gp = dev->priv;
  862. int entry;
  863. u64 ctrl;
  864. unsigned long flags;
  865. ctrl = 0;
  866. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  867. u64 csum_start_off, csum_stuff_off;
  868. csum_start_off = (u64) (skb->h.raw - skb->data);
  869. csum_stuff_off = csum_start_off + skb->csum_offset;
  870. ctrl = (TXDCTRL_CENAB |
  871. (csum_start_off << 15) |
  872. (csum_stuff_off << 21));
  873. }
  874. local_irq_save(flags);
  875. if (!spin_trylock(&gp->tx_lock)) {
  876. /* Tell upper layer to requeue */
  877. local_irq_restore(flags);
  878. return NETDEV_TX_LOCKED;
  879. }
  880. /* We raced with gem_do_stop() */
  881. if (!gp->running) {
  882. spin_unlock_irqrestore(&gp->tx_lock, flags);
  883. return NETDEV_TX_BUSY;
  884. }
  885. /* This is a hard error, log it. */
  886. if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
  887. netif_stop_queue(dev);
  888. spin_unlock_irqrestore(&gp->tx_lock, flags);
  889. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
  890. dev->name);
  891. return NETDEV_TX_BUSY;
  892. }
  893. entry = gp->tx_new;
  894. gp->tx_skbs[entry] = skb;
  895. if (skb_shinfo(skb)->nr_frags == 0) {
  896. struct gem_txd *txd = &gp->init_block->txd[entry];
  897. dma_addr_t mapping;
  898. u32 len;
  899. len = skb->len;
  900. mapping = pci_map_page(gp->pdev,
  901. virt_to_page(skb->data),
  902. offset_in_page(skb->data),
  903. len, PCI_DMA_TODEVICE);
  904. ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
  905. if (gem_intme(entry))
  906. ctrl |= TXDCTRL_INTME;
  907. txd->buffer = cpu_to_le64(mapping);
  908. wmb();
  909. txd->control_word = cpu_to_le64(ctrl);
  910. entry = NEXT_TX(entry);
  911. } else {
  912. struct gem_txd *txd;
  913. u32 first_len;
  914. u64 intme;
  915. dma_addr_t first_mapping;
  916. int frag, first_entry = entry;
  917. intme = 0;
  918. if (gem_intme(entry))
  919. intme |= TXDCTRL_INTME;
  920. /* We must give this initial chunk to the device last.
  921. * Otherwise we could race with the device.
  922. */
  923. first_len = skb_headlen(skb);
  924. first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
  925. offset_in_page(skb->data),
  926. first_len, PCI_DMA_TODEVICE);
  927. entry = NEXT_TX(entry);
  928. for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
  929. skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
  930. u32 len;
  931. dma_addr_t mapping;
  932. u64 this_ctrl;
  933. len = this_frag->size;
  934. mapping = pci_map_page(gp->pdev,
  935. this_frag->page,
  936. this_frag->page_offset,
  937. len, PCI_DMA_TODEVICE);
  938. this_ctrl = ctrl;
  939. if (frag == skb_shinfo(skb)->nr_frags - 1)
  940. this_ctrl |= TXDCTRL_EOF;
  941. txd = &gp->init_block->txd[entry];
  942. txd->buffer = cpu_to_le64(mapping);
  943. wmb();
  944. txd->control_word = cpu_to_le64(this_ctrl | len);
  945. if (gem_intme(entry))
  946. intme |= TXDCTRL_INTME;
  947. entry = NEXT_TX(entry);
  948. }
  949. txd = &gp->init_block->txd[first_entry];
  950. txd->buffer = cpu_to_le64(first_mapping);
  951. wmb();
  952. txd->control_word =
  953. cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
  954. }
  955. gp->tx_new = entry;
  956. if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
  957. netif_stop_queue(dev);
  958. if (netif_msg_tx_queued(gp))
  959. printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
  960. dev->name, entry, skb->len);
  961. mb();
  962. writel(gp->tx_new, gp->regs + TXDMA_KICK);
  963. spin_unlock_irqrestore(&gp->tx_lock, flags);
  964. dev->trans_start = jiffies;
  965. return NETDEV_TX_OK;
  966. }
  967. #define STOP_TRIES 32
  968. /* Must be invoked under gp->lock and gp->tx_lock. */
  969. static void gem_reset(struct gem *gp)
  970. {
  971. int limit;
  972. u32 val;
  973. /* Make sure we won't get any more interrupts */
  974. writel(0xffffffff, gp->regs + GREG_IMASK);
  975. /* Reset the chip */
  976. writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
  977. gp->regs + GREG_SWRST);
  978. limit = STOP_TRIES;
  979. do {
  980. udelay(20);
  981. val = readl(gp->regs + GREG_SWRST);
  982. if (limit-- <= 0)
  983. break;
  984. } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
  985. if (limit <= 0)
  986. printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
  987. }
  988. /* Must be invoked under gp->lock and gp->tx_lock. */
  989. static void gem_start_dma(struct gem *gp)
  990. {
  991. u32 val;
  992. /* We are ready to rock, turn everything on. */
  993. val = readl(gp->regs + TXDMA_CFG);
  994. writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
  995. val = readl(gp->regs + RXDMA_CFG);
  996. writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
  997. val = readl(gp->regs + MAC_TXCFG);
  998. writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
  999. val = readl(gp->regs + MAC_RXCFG);
  1000. writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
  1001. (void) readl(gp->regs + MAC_RXCFG);
  1002. udelay(100);
  1003. gem_enable_ints(gp);
  1004. writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
  1005. }
  1006. /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
  1007. * actually stopped before about 4ms tho ...
  1008. */
  1009. static void gem_stop_dma(struct gem *gp)
  1010. {
  1011. u32 val;
  1012. /* We are done rocking, turn everything off. */
  1013. val = readl(gp->regs + TXDMA_CFG);
  1014. writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
  1015. val = readl(gp->regs + RXDMA_CFG);
  1016. writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
  1017. val = readl(gp->regs + MAC_TXCFG);
  1018. writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
  1019. val = readl(gp->regs + MAC_RXCFG);
  1020. writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
  1021. (void) readl(gp->regs + MAC_RXCFG);
  1022. /* Need to wait a bit ... done by the caller */
  1023. }
  1024. /* Must be invoked under gp->lock and gp->tx_lock. */
  1025. // XXX dbl check what that function should do when called on PCS PHY
  1026. static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
  1027. {
  1028. u32 advertise, features;
  1029. int autoneg;
  1030. int speed;
  1031. int duplex;
  1032. if (gp->phy_type != phy_mii_mdio0 &&
  1033. gp->phy_type != phy_mii_mdio1)
  1034. goto non_mii;
  1035. /* Setup advertise */
  1036. if (found_mii_phy(gp))
  1037. features = gp->phy_mii.def->features;
  1038. else
  1039. features = 0;
  1040. advertise = features & ADVERTISE_MASK;
  1041. if (gp->phy_mii.advertising != 0)
  1042. advertise &= gp->phy_mii.advertising;
  1043. autoneg = gp->want_autoneg;
  1044. speed = gp->phy_mii.speed;
  1045. duplex = gp->phy_mii.duplex;
  1046. /* Setup link parameters */
  1047. if (!ep)
  1048. goto start_aneg;
  1049. if (ep->autoneg == AUTONEG_ENABLE) {
  1050. advertise = ep->advertising;
  1051. autoneg = 1;
  1052. } else {
  1053. autoneg = 0;
  1054. speed = ep->speed;
  1055. duplex = ep->duplex;
  1056. }
  1057. start_aneg:
  1058. /* Sanitize settings based on PHY capabilities */
  1059. if ((features & SUPPORTED_Autoneg) == 0)
  1060. autoneg = 0;
  1061. if (speed == SPEED_1000 &&
  1062. !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
  1063. speed = SPEED_100;
  1064. if (speed == SPEED_100 &&
  1065. !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
  1066. speed = SPEED_10;
  1067. if (duplex == DUPLEX_FULL &&
  1068. !(features & (SUPPORTED_1000baseT_Full |
  1069. SUPPORTED_100baseT_Full |
  1070. SUPPORTED_10baseT_Full)))
  1071. duplex = DUPLEX_HALF;
  1072. if (speed == 0)
  1073. speed = SPEED_10;
  1074. /* If we are asleep, we don't try to actually setup the PHY, we
  1075. * just store the settings
  1076. */
  1077. if (gp->asleep) {
  1078. gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
  1079. gp->phy_mii.speed = speed;
  1080. gp->phy_mii.duplex = duplex;
  1081. return;
  1082. }
  1083. /* Configure PHY & start aneg */
  1084. gp->want_autoneg = autoneg;
  1085. if (autoneg) {
  1086. if (found_mii_phy(gp))
  1087. gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
  1088. gp->lstate = link_aneg;
  1089. } else {
  1090. if (found_mii_phy(gp))
  1091. gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
  1092. gp->lstate = link_force_ok;
  1093. }
  1094. non_mii:
  1095. gp->timer_ticks = 0;
  1096. mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
  1097. }
  1098. /* A link-up condition has occurred, initialize and enable the
  1099. * rest of the chip.
  1100. *
  1101. * Must be invoked under gp->lock and gp->tx_lock.
  1102. */
  1103. static int gem_set_link_modes(struct gem *gp)
  1104. {
  1105. u32 val;
  1106. int full_duplex, speed, pause;
  1107. full_duplex = 0;
  1108. speed = SPEED_10;
  1109. pause = 0;
  1110. if (found_mii_phy(gp)) {
  1111. if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
  1112. return 1;
  1113. full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
  1114. speed = gp->phy_mii.speed;
  1115. pause = gp->phy_mii.pause;
  1116. } else if (gp->phy_type == phy_serialink ||
  1117. gp->phy_type == phy_serdes) {
  1118. u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
  1119. if (pcs_lpa & PCS_MIIADV_FD)
  1120. full_duplex = 1;
  1121. speed = SPEED_1000;
  1122. }
  1123. if (netif_msg_link(gp))
  1124. printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
  1125. gp->dev->name, speed, (full_duplex ? "full" : "half"));
  1126. if (!gp->running)
  1127. return 0;
  1128. val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
  1129. if (full_duplex) {
  1130. val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
  1131. } else {
  1132. /* MAC_TXCFG_NBO must be zero. */
  1133. }
  1134. writel(val, gp->regs + MAC_TXCFG);
  1135. val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
  1136. if (!full_duplex &&
  1137. (gp->phy_type == phy_mii_mdio0 ||
  1138. gp->phy_type == phy_mii_mdio1)) {
  1139. val |= MAC_XIFCFG_DISE;
  1140. } else if (full_duplex) {
  1141. val |= MAC_XIFCFG_FLED;
  1142. }
  1143. if (speed == SPEED_1000)
  1144. val |= (MAC_XIFCFG_GMII);
  1145. writel(val, gp->regs + MAC_XIFCFG);
  1146. /* If gigabit and half-duplex, enable carrier extension
  1147. * mode. Else, disable it.
  1148. */
  1149. if (speed == SPEED_1000 && !full_duplex) {
  1150. val = readl(gp->regs + MAC_TXCFG);
  1151. writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
  1152. val = readl(gp->regs + MAC_RXCFG);
  1153. writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
  1154. } else {
  1155. val = readl(gp->regs + MAC_TXCFG);
  1156. writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
  1157. val = readl(gp->regs + MAC_RXCFG);
  1158. writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
  1159. }
  1160. if (gp->phy_type == phy_serialink ||
  1161. gp->phy_type == phy_serdes) {
  1162. u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
  1163. if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
  1164. pause = 1;
  1165. }
  1166. if (netif_msg_link(gp)) {
  1167. if (pause) {
  1168. printk(KERN_INFO "%s: Pause is enabled "
  1169. "(rxfifo: %d off: %d on: %d)\n",
  1170. gp->dev->name,
  1171. gp->rx_fifo_sz,
  1172. gp->rx_pause_off,
  1173. gp->rx_pause_on);
  1174. } else {
  1175. printk(KERN_INFO "%s: Pause is disabled\n",
  1176. gp->dev->name);
  1177. }
  1178. }
  1179. if (!full_duplex)
  1180. writel(512, gp->regs + MAC_STIME);
  1181. else
  1182. writel(64, gp->regs + MAC_STIME);
  1183. val = readl(gp->regs + MAC_MCCFG);
  1184. if (pause)
  1185. val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
  1186. else
  1187. val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
  1188. writel(val, gp->regs + MAC_MCCFG);
  1189. gem_start_dma(gp);
  1190. return 0;
  1191. }
  1192. /* Must be invoked under gp->lock and gp->tx_lock. */
  1193. static int gem_mdio_link_not_up(struct gem *gp)
  1194. {
  1195. switch (gp->lstate) {
  1196. case link_force_ret:
  1197. if (netif_msg_link(gp))
  1198. printk(KERN_INFO "%s: Autoneg failed again, keeping"
  1199. " forced mode\n", gp->dev->name);
  1200. gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
  1201. gp->last_forced_speed, DUPLEX_HALF);
  1202. gp->timer_ticks = 5;
  1203. gp->lstate = link_force_ok;
  1204. return 0;
  1205. case link_aneg:
  1206. /* We try forced modes after a failed aneg only on PHYs that don't
  1207. * have "magic_aneg" bit set, which means they internally do the
  1208. * while forced-mode thingy. On these, we just restart aneg
  1209. */
  1210. if (gp->phy_mii.def->magic_aneg)
  1211. return 1;
  1212. if (netif_msg_link(gp))
  1213. printk(KERN_INFO "%s: switching to forced 100bt\n",
  1214. gp->dev->name);
  1215. /* Try forced modes. */
  1216. gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
  1217. DUPLEX_HALF);
  1218. gp->timer_ticks = 5;
  1219. gp->lstate = link_force_try;
  1220. return 0;
  1221. case link_force_try:
  1222. /* Downgrade from 100 to 10 Mbps if necessary.
  1223. * If already at 10Mbps, warn user about the
  1224. * situation every 10 ticks.
  1225. */
  1226. if (gp->phy_mii.speed == SPEED_100) {
  1227. gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
  1228. DUPLEX_HALF);
  1229. gp->timer_ticks = 5;
  1230. if (netif_msg_link(gp))
  1231. printk(KERN_INFO "%s: switching to forced 10bt\n",
  1232. gp->dev->name);
  1233. return 0;
  1234. } else
  1235. return 1;
  1236. default:
  1237. return 0;
  1238. }
  1239. }
  1240. static void gem_link_timer(unsigned long data)
  1241. {
  1242. struct gem *gp = (struct gem *) data;
  1243. int restart_aneg = 0;
  1244. if (gp->asleep)
  1245. return;
  1246. spin_lock_irq(&gp->lock);
  1247. spin_lock(&gp->tx_lock);
  1248. gem_get_cell(gp);
  1249. /* If the reset task is still pending, we just
  1250. * reschedule the link timer
  1251. */
  1252. if (gp->reset_task_pending)
  1253. goto restart;
  1254. if (gp->phy_type == phy_serialink ||
  1255. gp->phy_type == phy_serdes) {
  1256. u32 val = readl(gp->regs + PCS_MIISTAT);
  1257. if (!(val & PCS_MIISTAT_LS))
  1258. val = readl(gp->regs + PCS_MIISTAT);
  1259. if ((val & PCS_MIISTAT_LS) != 0) {
  1260. gp->lstate = link_up;
  1261. netif_carrier_on(gp->dev);
  1262. (void)gem_set_link_modes(gp);
  1263. }
  1264. goto restart;
  1265. }
  1266. if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
  1267. /* Ok, here we got a link. If we had it due to a forced
  1268. * fallback, and we were configured for autoneg, we do
  1269. * retry a short autoneg pass. If you know your hub is
  1270. * broken, use ethtool ;)
  1271. */
  1272. if (gp->lstate == link_force_try && gp->want_autoneg) {
  1273. gp->lstate = link_force_ret;
  1274. gp->last_forced_speed = gp->phy_mii.speed;
  1275. gp->timer_ticks = 5;
  1276. if (netif_msg_link(gp))
  1277. printk(KERN_INFO "%s: Got link after fallback, retrying"
  1278. " autoneg once...\n", gp->dev->name);
  1279. gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
  1280. } else if (gp->lstate != link_up) {
  1281. gp->lstate = link_up;
  1282. netif_carrier_on(gp->dev);
  1283. if (gem_set_link_modes(gp))
  1284. restart_aneg = 1;
  1285. }
  1286. } else {
  1287. /* If the link was previously up, we restart the
  1288. * whole process
  1289. */
  1290. if (gp->lstate == link_up) {
  1291. gp->lstate = link_down;
  1292. if (netif_msg_link(gp))
  1293. printk(KERN_INFO "%s: Link down\n",
  1294. gp->dev->name);
  1295. netif_carrier_off(gp->dev);
  1296. gp->reset_task_pending = 1;
  1297. schedule_work(&gp->reset_task);
  1298. restart_aneg = 1;
  1299. } else if (++gp->timer_ticks > 10) {
  1300. if (found_mii_phy(gp))
  1301. restart_aneg = gem_mdio_link_not_up(gp);
  1302. else
  1303. restart_aneg = 1;
  1304. }
  1305. }
  1306. if (restart_aneg) {
  1307. gem_begin_auto_negotiation(gp, NULL);
  1308. goto out_unlock;
  1309. }
  1310. restart:
  1311. mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
  1312. out_unlock:
  1313. gem_put_cell(gp);
  1314. spin_unlock(&gp->tx_lock);
  1315. spin_unlock_irq(&gp->lock);
  1316. }
  1317. /* Must be invoked under gp->lock and gp->tx_lock. */
  1318. static void gem_clean_rings(struct gem *gp)
  1319. {
  1320. struct gem_init_block *gb = gp->init_block;
  1321. struct sk_buff *skb;
  1322. int i;
  1323. dma_addr_t dma_addr;
  1324. for (i = 0; i < RX_RING_SIZE; i++) {
  1325. struct gem_rxd *rxd;
  1326. rxd = &gb->rxd[i];
  1327. if (gp->rx_skbs[i] != NULL) {
  1328. skb = gp->rx_skbs[i];
  1329. dma_addr = le64_to_cpu(rxd->buffer);
  1330. pci_unmap_page(gp->pdev, dma_addr,
  1331. RX_BUF_ALLOC_SIZE(gp),
  1332. PCI_DMA_FROMDEVICE);
  1333. dev_kfree_skb_any(skb);
  1334. gp->rx_skbs[i] = NULL;
  1335. }
  1336. rxd->status_word = 0;
  1337. wmb();
  1338. rxd->buffer = 0;
  1339. }
  1340. for (i = 0; i < TX_RING_SIZE; i++) {
  1341. if (gp->tx_skbs[i] != NULL) {
  1342. struct gem_txd *txd;
  1343. int frag;
  1344. skb = gp->tx_skbs[i];
  1345. gp->tx_skbs[i] = NULL;
  1346. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  1347. int ent = i & (TX_RING_SIZE - 1);
  1348. txd = &gb->txd[ent];
  1349. dma_addr = le64_to_cpu(txd->buffer);
  1350. pci_unmap_page(gp->pdev, dma_addr,
  1351. le64_to_cpu(txd->control_word) &
  1352. TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
  1353. if (frag != skb_shinfo(skb)->nr_frags)
  1354. i++;
  1355. }
  1356. dev_kfree_skb_any(skb);
  1357. }
  1358. }
  1359. }
  1360. /* Must be invoked under gp->lock and gp->tx_lock. */
  1361. static void gem_init_rings(struct gem *gp)
  1362. {
  1363. struct gem_init_block *gb = gp->init_block;
  1364. struct net_device *dev = gp->dev;
  1365. int i;
  1366. dma_addr_t dma_addr;
  1367. gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
  1368. gem_clean_rings(gp);
  1369. gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
  1370. (unsigned)VLAN_ETH_FRAME_LEN);
  1371. for (i = 0; i < RX_RING_SIZE; i++) {
  1372. struct sk_buff *skb;
  1373. struct gem_rxd *rxd = &gb->rxd[i];
  1374. skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
  1375. if (!skb) {
  1376. rxd->buffer = 0;
  1377. rxd->status_word = 0;
  1378. continue;
  1379. }
  1380. gp->rx_skbs[i] = skb;
  1381. skb->dev = dev;
  1382. skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
  1383. dma_addr = pci_map_page(gp->pdev,
  1384. virt_to_page(skb->data),
  1385. offset_in_page(skb->data),
  1386. RX_BUF_ALLOC_SIZE(gp),
  1387. PCI_DMA_FROMDEVICE);
  1388. rxd->buffer = cpu_to_le64(dma_addr);
  1389. wmb();
  1390. rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
  1391. skb_reserve(skb, RX_OFFSET);
  1392. }
  1393. for (i = 0; i < TX_RING_SIZE; i++) {
  1394. struct gem_txd *txd = &gb->txd[i];
  1395. txd->control_word = 0;
  1396. wmb();
  1397. txd->buffer = 0;
  1398. }
  1399. wmb();
  1400. }
  1401. /* Init PHY interface and start link poll state machine */
  1402. static void gem_init_phy(struct gem *gp)
  1403. {
  1404. u32 mifcfg;
  1405. /* Revert MIF CFG setting done on stop_phy */
  1406. mifcfg = readl(gp->regs + MIF_CFG);
  1407. mifcfg &= ~MIF_CFG_BBMODE;
  1408. writel(mifcfg, gp->regs + MIF_CFG);
  1409. if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
  1410. int i;
  1411. /* Those delay sucks, the HW seem to love them though, I'll
  1412. * serisouly consider breaking some locks here to be able
  1413. * to schedule instead
  1414. */
  1415. for (i = 0; i < 3; i++) {
  1416. #ifdef CONFIG_PPC_PMAC
  1417. pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
  1418. msleep(20);
  1419. #endif
  1420. /* Some PHYs used by apple have problem getting back to us,
  1421. * we do an additional reset here
  1422. */
  1423. phy_write(gp, MII_BMCR, BMCR_RESET);
  1424. msleep(20);
  1425. if (phy_read(gp, MII_BMCR) != 0xffff)
  1426. break;
  1427. if (i == 2)
  1428. printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
  1429. gp->dev->name);
  1430. }
  1431. }
  1432. if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
  1433. gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
  1434. u32 val;
  1435. /* Init datapath mode register. */
  1436. if (gp->phy_type == phy_mii_mdio0 ||
  1437. gp->phy_type == phy_mii_mdio1) {
  1438. val = PCS_DMODE_MGM;
  1439. } else if (gp->phy_type == phy_serialink) {
  1440. val = PCS_DMODE_SM | PCS_DMODE_GMOE;
  1441. } else {
  1442. val = PCS_DMODE_ESM;
  1443. }
  1444. writel(val, gp->regs + PCS_DMODE);
  1445. }
  1446. if (gp->phy_type == phy_mii_mdio0 ||
  1447. gp->phy_type == phy_mii_mdio1) {
  1448. // XXX check for errors
  1449. mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
  1450. /* Init PHY */
  1451. if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
  1452. gp->phy_mii.def->ops->init(&gp->phy_mii);
  1453. } else {
  1454. u32 val;
  1455. int limit;
  1456. /* Reset PCS unit. */
  1457. val = readl(gp->regs + PCS_MIICTRL);
  1458. val |= PCS_MIICTRL_RST;
  1459. writeb(val, gp->regs + PCS_MIICTRL);
  1460. limit = 32;
  1461. while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
  1462. udelay(100);
  1463. if (limit-- <= 0)
  1464. break;
  1465. }
  1466. if (limit <= 0)
  1467. printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
  1468. gp->dev->name);
  1469. /* Make sure PCS is disabled while changing advertisement
  1470. * configuration.
  1471. */
  1472. val = readl(gp->regs + PCS_CFG);
  1473. val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
  1474. writel(val, gp->regs + PCS_CFG);
  1475. /* Advertise all capabilities except assymetric
  1476. * pause.
  1477. */
  1478. val = readl(gp->regs + PCS_MIIADV);
  1479. val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
  1480. PCS_MIIADV_SP | PCS_MIIADV_AP);
  1481. writel(val, gp->regs + PCS_MIIADV);
  1482. /* Enable and restart auto-negotiation, disable wrapback/loopback,
  1483. * and re-enable PCS.
  1484. */
  1485. val = readl(gp->regs + PCS_MIICTRL);
  1486. val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
  1487. val &= ~PCS_MIICTRL_WB;
  1488. writel(val, gp->regs + PCS_MIICTRL);
  1489. val = readl(gp->regs + PCS_CFG);
  1490. val |= PCS_CFG_ENABLE;
  1491. writel(val, gp->regs + PCS_CFG);
  1492. /* Make sure serialink loopback is off. The meaning
  1493. * of this bit is logically inverted based upon whether
  1494. * you are in Serialink or SERDES mode.
  1495. */
  1496. val = readl(gp->regs + PCS_SCTRL);
  1497. if (gp->phy_type == phy_serialink)
  1498. val &= ~PCS_SCTRL_LOOP;
  1499. else
  1500. val |= PCS_SCTRL_LOOP;
  1501. writel(val, gp->regs + PCS_SCTRL);
  1502. }
  1503. /* Default aneg parameters */
  1504. gp->timer_ticks = 0;
  1505. gp->lstate = link_down;
  1506. netif_carrier_off(gp->dev);
  1507. /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
  1508. spin_lock_irq(&gp->lock);
  1509. gem_begin_auto_negotiation(gp, NULL);
  1510. spin_unlock_irq(&gp->lock);
  1511. }
  1512. /* Must be invoked under gp->lock and gp->tx_lock. */
  1513. static void gem_init_dma(struct gem *gp)
  1514. {
  1515. u64 desc_dma = (u64) gp->gblock_dvma;
  1516. u32 val;
  1517. val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
  1518. writel(val, gp->regs + TXDMA_CFG);
  1519. writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
  1520. writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
  1521. desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
  1522. writel(0, gp->regs + TXDMA_KICK);
  1523. val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
  1524. ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
  1525. writel(val, gp->regs + RXDMA_CFG);
  1526. writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
  1527. writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
  1528. writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
  1529. val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
  1530. val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
  1531. writel(val, gp->regs + RXDMA_PTHRESH);
  1532. if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
  1533. writel(((5 & RXDMA_BLANK_IPKTS) |
  1534. ((8 << 12) & RXDMA_BLANK_ITIME)),
  1535. gp->regs + RXDMA_BLANK);
  1536. else
  1537. writel(((5 & RXDMA_BLANK_IPKTS) |
  1538. ((4 << 12) & RXDMA_BLANK_ITIME)),
  1539. gp->regs + RXDMA_BLANK);
  1540. }
  1541. /* Must be invoked under gp->lock and gp->tx_lock. */
  1542. static u32 gem_setup_multicast(struct gem *gp)
  1543. {
  1544. u32 rxcfg = 0;
  1545. int i;
  1546. if ((gp->dev->flags & IFF_ALLMULTI) ||
  1547. (gp->dev->mc_count > 256)) {
  1548. for (i=0; i<16; i++)
  1549. writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
  1550. rxcfg |= MAC_RXCFG_HFE;
  1551. } else if (gp->dev->flags & IFF_PROMISC) {
  1552. rxcfg |= MAC_RXCFG_PROM;
  1553. } else {
  1554. u16 hash_table[16];
  1555. u32 crc;
  1556. struct dev_mc_list *dmi = gp->dev->mc_list;
  1557. int i;
  1558. for (i = 0; i < 16; i++)
  1559. hash_table[i] = 0;
  1560. for (i = 0; i < gp->dev->mc_count; i++) {
  1561. char *addrs = dmi->dmi_addr;
  1562. dmi = dmi->next;
  1563. if (!(*addrs & 1))
  1564. continue;
  1565. crc = ether_crc_le(6, addrs);
  1566. crc >>= 24;
  1567. hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
  1568. }
  1569. for (i=0; i<16; i++)
  1570. writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
  1571. rxcfg |= MAC_RXCFG_HFE;
  1572. }
  1573. return rxcfg;
  1574. }
  1575. /* Must be invoked under gp->lock and gp->tx_lock. */
  1576. static void gem_init_mac(struct gem *gp)
  1577. {
  1578. unsigned char *e = &gp->dev->dev_addr[0];
  1579. writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
  1580. writel(0x00, gp->regs + MAC_IPG0);
  1581. writel(0x08, gp->regs + MAC_IPG1);
  1582. writel(0x04, gp->regs + MAC_IPG2);
  1583. writel(0x40, gp->regs + MAC_STIME);
  1584. writel(0x40, gp->regs + MAC_MINFSZ);
  1585. /* Ethernet payload + header + FCS + optional VLAN tag. */
  1586. writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
  1587. writel(0x07, gp->regs + MAC_PASIZE);
  1588. writel(0x04, gp->regs + MAC_JAMSIZE);
  1589. writel(0x10, gp->regs + MAC_ATTLIM);
  1590. writel(0x8808, gp->regs + MAC_MCTYPE);
  1591. writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
  1592. writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
  1593. writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
  1594. writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
  1595. writel(0, gp->regs + MAC_ADDR3);
  1596. writel(0, gp->regs + MAC_ADDR4);
  1597. writel(0, gp->regs + MAC_ADDR5);
  1598. writel(0x0001, gp->regs + MAC_ADDR6);
  1599. writel(0xc200, gp->regs + MAC_ADDR7);
  1600. writel(0x0180, gp->regs + MAC_ADDR8);
  1601. writel(0, gp->regs + MAC_AFILT0);
  1602. writel(0, gp->regs + MAC_AFILT1);
  1603. writel(0, gp->regs + MAC_AFILT2);
  1604. writel(0, gp->regs + MAC_AF21MSK);
  1605. writel(0, gp->regs + MAC_AF0MSK);
  1606. gp->mac_rx_cfg = gem_setup_multicast(gp);
  1607. #ifdef STRIP_FCS
  1608. gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
  1609. #endif
  1610. writel(0, gp->regs + MAC_NCOLL);
  1611. writel(0, gp->regs + MAC_FASUCC);
  1612. writel(0, gp->regs + MAC_ECOLL);
  1613. writel(0, gp->regs + MAC_LCOLL);
  1614. writel(0, gp->regs + MAC_DTIMER);
  1615. writel(0, gp->regs + MAC_PATMPS);
  1616. writel(0, gp->regs + MAC_RFCTR);
  1617. writel(0, gp->regs + MAC_LERR);
  1618. writel(0, gp->regs + MAC_AERR);
  1619. writel(0, gp->regs + MAC_FCSERR);
  1620. writel(0, gp->regs + MAC_RXCVERR);
  1621. /* Clear RX/TX/MAC/XIF config, we will set these up and enable
  1622. * them once a link is established.
  1623. */
  1624. writel(0, gp->regs + MAC_TXCFG);
  1625. writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
  1626. writel(0, gp->regs + MAC_MCCFG);
  1627. writel(0, gp->regs + MAC_XIFCFG);
  1628. /* Setup MAC interrupts. We want to get all of the interesting
  1629. * counter expiration events, but we do not want to hear about
  1630. * normal rx/tx as the DMA engine tells us that.
  1631. */
  1632. writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
  1633. writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
  1634. /* Don't enable even the PAUSE interrupts for now, we
  1635. * make no use of those events other than to record them.
  1636. */
  1637. writel(0xffffffff, gp->regs + MAC_MCMASK);
  1638. /* Don't enable GEM's WOL in normal operations
  1639. */
  1640. if (gp->has_wol)
  1641. writel(0, gp->regs + WOL_WAKECSR);
  1642. }
  1643. /* Must be invoked under gp->lock and gp->tx_lock. */
  1644. static void gem_init_pause_thresholds(struct gem *gp)
  1645. {
  1646. u32 cfg;
  1647. /* Calculate pause thresholds. Setting the OFF threshold to the
  1648. * full RX fifo size effectively disables PAUSE generation which
  1649. * is what we do for 10/100 only GEMs which have FIFOs too small
  1650. * to make real gains from PAUSE.
  1651. */
  1652. if (gp->rx_fifo_sz <= (2 * 1024)) {
  1653. gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
  1654. } else {
  1655. int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
  1656. int off = (gp->rx_fifo_sz - (max_frame * 2));
  1657. int on = off - max_frame;
  1658. gp->rx_pause_off = off;
  1659. gp->rx_pause_on = on;
  1660. }
  1661. /* Configure the chip "burst" DMA mode & enable some
  1662. * HW bug fixes on Apple version
  1663. */
  1664. cfg = 0;
  1665. if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
  1666. cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
  1667. #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
  1668. cfg |= GREG_CFG_IBURST;
  1669. #endif
  1670. cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
  1671. cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
  1672. writel(cfg, gp->regs + GREG_CFG);
  1673. /* If Infinite Burst didn't stick, then use different
  1674. * thresholds (and Apple bug fixes don't exist)
  1675. */
  1676. if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
  1677. cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
  1678. cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
  1679. writel(cfg, gp->regs + GREG_CFG);
  1680. }
  1681. }
  1682. static int gem_check_invariants(struct gem *gp)
  1683. {
  1684. struct pci_dev *pdev = gp->pdev;
  1685. u32 mif_cfg;
  1686. /* On Apple's sungem, we can't rely on registers as the chip
  1687. * was been powered down by the firmware. The PHY is looked
  1688. * up later on.
  1689. */
  1690. if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
  1691. gp->phy_type = phy_mii_mdio0;
  1692. gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
  1693. gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
  1694. gp->swrst_base = 0;
  1695. mif_cfg = readl(gp->regs + MIF_CFG);
  1696. mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
  1697. mif_cfg |= MIF_CFG_MDI0;
  1698. writel(mif_cfg, gp->regs + MIF_CFG);
  1699. writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
  1700. writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
  1701. /* We hard-code the PHY address so we can properly bring it out of
  1702. * reset later on, we can't really probe it at this point, though
  1703. * that isn't an issue.
  1704. */
  1705. if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
  1706. gp->mii_phy_addr = 1;
  1707. else
  1708. gp->mii_phy_addr = 0;
  1709. return 0;
  1710. }
  1711. mif_cfg = readl(gp->regs + MIF_CFG);
  1712. if (pdev->vendor == PCI_VENDOR_ID_SUN &&
  1713. pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
  1714. /* One of the MII PHYs _must_ be present
  1715. * as this chip has no gigabit PHY.
  1716. */
  1717. if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
  1718. printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
  1719. mif_cfg);
  1720. return -1;
  1721. }
  1722. }
  1723. /* Determine initial PHY interface type guess. MDIO1 is the
  1724. * external PHY and thus takes precedence over MDIO0.
  1725. */
  1726. if (mif_cfg & MIF_CFG_MDI1) {
  1727. gp->phy_type = phy_mii_mdio1;
  1728. mif_cfg |= MIF_CFG_PSELECT;
  1729. writel(mif_cfg, gp->regs + MIF_CFG);
  1730. } else if (mif_cfg & MIF_CFG_MDI0) {
  1731. gp->phy_type = phy_mii_mdio0;
  1732. mif_cfg &= ~MIF_CFG_PSELECT;
  1733. writel(mif_cfg, gp->regs + MIF_CFG);
  1734. } else {
  1735. gp->phy_type = phy_serialink;
  1736. }
  1737. if (gp->phy_type == phy_mii_mdio1 ||
  1738. gp->phy_type == phy_mii_mdio0) {
  1739. int i;
  1740. for (i = 0; i < 32; i++) {
  1741. gp->mii_phy_addr = i;
  1742. if (phy_read(gp, MII_BMCR) != 0xffff)
  1743. break;
  1744. }
  1745. if (i == 32) {
  1746. if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
  1747. printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
  1748. return -1;
  1749. }
  1750. gp->phy_type = phy_serdes;
  1751. }
  1752. }
  1753. /* Fetch the FIFO configurations now too. */
  1754. gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
  1755. gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
  1756. if (pdev->vendor == PCI_VENDOR_ID_SUN) {
  1757. if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
  1758. if (gp->tx_fifo_sz != (9 * 1024) ||
  1759. gp->rx_fifo_sz != (20 * 1024)) {
  1760. printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
  1761. gp->tx_fifo_sz, gp->rx_fifo_sz);
  1762. return -1;
  1763. }
  1764. gp->swrst_base = 0;
  1765. } else {
  1766. if (gp->tx_fifo_sz != (2 * 1024) ||
  1767. gp->rx_fifo_sz != (2 * 1024)) {
  1768. printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
  1769. gp->tx_fifo_sz, gp->rx_fifo_sz);
  1770. return -1;
  1771. }
  1772. gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
  1773. }
  1774. }
  1775. return 0;
  1776. }
  1777. /* Must be invoked under gp->lock and gp->tx_lock. */
  1778. static void gem_reinit_chip(struct gem *gp)
  1779. {
  1780. /* Reset the chip */
  1781. gem_reset(gp);
  1782. /* Make sure ints are disabled */
  1783. gem_disable_ints(gp);
  1784. /* Allocate & setup ring buffers */
  1785. gem_init_rings(gp);
  1786. /* Configure pause thresholds */
  1787. gem_init_pause_thresholds(gp);
  1788. /* Init DMA & MAC engines */
  1789. gem_init_dma(gp);
  1790. gem_init_mac(gp);
  1791. }
  1792. /* Must be invoked with no lock held. */
  1793. static void gem_stop_phy(struct gem *gp, int wol)
  1794. {
  1795. u32 mifcfg;
  1796. unsigned long flags;
  1797. /* Let the chip settle down a bit, it seems that helps
  1798. * for sleep mode on some models
  1799. */
  1800. msleep(10);
  1801. /* Make sure we aren't polling PHY status change. We
  1802. * don't currently use that feature though
  1803. */
  1804. mifcfg = readl(gp->regs + MIF_CFG);
  1805. mifcfg &= ~MIF_CFG_POLL;
  1806. writel(mifcfg, gp->regs + MIF_CFG);
  1807. if (wol && gp->has_wol) {
  1808. unsigned char *e = &gp->dev->dev_addr[0];
  1809. u32 csr;
  1810. /* Setup wake-on-lan for MAGIC packet */
  1811. writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
  1812. gp->regs + MAC_RXCFG);
  1813. writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
  1814. writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
  1815. writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
  1816. writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
  1817. csr = WOL_WAKECSR_ENABLE;
  1818. if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
  1819. csr |= WOL_WAKECSR_MII;
  1820. writel(csr, gp->regs + WOL_WAKECSR);
  1821. } else {
  1822. writel(0, gp->regs + MAC_RXCFG);
  1823. (void)readl(gp->regs + MAC_RXCFG);
  1824. /* Machine sleep will die in strange ways if we
  1825. * dont wait a bit here, looks like the chip takes
  1826. * some time to really shut down
  1827. */
  1828. msleep(10);
  1829. }
  1830. writel(0, gp->regs + MAC_TXCFG);
  1831. writel(0, gp->regs + MAC_XIFCFG);
  1832. writel(0, gp->regs + TXDMA_CFG);
  1833. writel(0, gp->regs + RXDMA_CFG);
  1834. if (!wol) {
  1835. spin_lock_irqsave(&gp->lock, flags);
  1836. spin_lock(&gp->tx_lock);
  1837. gem_reset(gp);
  1838. writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
  1839. writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
  1840. spin_unlock(&gp->tx_lock);
  1841. spin_unlock_irqrestore(&gp->lock, flags);
  1842. /* No need to take the lock here */
  1843. if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
  1844. gp->phy_mii.def->ops->suspend(&gp->phy_mii);
  1845. /* According to Apple, we must set the MDIO pins to this begnign
  1846. * state or we may 1) eat more current, 2) damage some PHYs
  1847. */
  1848. writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
  1849. writel(0, gp->regs + MIF_BBCLK);
  1850. writel(0, gp->regs + MIF_BBDATA);
  1851. writel(0, gp->regs + MIF_BBOENAB);
  1852. writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
  1853. (void) readl(gp->regs + MAC_XIFCFG);
  1854. }
  1855. }
  1856. static int gem_do_start(struct net_device *dev)
  1857. {
  1858. struct gem *gp = dev->priv;
  1859. unsigned long flags;
  1860. spin_lock_irqsave(&gp->lock, flags);
  1861. spin_lock(&gp->tx_lock);
  1862. /* Enable the cell */
  1863. gem_get_cell(gp);
  1864. /* Init & setup chip hardware */
  1865. gem_reinit_chip(gp);
  1866. gp->running = 1;
  1867. if (gp->lstate == link_up) {
  1868. netif_carrier_on(gp->dev);
  1869. gem_set_link_modes(gp);
  1870. }
  1871. netif_wake_queue(gp->dev);
  1872. spin_unlock(&gp->tx_lock);
  1873. spin_unlock_irqrestore(&gp->lock, flags);
  1874. if (request_irq(gp->pdev->irq, gem_interrupt,
  1875. IRQF_SHARED, dev->name, (void *)dev)) {
  1876. printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
  1877. spin_lock_irqsave(&gp->lock, flags);
  1878. spin_lock(&gp->tx_lock);
  1879. gp->running = 0;
  1880. gem_reset(gp);
  1881. gem_clean_rings(gp);
  1882. gem_put_cell(gp);
  1883. spin_unlock(&gp->tx_lock);
  1884. spin_unlock_irqrestore(&gp->lock, flags);
  1885. return -EAGAIN;
  1886. }
  1887. return 0;
  1888. }
  1889. static void gem_do_stop(struct net_device *dev, int wol)
  1890. {
  1891. struct gem *gp = dev->priv;
  1892. unsigned long flags;
  1893. spin_lock_irqsave(&gp->lock, flags);
  1894. spin_lock(&gp->tx_lock);
  1895. gp->running = 0;
  1896. /* Stop netif queue */
  1897. netif_stop_queue(dev);
  1898. /* Make sure ints are disabled */
  1899. gem_disable_ints(gp);
  1900. /* We can drop the lock now */
  1901. spin_unlock(&gp->tx_lock);
  1902. spin_unlock_irqrestore(&gp->lock, flags);
  1903. /* If we are going to sleep with WOL */
  1904. gem_stop_dma(gp);
  1905. msleep(10);
  1906. if (!wol)
  1907. gem_reset(gp);
  1908. msleep(10);
  1909. /* Get rid of rings */
  1910. gem_clean_rings(gp);
  1911. /* No irq needed anymore */
  1912. free_irq(gp->pdev->irq, (void *) dev);
  1913. /* Cell not needed neither if no WOL */
  1914. if (!wol) {
  1915. spin_lock_irqsave(&gp->lock, flags);
  1916. gem_put_cell(gp);
  1917. spin_unlock_irqrestore(&gp->lock, flags);
  1918. }
  1919. }
  1920. static void gem_reset_task(struct work_struct *work)
  1921. {
  1922. struct gem *gp = container_of(work, struct gem, reset_task);
  1923. mutex_lock(&gp->pm_mutex);
  1924. netif_poll_disable(gp->dev);
  1925. spin_lock_irq(&gp->lock);
  1926. spin_lock(&gp->tx_lock);
  1927. if (gp->running == 0)
  1928. goto not_running;
  1929. if (gp->running) {
  1930. netif_stop_queue(gp->dev);
  1931. /* Reset the chip & rings */
  1932. gem_reinit_chip(gp);
  1933. if (gp->lstate == link_up)
  1934. gem_set_link_modes(gp);
  1935. netif_wake_queue(gp->dev);
  1936. }
  1937. not_running:
  1938. gp->reset_task_pending = 0;
  1939. spin_unlock(&gp->tx_lock);
  1940. spin_unlock_irq(&gp->lock);
  1941. netif_poll_enable(gp->dev);
  1942. mutex_unlock(&gp->pm_mutex);
  1943. }
  1944. static int gem_open(struct net_device *dev)
  1945. {
  1946. struct gem *gp = dev->priv;
  1947. int rc = 0;
  1948. mutex_lock(&gp->pm_mutex);
  1949. /* We need the cell enabled */
  1950. if (!gp->asleep)
  1951. rc = gem_do_start(dev);
  1952. gp->opened = (rc == 0);
  1953. mutex_unlock(&gp->pm_mutex);
  1954. return rc;
  1955. }
  1956. static int gem_close(struct net_device *dev)
  1957. {
  1958. struct gem *gp = dev->priv;
  1959. /* Note: we don't need to call netif_poll_disable() here because
  1960. * our caller (dev_close) already did it for us
  1961. */
  1962. mutex_lock(&gp->pm_mutex);
  1963. gp->opened = 0;
  1964. if (!gp->asleep)
  1965. gem_do_stop(dev, 0);
  1966. mutex_unlock(&gp->pm_mutex);
  1967. return 0;
  1968. }
  1969. #ifdef CONFIG_PM
  1970. static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
  1971. {
  1972. struct net_device *dev = pci_get_drvdata(pdev);
  1973. struct gem *gp = dev->priv;
  1974. unsigned long flags;
  1975. mutex_lock(&gp->pm_mutex);
  1976. netif_poll_disable(dev);
  1977. printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
  1978. dev->name,
  1979. (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
  1980. /* Keep the cell enabled during the entire operation */
  1981. spin_lock_irqsave(&gp->lock, flags);
  1982. spin_lock(&gp->tx_lock);
  1983. gem_get_cell(gp);
  1984. spin_unlock(&gp->tx_lock);
  1985. spin_unlock_irqrestore(&gp->lock, flags);
  1986. /* If the driver is opened, we stop the MAC */
  1987. if (gp->opened) {
  1988. /* Stop traffic, mark us closed */
  1989. netif_device_detach(dev);
  1990. /* Switch off MAC, remember WOL setting */
  1991. gp->asleep_wol = gp->wake_on_lan;
  1992. gem_do_stop(dev, gp->asleep_wol);
  1993. } else
  1994. gp->asleep_wol = 0;
  1995. /* Mark us asleep */
  1996. gp->asleep = 1;
  1997. wmb();
  1998. /* Stop the link timer */
  1999. del_timer_sync(&gp->link_timer);
  2000. /* Now we release the mutex to not block the reset task who
  2001. * can take it too. We are marked asleep, so there will be no
  2002. * conflict here
  2003. */
  2004. mutex_unlock(&gp->pm_mutex);
  2005. /* Wait for a pending reset task to complete */
  2006. while (gp->reset_task_pending)
  2007. yield();
  2008. flush_scheduled_work();
  2009. /* Shut the PHY down eventually and setup WOL */
  2010. gem_stop_phy(gp, gp->asleep_wol);
  2011. /* Make sure bus master is disabled */
  2012. pci_disable_device(gp->pdev);
  2013. /* Release the cell, no need to take a lock at this point since
  2014. * nothing else can happen now
  2015. */
  2016. gem_put_cell(gp);
  2017. return 0;
  2018. }
  2019. static int gem_resume(struct pci_dev *pdev)
  2020. {
  2021. struct net_device *dev = pci_get_drvdata(pdev);
  2022. struct gem *gp = dev->priv;
  2023. unsigned long flags;
  2024. printk(KERN_INFO "%s: resuming\n", dev->name);
  2025. mutex_lock(&gp->pm_mutex);
  2026. /* Keep the cell enabled during the entire operation, no need to
  2027. * take a lock here tho since nothing else can happen while we are
  2028. * marked asleep
  2029. */
  2030. gem_get_cell(gp);
  2031. /* Make sure PCI access and bus master are enabled */
  2032. if (pci_enable_device(gp->pdev)) {
  2033. printk(KERN_ERR "%s: Can't re-enable chip !\n",
  2034. dev->name);
  2035. /* Put cell and forget it for now, it will be considered as
  2036. * still asleep, a new sleep cycle may bring it back
  2037. */
  2038. gem_put_cell(gp);
  2039. mutex_unlock(&gp->pm_mutex);
  2040. return 0;
  2041. }
  2042. pci_set_master(gp->pdev);
  2043. /* Reset everything */
  2044. gem_reset(gp);
  2045. /* Mark us woken up */
  2046. gp->asleep = 0;
  2047. wmb();
  2048. /* Bring the PHY back. Again, lock is useless at this point as
  2049. * nothing can be happening until we restart the whole thing
  2050. */
  2051. gem_init_phy(gp);
  2052. /* If we were opened, bring everything back */
  2053. if (gp->opened) {
  2054. /* Restart MAC */
  2055. gem_do_start(dev);
  2056. /* Re-attach net device */
  2057. netif_device_attach(dev);
  2058. }
  2059. spin_lock_irqsave(&gp->lock, flags);
  2060. spin_lock(&gp->tx_lock);
  2061. /* If we had WOL enabled, the cell clock was never turned off during
  2062. * sleep, so we end up beeing unbalanced. Fix that here
  2063. */
  2064. if (gp->asleep_wol)
  2065. gem_put_cell(gp);
  2066. /* This function doesn't need to hold the cell, it will be held if the
  2067. * driver is open by gem_do_start().
  2068. */
  2069. gem_put_cell(gp);
  2070. spin_unlock(&gp->tx_lock);
  2071. spin_unlock_irqrestore(&gp->lock, flags);
  2072. netif_poll_enable(dev);
  2073. mutex_unlock(&gp->pm_mutex);
  2074. return 0;
  2075. }
  2076. #endif /* CONFIG_PM */
  2077. static struct net_device_stats *gem_get_stats(struct net_device *dev)
  2078. {
  2079. struct gem *gp = dev->priv;
  2080. struct net_device_stats *stats = &gp->net_stats;
  2081. spin_lock_irq(&gp->lock);
  2082. spin_lock(&gp->tx_lock);
  2083. /* I have seen this being called while the PM was in progress,
  2084. * so we shield against this
  2085. */
  2086. if (gp->running) {
  2087. stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
  2088. writel(0, gp->regs + MAC_FCSERR);
  2089. stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
  2090. writel(0, gp->regs + MAC_AERR);
  2091. stats->rx_length_errors += readl(gp->regs + MAC_LERR);
  2092. writel(0, gp->regs + MAC_LERR);
  2093. stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
  2094. stats->collisions +=
  2095. (readl(gp->regs + MAC_ECOLL) +
  2096. readl(gp->regs + MAC_LCOLL));
  2097. writel(0, gp->regs + MAC_ECOLL);
  2098. writel(0, gp->regs + MAC_LCOLL);
  2099. }
  2100. spin_unlock(&gp->tx_lock);
  2101. spin_unlock_irq(&gp->lock);
  2102. return &gp->net_stats;
  2103. }
  2104. static int gem_set_mac_address(struct net_device *dev, void *addr)
  2105. {
  2106. struct sockaddr *macaddr = (struct sockaddr *) addr;
  2107. struct gem *gp = dev->priv;
  2108. unsigned char *e = &dev->dev_addr[0];
  2109. if (!is_valid_ether_addr(macaddr->sa_data))
  2110. return -EADDRNOTAVAIL;
  2111. if (!netif_running(dev) || !netif_device_present(dev)) {
  2112. /* We'll just catch it later when the
  2113. * device is up'd or resumed.
  2114. */
  2115. memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
  2116. return 0;
  2117. }
  2118. mutex_lock(&gp->pm_mutex);
  2119. memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
  2120. if (gp->running) {
  2121. writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
  2122. writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
  2123. writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
  2124. }
  2125. mutex_unlock(&gp->pm_mutex);
  2126. return 0;
  2127. }
  2128. static void gem_set_multicast(struct net_device *dev)
  2129. {
  2130. struct gem *gp = dev->priv;
  2131. u32 rxcfg, rxcfg_new;
  2132. int limit = 10000;
  2133. spin_lock_irq(&gp->lock);
  2134. spin_lock(&gp->tx_lock);
  2135. if (!gp->running)
  2136. goto bail;
  2137. netif_stop_queue(dev);
  2138. rxcfg = readl(gp->regs + MAC_RXCFG);
  2139. rxcfg_new = gem_setup_multicast(gp);
  2140. #ifdef STRIP_FCS
  2141. rxcfg_new |= MAC_RXCFG_SFCS;
  2142. #endif
  2143. gp->mac_rx_cfg = rxcfg_new;
  2144. writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
  2145. while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
  2146. if (!limit--)
  2147. break;
  2148. udelay(10);
  2149. }
  2150. rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
  2151. rxcfg |= rxcfg_new;
  2152. writel(rxcfg, gp->regs + MAC_RXCFG);
  2153. netif_wake_queue(dev);
  2154. bail:
  2155. spin_unlock(&gp->tx_lock);
  2156. spin_unlock_irq(&gp->lock);
  2157. }
  2158. /* Jumbo-grams don't seem to work :-( */
  2159. #define GEM_MIN_MTU 68
  2160. #if 1
  2161. #define GEM_MAX_MTU 1500
  2162. #else
  2163. #define GEM_MAX_MTU 9000
  2164. #endif
  2165. static int gem_change_mtu(struct net_device *dev, int new_mtu)
  2166. {
  2167. struct gem *gp = dev->priv;
  2168. if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
  2169. return -EINVAL;
  2170. if (!netif_running(dev) || !netif_device_present(dev)) {
  2171. /* We'll just catch it later when the
  2172. * device is up'd or resumed.
  2173. */
  2174. dev->mtu = new_mtu;
  2175. return 0;
  2176. }
  2177. mutex_lock(&gp->pm_mutex);
  2178. spin_lock_irq(&gp->lock);
  2179. spin_lock(&gp->tx_lock);
  2180. dev->mtu = new_mtu;
  2181. if (gp->running) {
  2182. gem_reinit_chip(gp);
  2183. if (gp->lstate == link_up)
  2184. gem_set_link_modes(gp);
  2185. }
  2186. spin_unlock(&gp->tx_lock);
  2187. spin_unlock_irq(&gp->lock);
  2188. mutex_unlock(&gp->pm_mutex);
  2189. return 0;
  2190. }
  2191. static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  2192. {
  2193. struct gem *gp = dev->priv;
  2194. strcpy(info->driver, DRV_NAME);
  2195. strcpy(info->version, DRV_VERSION);
  2196. strcpy(info->bus_info, pci_name(gp->pdev));
  2197. }
  2198. static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2199. {
  2200. struct gem *gp = dev->priv;
  2201. if (gp->phy_type == phy_mii_mdio0 ||
  2202. gp->phy_type == phy_mii_mdio1) {
  2203. if (gp->phy_mii.def)
  2204. cmd->supported = gp->phy_mii.def->features;
  2205. else
  2206. cmd->supported = (SUPPORTED_10baseT_Half |
  2207. SUPPORTED_10baseT_Full);
  2208. /* XXX hardcoded stuff for now */
  2209. cmd->port = PORT_MII;
  2210. cmd->transceiver = XCVR_EXTERNAL;
  2211. cmd->phy_address = 0; /* XXX fixed PHYAD */
  2212. /* Return current PHY settings */
  2213. spin_lock_irq(&gp->lock);
  2214. cmd->autoneg = gp->want_autoneg;
  2215. cmd->speed = gp->phy_mii.speed;
  2216. cmd->duplex = gp->phy_mii.duplex;
  2217. cmd->advertising = gp->phy_mii.advertising;
  2218. /* If we started with a forced mode, we don't have a default
  2219. * advertise set, we need to return something sensible so
  2220. * userland can re-enable autoneg properly.
  2221. */
  2222. if (cmd->advertising == 0)
  2223. cmd->advertising = cmd->supported;
  2224. spin_unlock_irq(&gp->lock);
  2225. } else { // XXX PCS ?
  2226. cmd->supported =
  2227. (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  2228. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  2229. SUPPORTED_Autoneg);
  2230. cmd->advertising = cmd->supported;
  2231. cmd->speed = 0;
  2232. cmd->duplex = cmd->port = cmd->phy_address =
  2233. cmd->transceiver = cmd->autoneg = 0;
  2234. }
  2235. cmd->maxtxpkt = cmd->maxrxpkt = 0;
  2236. return 0;
  2237. }
  2238. static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2239. {
  2240. struct gem *gp = dev->priv;
  2241. /* Verify the settings we care about. */
  2242. if (cmd->autoneg != AUTONEG_ENABLE &&
  2243. cmd->autoneg != AUTONEG_DISABLE)
  2244. return -EINVAL;
  2245. if (cmd->autoneg == AUTONEG_ENABLE &&
  2246. cmd->advertising == 0)
  2247. return -EINVAL;
  2248. if (cmd->autoneg == AUTONEG_DISABLE &&
  2249. ((cmd->speed != SPEED_1000 &&
  2250. cmd->speed != SPEED_100 &&
  2251. cmd->speed != SPEED_10) ||
  2252. (cmd->duplex != DUPLEX_HALF &&
  2253. cmd->duplex != DUPLEX_FULL)))
  2254. return -EINVAL;
  2255. /* Apply settings and restart link process. */
  2256. spin_lock_irq(&gp->lock);
  2257. gem_get_cell(gp);
  2258. gem_begin_auto_negotiation(gp, cmd);
  2259. gem_put_cell(gp);
  2260. spin_unlock_irq(&gp->lock);
  2261. return 0;
  2262. }
  2263. static int gem_nway_reset(struct net_device *dev)
  2264. {
  2265. struct gem *gp = dev->priv;
  2266. if (!gp->want_autoneg)
  2267. return -EINVAL;
  2268. /* Restart link process. */
  2269. spin_lock_irq(&gp->lock);
  2270. gem_get_cell(gp);
  2271. gem_begin_auto_negotiation(gp, NULL);
  2272. gem_put_cell(gp);
  2273. spin_unlock_irq(&gp->lock);
  2274. return 0;
  2275. }
  2276. static u32 gem_get_msglevel(struct net_device *dev)
  2277. {
  2278. struct gem *gp = dev->priv;
  2279. return gp->msg_enable;
  2280. }
  2281. static void gem_set_msglevel(struct net_device *dev, u32 value)
  2282. {
  2283. struct gem *gp = dev->priv;
  2284. gp->msg_enable = value;
  2285. }
  2286. /* Add more when I understand how to program the chip */
  2287. /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
  2288. #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
  2289. static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2290. {
  2291. struct gem *gp = dev->priv;
  2292. /* Add more when I understand how to program the chip */
  2293. if (gp->has_wol) {
  2294. wol->supported = WOL_SUPPORTED_MASK;
  2295. wol->wolopts = gp->wake_on_lan;
  2296. } else {
  2297. wol->supported = 0;
  2298. wol->wolopts = 0;
  2299. }
  2300. }
  2301. static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2302. {
  2303. struct gem *gp = dev->priv;
  2304. if (!gp->has_wol)
  2305. return -EOPNOTSUPP;
  2306. gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
  2307. return 0;
  2308. }
  2309. static const struct ethtool_ops gem_ethtool_ops = {
  2310. .get_drvinfo = gem_get_drvinfo,
  2311. .get_link = ethtool_op_get_link,
  2312. .get_settings = gem_get_settings,
  2313. .set_settings = gem_set_settings,
  2314. .nway_reset = gem_nway_reset,
  2315. .get_msglevel = gem_get_msglevel,
  2316. .set_msglevel = gem_set_msglevel,
  2317. .get_wol = gem_get_wol,
  2318. .set_wol = gem_set_wol,
  2319. };
  2320. static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  2321. {
  2322. struct gem *gp = dev->priv;
  2323. struct mii_ioctl_data *data = if_mii(ifr);
  2324. int rc = -EOPNOTSUPP;
  2325. unsigned long flags;
  2326. /* Hold the PM mutex while doing ioctl's or we may collide
  2327. * with power management.
  2328. */
  2329. mutex_lock(&gp->pm_mutex);
  2330. spin_lock_irqsave(&gp->lock, flags);
  2331. gem_get_cell(gp);
  2332. spin_unlock_irqrestore(&gp->lock, flags);
  2333. switch (cmd) {
  2334. case SIOCGMIIPHY: /* Get address of MII PHY in use. */
  2335. data->phy_id = gp->mii_phy_addr;
  2336. /* Fallthrough... */
  2337. case SIOCGMIIREG: /* Read MII PHY register. */
  2338. if (!gp->running)
  2339. rc = -EAGAIN;
  2340. else {
  2341. data->val_out = __phy_read(gp, data->phy_id & 0x1f,
  2342. data->reg_num & 0x1f);
  2343. rc = 0;
  2344. }
  2345. break;
  2346. case SIOCSMIIREG: /* Write MII PHY register. */
  2347. if (!capable(CAP_NET_ADMIN))
  2348. rc = -EPERM;
  2349. else if (!gp->running)
  2350. rc = -EAGAIN;
  2351. else {
  2352. __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
  2353. data->val_in);
  2354. rc = 0;
  2355. }
  2356. break;
  2357. };
  2358. spin_lock_irqsave(&gp->lock, flags);
  2359. gem_put_cell(gp);
  2360. spin_unlock_irqrestore(&gp->lock, flags);
  2361. mutex_unlock(&gp->pm_mutex);
  2362. return rc;
  2363. }
  2364. #if (!defined(__sparc__) && !defined(CONFIG_PPC_PMAC))
  2365. /* Fetch MAC address from vital product data of PCI ROM. */
  2366. static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
  2367. {
  2368. int this_offset;
  2369. for (this_offset = 0x20; this_offset < len; this_offset++) {
  2370. void __iomem *p = rom_base + this_offset;
  2371. int i;
  2372. if (readb(p + 0) != 0x90 ||
  2373. readb(p + 1) != 0x00 ||
  2374. readb(p + 2) != 0x09 ||
  2375. readb(p + 3) != 0x4e ||
  2376. readb(p + 4) != 0x41 ||
  2377. readb(p + 5) != 0x06)
  2378. continue;
  2379. this_offset += 6;
  2380. p += 6;
  2381. for (i = 0; i < 6; i++)
  2382. dev_addr[i] = readb(p + i);
  2383. return 1;
  2384. }
  2385. return 0;
  2386. }
  2387. static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
  2388. {
  2389. size_t size;
  2390. void __iomem *p = pci_map_rom(pdev, &size);
  2391. if (p) {
  2392. int found;
  2393. found = readb(p) == 0x55 &&
  2394. readb(p + 1) == 0xaa &&
  2395. find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
  2396. pci_unmap_rom(pdev, p);
  2397. if (found)
  2398. return;
  2399. }
  2400. /* Sun MAC prefix then 3 random bytes. */
  2401. dev_addr[0] = 0x08;
  2402. dev_addr[1] = 0x00;
  2403. dev_addr[2] = 0x20;
  2404. get_random_bytes(dev_addr + 3, 3);
  2405. return;
  2406. }
  2407. #endif /* not Sparc and not PPC */
  2408. static int __devinit gem_get_device_address(struct gem *gp)
  2409. {
  2410. #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
  2411. struct net_device *dev = gp->dev;
  2412. #endif
  2413. #if defined(__sparc__)
  2414. struct pci_dev *pdev = gp->pdev;
  2415. struct pcidev_cookie *pcp = pdev->sysdata;
  2416. int use_idprom = 1;
  2417. if (pcp != NULL) {
  2418. unsigned char *addr;
  2419. int len;
  2420. addr = of_get_property(pcp->prom_node, "local-mac-address",
  2421. &len);
  2422. if (addr && len == 6) {
  2423. use_idprom = 0;
  2424. memcpy(dev->dev_addr, addr, 6);
  2425. }
  2426. }
  2427. if (use_idprom)
  2428. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  2429. #elif defined(CONFIG_PPC_PMAC)
  2430. const unsigned char *addr;
  2431. addr = get_property(gp->of_node, "local-mac-address", NULL);
  2432. if (addr == NULL) {
  2433. printk("\n");
  2434. printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
  2435. return -1;
  2436. }
  2437. memcpy(dev->dev_addr, addr, 6);
  2438. #else
  2439. get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
  2440. #endif
  2441. return 0;
  2442. }
  2443. static void gem_remove_one(struct pci_dev *pdev)
  2444. {
  2445. struct net_device *dev = pci_get_drvdata(pdev);
  2446. if (dev) {
  2447. struct gem *gp = dev->priv;
  2448. unregister_netdev(dev);
  2449. /* Stop the link timer */
  2450. del_timer_sync(&gp->link_timer);
  2451. /* We shouldn't need any locking here */
  2452. gem_get_cell(gp);
  2453. /* Wait for a pending reset task to complete */
  2454. while (gp->reset_task_pending)
  2455. yield();
  2456. flush_scheduled_work();
  2457. /* Shut the PHY down */
  2458. gem_stop_phy(gp, 0);
  2459. gem_put_cell(gp);
  2460. /* Make sure bus master is disabled */
  2461. pci_disable_device(gp->pdev);
  2462. /* Free resources */
  2463. pci_free_consistent(pdev,
  2464. sizeof(struct gem_init_block),
  2465. gp->init_block,
  2466. gp->gblock_dvma);
  2467. iounmap(gp->regs);
  2468. pci_release_regions(pdev);
  2469. free_netdev(dev);
  2470. pci_set_drvdata(pdev, NULL);
  2471. }
  2472. }
  2473. static int __devinit gem_init_one(struct pci_dev *pdev,
  2474. const struct pci_device_id *ent)
  2475. {
  2476. static int gem_version_printed = 0;
  2477. unsigned long gemreg_base, gemreg_len;
  2478. struct net_device *dev;
  2479. struct gem *gp;
  2480. int i, err, pci_using_dac;
  2481. if (gem_version_printed++ == 0)
  2482. printk(KERN_INFO "%s", version);
  2483. /* Apple gmac note: during probe, the chip is powered up by
  2484. * the arch code to allow the code below to work (and to let
  2485. * the chip be probed on the config space. It won't stay powered
  2486. * up until the interface is brought up however, so we can't rely
  2487. * on register configuration done at this point.
  2488. */
  2489. err = pci_enable_device(pdev);
  2490. if (err) {
  2491. printk(KERN_ERR PFX "Cannot enable MMIO operation, "
  2492. "aborting.\n");
  2493. return err;
  2494. }
  2495. pci_set_master(pdev);
  2496. /* Configure DMA attributes. */
  2497. /* All of the GEM documentation states that 64-bit DMA addressing
  2498. * is fully supported and should work just fine. However the
  2499. * front end for RIO based GEMs is different and only supports
  2500. * 32-bit addressing.
  2501. *
  2502. * For now we assume the various PPC GEMs are 32-bit only as well.
  2503. */
  2504. if (pdev->vendor == PCI_VENDOR_ID_SUN &&
  2505. pdev->device == PCI_DEVICE_ID_SUN_GEM &&
  2506. !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  2507. pci_using_dac = 1;
  2508. } else {
  2509. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2510. if (err) {
  2511. printk(KERN_ERR PFX "No usable DMA configuration, "
  2512. "aborting.\n");
  2513. goto err_disable_device;
  2514. }
  2515. pci_using_dac = 0;
  2516. }
  2517. gemreg_base = pci_resource_start(pdev, 0);
  2518. gemreg_len = pci_resource_len(pdev, 0);
  2519. if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
  2520. printk(KERN_ERR PFX "Cannot find proper PCI device "
  2521. "base address, aborting.\n");
  2522. err = -ENODEV;
  2523. goto err_disable_device;
  2524. }
  2525. dev = alloc_etherdev(sizeof(*gp));
  2526. if (!dev) {
  2527. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  2528. err = -ENOMEM;
  2529. goto err_disable_device;
  2530. }
  2531. SET_MODULE_OWNER(dev);
  2532. SET_NETDEV_DEV(dev, &pdev->dev);
  2533. gp = dev->priv;
  2534. err = pci_request_regions(pdev, DRV_NAME);
  2535. if (err) {
  2536. printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  2537. "aborting.\n");
  2538. goto err_out_free_netdev;
  2539. }
  2540. gp->pdev = pdev;
  2541. dev->base_addr = (long) pdev;
  2542. gp->dev = dev;
  2543. gp->msg_enable = DEFAULT_MSG;
  2544. spin_lock_init(&gp->lock);
  2545. spin_lock_init(&gp->tx_lock);
  2546. mutex_init(&gp->pm_mutex);
  2547. init_timer(&gp->link_timer);
  2548. gp->link_timer.function = gem_link_timer;
  2549. gp->link_timer.data = (unsigned long) gp;
  2550. INIT_WORK(&gp->reset_task, gem_reset_task);
  2551. gp->lstate = link_down;
  2552. gp->timer_ticks = 0;
  2553. netif_carrier_off(dev);
  2554. gp->regs = ioremap(gemreg_base, gemreg_len);
  2555. if (gp->regs == 0UL) {
  2556. printk(KERN_ERR PFX "Cannot map device registers, "
  2557. "aborting.\n");
  2558. err = -EIO;
  2559. goto err_out_free_res;
  2560. }
  2561. /* On Apple, we want a reference to the Open Firmware device-tree
  2562. * node. We use it for clock control.
  2563. */
  2564. #ifdef CONFIG_PPC_PMAC
  2565. gp->of_node = pci_device_to_OF_node(pdev);
  2566. #endif
  2567. /* Only Apple version supports WOL afaik */
  2568. if (pdev->vendor == PCI_VENDOR_ID_APPLE)
  2569. gp->has_wol = 1;
  2570. /* Make sure cell is enabled */
  2571. gem_get_cell(gp);
  2572. /* Make sure everything is stopped and in init state */
  2573. gem_reset(gp);
  2574. /* Fill up the mii_phy structure (even if we won't use it) */
  2575. gp->phy_mii.dev = dev;
  2576. gp->phy_mii.mdio_read = _phy_read;
  2577. gp->phy_mii.mdio_write = _phy_write;
  2578. #ifdef CONFIG_PPC_PMAC
  2579. gp->phy_mii.platform_data = gp->of_node;
  2580. #endif
  2581. /* By default, we start with autoneg */
  2582. gp->want_autoneg = 1;
  2583. /* Check fifo sizes, PHY type, etc... */
  2584. if (gem_check_invariants(gp)) {
  2585. err = -ENODEV;
  2586. goto err_out_iounmap;
  2587. }
  2588. /* It is guaranteed that the returned buffer will be at least
  2589. * PAGE_SIZE aligned.
  2590. */
  2591. gp->init_block = (struct gem_init_block *)
  2592. pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
  2593. &gp->gblock_dvma);
  2594. if (!gp->init_block) {
  2595. printk(KERN_ERR PFX "Cannot allocate init block, "
  2596. "aborting.\n");
  2597. err = -ENOMEM;
  2598. goto err_out_iounmap;
  2599. }
  2600. if (gem_get_device_address(gp))
  2601. goto err_out_free_consistent;
  2602. dev->open = gem_open;
  2603. dev->stop = gem_close;
  2604. dev->hard_start_xmit = gem_start_xmit;
  2605. dev->get_stats = gem_get_stats;
  2606. dev->set_multicast_list = gem_set_multicast;
  2607. dev->do_ioctl = gem_ioctl;
  2608. dev->poll = gem_poll;
  2609. dev->weight = 64;
  2610. dev->ethtool_ops = &gem_ethtool_ops;
  2611. dev->tx_timeout = gem_tx_timeout;
  2612. dev->watchdog_timeo = 5 * HZ;
  2613. dev->change_mtu = gem_change_mtu;
  2614. dev->irq = pdev->irq;
  2615. dev->dma = 0;
  2616. dev->set_mac_address = gem_set_mac_address;
  2617. #ifdef CONFIG_NET_POLL_CONTROLLER
  2618. dev->poll_controller = gem_poll_controller;
  2619. #endif
  2620. /* Set that now, in case PM kicks in now */
  2621. pci_set_drvdata(pdev, dev);
  2622. /* Detect & init PHY, start autoneg, we release the cell now
  2623. * too, it will be managed by whoever needs it
  2624. */
  2625. gem_init_phy(gp);
  2626. spin_lock_irq(&gp->lock);
  2627. gem_put_cell(gp);
  2628. spin_unlock_irq(&gp->lock);
  2629. /* Register with kernel */
  2630. if (register_netdev(dev)) {
  2631. printk(KERN_ERR PFX "Cannot register net device, "
  2632. "aborting.\n");
  2633. err = -ENOMEM;
  2634. goto err_out_free_consistent;
  2635. }
  2636. printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
  2637. dev->name);
  2638. for (i = 0; i < 6; i++)
  2639. printk("%2.2x%c", dev->dev_addr[i],
  2640. i == 5 ? ' ' : ':');
  2641. printk("\n");
  2642. if (gp->phy_type == phy_mii_mdio0 ||
  2643. gp->phy_type == phy_mii_mdio1)
  2644. printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
  2645. gp->phy_mii.def ? gp->phy_mii.def->name : "no");
  2646. /* GEM can do it all... */
  2647. dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
  2648. if (pci_using_dac)
  2649. dev->features |= NETIF_F_HIGHDMA;
  2650. return 0;
  2651. err_out_free_consistent:
  2652. gem_remove_one(pdev);
  2653. err_out_iounmap:
  2654. gem_put_cell(gp);
  2655. iounmap(gp->regs);
  2656. err_out_free_res:
  2657. pci_release_regions(pdev);
  2658. err_out_free_netdev:
  2659. free_netdev(dev);
  2660. err_disable_device:
  2661. pci_disable_device(pdev);
  2662. return err;
  2663. }
  2664. static struct pci_driver gem_driver = {
  2665. .name = GEM_MODULE_NAME,
  2666. .id_table = gem_pci_tbl,
  2667. .probe = gem_init_one,
  2668. .remove = gem_remove_one,
  2669. #ifdef CONFIG_PM
  2670. .suspend = gem_suspend,
  2671. .resume = gem_resume,
  2672. #endif /* CONFIG_PM */
  2673. };
  2674. static int __init gem_init(void)
  2675. {
  2676. return pci_register_driver(&gem_driver);
  2677. }
  2678. static void __exit gem_cleanup(void)
  2679. {
  2680. pci_unregister_driver(&gem_driver);
  2681. }
  2682. module_init(gem_init);
  2683. module_exit(gem_cleanup);