sunbmac.h 18 KB

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  1. /* $Id: sunbmac.h,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  2. * sunbmac.h: Defines for the Sun "Big MAC" 100baseT ethernet cards.
  3. *
  4. * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
  5. */
  6. #ifndef _SUNBMAC_H
  7. #define _SUNBMAC_H
  8. /* QEC global registers. */
  9. #define GLOB_CTRL 0x00UL /* Control */
  10. #define GLOB_STAT 0x04UL /* Status */
  11. #define GLOB_PSIZE 0x08UL /* Packet Size */
  12. #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
  13. #define GLOB_RSIZE 0x10UL /* Receive partition size */
  14. #define GLOB_TSIZE 0x14UL /* Transmit partition size */
  15. #define GLOB_REG_SIZE 0x18UL
  16. #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */
  17. #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */
  18. #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
  19. #define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */
  20. #define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */
  21. #define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */
  22. #define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */
  23. #define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */
  24. #define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */
  25. #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */
  26. #define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */
  27. #define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */
  28. #define GLOB_PSIZE_2048 0x00 /* 2k packet size */
  29. #define GLOB_PSIZE_4096 0x01 /* 4k packet size */
  30. #define GLOB_PSIZE_6144 0x10 /* 6k packet size */
  31. #define GLOB_PSIZE_8192 0x11 /* 8k packet size */
  32. /* QEC BigMAC channel registers. */
  33. #define CREG_CTRL 0x00UL /* Control */
  34. #define CREG_STAT 0x04UL /* Status */
  35. #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
  36. #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
  37. #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
  38. #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
  39. #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
  40. #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
  41. #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
  42. #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
  43. #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
  44. #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
  45. #define CREG_CCNT 0x30UL /* Collision Counter */
  46. #define CREG_REG_SIZE 0x34UL
  47. #define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */
  48. #define CREG_STAT_BERROR 0x80000000 /* BigMAC error */
  49. #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
  50. #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
  51. #define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */
  52. #define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */
  53. #define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */
  54. #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
  55. #define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */
  56. #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */
  57. #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */
  58. #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */
  59. #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */
  60. #define CREG_STAT_ERRORS (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR| \
  61. CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP| \
  62. CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR| \
  63. CREG_STAT_RXSERR)
  64. #define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */
  65. #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
  66. #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
  67. #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
  68. #define CREG_QMASK_RXDROP 0x00000010 /* RX drop */
  69. #define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */
  70. #define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */
  71. #define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */
  72. #define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */
  73. /* BIGMAC core registers */
  74. #define BMAC_XIFCFG 0x000UL /* XIF config register */
  75. /* 0x004-->0x0fc, reserved */
  76. #define BMAC_STATUS 0x100UL /* Status register, clear on read */
  77. #define BMAC_IMASK 0x104UL /* Interrupt mask register */
  78. /* 0x108-->0x204, reserved */
  79. #define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */
  80. #define BMAC_TXCFG 0x20cUL /* Transmitter config register */
  81. #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
  82. #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
  83. #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
  84. #define BMAC_STIME 0x21cUL /* Transmit slot time */
  85. #define BMAC_PLEN 0x220UL /* Size of transmit preamble */
  86. #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
  87. #define BMAC_TXDELIM 0x228UL /* Transmit delimiter */
  88. #define BMAC_JSIZE 0x22cUL /* Toe jam... */
  89. #define BMAC_TXPMAX 0x230UL /* Transmit max pkt size */
  90. #define BMAC_TXPMIN 0x234UL /* Transmit min pkt size */
  91. #define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */
  92. #define BMAC_DTCTR 0x23cUL /* Transmit defer timer */
  93. #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
  94. #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
  95. #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
  96. #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
  97. #define BMAC_RSEED 0x250UL /* Transmit random number seed */
  98. #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */
  99. /* 0x258-->0x304, reserved */
  100. #define BMAC_RXSWRESET 0x308UL /* Receiver software reset */
  101. #define BMAC_RXCFG 0x30cUL /* Receiver config register */
  102. #define BMAC_RXPMAX 0x310UL /* Receive max pkt size */
  103. #define BMAC_RXPMIN 0x314UL /* Receive min pkt size */
  104. #define BMAC_MACADDR2 0x318UL /* Ether address register 2 */
  105. #define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */
  106. #define BMAC_MACADDR0 0x320UL /* Ether address register 0 */
  107. #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
  108. #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
  109. #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
  110. #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
  111. #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */
  112. #define BMAC_RXCVALID 0x338UL /* Receiver code violation */
  113. /* 0x33c, reserved */
  114. #define BMAC_HTABLE3 0x340UL /* Hash table 3 */
  115. #define BMAC_HTABLE2 0x344UL /* Hash table 2 */
  116. #define BMAC_HTABLE1 0x348UL /* Hash table 1 */
  117. #define BMAC_HTABLE0 0x34cUL /* Hash table 0 */
  118. #define BMAC_AFILTER2 0x350UL /* Address filter 2 */
  119. #define BMAC_AFILTER1 0x354UL /* Address filter 1 */
  120. #define BMAC_AFILTER0 0x358UL /* Address filter 0 */
  121. #define BMAC_AFMASK 0x35cUL /* Address filter mask */
  122. #define BMAC_REG_SIZE 0x360UL
  123. /* BigMac XIF config register. */
  124. #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
  125. #define BIGMAC_XCFG_RESV 0x00000002 /* Reserved, write always as 1 */
  126. #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
  127. #define BIGMAC_XCFG_SMODE 0x00000008 /* Enable serial mode */
  128. /* BigMAC status register. */
  129. #define BIGMAC_STAT_GOTFRAME 0x00000001 /* Received a frame */
  130. #define BIGMAC_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
  131. #define BIGMAC_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
  132. #define BIGMAC_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
  133. #define BIGMAC_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
  134. #define BIGMAC_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
  135. #define BIGMAC_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
  136. #define BIGMAC_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
  137. #define BIGMAC_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
  138. #define BIGMAC_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
  139. #define BIGMAC_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
  140. #define BIGMAC_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
  141. #define BIGMAC_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
  142. #define BIGMAC_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
  143. #define BIGMAC_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
  144. /* BigMAC interrupt mask register. */
  145. #define BIGMAC_IMASK_GOTFRAME 0x00000001 /* Received a frame */
  146. #define BIGMAC_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
  147. #define BIGMAC_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
  148. #define BIGMAC_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
  149. #define BIGMAC_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
  150. #define BIGMAC_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
  151. #define BIGMAC_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
  152. #define BIGMAC_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
  153. #define BIGMAC_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
  154. #define BIGMAC_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
  155. #define BIGMAC_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
  156. #define BIGMAC_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
  157. #define BIGMAC_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
  158. #define BIGMAC_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
  159. #define BIGMAC_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
  160. /* BigMac transmit config register. */
  161. #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
  162. #define BIGMAC_TXCFG_FIFO 0x00000010 /* Default tx fthresh... */
  163. #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
  164. #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
  165. #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
  166. #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
  167. #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
  168. /* BigMac receive config register. */
  169. #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
  170. #define BIGMAC_RXCFG_FIFO 0x0000000e /* Default rx fthresh... */
  171. #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
  172. #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
  173. #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
  174. #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
  175. #define BIGMAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
  176. #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
  177. #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
  178. #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
  179. /* The BigMAC PHY transceiver. Not nearly as sophisticated as the happy meal
  180. * one. But it does have the "bit banger", oh baby.
  181. */
  182. #define TCVR_TPAL 0x00UL
  183. #define TCVR_MPAL 0x04UL
  184. #define TCVR_REG_SIZE 0x08UL
  185. /* Frame commands. */
  186. #define FRAME_WRITE 0x50020000
  187. #define FRAME_READ 0x60020000
  188. /* Tranceiver registers. */
  189. #define TCVR_PAL_SERIAL 0x00000001 /* Enable serial mode */
  190. #define TCVR_PAL_EXTLBACK 0x00000002 /* Enable external loopback */
  191. #define TCVR_PAL_MSENSE 0x00000004 /* Media sense */
  192. #define TCVR_PAL_LTENABLE 0x00000008 /* Link test enable */
  193. #define TCVR_PAL_LTSTATUS 0x00000010 /* Link test status (P1 only) */
  194. /* Management PAL. */
  195. #define MGMT_PAL_DCLOCK 0x00000001 /* Data clock */
  196. #define MGMT_PAL_OENAB 0x00000002 /* Output enabler */
  197. #define MGMT_PAL_MDIO 0x00000004 /* MDIO Data/attached */
  198. #define MGMT_PAL_TIMEO 0x00000008 /* Transmit enable timeout error */
  199. #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO
  200. #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO
  201. /* Here are some PHY addresses. */
  202. #define BIGMAC_PHY_EXTERNAL 0 /* External transceiver */
  203. #define BIGMAC_PHY_INTERNAL 1 /* Internal transceiver */
  204. /* PHY registers */
  205. #define BIGMAC_BMCR 0x00 /* Basic mode control register */
  206. #define BIGMAC_BMSR 0x01 /* Basic mode status register */
  207. /* BMCR bits */
  208. #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
  209. #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
  210. #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
  211. #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
  212. #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
  213. #define BMCR_RESET 0x8000 /* Reset the DP83840 */
  214. /* BMSR bits */
  215. #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
  216. #define BMSR_JCD 0x0002 /* Jabber detected */
  217. #define BMSR_LSTATUS 0x0004 /* Link status */
  218. /* Ring descriptors and such, same as Quad Ethernet. */
  219. struct be_rxd {
  220. u32 rx_flags;
  221. u32 rx_addr;
  222. };
  223. #define RXD_OWN 0x80000000 /* Ownership. */
  224. #define RXD_UPDATE 0x10000000 /* Being Updated? */
  225. #define RXD_LENGTH 0x000007ff /* Packet Length. */
  226. struct be_txd {
  227. u32 tx_flags;
  228. u32 tx_addr;
  229. };
  230. #define TXD_OWN 0x80000000 /* Ownership. */
  231. #define TXD_SOP 0x40000000 /* Start Of Packet */
  232. #define TXD_EOP 0x20000000 /* End Of Packet */
  233. #define TXD_UPDATE 0x10000000 /* Being Updated? */
  234. #define TXD_LENGTH 0x000007ff /* Packet Length. */
  235. #define TX_RING_MAXSIZE 256
  236. #define RX_RING_MAXSIZE 256
  237. #define TX_RING_SIZE 256
  238. #define RX_RING_SIZE 256
  239. #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
  240. #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
  241. #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
  242. #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
  243. #define TX_BUFFS_AVAIL(bp) \
  244. (((bp)->tx_old <= (bp)->tx_new) ? \
  245. (bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new : \
  246. (bp)->tx_old - (bp)->tx_new - 1)
  247. #define RX_COPY_THRESHOLD 256
  248. #define RX_BUF_ALLOC_SIZE (ETH_FRAME_LEN + (64 * 3))
  249. struct bmac_init_block {
  250. struct be_rxd be_rxd[RX_RING_MAXSIZE];
  251. struct be_txd be_txd[TX_RING_MAXSIZE];
  252. };
  253. #define bib_offset(mem, elem) \
  254. ((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem]))))
  255. /* Now software state stuff. */
  256. enum bigmac_transceiver {
  257. external = 0,
  258. internal = 1,
  259. none = 2,
  260. };
  261. /* Timer state engine. */
  262. enum bigmac_timer_state {
  263. ltrywait = 1, /* Forcing try of all modes, from fastest to slowest. */
  264. asleep = 2, /* Timer inactive. */
  265. };
  266. struct bigmac {
  267. void __iomem *gregs; /* QEC Global Registers */
  268. void __iomem *creg; /* QEC BigMAC Channel Registers */
  269. void __iomem *bregs; /* BigMAC Registers */
  270. void __iomem *tregs; /* BigMAC Transceiver */
  271. struct bmac_init_block *bmac_block; /* RX and TX descriptors */
  272. __u32 bblock_dvma; /* RX and TX descriptors */
  273. spinlock_t lock;
  274. struct sk_buff *rx_skbs[RX_RING_SIZE];
  275. struct sk_buff *tx_skbs[TX_RING_SIZE];
  276. int rx_new, tx_new, rx_old, tx_old;
  277. int board_rev; /* BigMAC board revision. */
  278. enum bigmac_transceiver tcvr_type;
  279. unsigned int bigmac_bursts;
  280. unsigned int paddr;
  281. unsigned short sw_bmsr; /* SW copy of PHY BMSR */
  282. unsigned short sw_bmcr; /* SW copy of PHY BMCR */
  283. struct timer_list bigmac_timer;
  284. enum bigmac_timer_state timer_state;
  285. unsigned int timer_ticks;
  286. struct net_device_stats enet_stats;
  287. struct sbus_dev *qec_sdev;
  288. struct sbus_dev *bigmac_sdev;
  289. struct net_device *dev;
  290. };
  291. /* We use this to acquire receive skb's that we can DMA directly into. */
  292. #define ALIGNED_RX_SKB_ADDR(addr) \
  293. ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
  294. static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, gfp_t gfp_flags)
  295. {
  296. struct sk_buff *skb;
  297. skb = alloc_skb(length + 64, gfp_flags);
  298. if(skb) {
  299. int offset = ALIGNED_RX_SKB_ADDR(skb->data);
  300. if(offset)
  301. skb_reserve(skb, offset);
  302. }
  303. return skb;
  304. }
  305. #endif /* !(_SUNBMAC_H) */