sunbmac.c 34 KB

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  1. /* $Id: sunbmac.c,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  2. * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
  3. *
  4. * Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com)
  5. */
  6. #include <linux/module.h>
  7. #include <linux/kernel.h>
  8. #include <linux/types.h>
  9. #include <linux/fcntl.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/ioport.h>
  12. #include <linux/in.h>
  13. #include <linux/slab.h>
  14. #include <linux/string.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <linux/crc32.h>
  18. #include <linux/errno.h>
  19. #include <linux/ethtool.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/etherdevice.h>
  22. #include <linux/skbuff.h>
  23. #include <linux/bitops.h>
  24. #include <asm/auxio.h>
  25. #include <asm/byteorder.h>
  26. #include <asm/dma.h>
  27. #include <asm/idprom.h>
  28. #include <asm/io.h>
  29. #include <asm/openprom.h>
  30. #include <asm/oplib.h>
  31. #include <asm/pgtable.h>
  32. #include <asm/sbus.h>
  33. #include <asm/system.h>
  34. #include "sunbmac.h"
  35. #define DRV_NAME "sunbmac"
  36. #define DRV_VERSION "2.0"
  37. #define DRV_RELDATE "11/24/03"
  38. #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
  39. static char version[] =
  40. DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
  41. MODULE_VERSION(DRV_VERSION);
  42. MODULE_AUTHOR(DRV_AUTHOR);
  43. MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
  44. MODULE_LICENSE("GPL");
  45. #undef DEBUG_PROBE
  46. #undef DEBUG_TX
  47. #undef DEBUG_IRQ
  48. #ifdef DEBUG_PROBE
  49. #define DP(x) printk x
  50. #else
  51. #define DP(x)
  52. #endif
  53. #ifdef DEBUG_TX
  54. #define DTX(x) printk x
  55. #else
  56. #define DTX(x)
  57. #endif
  58. #ifdef DEBUG_IRQ
  59. #define DIRQ(x) printk x
  60. #else
  61. #define DIRQ(x)
  62. #endif
  63. #define DEFAULT_JAMSIZE 4 /* Toe jam */
  64. #define QEC_RESET_TRIES 200
  65. static int qec_global_reset(void __iomem *gregs)
  66. {
  67. int tries = QEC_RESET_TRIES;
  68. sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
  69. while (--tries) {
  70. if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
  71. udelay(20);
  72. continue;
  73. }
  74. break;
  75. }
  76. if (tries)
  77. return 0;
  78. printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
  79. return -1;
  80. }
  81. static void qec_init(struct bigmac *bp)
  82. {
  83. void __iomem *gregs = bp->gregs;
  84. struct sbus_dev *qec_sdev = bp->qec_sdev;
  85. u8 bsizes = bp->bigmac_bursts;
  86. u32 regval;
  87. /* 64byte bursts do not work at the moment, do
  88. * not even try to enable them. -DaveM
  89. */
  90. if (bsizes & DMA_BURST32)
  91. regval = GLOB_CTRL_B32;
  92. else
  93. regval = GLOB_CTRL_B16;
  94. sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
  95. sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
  96. /* All of memsize is given to bigmac. */
  97. sbus_writel(qec_sdev->reg_addrs[1].reg_size,
  98. gregs + GLOB_MSIZE);
  99. /* Half to the transmitter, half to the receiver. */
  100. sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
  101. gregs + GLOB_TSIZE);
  102. sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
  103. gregs + GLOB_RSIZE);
  104. }
  105. #define TX_RESET_TRIES 32
  106. #define RX_RESET_TRIES 32
  107. static void bigmac_tx_reset(void __iomem *bregs)
  108. {
  109. int tries = TX_RESET_TRIES;
  110. sbus_writel(0, bregs + BMAC_TXCFG);
  111. /* The fifo threshold bit is read-only and does
  112. * not clear. -DaveM
  113. */
  114. while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
  115. --tries != 0)
  116. udelay(20);
  117. if (!tries) {
  118. printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
  119. printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
  120. sbus_readl(bregs + BMAC_TXCFG));
  121. }
  122. }
  123. static void bigmac_rx_reset(void __iomem *bregs)
  124. {
  125. int tries = RX_RESET_TRIES;
  126. sbus_writel(0, bregs + BMAC_RXCFG);
  127. while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
  128. udelay(20);
  129. if (!tries) {
  130. printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
  131. printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
  132. sbus_readl(bregs + BMAC_RXCFG));
  133. }
  134. }
  135. /* Reset the transmitter and receiver. */
  136. static void bigmac_stop(struct bigmac *bp)
  137. {
  138. bigmac_tx_reset(bp->bregs);
  139. bigmac_rx_reset(bp->bregs);
  140. }
  141. static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs)
  142. {
  143. struct net_device_stats *stats = &bp->enet_stats;
  144. stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
  145. sbus_writel(0, bregs + BMAC_RCRCECTR);
  146. stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
  147. sbus_writel(0, bregs + BMAC_UNALECTR);
  148. stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
  149. sbus_writel(0, bregs + BMAC_GLECTR);
  150. stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
  151. stats->collisions +=
  152. (sbus_readl(bregs + BMAC_EXCTR) +
  153. sbus_readl(bregs + BMAC_LTCTR));
  154. sbus_writel(0, bregs + BMAC_EXCTR);
  155. sbus_writel(0, bregs + BMAC_LTCTR);
  156. }
  157. static void bigmac_clean_rings(struct bigmac *bp)
  158. {
  159. int i;
  160. for (i = 0; i < RX_RING_SIZE; i++) {
  161. if (bp->rx_skbs[i] != NULL) {
  162. dev_kfree_skb_any(bp->rx_skbs[i]);
  163. bp->rx_skbs[i] = NULL;
  164. }
  165. }
  166. for (i = 0; i < TX_RING_SIZE; i++) {
  167. if (bp->tx_skbs[i] != NULL) {
  168. dev_kfree_skb_any(bp->tx_skbs[i]);
  169. bp->tx_skbs[i] = NULL;
  170. }
  171. }
  172. }
  173. static void bigmac_init_rings(struct bigmac *bp, int from_irq)
  174. {
  175. struct bmac_init_block *bb = bp->bmac_block;
  176. struct net_device *dev = bp->dev;
  177. int i;
  178. gfp_t gfp_flags = GFP_KERNEL;
  179. if (from_irq || in_interrupt())
  180. gfp_flags = GFP_ATOMIC;
  181. bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
  182. /* Free any skippy bufs left around in the rings. */
  183. bigmac_clean_rings(bp);
  184. /* Now get new skbufs for the receive ring. */
  185. for (i = 0; i < RX_RING_SIZE; i++) {
  186. struct sk_buff *skb;
  187. skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
  188. if (!skb)
  189. continue;
  190. bp->rx_skbs[i] = skb;
  191. skb->dev = dev;
  192. /* Because we reserve afterwards. */
  193. skb_put(skb, ETH_FRAME_LEN);
  194. skb_reserve(skb, 34);
  195. bb->be_rxd[i].rx_addr =
  196. sbus_map_single(bp->bigmac_sdev, skb->data,
  197. RX_BUF_ALLOC_SIZE - 34,
  198. SBUS_DMA_FROMDEVICE);
  199. bb->be_rxd[i].rx_flags =
  200. (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
  201. }
  202. for (i = 0; i < TX_RING_SIZE; i++)
  203. bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
  204. }
  205. #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
  206. #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
  207. static void idle_transceiver(void __iomem *tregs)
  208. {
  209. int i = 20;
  210. while (i--) {
  211. sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
  212. sbus_readl(tregs + TCVR_MPAL);
  213. sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
  214. sbus_readl(tregs + TCVR_MPAL);
  215. }
  216. }
  217. static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit)
  218. {
  219. if (bp->tcvr_type == internal) {
  220. bit = (bit & 1) << 3;
  221. sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
  222. tregs + TCVR_MPAL);
  223. sbus_readl(tregs + TCVR_MPAL);
  224. sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
  225. tregs + TCVR_MPAL);
  226. sbus_readl(tregs + TCVR_MPAL);
  227. } else if (bp->tcvr_type == external) {
  228. bit = (bit & 1) << 2;
  229. sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
  230. tregs + TCVR_MPAL);
  231. sbus_readl(tregs + TCVR_MPAL);
  232. sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
  233. tregs + TCVR_MPAL);
  234. sbus_readl(tregs + TCVR_MPAL);
  235. } else {
  236. printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
  237. }
  238. }
  239. static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs)
  240. {
  241. int retval = 0;
  242. if (bp->tcvr_type == internal) {
  243. sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
  244. sbus_readl(tregs + TCVR_MPAL);
  245. sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
  246. tregs + TCVR_MPAL);
  247. sbus_readl(tregs + TCVR_MPAL);
  248. retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
  249. } else if (bp->tcvr_type == external) {
  250. sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
  251. sbus_readl(tregs + TCVR_MPAL);
  252. sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
  253. sbus_readl(tregs + TCVR_MPAL);
  254. retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
  255. } else {
  256. printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
  257. }
  258. return retval;
  259. }
  260. static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs)
  261. {
  262. int retval = 0;
  263. if (bp->tcvr_type == internal) {
  264. sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
  265. sbus_readl(tregs + TCVR_MPAL);
  266. retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
  267. sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
  268. sbus_readl(tregs + TCVR_MPAL);
  269. } else if (bp->tcvr_type == external) {
  270. sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
  271. sbus_readl(tregs + TCVR_MPAL);
  272. retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
  273. sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
  274. sbus_readl(tregs + TCVR_MPAL);
  275. } else {
  276. printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
  277. }
  278. return retval;
  279. }
  280. static void put_tcvr_byte(struct bigmac *bp,
  281. void __iomem *tregs,
  282. unsigned int byte)
  283. {
  284. int shift = 4;
  285. do {
  286. write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
  287. shift -= 1;
  288. } while (shift >= 0);
  289. }
  290. static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs,
  291. int reg, unsigned short val)
  292. {
  293. int shift;
  294. reg &= 0xff;
  295. val &= 0xffff;
  296. switch(bp->tcvr_type) {
  297. case internal:
  298. case external:
  299. break;
  300. default:
  301. printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
  302. return;
  303. };
  304. idle_transceiver(tregs);
  305. write_tcvr_bit(bp, tregs, 0);
  306. write_tcvr_bit(bp, tregs, 1);
  307. write_tcvr_bit(bp, tregs, 0);
  308. write_tcvr_bit(bp, tregs, 1);
  309. put_tcvr_byte(bp, tregs,
  310. ((bp->tcvr_type == internal) ?
  311. BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
  312. put_tcvr_byte(bp, tregs, reg);
  313. write_tcvr_bit(bp, tregs, 1);
  314. write_tcvr_bit(bp, tregs, 0);
  315. shift = 15;
  316. do {
  317. write_tcvr_bit(bp, tregs, (val >> shift) & 1);
  318. shift -= 1;
  319. } while (shift >= 0);
  320. }
  321. static unsigned short bigmac_tcvr_read(struct bigmac *bp,
  322. void __iomem *tregs,
  323. int reg)
  324. {
  325. unsigned short retval = 0;
  326. reg &= 0xff;
  327. switch(bp->tcvr_type) {
  328. case internal:
  329. case external:
  330. break;
  331. default:
  332. printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
  333. return 0xffff;
  334. };
  335. idle_transceiver(tregs);
  336. write_tcvr_bit(bp, tregs, 0);
  337. write_tcvr_bit(bp, tregs, 1);
  338. write_tcvr_bit(bp, tregs, 1);
  339. write_tcvr_bit(bp, tregs, 0);
  340. put_tcvr_byte(bp, tregs,
  341. ((bp->tcvr_type == internal) ?
  342. BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
  343. put_tcvr_byte(bp, tregs, reg);
  344. if (bp->tcvr_type == external) {
  345. int shift = 15;
  346. (void) read_tcvr_bit2(bp, tregs);
  347. (void) read_tcvr_bit2(bp, tregs);
  348. do {
  349. int tmp;
  350. tmp = read_tcvr_bit2(bp, tregs);
  351. retval |= ((tmp & 1) << shift);
  352. shift -= 1;
  353. } while (shift >= 0);
  354. (void) read_tcvr_bit2(bp, tregs);
  355. (void) read_tcvr_bit2(bp, tregs);
  356. (void) read_tcvr_bit2(bp, tregs);
  357. } else {
  358. int shift = 15;
  359. (void) read_tcvr_bit(bp, tregs);
  360. (void) read_tcvr_bit(bp, tregs);
  361. do {
  362. int tmp;
  363. tmp = read_tcvr_bit(bp, tregs);
  364. retval |= ((tmp & 1) << shift);
  365. shift -= 1;
  366. } while (shift >= 0);
  367. (void) read_tcvr_bit(bp, tregs);
  368. (void) read_tcvr_bit(bp, tregs);
  369. (void) read_tcvr_bit(bp, tregs);
  370. }
  371. return retval;
  372. }
  373. static void bigmac_tcvr_init(struct bigmac *bp)
  374. {
  375. void __iomem *tregs = bp->tregs;
  376. u32 mpal;
  377. idle_transceiver(tregs);
  378. sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
  379. tregs + TCVR_MPAL);
  380. sbus_readl(tregs + TCVR_MPAL);
  381. /* Only the bit for the present transceiver (internal or
  382. * external) will stick, set them both and see what stays.
  383. */
  384. sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
  385. sbus_readl(tregs + TCVR_MPAL);
  386. udelay(20);
  387. mpal = sbus_readl(tregs + TCVR_MPAL);
  388. if (mpal & MGMT_PAL_EXT_MDIO) {
  389. bp->tcvr_type = external;
  390. sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
  391. tregs + TCVR_TPAL);
  392. sbus_readl(tregs + TCVR_TPAL);
  393. } else if (mpal & MGMT_PAL_INT_MDIO) {
  394. bp->tcvr_type = internal;
  395. sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
  396. TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
  397. tregs + TCVR_TPAL);
  398. sbus_readl(tregs + TCVR_TPAL);
  399. } else {
  400. printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
  401. "external MDIO available!\n");
  402. printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
  403. sbus_readl(tregs + TCVR_MPAL),
  404. sbus_readl(tregs + TCVR_TPAL));
  405. }
  406. }
  407. static int bigmac_init_hw(struct bigmac *, int);
  408. static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
  409. {
  410. if (bp->sw_bmcr & BMCR_SPEED100) {
  411. int timeout;
  412. /* Reset the PHY. */
  413. bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
  414. bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
  415. bp->sw_bmcr = (BMCR_RESET);
  416. bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
  417. timeout = 64;
  418. while (--timeout) {
  419. bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
  420. if ((bp->sw_bmcr & BMCR_RESET) == 0)
  421. break;
  422. udelay(20);
  423. }
  424. if (timeout == 0)
  425. printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
  426. bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
  427. /* Now we try 10baseT. */
  428. bp->sw_bmcr &= ~(BMCR_SPEED100);
  429. bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
  430. return 0;
  431. }
  432. /* We've tried them all. */
  433. return -1;
  434. }
  435. static void bigmac_timer(unsigned long data)
  436. {
  437. struct bigmac *bp = (struct bigmac *) data;
  438. void __iomem *tregs = bp->tregs;
  439. int restart_timer = 0;
  440. bp->timer_ticks++;
  441. if (bp->timer_state == ltrywait) {
  442. bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
  443. bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
  444. if (bp->sw_bmsr & BMSR_LSTATUS) {
  445. printk(KERN_INFO "%s: Link is now up at %s.\n",
  446. bp->dev->name,
  447. (bp->sw_bmcr & BMCR_SPEED100) ?
  448. "100baseT" : "10baseT");
  449. bp->timer_state = asleep;
  450. restart_timer = 0;
  451. } else {
  452. if (bp->timer_ticks >= 4) {
  453. int ret;
  454. ret = try_next_permutation(bp, tregs);
  455. if (ret == -1) {
  456. printk(KERN_ERR "%s: Link down, cable problem?\n",
  457. bp->dev->name);
  458. ret = bigmac_init_hw(bp, 0);
  459. if (ret) {
  460. printk(KERN_ERR "%s: Error, cannot re-init the "
  461. "BigMAC.\n", bp->dev->name);
  462. }
  463. return;
  464. }
  465. bp->timer_ticks = 0;
  466. restart_timer = 1;
  467. } else {
  468. restart_timer = 1;
  469. }
  470. }
  471. } else {
  472. /* Can't happens.... */
  473. printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
  474. bp->dev->name);
  475. restart_timer = 0;
  476. bp->timer_ticks = 0;
  477. bp->timer_state = asleep; /* foo on you */
  478. }
  479. if (restart_timer != 0) {
  480. bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
  481. add_timer(&bp->bigmac_timer);
  482. }
  483. }
  484. /* Well, really we just force the chip into 100baseT then
  485. * 10baseT, each time checking for a link status.
  486. */
  487. static void bigmac_begin_auto_negotiation(struct bigmac *bp)
  488. {
  489. void __iomem *tregs = bp->tregs;
  490. int timeout;
  491. /* Grab new software copies of PHY registers. */
  492. bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
  493. bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
  494. /* Reset the PHY. */
  495. bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
  496. bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
  497. bp->sw_bmcr = (BMCR_RESET);
  498. bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
  499. timeout = 64;
  500. while (--timeout) {
  501. bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
  502. if ((bp->sw_bmcr & BMCR_RESET) == 0)
  503. break;
  504. udelay(20);
  505. }
  506. if (timeout == 0)
  507. printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
  508. bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
  509. /* First we try 100baseT. */
  510. bp->sw_bmcr |= BMCR_SPEED100;
  511. bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
  512. bp->timer_state = ltrywait;
  513. bp->timer_ticks = 0;
  514. bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
  515. bp->bigmac_timer.data = (unsigned long) bp;
  516. bp->bigmac_timer.function = &bigmac_timer;
  517. add_timer(&bp->bigmac_timer);
  518. }
  519. static int bigmac_init_hw(struct bigmac *bp, int from_irq)
  520. {
  521. void __iomem *gregs = bp->gregs;
  522. void __iomem *cregs = bp->creg;
  523. void __iomem *bregs = bp->bregs;
  524. unsigned char *e = &bp->dev->dev_addr[0];
  525. /* Latch current counters into statistics. */
  526. bigmac_get_counters(bp, bregs);
  527. /* Reset QEC. */
  528. qec_global_reset(gregs);
  529. /* Init QEC. */
  530. qec_init(bp);
  531. /* Alloc and reset the tx/rx descriptor chains. */
  532. bigmac_init_rings(bp, from_irq);
  533. /* Initialize the PHY. */
  534. bigmac_tcvr_init(bp);
  535. /* Stop transmitter and receiver. */
  536. bigmac_stop(bp);
  537. /* Set hardware ethernet address. */
  538. sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
  539. sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
  540. sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
  541. /* Clear the hash table until mc upload occurs. */
  542. sbus_writel(0, bregs + BMAC_HTABLE3);
  543. sbus_writel(0, bregs + BMAC_HTABLE2);
  544. sbus_writel(0, bregs + BMAC_HTABLE1);
  545. sbus_writel(0, bregs + BMAC_HTABLE0);
  546. /* Enable Big Mac hash table filter. */
  547. sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
  548. bregs + BMAC_RXCFG);
  549. udelay(20);
  550. /* Ok, configure the Big Mac transmitter. */
  551. sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
  552. /* The HME docs recommend to use the 10LSB of our MAC here. */
  553. sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
  554. bregs + BMAC_RSEED);
  555. /* Enable the output drivers no matter what. */
  556. sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
  557. bregs + BMAC_XIFCFG);
  558. /* Tell the QEC where the ring descriptors are. */
  559. sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
  560. cregs + CREG_RXDS);
  561. sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
  562. cregs + CREG_TXDS);
  563. /* Setup the FIFO pointers into QEC local memory. */
  564. sbus_writel(0, cregs + CREG_RXRBUFPTR);
  565. sbus_writel(0, cregs + CREG_RXWBUFPTR);
  566. sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
  567. cregs + CREG_TXRBUFPTR);
  568. sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
  569. cregs + CREG_TXWBUFPTR);
  570. /* Tell bigmac what interrupts we don't want to hear about. */
  571. sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
  572. bregs + BMAC_IMASK);
  573. /* Enable the various other irq's. */
  574. sbus_writel(0, cregs + CREG_RIMASK);
  575. sbus_writel(0, cregs + CREG_TIMASK);
  576. sbus_writel(0, cregs + CREG_QMASK);
  577. sbus_writel(0, cregs + CREG_BMASK);
  578. /* Set jam size to a reasonable default. */
  579. sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
  580. /* Clear collision counter. */
  581. sbus_writel(0, cregs + CREG_CCNT);
  582. /* Enable transmitter and receiver. */
  583. sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
  584. bregs + BMAC_TXCFG);
  585. sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
  586. bregs + BMAC_RXCFG);
  587. /* Ok, start detecting link speed/duplex. */
  588. bigmac_begin_auto_negotiation(bp);
  589. /* Success. */
  590. return 0;
  591. }
  592. /* Error interrupts get sent here. */
  593. static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
  594. {
  595. printk(KERN_ERR "bigmac_is_medium_rare: ");
  596. if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
  597. if (qec_status & GLOB_STAT_ER)
  598. printk("QEC_ERROR, ");
  599. if (qec_status & GLOB_STAT_BM)
  600. printk("QEC_BMAC_ERROR, ");
  601. }
  602. if (bmac_status & CREG_STAT_ERRORS) {
  603. if (bmac_status & CREG_STAT_BERROR)
  604. printk("BMAC_ERROR, ");
  605. if (bmac_status & CREG_STAT_TXDERROR)
  606. printk("TXD_ERROR, ");
  607. if (bmac_status & CREG_STAT_TXLERR)
  608. printk("TX_LATE_ERROR, ");
  609. if (bmac_status & CREG_STAT_TXPERR)
  610. printk("TX_PARITY_ERROR, ");
  611. if (bmac_status & CREG_STAT_TXSERR)
  612. printk("TX_SBUS_ERROR, ");
  613. if (bmac_status & CREG_STAT_RXDROP)
  614. printk("RX_DROP_ERROR, ");
  615. if (bmac_status & CREG_STAT_RXSMALL)
  616. printk("RX_SMALL_ERROR, ");
  617. if (bmac_status & CREG_STAT_RXLERR)
  618. printk("RX_LATE_ERROR, ");
  619. if (bmac_status & CREG_STAT_RXPERR)
  620. printk("RX_PARITY_ERROR, ");
  621. if (bmac_status & CREG_STAT_RXSERR)
  622. printk("RX_SBUS_ERROR, ");
  623. }
  624. printk(" RESET\n");
  625. bigmac_init_hw(bp, 1);
  626. }
  627. /* BigMAC transmit complete service routines. */
  628. static void bigmac_tx(struct bigmac *bp)
  629. {
  630. struct be_txd *txbase = &bp->bmac_block->be_txd[0];
  631. struct net_device *dev = bp->dev;
  632. int elem;
  633. spin_lock(&bp->lock);
  634. elem = bp->tx_old;
  635. DTX(("bigmac_tx: tx_old[%d] ", elem));
  636. while (elem != bp->tx_new) {
  637. struct sk_buff *skb;
  638. struct be_txd *this = &txbase[elem];
  639. DTX(("this(%p) [flags(%08x)addr(%08x)]",
  640. this, this->tx_flags, this->tx_addr));
  641. if (this->tx_flags & TXD_OWN)
  642. break;
  643. skb = bp->tx_skbs[elem];
  644. bp->enet_stats.tx_packets++;
  645. bp->enet_stats.tx_bytes += skb->len;
  646. sbus_unmap_single(bp->bigmac_sdev,
  647. this->tx_addr, skb->len,
  648. SBUS_DMA_TODEVICE);
  649. DTX(("skb(%p) ", skb));
  650. bp->tx_skbs[elem] = NULL;
  651. dev_kfree_skb_irq(skb);
  652. elem = NEXT_TX(elem);
  653. }
  654. DTX((" DONE, tx_old=%d\n", elem));
  655. bp->tx_old = elem;
  656. if (netif_queue_stopped(dev) &&
  657. TX_BUFFS_AVAIL(bp) > 0)
  658. netif_wake_queue(bp->dev);
  659. spin_unlock(&bp->lock);
  660. }
  661. /* BigMAC receive complete service routines. */
  662. static void bigmac_rx(struct bigmac *bp)
  663. {
  664. struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
  665. struct be_rxd *this;
  666. int elem = bp->rx_new, drops = 0;
  667. u32 flags;
  668. this = &rxbase[elem];
  669. while (!((flags = this->rx_flags) & RXD_OWN)) {
  670. struct sk_buff *skb;
  671. int len = (flags & RXD_LENGTH); /* FCS not included */
  672. /* Check for errors. */
  673. if (len < ETH_ZLEN) {
  674. bp->enet_stats.rx_errors++;
  675. bp->enet_stats.rx_length_errors++;
  676. drop_it:
  677. /* Return it to the BigMAC. */
  678. bp->enet_stats.rx_dropped++;
  679. this->rx_flags =
  680. (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
  681. goto next;
  682. }
  683. skb = bp->rx_skbs[elem];
  684. if (len > RX_COPY_THRESHOLD) {
  685. struct sk_buff *new_skb;
  686. /* Now refill the entry, if we can. */
  687. new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
  688. if (new_skb == NULL) {
  689. drops++;
  690. goto drop_it;
  691. }
  692. sbus_unmap_single(bp->bigmac_sdev,
  693. this->rx_addr,
  694. RX_BUF_ALLOC_SIZE - 34,
  695. SBUS_DMA_FROMDEVICE);
  696. bp->rx_skbs[elem] = new_skb;
  697. new_skb->dev = bp->dev;
  698. skb_put(new_skb, ETH_FRAME_LEN);
  699. skb_reserve(new_skb, 34);
  700. this->rx_addr = sbus_map_single(bp->bigmac_sdev,
  701. new_skb->data,
  702. RX_BUF_ALLOC_SIZE - 34,
  703. SBUS_DMA_FROMDEVICE);
  704. this->rx_flags =
  705. (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
  706. /* Trim the original skb for the netif. */
  707. skb_trim(skb, len);
  708. } else {
  709. struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
  710. if (copy_skb == NULL) {
  711. drops++;
  712. goto drop_it;
  713. }
  714. copy_skb->dev = bp->dev;
  715. skb_reserve(copy_skb, 2);
  716. skb_put(copy_skb, len);
  717. sbus_dma_sync_single_for_cpu(bp->bigmac_sdev,
  718. this->rx_addr, len,
  719. SBUS_DMA_FROMDEVICE);
  720. eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
  721. sbus_dma_sync_single_for_device(bp->bigmac_sdev,
  722. this->rx_addr, len,
  723. SBUS_DMA_FROMDEVICE);
  724. /* Reuse original ring buffer. */
  725. this->rx_flags =
  726. (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
  727. skb = copy_skb;
  728. }
  729. /* No checksums done by the BigMAC ;-( */
  730. skb->protocol = eth_type_trans(skb, bp->dev);
  731. netif_rx(skb);
  732. bp->dev->last_rx = jiffies;
  733. bp->enet_stats.rx_packets++;
  734. bp->enet_stats.rx_bytes += len;
  735. next:
  736. elem = NEXT_RX(elem);
  737. this = &rxbase[elem];
  738. }
  739. bp->rx_new = elem;
  740. if (drops)
  741. printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
  742. }
  743. static irqreturn_t bigmac_interrupt(int irq, void *dev_id)
  744. {
  745. struct bigmac *bp = (struct bigmac *) dev_id;
  746. u32 qec_status, bmac_status;
  747. DIRQ(("bigmac_interrupt: "));
  748. /* Latch status registers now. */
  749. bmac_status = sbus_readl(bp->creg + CREG_STAT);
  750. qec_status = sbus_readl(bp->gregs + GLOB_STAT);
  751. DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
  752. if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
  753. (bmac_status & CREG_STAT_ERRORS))
  754. bigmac_is_medium_rare(bp, qec_status, bmac_status);
  755. if (bmac_status & CREG_STAT_TXIRQ)
  756. bigmac_tx(bp);
  757. if (bmac_status & CREG_STAT_RXIRQ)
  758. bigmac_rx(bp);
  759. return IRQ_HANDLED;
  760. }
  761. static int bigmac_open(struct net_device *dev)
  762. {
  763. struct bigmac *bp = (struct bigmac *) dev->priv;
  764. int ret;
  765. ret = request_irq(dev->irq, &bigmac_interrupt, IRQF_SHARED, dev->name, bp);
  766. if (ret) {
  767. printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
  768. return ret;
  769. }
  770. init_timer(&bp->bigmac_timer);
  771. ret = bigmac_init_hw(bp, 0);
  772. if (ret)
  773. free_irq(dev->irq, bp);
  774. return ret;
  775. }
  776. static int bigmac_close(struct net_device *dev)
  777. {
  778. struct bigmac *bp = (struct bigmac *) dev->priv;
  779. del_timer(&bp->bigmac_timer);
  780. bp->timer_state = asleep;
  781. bp->timer_ticks = 0;
  782. bigmac_stop(bp);
  783. bigmac_clean_rings(bp);
  784. free_irq(dev->irq, bp);
  785. return 0;
  786. }
  787. static void bigmac_tx_timeout(struct net_device *dev)
  788. {
  789. struct bigmac *bp = (struct bigmac *) dev->priv;
  790. bigmac_init_hw(bp, 0);
  791. netif_wake_queue(dev);
  792. }
  793. /* Put a packet on the wire. */
  794. static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
  795. {
  796. struct bigmac *bp = (struct bigmac *) dev->priv;
  797. int len, entry;
  798. u32 mapping;
  799. len = skb->len;
  800. mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
  801. /* Avoid a race... */
  802. spin_lock_irq(&bp->lock);
  803. entry = bp->tx_new;
  804. DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
  805. bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
  806. bp->tx_skbs[entry] = skb;
  807. bp->bmac_block->be_txd[entry].tx_addr = mapping;
  808. bp->bmac_block->be_txd[entry].tx_flags =
  809. (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
  810. bp->tx_new = NEXT_TX(entry);
  811. if (TX_BUFFS_AVAIL(bp) <= 0)
  812. netif_stop_queue(dev);
  813. spin_unlock_irq(&bp->lock);
  814. /* Get it going. */
  815. sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
  816. dev->trans_start = jiffies;
  817. return 0;
  818. }
  819. static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
  820. {
  821. struct bigmac *bp = (struct bigmac *) dev->priv;
  822. bigmac_get_counters(bp, bp->bregs);
  823. return &bp->enet_stats;
  824. }
  825. static void bigmac_set_multicast(struct net_device *dev)
  826. {
  827. struct bigmac *bp = (struct bigmac *) dev->priv;
  828. void __iomem *bregs = bp->bregs;
  829. struct dev_mc_list *dmi = dev->mc_list;
  830. char *addrs;
  831. int i;
  832. u32 tmp, crc;
  833. /* Disable the receiver. The bit self-clears when
  834. * the operation is complete.
  835. */
  836. tmp = sbus_readl(bregs + BMAC_RXCFG);
  837. tmp &= ~(BIGMAC_RXCFG_ENABLE);
  838. sbus_writel(tmp, bregs + BMAC_RXCFG);
  839. while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
  840. udelay(20);
  841. if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
  842. sbus_writel(0xffff, bregs + BMAC_HTABLE0);
  843. sbus_writel(0xffff, bregs + BMAC_HTABLE1);
  844. sbus_writel(0xffff, bregs + BMAC_HTABLE2);
  845. sbus_writel(0xffff, bregs + BMAC_HTABLE3);
  846. } else if (dev->flags & IFF_PROMISC) {
  847. tmp = sbus_readl(bregs + BMAC_RXCFG);
  848. tmp |= BIGMAC_RXCFG_PMISC;
  849. sbus_writel(tmp, bregs + BMAC_RXCFG);
  850. } else {
  851. u16 hash_table[4];
  852. for (i = 0; i < 4; i++)
  853. hash_table[i] = 0;
  854. for (i = 0; i < dev->mc_count; i++) {
  855. addrs = dmi->dmi_addr;
  856. dmi = dmi->next;
  857. if (!(*addrs & 1))
  858. continue;
  859. crc = ether_crc_le(6, addrs);
  860. crc >>= 26;
  861. hash_table[crc >> 4] |= 1 << (crc & 0xf);
  862. }
  863. sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
  864. sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
  865. sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
  866. sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
  867. }
  868. /* Re-enable the receiver. */
  869. tmp = sbus_readl(bregs + BMAC_RXCFG);
  870. tmp |= BIGMAC_RXCFG_ENABLE;
  871. sbus_writel(tmp, bregs + BMAC_RXCFG);
  872. }
  873. /* Ethtool support... */
  874. static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  875. {
  876. struct bigmac *bp = dev->priv;
  877. strcpy(info->driver, "sunbmac");
  878. strcpy(info->version, "2.0");
  879. sprintf(info->bus_info, "SBUS:%d",
  880. bp->qec_sdev->slot);
  881. }
  882. static u32 bigmac_get_link(struct net_device *dev)
  883. {
  884. struct bigmac *bp = dev->priv;
  885. spin_lock_irq(&bp->lock);
  886. bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR);
  887. spin_unlock_irq(&bp->lock);
  888. return (bp->sw_bmsr & BMSR_LSTATUS);
  889. }
  890. static const struct ethtool_ops bigmac_ethtool_ops = {
  891. .get_drvinfo = bigmac_get_drvinfo,
  892. .get_link = bigmac_get_link,
  893. };
  894. static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
  895. {
  896. struct net_device *dev;
  897. static int version_printed;
  898. struct bigmac *bp;
  899. u8 bsizes, bsizes_more;
  900. int i;
  901. /* Get a new device struct for this interface. */
  902. dev = alloc_etherdev(sizeof(struct bigmac));
  903. if (!dev)
  904. return -ENOMEM;
  905. SET_MODULE_OWNER(dev);
  906. if (version_printed++ == 0)
  907. printk(KERN_INFO "%s", version);
  908. dev->base_addr = (long) qec_sdev;
  909. for (i = 0; i < 6; i++)
  910. dev->dev_addr[i] = idprom->id_ethaddr[i];
  911. /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
  912. bp = dev->priv;
  913. bp->qec_sdev = qec_sdev;
  914. bp->bigmac_sdev = qec_sdev->child;
  915. SET_NETDEV_DEV(dev, &bp->bigmac_sdev->ofdev.dev);
  916. spin_lock_init(&bp->lock);
  917. /* Verify the registers we expect, are actually there. */
  918. if ((bp->bigmac_sdev->num_registers != 3) ||
  919. (bp->qec_sdev->num_registers != 2)) {
  920. printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
  921. bp->qec_sdev->num_registers,
  922. bp->bigmac_sdev->num_registers);
  923. printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
  924. goto fail_and_cleanup;
  925. }
  926. /* Map in QEC global control registers. */
  927. bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
  928. GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
  929. if (!bp->gregs) {
  930. printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
  931. goto fail_and_cleanup;
  932. }
  933. /* Make sure QEC is in BigMAC mode. */
  934. if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
  935. printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
  936. goto fail_and_cleanup;
  937. }
  938. /* Reset the QEC. */
  939. if (qec_global_reset(bp->gregs))
  940. goto fail_and_cleanup;
  941. /* Get supported SBUS burst sizes. */
  942. bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
  943. "burst-sizes",
  944. 0xff);
  945. bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
  946. "burst-sizes",
  947. 0xff);
  948. bsizes &= 0xff;
  949. if (bsizes_more != 0xff)
  950. bsizes &= bsizes_more;
  951. if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
  952. (bsizes & DMA_BURST32) == 0)
  953. bsizes = (DMA_BURST32 - 1);
  954. bp->bigmac_bursts = bsizes;
  955. /* Perform QEC initialization. */
  956. qec_init(bp);
  957. /* Map in the BigMAC channel registers. */
  958. bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
  959. CREG_REG_SIZE, "BigMAC QEC Channel Regs");
  960. if (!bp->creg) {
  961. printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
  962. goto fail_and_cleanup;
  963. }
  964. /* Map in the BigMAC control registers. */
  965. bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
  966. BMAC_REG_SIZE, "BigMAC Primary Regs");
  967. if (!bp->bregs) {
  968. printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
  969. goto fail_and_cleanup;
  970. }
  971. /* Map in the BigMAC transceiver registers, this is how you poke at
  972. * the BigMAC's PHY.
  973. */
  974. bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
  975. TCVR_REG_SIZE, "BigMAC Transceiver Regs");
  976. if (!bp->tregs) {
  977. printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
  978. goto fail_and_cleanup;
  979. }
  980. /* Stop the BigMAC. */
  981. bigmac_stop(bp);
  982. /* Allocate transmit/receive descriptor DVMA block. */
  983. bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
  984. PAGE_SIZE,
  985. &bp->bblock_dvma);
  986. if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
  987. printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
  988. goto fail_and_cleanup;
  989. }
  990. /* Get the board revision of this BigMAC. */
  991. bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
  992. "board-version", 1);
  993. /* Init auto-negotiation timer state. */
  994. init_timer(&bp->bigmac_timer);
  995. bp->timer_state = asleep;
  996. bp->timer_ticks = 0;
  997. /* Backlink to generic net device struct. */
  998. bp->dev = dev;
  999. /* Set links to our BigMAC open and close routines. */
  1000. dev->open = &bigmac_open;
  1001. dev->stop = &bigmac_close;
  1002. dev->hard_start_xmit = &bigmac_start_xmit;
  1003. dev->ethtool_ops = &bigmac_ethtool_ops;
  1004. /* Set links to BigMAC statistic and multi-cast loading code. */
  1005. dev->get_stats = &bigmac_get_stats;
  1006. dev->set_multicast_list = &bigmac_set_multicast;
  1007. dev->tx_timeout = &bigmac_tx_timeout;
  1008. dev->watchdog_timeo = 5*HZ;
  1009. /* Finish net device registration. */
  1010. dev->irq = bp->bigmac_sdev->irqs[0];
  1011. dev->dma = 0;
  1012. if (register_netdev(dev)) {
  1013. printk(KERN_ERR "BIGMAC: Cannot register device.\n");
  1014. goto fail_and_cleanup;
  1015. }
  1016. dev_set_drvdata(&bp->bigmac_sdev->ofdev.dev, bp);
  1017. printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
  1018. for (i = 0; i < 6; i++)
  1019. printk("%2.2x%c", dev->dev_addr[i],
  1020. i == 5 ? ' ' : ':');
  1021. printk("\n");
  1022. return 0;
  1023. fail_and_cleanup:
  1024. /* Something went wrong, undo whatever we did so far. */
  1025. /* Free register mappings if any. */
  1026. if (bp->gregs)
  1027. sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
  1028. if (bp->creg)
  1029. sbus_iounmap(bp->creg, CREG_REG_SIZE);
  1030. if (bp->bregs)
  1031. sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
  1032. if (bp->tregs)
  1033. sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
  1034. if (bp->bmac_block)
  1035. sbus_free_consistent(bp->bigmac_sdev,
  1036. PAGE_SIZE,
  1037. bp->bmac_block,
  1038. bp->bblock_dvma);
  1039. /* This also frees the co-located 'dev->priv' */
  1040. free_netdev(dev);
  1041. return -ENODEV;
  1042. }
  1043. /* QEC can be the parent of either QuadEthernet or
  1044. * a BigMAC. We want the latter.
  1045. */
  1046. static int __devinit bigmac_sbus_probe(struct of_device *dev, const struct of_device_id *match)
  1047. {
  1048. struct sbus_dev *sdev = to_sbus_device(&dev->dev);
  1049. struct device_node *dp = dev->node;
  1050. if (!strcmp(dp->name, "be"))
  1051. sdev = sdev->parent;
  1052. return bigmac_ether_init(sdev);
  1053. }
  1054. static int __devexit bigmac_sbus_remove(struct of_device *dev)
  1055. {
  1056. struct bigmac *bp = dev_get_drvdata(&dev->dev);
  1057. struct net_device *net_dev = bp->dev;
  1058. unregister_netdevice(net_dev);
  1059. sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
  1060. sbus_iounmap(bp->creg, CREG_REG_SIZE);
  1061. sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
  1062. sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
  1063. sbus_free_consistent(bp->bigmac_sdev,
  1064. PAGE_SIZE,
  1065. bp->bmac_block,
  1066. bp->bblock_dvma);
  1067. free_netdev(net_dev);
  1068. dev_set_drvdata(&dev->dev, NULL);
  1069. return 0;
  1070. }
  1071. static struct of_device_id bigmac_sbus_match[] = {
  1072. {
  1073. .name = "qec",
  1074. },
  1075. {
  1076. .name = "be",
  1077. },
  1078. {},
  1079. };
  1080. MODULE_DEVICE_TABLE(of, bigmac_sbus_match);
  1081. static struct of_platform_driver bigmac_sbus_driver = {
  1082. .name = "sunbmac",
  1083. .match_table = bigmac_sbus_match,
  1084. .probe = bigmac_sbus_probe,
  1085. .remove = __devexit_p(bigmac_sbus_remove),
  1086. };
  1087. static int __init bigmac_init(void)
  1088. {
  1089. return of_register_driver(&bigmac_sbus_driver, &sbus_bus_type);
  1090. }
  1091. static void __exit bigmac_exit(void)
  1092. {
  1093. of_unregister_driver(&bigmac_sbus_driver);
  1094. }
  1095. module_init(bigmac_init);
  1096. module_exit(bigmac_exit);