smc91x.h 35 KB

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  1. /*------------------------------------------------------------------------
  2. . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
  3. .
  4. . Copyright (C) 1996 by Erik Stahlman
  5. . Copyright (C) 2001 Standard Microsystems Corporation
  6. . Developed by Simple Network Magic Corporation
  7. . Copyright (C) 2003 Monta Vista Software, Inc.
  8. . Unified SMC91x driver by Nicolas Pitre
  9. .
  10. . This program is free software; you can redistribute it and/or modify
  11. . it under the terms of the GNU General Public License as published by
  12. . the Free Software Foundation; either version 2 of the License, or
  13. . (at your option) any later version.
  14. .
  15. . This program is distributed in the hope that it will be useful,
  16. . but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. . GNU General Public License for more details.
  19. .
  20. . You should have received a copy of the GNU General Public License
  21. . along with this program; if not, write to the Free Software
  22. . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. .
  24. . Information contained in this file was obtained from the LAN91C111
  25. . manual from SMC. To get a copy, if you really want one, you can find
  26. . information under www.smsc.com.
  27. .
  28. . Authors
  29. . Erik Stahlman <erik@vt.edu>
  30. . Daris A Nevil <dnevil@snmc.com>
  31. . Nicolas Pitre <nico@cam.org>
  32. .
  33. ---------------------------------------------------------------------------*/
  34. #ifndef _SMC91X_H_
  35. #define _SMC91X_H_
  36. /*
  37. * Define your architecture specific bus configuration parameters here.
  38. */
  39. #if defined(CONFIG_ARCH_LUBBOCK)
  40. /* We can only do 16-bit reads and writes in the static memory space. */
  41. #define SMC_CAN_USE_8BIT 0
  42. #define SMC_CAN_USE_16BIT 1
  43. #define SMC_CAN_USE_32BIT 0
  44. #define SMC_NOWAIT 1
  45. /* The first two address lines aren't connected... */
  46. #define SMC_IO_SHIFT 2
  47. #define SMC_inw(a, r) readw((a) + (r))
  48. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  49. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  50. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  51. #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
  52. /* We can only do 16-bit reads and writes in the static memory space. */
  53. #define SMC_CAN_USE_8BIT 0
  54. #define SMC_CAN_USE_16BIT 1
  55. #define SMC_CAN_USE_32BIT 0
  56. #define SMC_NOWAIT 1
  57. #define SMC_IO_SHIFT 0
  58. #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
  59. #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
  60. #define SMC_insw(a, r, p, l) \
  61. do { \
  62. unsigned long __port = (a) + (r); \
  63. u16 *__p = (u16 *)(p); \
  64. int __l = (l); \
  65. insw(__port, __p, __l); \
  66. while (__l > 0) { \
  67. *__p = swab16(*__p); \
  68. __p++; \
  69. __l--; \
  70. } \
  71. } while (0)
  72. #define SMC_outsw(a, r, p, l) \
  73. do { \
  74. unsigned long __port = (a) + (r); \
  75. u16 *__p = (u16 *)(p); \
  76. int __l = (l); \
  77. while (__l > 0) { \
  78. /* Believe it or not, the swab isn't needed. */ \
  79. outw( /* swab16 */ (*__p++), __port); \
  80. __l--; \
  81. } \
  82. } while (0)
  83. #define SMC_IRQ_FLAGS (0)
  84. #elif defined(CONFIG_SA1100_PLEB)
  85. /* We can only do 16-bit reads and writes in the static memory space. */
  86. #define SMC_CAN_USE_8BIT 1
  87. #define SMC_CAN_USE_16BIT 1
  88. #define SMC_CAN_USE_32BIT 0
  89. #define SMC_IO_SHIFT 0
  90. #define SMC_NOWAIT 1
  91. #define SMC_inb(a, r) readb((a) + (r))
  92. #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
  93. #define SMC_inw(a, r) readw((a) + (r))
  94. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  95. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  96. #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
  97. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  98. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  99. #define SMC_IRQ_FLAGS (0)
  100. #elif defined(CONFIG_SA1100_ASSABET)
  101. #include <asm/arch/neponset.h>
  102. /* We can only do 8-bit reads and writes in the static memory space. */
  103. #define SMC_CAN_USE_8BIT 1
  104. #define SMC_CAN_USE_16BIT 0
  105. #define SMC_CAN_USE_32BIT 0
  106. #define SMC_NOWAIT 1
  107. /* The first two address lines aren't connected... */
  108. #define SMC_IO_SHIFT 2
  109. #define SMC_inb(a, r) readb((a) + (r))
  110. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  111. #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
  112. #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
  113. #elif defined(CONFIG_MACH_LOGICPD_PXA270)
  114. #define SMC_CAN_USE_8BIT 0
  115. #define SMC_CAN_USE_16BIT 1
  116. #define SMC_CAN_USE_32BIT 0
  117. #define SMC_IO_SHIFT 0
  118. #define SMC_NOWAIT 1
  119. #define SMC_inw(a, r) readw((a) + (r))
  120. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  121. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  122. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  123. #elif defined(CONFIG_ARCH_INNOKOM) || \
  124. defined(CONFIG_MACH_MAINSTONE) || \
  125. defined(CONFIG_ARCH_PXA_IDP) || \
  126. defined(CONFIG_ARCH_RAMSES)
  127. #define SMC_CAN_USE_8BIT 1
  128. #define SMC_CAN_USE_16BIT 1
  129. #define SMC_CAN_USE_32BIT 1
  130. #define SMC_IO_SHIFT 0
  131. #define SMC_NOWAIT 1
  132. #define SMC_USE_PXA_DMA 1
  133. #define SMC_inb(a, r) readb((a) + (r))
  134. #define SMC_inw(a, r) readw((a) + (r))
  135. #define SMC_inl(a, r) readl((a) + (r))
  136. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  137. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  138. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  139. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  140. /* We actually can't write halfwords properly if not word aligned */
  141. static inline void
  142. SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  143. {
  144. if (reg & 2) {
  145. unsigned int v = val << 16;
  146. v |= readl(ioaddr + (reg & ~2)) & 0xffff;
  147. writel(v, ioaddr + (reg & ~2));
  148. } else {
  149. writew(val, ioaddr + reg);
  150. }
  151. }
  152. #elif defined(CONFIG_ARCH_OMAP)
  153. /* We can only do 16-bit reads and writes in the static memory space. */
  154. #define SMC_CAN_USE_8BIT 0
  155. #define SMC_CAN_USE_16BIT 1
  156. #define SMC_CAN_USE_32BIT 0
  157. #define SMC_IO_SHIFT 0
  158. #define SMC_NOWAIT 1
  159. #define SMC_inw(a, r) readw((a) + (r))
  160. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  161. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  162. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  163. #include <asm/mach-types.h>
  164. #include <asm/arch/cpu.h>
  165. #define SMC_IRQ_FLAGS (( \
  166. machine_is_omap_h2() \
  167. || machine_is_omap_h3() \
  168. || machine_is_omap_h4() \
  169. || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
  170. ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
  171. #elif defined(CONFIG_SH_SH4202_MICRODEV)
  172. #define SMC_CAN_USE_8BIT 0
  173. #define SMC_CAN_USE_16BIT 1
  174. #define SMC_CAN_USE_32BIT 0
  175. #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
  176. #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
  177. #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
  178. #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
  179. #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
  180. #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
  181. #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
  182. #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
  183. #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
  184. #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
  185. #define SMC_IRQ_FLAGS (0)
  186. #elif defined(CONFIG_ISA)
  187. #define SMC_CAN_USE_8BIT 1
  188. #define SMC_CAN_USE_16BIT 1
  189. #define SMC_CAN_USE_32BIT 0
  190. #define SMC_inb(a, r) inb((a) + (r))
  191. #define SMC_inw(a, r) inw((a) + (r))
  192. #define SMC_outb(v, a, r) outb(v, (a) + (r))
  193. #define SMC_outw(v, a, r) outw(v, (a) + (r))
  194. #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
  195. #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
  196. #elif defined(CONFIG_M32R)
  197. #define SMC_CAN_USE_8BIT 0
  198. #define SMC_CAN_USE_16BIT 1
  199. #define SMC_CAN_USE_32BIT 0
  200. #define SMC_inb(a, r) inb(((u32)a) + (r))
  201. #define SMC_inw(a, r) inw(((u32)a) + (r))
  202. #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
  203. #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
  204. #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
  205. #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
  206. #define SMC_IRQ_FLAGS (0)
  207. #define RPC_LSA_DEFAULT RPC_LED_TX_RX
  208. #define RPC_LSB_DEFAULT RPC_LED_100_10
  209. #elif defined(CONFIG_MACH_LPD79520) \
  210. || defined(CONFIG_MACH_LPD7A400) \
  211. || defined(CONFIG_MACH_LPD7A404)
  212. /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
  213. * way that the CPU handles chip selects and the way that the SMC chip
  214. * expects the chip select to operate. Refer to
  215. * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
  216. * IOBARRIER is a byte, in order that we read the least-common
  217. * denominator. It would be wasteful to read 32 bits from an 8-bit
  218. * accessible region.
  219. *
  220. * There is no explicit protection against interrupts intervening
  221. * between the writew and the IOBARRIER. In SMC ISR there is a
  222. * preamble that performs an IOBARRIER in the extremely unlikely event
  223. * that the driver interrupts itself between a writew to the chip an
  224. * the IOBARRIER that follows *and* the cache is large enough that the
  225. * first off-chip access while handing the interrupt is to the SMC
  226. * chip. Other devices in the same address space as the SMC chip must
  227. * be aware of the potential for trouble and perform a similar
  228. * IOBARRIER on entry to their ISR.
  229. */
  230. #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
  231. #define SMC_CAN_USE_8BIT 0
  232. #define SMC_CAN_USE_16BIT 1
  233. #define SMC_CAN_USE_32BIT 0
  234. #define SMC_NOWAIT 0
  235. #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
  236. #define SMC_inw(a,r)\
  237. ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
  238. #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
  239. #define SMC_insw LPD7_SMC_insw
  240. static inline void LPD7_SMC_insw (unsigned char* a, int r,
  241. unsigned char* p, int l)
  242. {
  243. unsigned short* ps = (unsigned short*) p;
  244. while (l-- > 0) {
  245. *ps++ = readw (a + r);
  246. LPD7X_IOBARRIER;
  247. }
  248. }
  249. #define SMC_outsw LPD7_SMC_outsw
  250. static inline void LPD7_SMC_outsw (unsigned char* a, int r,
  251. unsigned char* p, int l)
  252. {
  253. unsigned short* ps = (unsigned short*) p;
  254. while (l-- > 0) {
  255. writew (*ps++, a + r);
  256. LPD7X_IOBARRIER;
  257. }
  258. }
  259. #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
  260. #define RPC_LSA_DEFAULT RPC_LED_TX_RX
  261. #define RPC_LSB_DEFAULT RPC_LED_100_10
  262. #elif defined(CONFIG_SOC_AU1X00)
  263. #include <au1xxx.h>
  264. /* We can only do 16-bit reads and writes in the static memory space. */
  265. #define SMC_CAN_USE_8BIT 0
  266. #define SMC_CAN_USE_16BIT 1
  267. #define SMC_CAN_USE_32BIT 0
  268. #define SMC_IO_SHIFT 0
  269. #define SMC_NOWAIT 1
  270. #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
  271. #define SMC_insw(a, r, p, l) \
  272. do { \
  273. unsigned long _a = (unsigned long)((a) + (r)); \
  274. int _l = (l); \
  275. u16 *_p = (u16 *)(p); \
  276. while (_l-- > 0) \
  277. *_p++ = au_readw(_a); \
  278. } while(0)
  279. #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
  280. #define SMC_outsw(a, r, p, l) \
  281. do { \
  282. unsigned long _a = (unsigned long)((a) + (r)); \
  283. int _l = (l); \
  284. const u16 *_p = (const u16 *)(p); \
  285. while (_l-- > 0) \
  286. au_writew(*_p++ , _a); \
  287. } while(0)
  288. #define SMC_IRQ_FLAGS (0)
  289. #elif defined(CONFIG_ARCH_VERSATILE)
  290. #define SMC_CAN_USE_8BIT 1
  291. #define SMC_CAN_USE_16BIT 1
  292. #define SMC_CAN_USE_32BIT 1
  293. #define SMC_NOWAIT 1
  294. #define SMC_inb(a, r) readb((a) + (r))
  295. #define SMC_inw(a, r) readw((a) + (r))
  296. #define SMC_inl(a, r) readl((a) + (r))
  297. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  298. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  299. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  300. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  301. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  302. #define SMC_IRQ_FLAGS (0)
  303. #else
  304. #define SMC_CAN_USE_8BIT 1
  305. #define SMC_CAN_USE_16BIT 1
  306. #define SMC_CAN_USE_32BIT 1
  307. #define SMC_NOWAIT 1
  308. #define SMC_inb(a, r) readb((a) + (r))
  309. #define SMC_inw(a, r) readw((a) + (r))
  310. #define SMC_inl(a, r) readl((a) + (r))
  311. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  312. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  313. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  314. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  315. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  316. #define RPC_LSA_DEFAULT RPC_LED_100_10
  317. #define RPC_LSB_DEFAULT RPC_LED_TX_RX
  318. #endif
  319. #ifdef SMC_USE_PXA_DMA
  320. /*
  321. * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
  322. * always happening in irq context so no need to worry about races. TX is
  323. * different and probably not worth it for that reason, and not as critical
  324. * as RX which can overrun memory and lose packets.
  325. */
  326. #include <linux/dma-mapping.h>
  327. #include <asm/dma.h>
  328. #include <asm/arch/pxa-regs.h>
  329. #ifdef SMC_insl
  330. #undef SMC_insl
  331. #define SMC_insl(a, r, p, l) \
  332. smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
  333. static inline void
  334. smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
  335. u_char *buf, int len)
  336. {
  337. dma_addr_t dmabuf;
  338. /* fallback if no DMA available */
  339. if (dma == (unsigned char)-1) {
  340. readsl(ioaddr + reg, buf, len);
  341. return;
  342. }
  343. /* 64 bit alignment is required for memory to memory DMA */
  344. if ((long)buf & 4) {
  345. *((u32 *)buf) = SMC_inl(ioaddr, reg);
  346. buf += 4;
  347. len--;
  348. }
  349. len *= 4;
  350. dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
  351. DCSR(dma) = DCSR_NODESC;
  352. DTADR(dma) = dmabuf;
  353. DSADR(dma) = physaddr + reg;
  354. DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
  355. DCMD_WIDTH4 | (DCMD_LENGTH & len));
  356. DCSR(dma) = DCSR_NODESC | DCSR_RUN;
  357. while (!(DCSR(dma) & DCSR_STOPSTATE))
  358. cpu_relax();
  359. DCSR(dma) = 0;
  360. dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
  361. }
  362. #endif
  363. #ifdef SMC_insw
  364. #undef SMC_insw
  365. #define SMC_insw(a, r, p, l) \
  366. smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
  367. static inline void
  368. smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
  369. u_char *buf, int len)
  370. {
  371. dma_addr_t dmabuf;
  372. /* fallback if no DMA available */
  373. if (dma == (unsigned char)-1) {
  374. readsw(ioaddr + reg, buf, len);
  375. return;
  376. }
  377. /* 64 bit alignment is required for memory to memory DMA */
  378. while ((long)buf & 6) {
  379. *((u16 *)buf) = SMC_inw(ioaddr, reg);
  380. buf += 2;
  381. len--;
  382. }
  383. len *= 2;
  384. dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
  385. DCSR(dma) = DCSR_NODESC;
  386. DTADR(dma) = dmabuf;
  387. DSADR(dma) = physaddr + reg;
  388. DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
  389. DCMD_WIDTH2 | (DCMD_LENGTH & len));
  390. DCSR(dma) = DCSR_NODESC | DCSR_RUN;
  391. while (!(DCSR(dma) & DCSR_STOPSTATE))
  392. cpu_relax();
  393. DCSR(dma) = 0;
  394. dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
  395. }
  396. #endif
  397. static void
  398. smc_pxa_dma_irq(int dma, void *dummy)
  399. {
  400. DCSR(dma) = 0;
  401. }
  402. #endif /* SMC_USE_PXA_DMA */
  403. /*
  404. * Everything a particular hardware setup needs should have been defined
  405. * at this point. Add stubs for the undefined cases, mainly to avoid
  406. * compilation warnings since they'll be optimized away, or to prevent buggy
  407. * use of them.
  408. */
  409. #if ! SMC_CAN_USE_32BIT
  410. #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
  411. #define SMC_outl(x, ioaddr, reg) BUG()
  412. #define SMC_insl(a, r, p, l) BUG()
  413. #define SMC_outsl(a, r, p, l) BUG()
  414. #endif
  415. #if !defined(SMC_insl) || !defined(SMC_outsl)
  416. #define SMC_insl(a, r, p, l) BUG()
  417. #define SMC_outsl(a, r, p, l) BUG()
  418. #endif
  419. #if ! SMC_CAN_USE_16BIT
  420. /*
  421. * Any 16-bit access is performed with two 8-bit accesses if the hardware
  422. * can't do it directly. Most registers are 16-bit so those are mandatory.
  423. */
  424. #define SMC_outw(x, ioaddr, reg) \
  425. do { \
  426. unsigned int __val16 = (x); \
  427. SMC_outb( __val16, ioaddr, reg ); \
  428. SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
  429. } while (0)
  430. #define SMC_inw(ioaddr, reg) \
  431. ({ \
  432. unsigned int __val16; \
  433. __val16 = SMC_inb( ioaddr, reg ); \
  434. __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
  435. __val16; \
  436. })
  437. #define SMC_insw(a, r, p, l) BUG()
  438. #define SMC_outsw(a, r, p, l) BUG()
  439. #endif
  440. #if !defined(SMC_insw) || !defined(SMC_outsw)
  441. #define SMC_insw(a, r, p, l) BUG()
  442. #define SMC_outsw(a, r, p, l) BUG()
  443. #endif
  444. #if ! SMC_CAN_USE_8BIT
  445. #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
  446. #define SMC_outb(x, ioaddr, reg) BUG()
  447. #define SMC_insb(a, r, p, l) BUG()
  448. #define SMC_outsb(a, r, p, l) BUG()
  449. #endif
  450. #if !defined(SMC_insb) || !defined(SMC_outsb)
  451. #define SMC_insb(a, r, p, l) BUG()
  452. #define SMC_outsb(a, r, p, l) BUG()
  453. #endif
  454. #ifndef SMC_CAN_USE_DATACS
  455. #define SMC_CAN_USE_DATACS 0
  456. #endif
  457. #ifndef SMC_IO_SHIFT
  458. #define SMC_IO_SHIFT 0
  459. #endif
  460. #ifndef SMC_IRQ_FLAGS
  461. #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
  462. #endif
  463. #ifndef SMC_INTERRUPT_PREAMBLE
  464. #define SMC_INTERRUPT_PREAMBLE
  465. #endif
  466. /* Because of bank switching, the LAN91x uses only 16 I/O ports */
  467. #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
  468. #define SMC_DATA_EXTENT (4)
  469. /*
  470. . Bank Select Register:
  471. .
  472. . yyyy yyyy 0000 00xx
  473. . xx = bank number
  474. . yyyy yyyy = 0x33, for identification purposes.
  475. */
  476. #define BANK_SELECT (14 << SMC_IO_SHIFT)
  477. // Transmit Control Register
  478. /* BANK 0 */
  479. #define TCR_REG SMC_REG(0x0000, 0)
  480. #define TCR_ENABLE 0x0001 // When 1 we can transmit
  481. #define TCR_LOOP 0x0002 // Controls output pin LBK
  482. #define TCR_FORCOL 0x0004 // When 1 will force a collision
  483. #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
  484. #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
  485. #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
  486. #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
  487. #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
  488. #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
  489. #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
  490. #define TCR_CLEAR 0 /* do NOTHING */
  491. /* the default settings for the TCR register : */
  492. #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
  493. // EPH Status Register
  494. /* BANK 0 */
  495. #define EPH_STATUS_REG SMC_REG(0x0002, 0)
  496. #define ES_TX_SUC 0x0001 // Last TX was successful
  497. #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
  498. #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
  499. #define ES_LTX_MULT 0x0008 // Last tx was a multicast
  500. #define ES_16COL 0x0010 // 16 Collisions Reached
  501. #define ES_SQET 0x0020 // Signal Quality Error Test
  502. #define ES_LTXBRD 0x0040 // Last tx was a broadcast
  503. #define ES_TXDEFR 0x0080 // Transmit Deferred
  504. #define ES_LATCOL 0x0200 // Late collision detected on last tx
  505. #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
  506. #define ES_EXC_DEF 0x0800 // Excessive Deferral
  507. #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
  508. #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
  509. #define ES_TXUNRN 0x8000 // Tx Underrun
  510. // Receive Control Register
  511. /* BANK 0 */
  512. #define RCR_REG SMC_REG(0x0004, 0)
  513. #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
  514. #define RCR_PRMS 0x0002 // Enable promiscuous mode
  515. #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
  516. #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
  517. #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
  518. #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
  519. #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
  520. #define RCR_SOFTRST 0x8000 // resets the chip
  521. /* the normal settings for the RCR register : */
  522. #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
  523. #define RCR_CLEAR 0x0 // set it to a base state
  524. // Counter Register
  525. /* BANK 0 */
  526. #define COUNTER_REG SMC_REG(0x0006, 0)
  527. // Memory Information Register
  528. /* BANK 0 */
  529. #define MIR_REG SMC_REG(0x0008, 0)
  530. // Receive/Phy Control Register
  531. /* BANK 0 */
  532. #define RPC_REG SMC_REG(0x000A, 0)
  533. #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
  534. #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
  535. #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
  536. #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
  537. #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
  538. #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
  539. #define RPC_LED_RES (0x01) // LED = Reserved
  540. #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
  541. #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
  542. #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
  543. #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
  544. #define RPC_LED_TX (0x06) // LED = TX packet occurred
  545. #define RPC_LED_RX (0x07) // LED = RX packet occurred
  546. #ifndef RPC_LSA_DEFAULT
  547. #define RPC_LSA_DEFAULT RPC_LED_100
  548. #endif
  549. #ifndef RPC_LSB_DEFAULT
  550. #define RPC_LSB_DEFAULT RPC_LED_FD
  551. #endif
  552. #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
  553. /* Bank 0 0x0C is reserved */
  554. // Bank Select Register
  555. /* All Banks */
  556. #define BSR_REG 0x000E
  557. // Configuration Reg
  558. /* BANK 1 */
  559. #define CONFIG_REG SMC_REG(0x0000, 1)
  560. #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
  561. #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
  562. #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
  563. #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
  564. // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
  565. #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
  566. // Base Address Register
  567. /* BANK 1 */
  568. #define BASE_REG SMC_REG(0x0002, 1)
  569. // Individual Address Registers
  570. /* BANK 1 */
  571. #define ADDR0_REG SMC_REG(0x0004, 1)
  572. #define ADDR1_REG SMC_REG(0x0006, 1)
  573. #define ADDR2_REG SMC_REG(0x0008, 1)
  574. // General Purpose Register
  575. /* BANK 1 */
  576. #define GP_REG SMC_REG(0x000A, 1)
  577. // Control Register
  578. /* BANK 1 */
  579. #define CTL_REG SMC_REG(0x000C, 1)
  580. #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
  581. #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
  582. #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
  583. #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
  584. #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
  585. #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
  586. #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
  587. #define CTL_STORE 0x0001 // When set stores registers into EEPROM
  588. // MMU Command Register
  589. /* BANK 2 */
  590. #define MMU_CMD_REG SMC_REG(0x0000, 2)
  591. #define MC_BUSY 1 // When 1 the last release has not completed
  592. #define MC_NOP (0<<5) // No Op
  593. #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
  594. #define MC_RESET (2<<5) // Reset MMU to initial state
  595. #define MC_REMOVE (3<<5) // Remove the current rx packet
  596. #define MC_RELEASE (4<<5) // Remove and release the current rx packet
  597. #define MC_FREEPKT (5<<5) // Release packet in PNR register
  598. #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
  599. #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
  600. // Packet Number Register
  601. /* BANK 2 */
  602. #define PN_REG SMC_REG(0x0002, 2)
  603. // Allocation Result Register
  604. /* BANK 2 */
  605. #define AR_REG SMC_REG(0x0003, 2)
  606. #define AR_FAILED 0x80 // Alocation Failed
  607. // TX FIFO Ports Register
  608. /* BANK 2 */
  609. #define TXFIFO_REG SMC_REG(0x0004, 2)
  610. #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
  611. // RX FIFO Ports Register
  612. /* BANK 2 */
  613. #define RXFIFO_REG SMC_REG(0x0005, 2)
  614. #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
  615. #define FIFO_REG SMC_REG(0x0004, 2)
  616. // Pointer Register
  617. /* BANK 2 */
  618. #define PTR_REG SMC_REG(0x0006, 2)
  619. #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
  620. #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
  621. #define PTR_READ 0x2000 // When 1 the operation is a read
  622. // Data Register
  623. /* BANK 2 */
  624. #define DATA_REG SMC_REG(0x0008, 2)
  625. // Interrupt Status/Acknowledge Register
  626. /* BANK 2 */
  627. #define INT_REG SMC_REG(0x000C, 2)
  628. // Interrupt Mask Register
  629. /* BANK 2 */
  630. #define IM_REG SMC_REG(0x000D, 2)
  631. #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
  632. #define IM_ERCV_INT 0x40 // Early Receive Interrupt
  633. #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
  634. #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
  635. #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
  636. #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
  637. #define IM_TX_INT 0x02 // Transmit Interrupt
  638. #define IM_RCV_INT 0x01 // Receive Interrupt
  639. // Multicast Table Registers
  640. /* BANK 3 */
  641. #define MCAST_REG1 SMC_REG(0x0000, 3)
  642. #define MCAST_REG2 SMC_REG(0x0002, 3)
  643. #define MCAST_REG3 SMC_REG(0x0004, 3)
  644. #define MCAST_REG4 SMC_REG(0x0006, 3)
  645. // Management Interface Register (MII)
  646. /* BANK 3 */
  647. #define MII_REG SMC_REG(0x0008, 3)
  648. #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
  649. #define MII_MDOE 0x0008 // MII Output Enable
  650. #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
  651. #define MII_MDI 0x0002 // MII Input, pin MDI
  652. #define MII_MDO 0x0001 // MII Output, pin MDO
  653. // Revision Register
  654. /* BANK 3 */
  655. /* ( hi: chip id low: rev # ) */
  656. #define REV_REG SMC_REG(0x000A, 3)
  657. // Early RCV Register
  658. /* BANK 3 */
  659. /* this is NOT on SMC9192 */
  660. #define ERCV_REG SMC_REG(0x000C, 3)
  661. #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
  662. #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
  663. // External Register
  664. /* BANK 7 */
  665. #define EXT_REG SMC_REG(0x0000, 7)
  666. #define CHIP_9192 3
  667. #define CHIP_9194 4
  668. #define CHIP_9195 5
  669. #define CHIP_9196 6
  670. #define CHIP_91100 7
  671. #define CHIP_91100FD 8
  672. #define CHIP_91111FD 9
  673. static const char * chip_ids[ 16 ] = {
  674. NULL, NULL, NULL,
  675. /* 3 */ "SMC91C90/91C92",
  676. /* 4 */ "SMC91C94",
  677. /* 5 */ "SMC91C95",
  678. /* 6 */ "SMC91C96",
  679. /* 7 */ "SMC91C100",
  680. /* 8 */ "SMC91C100FD",
  681. /* 9 */ "SMC91C11xFD",
  682. NULL, NULL, NULL,
  683. NULL, NULL, NULL};
  684. /*
  685. . Receive status bits
  686. */
  687. #define RS_ALGNERR 0x8000
  688. #define RS_BRODCAST 0x4000
  689. #define RS_BADCRC 0x2000
  690. #define RS_ODDFRAME 0x1000
  691. #define RS_TOOLONG 0x0800
  692. #define RS_TOOSHORT 0x0400
  693. #define RS_MULTICAST 0x0001
  694. #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
  695. /*
  696. * PHY IDs
  697. * LAN83C183 == LAN91C111 Internal PHY
  698. */
  699. #define PHY_LAN83C183 0x0016f840
  700. #define PHY_LAN83C180 0x02821c50
  701. /*
  702. * PHY Register Addresses (LAN91C111 Internal PHY)
  703. *
  704. * Generic PHY registers can be found in <linux/mii.h>
  705. *
  706. * These phy registers are specific to our on-board phy.
  707. */
  708. // PHY Configuration Register 1
  709. #define PHY_CFG1_REG 0x10
  710. #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
  711. #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
  712. #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
  713. #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
  714. #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
  715. #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
  716. #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
  717. #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
  718. #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
  719. #define PHY_CFG1_TLVL_MASK 0x003C
  720. #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
  721. // PHY Configuration Register 2
  722. #define PHY_CFG2_REG 0x11
  723. #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
  724. #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
  725. #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
  726. #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
  727. // PHY Status Output (and Interrupt status) Register
  728. #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
  729. #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
  730. #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
  731. #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
  732. #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
  733. #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
  734. #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
  735. #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
  736. #define PHY_INT_JAB 0x0100 // 1=Jabber detected
  737. #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
  738. #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
  739. // PHY Interrupt/Status Mask Register
  740. #define PHY_MASK_REG 0x13 // Interrupt Mask
  741. // Uses the same bit definitions as PHY_INT_REG
  742. /*
  743. * SMC91C96 ethernet config and status registers.
  744. * These are in the "attribute" space.
  745. */
  746. #define ECOR 0x8000
  747. #define ECOR_RESET 0x80
  748. #define ECOR_LEVEL_IRQ 0x40
  749. #define ECOR_WR_ATTRIB 0x04
  750. #define ECOR_ENABLE 0x01
  751. #define ECSR 0x8002
  752. #define ECSR_IOIS8 0x20
  753. #define ECSR_PWRDWN 0x04
  754. #define ECSR_INT 0x02
  755. #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
  756. /*
  757. * Macros to abstract register access according to the data bus
  758. * capabilities. Please use those and not the in/out primitives.
  759. * Note: the following macros do *not* select the bank -- this must
  760. * be done separately as needed in the main code. The SMC_REG() macro
  761. * only uses the bank argument for debugging purposes (when enabled).
  762. *
  763. * Note: despite inline functions being safer, everything leading to this
  764. * should preferably be macros to let BUG() display the line number in
  765. * the core source code since we're interested in the top call site
  766. * not in any inline function location.
  767. */
  768. #if SMC_DEBUG > 0
  769. #define SMC_REG(reg, bank) \
  770. ({ \
  771. int __b = SMC_CURRENT_BANK(); \
  772. if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
  773. printk( "%s: bank reg screwed (0x%04x)\n", \
  774. CARDNAME, __b ); \
  775. BUG(); \
  776. } \
  777. reg<<SMC_IO_SHIFT; \
  778. })
  779. #else
  780. #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
  781. #endif
  782. /*
  783. * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
  784. * aligned to a 32 bit boundary. I tell you that does exist!
  785. * Fortunately the affected register accesses can be easily worked around
  786. * since we can write zeroes to the preceeding 16 bits without adverse
  787. * effects and use a 32-bit access.
  788. *
  789. * Enforce it on any 32-bit capable setup for now.
  790. */
  791. #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
  792. #define SMC_GET_PN() \
  793. ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
  794. : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
  795. #define SMC_SET_PN(x) \
  796. do { \
  797. if (SMC_MUST_ALIGN_WRITE) \
  798. SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
  799. else if (SMC_CAN_USE_8BIT) \
  800. SMC_outb(x, ioaddr, PN_REG); \
  801. else \
  802. SMC_outw(x, ioaddr, PN_REG); \
  803. } while (0)
  804. #define SMC_GET_AR() \
  805. ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
  806. : (SMC_inw(ioaddr, PN_REG) >> 8) )
  807. #define SMC_GET_TXFIFO() \
  808. ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
  809. : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
  810. #define SMC_GET_RXFIFO() \
  811. ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
  812. : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
  813. #define SMC_GET_INT() \
  814. ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
  815. : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
  816. #define SMC_ACK_INT(x) \
  817. do { \
  818. if (SMC_CAN_USE_8BIT) \
  819. SMC_outb(x, ioaddr, INT_REG); \
  820. else { \
  821. unsigned long __flags; \
  822. int __mask; \
  823. local_irq_save(__flags); \
  824. __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
  825. SMC_outw( __mask | (x), ioaddr, INT_REG ); \
  826. local_irq_restore(__flags); \
  827. } \
  828. } while (0)
  829. #define SMC_GET_INT_MASK() \
  830. ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
  831. : (SMC_inw( ioaddr, INT_REG ) >> 8) )
  832. #define SMC_SET_INT_MASK(x) \
  833. do { \
  834. if (SMC_CAN_USE_8BIT) \
  835. SMC_outb(x, ioaddr, IM_REG); \
  836. else \
  837. SMC_outw((x) << 8, ioaddr, INT_REG); \
  838. } while (0)
  839. #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
  840. #define SMC_SELECT_BANK(x) \
  841. do { \
  842. if (SMC_MUST_ALIGN_WRITE) \
  843. SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
  844. else \
  845. SMC_outw(x, ioaddr, BANK_SELECT); \
  846. } while (0)
  847. #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
  848. #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
  849. #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
  850. #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
  851. #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
  852. #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
  853. #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
  854. #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
  855. #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
  856. #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
  857. #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
  858. #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
  859. #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
  860. #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
  861. #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
  862. #define SMC_SET_PTR(x) \
  863. do { \
  864. if (SMC_MUST_ALIGN_WRITE) \
  865. SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
  866. else \
  867. SMC_outw(x, ioaddr, PTR_REG); \
  868. } while (0)
  869. #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
  870. #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
  871. #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
  872. #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
  873. #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
  874. #define SMC_SET_RPC(x) \
  875. do { \
  876. if (SMC_MUST_ALIGN_WRITE) \
  877. SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
  878. else \
  879. SMC_outw(x, ioaddr, RPC_REG); \
  880. } while (0)
  881. #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
  882. #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
  883. #ifndef SMC_GET_MAC_ADDR
  884. #define SMC_GET_MAC_ADDR(addr) \
  885. do { \
  886. unsigned int __v; \
  887. __v = SMC_inw( ioaddr, ADDR0_REG ); \
  888. addr[0] = __v; addr[1] = __v >> 8; \
  889. __v = SMC_inw( ioaddr, ADDR1_REG ); \
  890. addr[2] = __v; addr[3] = __v >> 8; \
  891. __v = SMC_inw( ioaddr, ADDR2_REG ); \
  892. addr[4] = __v; addr[5] = __v >> 8; \
  893. } while (0)
  894. #endif
  895. #define SMC_SET_MAC_ADDR(addr) \
  896. do { \
  897. SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
  898. SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
  899. SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
  900. } while (0)
  901. #define SMC_SET_MCAST(x) \
  902. do { \
  903. const unsigned char *mt = (x); \
  904. SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
  905. SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
  906. SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
  907. SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
  908. } while (0)
  909. #define SMC_PUT_PKT_HDR(status, length) \
  910. do { \
  911. if (SMC_CAN_USE_32BIT) \
  912. SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
  913. else { \
  914. SMC_outw(status, ioaddr, DATA_REG); \
  915. SMC_outw(length, ioaddr, DATA_REG); \
  916. } \
  917. } while (0)
  918. #define SMC_GET_PKT_HDR(status, length) \
  919. do { \
  920. if (SMC_CAN_USE_32BIT) { \
  921. unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
  922. (status) = __val & 0xffff; \
  923. (length) = __val >> 16; \
  924. } else { \
  925. (status) = SMC_inw(ioaddr, DATA_REG); \
  926. (length) = SMC_inw(ioaddr, DATA_REG); \
  927. } \
  928. } while (0)
  929. #define SMC_PUSH_DATA(p, l) \
  930. do { \
  931. if (SMC_CAN_USE_32BIT) { \
  932. void *__ptr = (p); \
  933. int __len = (l); \
  934. void __iomem *__ioaddr = ioaddr; \
  935. if (__len >= 2 && (unsigned long)__ptr & 2) { \
  936. __len -= 2; \
  937. SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
  938. __ptr += 2; \
  939. } \
  940. if (SMC_CAN_USE_DATACS && lp->datacs) \
  941. __ioaddr = lp->datacs; \
  942. SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
  943. if (__len & 2) { \
  944. __ptr += (__len & ~3); \
  945. SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
  946. } \
  947. } else if (SMC_CAN_USE_16BIT) \
  948. SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
  949. else if (SMC_CAN_USE_8BIT) \
  950. SMC_outsb(ioaddr, DATA_REG, p, l); \
  951. } while (0)
  952. #define SMC_PULL_DATA(p, l) \
  953. do { \
  954. if (SMC_CAN_USE_32BIT) { \
  955. void *__ptr = (p); \
  956. int __len = (l); \
  957. void __iomem *__ioaddr = ioaddr; \
  958. if ((unsigned long)__ptr & 2) { \
  959. /* \
  960. * We want 32bit alignment here. \
  961. * Since some buses perform a full \
  962. * 32bit fetch even for 16bit data \
  963. * we can't use SMC_inw() here. \
  964. * Back both source (on-chip) and \
  965. * destination pointers of 2 bytes. \
  966. * This is possible since the call to \
  967. * SMC_GET_PKT_HDR() already advanced \
  968. * the source pointer of 4 bytes, and \
  969. * the skb_reserve(skb, 2) advanced \
  970. * the destination pointer of 2 bytes. \
  971. */ \
  972. __ptr -= 2; \
  973. __len += 2; \
  974. SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
  975. } \
  976. if (SMC_CAN_USE_DATACS && lp->datacs) \
  977. __ioaddr = lp->datacs; \
  978. __len += 2; \
  979. SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
  980. } else if (SMC_CAN_USE_16BIT) \
  981. SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
  982. else if (SMC_CAN_USE_8BIT) \
  983. SMC_insb(ioaddr, DATA_REG, p, l); \
  984. } while (0)
  985. #endif /* _SMC91X_H_ */