smc9194.h 6.7 KB

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  1. /*------------------------------------------------------------------------
  2. . smc9194.h
  3. . Copyright (C) 1996 by Erik Stahlman
  4. .
  5. . This software may be used and distributed according to the terms
  6. . of the GNU General Public License, incorporated herein by reference.
  7. .
  8. . This file contains register information and access macros for
  9. . the SMC91xxx chipset.
  10. .
  11. . Information contained in this file was obtained from the SMC91C94
  12. . manual from SMC. To get a copy, if you really want one, you can find
  13. . information under www.smc.com in the components division.
  14. . ( this thanks to advice from Donald Becker ).
  15. .
  16. . Authors
  17. . Erik Stahlman ( erik@vt.edu )
  18. .
  19. . History
  20. . 01/06/96 Erik Stahlman moved definitions here from main .c file
  21. . 01/19/96 Erik Stahlman polished this up some, and added better
  22. . error handling
  23. .
  24. ---------------------------------------------------------------------------*/
  25. #ifndef _SMC9194_H_
  26. #define _SMC9194_H_
  27. /* I want some simple types */
  28. typedef unsigned char byte;
  29. typedef unsigned short word;
  30. typedef unsigned long int dword;
  31. /* Because of bank switching, the SMC91xxx uses only 16 I/O ports */
  32. #define SMC_IO_EXTENT 16
  33. /*---------------------------------------------------------------
  34. .
  35. . A description of the SMC registers is probably in order here,
  36. . although for details, the SMC datasheet is invaluable.
  37. .
  38. . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
  39. . are accessed by writing a number into the BANK_SELECT register
  40. . ( I also use a SMC_SELECT_BANK macro for this ).
  41. .
  42. . The banks are configured so that for most purposes, bank 2 is all
  43. . that is needed for simple run time tasks.
  44. -----------------------------------------------------------------------*/
  45. /*
  46. . Bank Select Register:
  47. .
  48. . yyyy yyyy 0000 00xx
  49. . xx = bank number
  50. . yyyy yyyy = 0x33, for identification purposes.
  51. */
  52. #define BANK_SELECT 14
  53. /* BANK 0 */
  54. #define TCR 0 /* transmit control register */
  55. #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
  56. #define TCR_FDUPLX 0x0800 /* receive packets sent out */
  57. #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
  58. #define TCR_MON_CNS 0x0400 /* monitors the carrier status */
  59. #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
  60. #define TCR_CLEAR 0 /* do NOTHING */
  61. /* the normal settings for the TCR register : */
  62. /* QUESTION: do I want to enable padding of short packets ? */
  63. #define TCR_NORMAL TCR_ENABLE
  64. #define EPH_STATUS 2
  65. #define ES_LINK_OK 0x4000 /* is the link integrity ok ? */
  66. #define RCR 4
  67. #define RCR_SOFTRESET 0x8000 /* resets the chip */
  68. #define RCR_STRIP_CRC 0x200 /* strips CRC */
  69. #define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
  70. #define RCR_ALMUL 0x4 /* receive all multicast packets */
  71. #define RCR_PROMISC 0x2 /* enable promiscuous mode */
  72. /* the normal settings for the RCR register : */
  73. #define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)
  74. #define RCR_CLEAR 0x0 /* set it to a base state */
  75. #define COUNTER 6
  76. #define MIR 8
  77. #define MCR 10
  78. /* 12 is reserved */
  79. /* BANK 1 */
  80. #define CONFIG 0
  81. #define CFG_AUI_SELECT 0x100
  82. #define BASE 2
  83. #define ADDR0 4
  84. #define ADDR1 6
  85. #define ADDR2 8
  86. #define GENERAL 10
  87. #define CONTROL 12
  88. #define CTL_POWERDOWN 0x2000
  89. #define CTL_LE_ENABLE 0x80
  90. #define CTL_CR_ENABLE 0x40
  91. #define CTL_TE_ENABLE 0x0020
  92. #define CTL_AUTO_RELEASE 0x0800
  93. #define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */
  94. /* BANK 2 */
  95. #define MMU_CMD 0
  96. #define MC_BUSY 1 /* only readable bit in the register */
  97. #define MC_NOP 0
  98. #define MC_ALLOC 0x20 /* or with number of 256 byte packets */
  99. #define MC_RESET 0x40
  100. #define MC_REMOVE 0x60 /* remove the current rx packet */
  101. #define MC_RELEASE 0x80 /* remove and release the current rx packet */
  102. #define MC_FREEPKT 0xA0 /* Release packet in PNR register */
  103. #define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
  104. #define PNR_ARR 2
  105. #define FIFO_PORTS 4
  106. #define FP_RXEMPTY 0x8000
  107. #define FP_TXEMPTY 0x80
  108. #define POINTER 6
  109. #define PTR_READ 0x2000
  110. #define PTR_RCV 0x8000
  111. #define PTR_AUTOINC 0x4000
  112. #define PTR_AUTO_INC 0x0040
  113. #define DATA_1 8
  114. #define DATA_2 10
  115. #define INTERRUPT 12
  116. #define INT_MASK 13
  117. #define IM_RCV_INT 0x1
  118. #define IM_TX_INT 0x2
  119. #define IM_TX_EMPTY_INT 0x4
  120. #define IM_ALLOC_INT 0x8
  121. #define IM_RX_OVRN_INT 0x10
  122. #define IM_EPH_INT 0x20
  123. #define IM_ERCV_INT 0x40 /* not on SMC9192 */
  124. /* BANK 3 */
  125. #define MULTICAST1 0
  126. #define MULTICAST2 2
  127. #define MULTICAST3 4
  128. #define MULTICAST4 6
  129. #define MGMT 8
  130. #define REVISION 10 /* ( hi: chip id low: rev # ) */
  131. /* this is NOT on SMC9192 */
  132. #define ERCV 12
  133. #define CHIP_9190 3
  134. #define CHIP_9194 4
  135. #define CHIP_9195 5
  136. #define CHIP_91100 7
  137. static const char * chip_ids[ 15 ] = {
  138. NULL, NULL, NULL,
  139. /* 3 */ "SMC91C90/91C92",
  140. /* 4 */ "SMC91C94",
  141. /* 5 */ "SMC91C95",
  142. NULL,
  143. /* 7 */ "SMC91C100",
  144. /* 8 */ "SMC91C100FD",
  145. NULL, NULL, NULL,
  146. NULL, NULL, NULL};
  147. /*
  148. . Transmit status bits
  149. */
  150. #define TS_SUCCESS 0x0001
  151. #define TS_LOSTCAR 0x0400
  152. #define TS_LATCOL 0x0200
  153. #define TS_16COL 0x0010
  154. /*
  155. . Receive status bits
  156. */
  157. #define RS_ALGNERR 0x8000
  158. #define RS_BADCRC 0x2000
  159. #define RS_ODDFRAME 0x1000
  160. #define RS_TOOLONG 0x0800
  161. #define RS_TOOSHORT 0x0400
  162. #define RS_MULTICAST 0x0001
  163. #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
  164. static const char * interfaces[ 2 ] = { "TP", "AUI" };
  165. /*-------------------------------------------------------------------------
  166. . I define some macros to make it easier to do somewhat common
  167. . or slightly complicated, repeated tasks.
  168. --------------------------------------------------------------------------*/
  169. /* select a register bank, 0 to 3 */
  170. #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
  171. /* define a small delay for the reset */
  172. #define SMC_DELAY() { inw( ioaddr + RCR );\
  173. inw( ioaddr + RCR );\
  174. inw( ioaddr + RCR ); }
  175. /* this enables an interrupt in the interrupt mask register */
  176. #define SMC_ENABLE_INT(x) {\
  177. unsigned char mask;\
  178. SMC_SELECT_BANK(2);\
  179. mask = inb( ioaddr + INT_MASK );\
  180. mask |= (x);\
  181. outb( mask, ioaddr + INT_MASK ); \
  182. }
  183. /* this disables an interrupt from the interrupt mask register */
  184. #define SMC_DISABLE_INT(x) {\
  185. unsigned char mask;\
  186. SMC_SELECT_BANK(2);\
  187. mask = inb( ioaddr + INT_MASK );\
  188. mask &= ~(x);\
  189. outb( mask, ioaddr + INT_MASK ); \
  190. }
  191. /*----------------------------------------------------------------------
  192. . Define the interrupts that I want to receive from the card
  193. .
  194. . I want:
  195. . IM_EPH_INT, for nasty errors
  196. . IM_RCV_INT, for happy received packets
  197. . IM_RX_OVRN_INT, because I have to kick the receiver
  198. --------------------------------------------------------------------------*/
  199. #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)
  200. #endif /* _SMC_9194_H_ */