sky2.c 102 KB

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  1. /*
  2. * New driver for Marvell Yukon 2 chipset.
  3. * Based on earlier sk98lin, and skge driver.
  4. *
  5. * This driver intentionally does not support all the features
  6. * of the original driver such as link fail-over and link management because
  7. * those should be done at higher levels.
  8. *
  9. * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <linux/crc32.h>
  25. #include <linux/kernel.h>
  26. #include <linux/version.h>
  27. #include <linux/module.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/pci.h>
  33. #include <linux/ip.h>
  34. #include <linux/tcp.h>
  35. #include <linux/in.h>
  36. #include <linux/delay.h>
  37. #include <linux/workqueue.h>
  38. #include <linux/if_vlan.h>
  39. #include <linux/prefetch.h>
  40. #include <linux/mii.h>
  41. #include <asm/irq.h>
  42. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  43. #define SKY2_VLAN_TAG_USED 1
  44. #endif
  45. #include "sky2.h"
  46. #define DRV_NAME "sky2"
  47. #define DRV_VERSION "1.14"
  48. #define PFX DRV_NAME " "
  49. /*
  50. * The Yukon II chipset takes 64 bit command blocks (called list elements)
  51. * that are organized into three (receive, transmit, status) different rings
  52. * similar to Tigon3.
  53. */
  54. #define RX_LE_SIZE 1024
  55. #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
  56. #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
  57. #define RX_DEF_PENDING RX_MAX_PENDING
  58. #define RX_SKB_ALIGN 8
  59. #define RX_BUF_WRITE 16
  60. #define TX_RING_SIZE 512
  61. #define TX_DEF_PENDING (TX_RING_SIZE - 1)
  62. #define TX_MIN_PENDING 64
  63. #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
  64. #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
  65. #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
  66. #define TX_WATCHDOG (5 * HZ)
  67. #define NAPI_WEIGHT 64
  68. #define PHY_RETRIES 1000
  69. #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
  70. static const u32 default_msg =
  71. NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  72. | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
  73. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  74. static int debug = -1; /* defaults above */
  75. module_param(debug, int, 0);
  76. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  77. static int copybreak __read_mostly = 128;
  78. module_param(copybreak, int, 0);
  79. MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  80. static int disable_msi = 0;
  81. module_param(disable_msi, int, 0);
  82. MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  83. static int idle_timeout = 0;
  84. module_param(idle_timeout, int, 0);
  85. MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
  86. static const struct pci_device_id sky2_id_table[] = {
  87. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
  88. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
  89. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
  90. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
  91. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
  92. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
  93. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
  94. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
  95. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
  96. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
  97. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
  98. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
  99. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
  100. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
  101. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
  102. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
  103. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
  104. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
  105. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
  106. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
  107. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
  108. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
  109. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
  110. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
  111. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
  112. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
  113. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
  114. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
  115. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
  116. // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
  117. { 0 }
  118. };
  119. MODULE_DEVICE_TABLE(pci, sky2_id_table);
  120. /* Avoid conditionals by using array */
  121. static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
  122. static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
  123. static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
  124. /* This driver supports yukon2 chipset only */
  125. static const char *yukon2_name[] = {
  126. "XL", /* 0xb3 */
  127. "EC Ultra", /* 0xb4 */
  128. "Extreme", /* 0xb5 */
  129. "EC", /* 0xb6 */
  130. "FE", /* 0xb7 */
  131. };
  132. /* Access to external PHY */
  133. static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
  134. {
  135. int i;
  136. gma_write16(hw, port, GM_SMI_DATA, val);
  137. gma_write16(hw, port, GM_SMI_CTRL,
  138. GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
  139. for (i = 0; i < PHY_RETRIES; i++) {
  140. if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
  141. return 0;
  142. udelay(1);
  143. }
  144. printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
  145. return -ETIMEDOUT;
  146. }
  147. static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
  148. {
  149. int i;
  150. gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
  151. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  152. for (i = 0; i < PHY_RETRIES; i++) {
  153. if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
  154. *val = gma_read16(hw, port, GM_SMI_DATA);
  155. return 0;
  156. }
  157. udelay(1);
  158. }
  159. return -ETIMEDOUT;
  160. }
  161. static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
  162. {
  163. u16 v;
  164. if (__gm_phy_read(hw, port, reg, &v) != 0)
  165. printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
  166. return v;
  167. }
  168. static void sky2_power_on(struct sky2_hw *hw)
  169. {
  170. /* switch power to VCC (WA for VAUX problem) */
  171. sky2_write8(hw, B0_POWER_CTRL,
  172. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  173. /* disable Core Clock Division, */
  174. sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
  175. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  176. /* enable bits are inverted */
  177. sky2_write8(hw, B2_Y2_CLK_GATE,
  178. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  179. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  180. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  181. else
  182. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  183. if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
  184. u32 reg1;
  185. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  186. reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
  187. reg1 &= P_ASPM_CONTROL_MSK;
  188. sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
  189. sky2_pci_write32(hw, PCI_DEV_REG5, 0);
  190. }
  191. }
  192. static void sky2_power_aux(struct sky2_hw *hw)
  193. {
  194. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  195. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  196. else
  197. /* enable bits are inverted */
  198. sky2_write8(hw, B2_Y2_CLK_GATE,
  199. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  200. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  201. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  202. /* switch power to VAUX */
  203. if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
  204. sky2_write8(hw, B0_POWER_CTRL,
  205. (PC_VAUX_ENA | PC_VCC_ENA |
  206. PC_VAUX_ON | PC_VCC_OFF));
  207. }
  208. static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
  209. {
  210. u16 reg;
  211. /* disable all GMAC IRQ's */
  212. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  213. /* disable PHY IRQs */
  214. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  215. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  216. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  217. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  218. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  219. reg = gma_read16(hw, port, GM_RX_CTRL);
  220. reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
  221. gma_write16(hw, port, GM_RX_CTRL, reg);
  222. }
  223. /* flow control to advertise bits */
  224. static const u16 copper_fc_adv[] = {
  225. [FC_NONE] = 0,
  226. [FC_TX] = PHY_M_AN_ASP,
  227. [FC_RX] = PHY_M_AN_PC,
  228. [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
  229. };
  230. /* flow control to advertise bits when using 1000BaseX */
  231. static const u16 fiber_fc_adv[] = {
  232. [FC_BOTH] = PHY_M_P_BOTH_MD_X,
  233. [FC_TX] = PHY_M_P_ASYM_MD_X,
  234. [FC_RX] = PHY_M_P_SYM_MD_X,
  235. [FC_NONE] = PHY_M_P_NO_PAUSE_X,
  236. };
  237. /* flow control to GMA disable bits */
  238. static const u16 gm_fc_disable[] = {
  239. [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
  240. [FC_TX] = GM_GPCR_FC_RX_DIS,
  241. [FC_RX] = GM_GPCR_FC_TX_DIS,
  242. [FC_BOTH] = 0,
  243. };
  244. static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
  245. {
  246. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  247. u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
  248. if (sky2->autoneg == AUTONEG_ENABLE
  249. && !(hw->chip_id == CHIP_ID_YUKON_XL
  250. || hw->chip_id == CHIP_ID_YUKON_EC_U
  251. || hw->chip_id == CHIP_ID_YUKON_EX)) {
  252. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  253. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  254. PHY_M_EC_MAC_S_MSK);
  255. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  256. if (hw->chip_id == CHIP_ID_YUKON_EC)
  257. ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
  258. else
  259. ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
  260. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  261. }
  262. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  263. if (sky2_is_copper(hw)) {
  264. if (hw->chip_id == CHIP_ID_YUKON_FE) {
  265. /* enable automatic crossover */
  266. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
  267. } else {
  268. /* disable energy detect */
  269. ctrl &= ~PHY_M_PC_EN_DET_MSK;
  270. /* enable automatic crossover */
  271. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
  272. if (sky2->autoneg == AUTONEG_ENABLE
  273. && (hw->chip_id == CHIP_ID_YUKON_XL
  274. || hw->chip_id == CHIP_ID_YUKON_EC_U
  275. || hw->chip_id == CHIP_ID_YUKON_EX)) {
  276. ctrl &= ~PHY_M_PC_DSC_MSK;
  277. ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
  278. }
  279. }
  280. } else {
  281. /* workaround for deviation #4.88 (CRC errors) */
  282. /* disable Automatic Crossover */
  283. ctrl &= ~PHY_M_PC_MDIX_MSK;
  284. }
  285. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  286. /* special setup for PHY 88E1112 Fiber */
  287. if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
  288. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  289. /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
  290. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  291. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  292. ctrl &= ~PHY_M_MAC_MD_MSK;
  293. ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
  294. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  295. if (hw->pmd_type == 'P') {
  296. /* select page 1 to access Fiber registers */
  297. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
  298. /* for SFP-module set SIGDET polarity to low */
  299. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  300. ctrl |= PHY_M_FIB_SIGD_POL;
  301. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  302. }
  303. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  304. }
  305. ctrl = PHY_CT_RESET;
  306. ct1000 = 0;
  307. adv = PHY_AN_CSMA;
  308. reg = 0;
  309. if (sky2->autoneg == AUTONEG_ENABLE) {
  310. if (sky2_is_copper(hw)) {
  311. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  312. ct1000 |= PHY_M_1000C_AFD;
  313. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  314. ct1000 |= PHY_M_1000C_AHD;
  315. if (sky2->advertising & ADVERTISED_100baseT_Full)
  316. adv |= PHY_M_AN_100_FD;
  317. if (sky2->advertising & ADVERTISED_100baseT_Half)
  318. adv |= PHY_M_AN_100_HD;
  319. if (sky2->advertising & ADVERTISED_10baseT_Full)
  320. adv |= PHY_M_AN_10_FD;
  321. if (sky2->advertising & ADVERTISED_10baseT_Half)
  322. adv |= PHY_M_AN_10_HD;
  323. adv |= copper_fc_adv[sky2->flow_mode];
  324. } else { /* special defines for FIBER (88E1040S only) */
  325. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  326. adv |= PHY_M_AN_1000X_AFD;
  327. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  328. adv |= PHY_M_AN_1000X_AHD;
  329. adv |= fiber_fc_adv[sky2->flow_mode];
  330. }
  331. /* Restart Auto-negotiation */
  332. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  333. } else {
  334. /* forced speed/duplex settings */
  335. ct1000 = PHY_M_1000C_MSE;
  336. /* Disable auto update for duplex flow control and speed */
  337. reg |= GM_GPCR_AU_ALL_DIS;
  338. switch (sky2->speed) {
  339. case SPEED_1000:
  340. ctrl |= PHY_CT_SP1000;
  341. reg |= GM_GPCR_SPEED_1000;
  342. break;
  343. case SPEED_100:
  344. ctrl |= PHY_CT_SP100;
  345. reg |= GM_GPCR_SPEED_100;
  346. break;
  347. }
  348. if (sky2->duplex == DUPLEX_FULL) {
  349. reg |= GM_GPCR_DUP_FULL;
  350. ctrl |= PHY_CT_DUP_MD;
  351. } else if (sky2->speed < SPEED_1000)
  352. sky2->flow_mode = FC_NONE;
  353. reg |= gm_fc_disable[sky2->flow_mode];
  354. /* Forward pause packets to GMAC? */
  355. if (sky2->flow_mode & FC_RX)
  356. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  357. else
  358. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  359. }
  360. gma_write16(hw, port, GM_GP_CTRL, reg);
  361. if (hw->chip_id != CHIP_ID_YUKON_FE)
  362. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  363. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  364. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  365. /* Setup Phy LED's */
  366. ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
  367. ledover = 0;
  368. switch (hw->chip_id) {
  369. case CHIP_ID_YUKON_FE:
  370. /* on 88E3082 these bits are at 11..9 (shifted left) */
  371. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
  372. ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
  373. /* delete ACT LED control bits */
  374. ctrl &= ~PHY_M_FELP_LED1_MSK;
  375. /* change ACT LED control to blink mode */
  376. ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
  377. gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
  378. break;
  379. case CHIP_ID_YUKON_XL:
  380. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  381. /* select page 3 to access LED control register */
  382. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  383. /* set LED Function Control register */
  384. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  385. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  386. PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
  387. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  388. PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
  389. /* set Polarity Control register */
  390. gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
  391. (PHY_M_POLC_LS1_P_MIX(4) |
  392. PHY_M_POLC_IS0_P_MIX(4) |
  393. PHY_M_POLC_LOS_CTRL(2) |
  394. PHY_M_POLC_INIT_CTRL(2) |
  395. PHY_M_POLC_STA1_CTRL(2) |
  396. PHY_M_POLC_STA0_CTRL(2)));
  397. /* restore page register */
  398. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  399. break;
  400. case CHIP_ID_YUKON_EC_U:
  401. case CHIP_ID_YUKON_EX:
  402. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  403. /* select page 3 to access LED control register */
  404. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  405. /* set LED Function Control register */
  406. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  407. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  408. PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
  409. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  410. PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
  411. /* set Blink Rate in LED Timer Control Register */
  412. gm_phy_write(hw, port, PHY_MARV_INT_MASK,
  413. ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
  414. /* restore page register */
  415. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  416. break;
  417. default:
  418. /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
  419. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
  420. /* turn off the Rx LED (LED_RX) */
  421. ledover &= ~PHY_M_LED_MO_RX;
  422. }
  423. if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
  424. hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
  425. /* apply fixes in PHY AFE */
  426. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
  427. /* increase differential signal amplitude in 10BASE-T */
  428. gm_phy_write(hw, port, 0x18, 0xaa99);
  429. gm_phy_write(hw, port, 0x17, 0x2011);
  430. /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
  431. gm_phy_write(hw, port, 0x18, 0xa204);
  432. gm_phy_write(hw, port, 0x17, 0x2002);
  433. /* set page register to 0 */
  434. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  435. } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
  436. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  437. if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
  438. /* turn on 100 Mbps LED (LED_LINK100) */
  439. ledover |= PHY_M_LED_MO_100;
  440. }
  441. if (ledover)
  442. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  443. }
  444. /* Enable phy interrupt on auto-negotiation complete (or link up) */
  445. if (sky2->autoneg == AUTONEG_ENABLE)
  446. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
  447. else
  448. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  449. }
  450. static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
  451. {
  452. u32 reg1;
  453. static const u32 phy_power[]
  454. = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
  455. /* looks like this XL is back asswards .. */
  456. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  457. onoff = !onoff;
  458. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  459. reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
  460. if (onoff)
  461. /* Turn off phy power saving */
  462. reg1 &= ~phy_power[port];
  463. else
  464. reg1 |= phy_power[port];
  465. sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
  466. sky2_pci_read32(hw, PCI_DEV_REG1);
  467. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  468. udelay(100);
  469. }
  470. /* Force a renegotiation */
  471. static void sky2_phy_reinit(struct sky2_port *sky2)
  472. {
  473. spin_lock_bh(&sky2->phy_lock);
  474. sky2_phy_init(sky2->hw, sky2->port);
  475. spin_unlock_bh(&sky2->phy_lock);
  476. }
  477. /* Put device in state to listen for Wake On Lan */
  478. static void sky2_wol_init(struct sky2_port *sky2)
  479. {
  480. struct sky2_hw *hw = sky2->hw;
  481. unsigned port = sky2->port;
  482. enum flow_control save_mode;
  483. u16 ctrl;
  484. u32 reg1;
  485. /* Bring hardware out of reset */
  486. sky2_write16(hw, B0_CTST, CS_RST_CLR);
  487. sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
  488. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  489. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  490. /* Force to 10/100
  491. * sky2_reset will re-enable on resume
  492. */
  493. save_mode = sky2->flow_mode;
  494. ctrl = sky2->advertising;
  495. sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
  496. sky2->flow_mode = FC_NONE;
  497. sky2_phy_power(hw, port, 1);
  498. sky2_phy_reinit(sky2);
  499. sky2->flow_mode = save_mode;
  500. sky2->advertising = ctrl;
  501. /* Set GMAC to no flow control and auto update for speed/duplex */
  502. gma_write16(hw, port, GM_GP_CTRL,
  503. GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
  504. GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
  505. /* Set WOL address */
  506. memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
  507. sky2->netdev->dev_addr, ETH_ALEN);
  508. /* Turn on appropriate WOL control bits */
  509. sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
  510. ctrl = 0;
  511. if (sky2->wol & WAKE_PHY)
  512. ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
  513. else
  514. ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
  515. if (sky2->wol & WAKE_MAGIC)
  516. ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
  517. else
  518. ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
  519. ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
  520. sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
  521. /* Turn on legacy PCI-Express PME mode */
  522. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  523. reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
  524. reg1 |= PCI_Y2_PME_LEGACY;
  525. sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
  526. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  527. /* block receiver */
  528. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  529. }
  530. static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
  531. {
  532. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  533. u16 reg;
  534. int i;
  535. const u8 *addr = hw->dev[port]->dev_addr;
  536. sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  537. sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
  538. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  539. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
  540. /* WA DEV_472 -- looks like crossed wires on port 2 */
  541. /* clear GMAC 1 Control reset */
  542. sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
  543. do {
  544. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
  545. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
  546. } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
  547. gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
  548. gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
  549. }
  550. sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  551. /* Enable Transmit FIFO Underrun */
  552. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  553. spin_lock_bh(&sky2->phy_lock);
  554. sky2_phy_init(hw, port);
  555. spin_unlock_bh(&sky2->phy_lock);
  556. /* MIB clear */
  557. reg = gma_read16(hw, port, GM_PHY_ADDR);
  558. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  559. for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
  560. gma_read16(hw, port, i);
  561. gma_write16(hw, port, GM_PHY_ADDR, reg);
  562. /* transmit control */
  563. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  564. /* receive control reg: unicast + multicast + no FCS */
  565. gma_write16(hw, port, GM_RX_CTRL,
  566. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  567. /* transmit flow control */
  568. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  569. /* transmit parameter */
  570. gma_write16(hw, port, GM_TX_PARAM,
  571. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  572. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  573. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
  574. TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
  575. /* serial mode register */
  576. reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  577. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  578. if (hw->dev[port]->mtu > ETH_DATA_LEN)
  579. reg |= GM_SMOD_JUMBO_ENA;
  580. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  581. /* virtual address for data */
  582. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  583. /* physical address: used for pause frames */
  584. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  585. /* ignore counter overflows */
  586. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  587. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  588. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  589. /* Configure Rx MAC FIFO */
  590. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  591. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
  592. GMF_OPER_ON | GMF_RX_F_FL_ON);
  593. /* Flush Rx MAC FIFO on any flow control or error */
  594. sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
  595. /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
  596. sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
  597. /* Configure Tx MAC FIFO */
  598. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  599. sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  600. if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
  601. sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
  602. sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
  603. /* set Tx GMAC FIFO Almost Empty Threshold */
  604. sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
  605. (ECU_JUMBO_WM << 16) | ECU_AE_THR);
  606. if (hw->dev[port]->mtu > ETH_DATA_LEN)
  607. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  608. TX_JUMBO_ENA | TX_STFW_DIS);
  609. else
  610. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  611. TX_JUMBO_DIS | TX_STFW_ENA);
  612. }
  613. }
  614. /* Assign Ram Buffer allocation to queue */
  615. static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
  616. {
  617. u32 end;
  618. /* convert from K bytes to qwords used for hw register */
  619. start *= 1024/8;
  620. space *= 1024/8;
  621. end = start + space - 1;
  622. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  623. sky2_write32(hw, RB_ADDR(q, RB_START), start);
  624. sky2_write32(hw, RB_ADDR(q, RB_END), end);
  625. sky2_write32(hw, RB_ADDR(q, RB_WP), start);
  626. sky2_write32(hw, RB_ADDR(q, RB_RP), start);
  627. if (q == Q_R1 || q == Q_R2) {
  628. u32 tp = space - space/4;
  629. /* On receive queue's set the thresholds
  630. * give receiver priority when > 3/4 full
  631. * send pause when down to 2K
  632. */
  633. sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
  634. sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
  635. tp = space - 2048/8;
  636. sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
  637. sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
  638. } else {
  639. /* Enable store & forward on Tx queue's because
  640. * Tx FIFO is only 1K on Yukon
  641. */
  642. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  643. }
  644. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  645. sky2_read8(hw, RB_ADDR(q, RB_CTRL));
  646. }
  647. /* Setup Bus Memory Interface */
  648. static void sky2_qset(struct sky2_hw *hw, u16 q)
  649. {
  650. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
  651. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
  652. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
  653. sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
  654. }
  655. /* Setup prefetch unit registers. This is the interface between
  656. * hardware and driver list elements
  657. */
  658. static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
  659. u64 addr, u32 last)
  660. {
  661. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  662. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
  663. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
  664. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
  665. sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
  666. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
  667. sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
  668. }
  669. static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
  670. {
  671. struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
  672. sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
  673. le->ctrl = 0;
  674. return le;
  675. }
  676. static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
  677. struct sky2_tx_le *le)
  678. {
  679. return sky2->tx_ring + (le - sky2->tx_le);
  680. }
  681. /* Update chip's next pointer */
  682. static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
  683. {
  684. q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
  685. wmb();
  686. sky2_write16(hw, q, idx);
  687. sky2_read16(hw, q);
  688. }
  689. static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
  690. {
  691. struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
  692. sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
  693. le->ctrl = 0;
  694. return le;
  695. }
  696. /* Return high part of DMA address (could be 32 or 64 bit) */
  697. static inline u32 high32(dma_addr_t a)
  698. {
  699. return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
  700. }
  701. /* Build description to hardware for one receive segment */
  702. static void sky2_rx_add(struct sky2_port *sky2, u8 op,
  703. dma_addr_t map, unsigned len)
  704. {
  705. struct sky2_rx_le *le;
  706. u32 hi = high32(map);
  707. if (sky2->rx_addr64 != hi) {
  708. le = sky2_next_rx(sky2);
  709. le->addr = cpu_to_le32(hi);
  710. le->opcode = OP_ADDR64 | HW_OWNER;
  711. sky2->rx_addr64 = high32(map + len);
  712. }
  713. le = sky2_next_rx(sky2);
  714. le->addr = cpu_to_le32((u32) map);
  715. le->length = cpu_to_le16(len);
  716. le->opcode = op | HW_OWNER;
  717. }
  718. /* Build description to hardware for one possibly fragmented skb */
  719. static void sky2_rx_submit(struct sky2_port *sky2,
  720. const struct rx_ring_info *re)
  721. {
  722. int i;
  723. sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
  724. for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
  725. sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
  726. }
  727. static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
  728. unsigned size)
  729. {
  730. struct sk_buff *skb = re->skb;
  731. int i;
  732. re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
  733. pci_unmap_len_set(re, data_size, size);
  734. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
  735. re->frag_addr[i] = pci_map_page(pdev,
  736. skb_shinfo(skb)->frags[i].page,
  737. skb_shinfo(skb)->frags[i].page_offset,
  738. skb_shinfo(skb)->frags[i].size,
  739. PCI_DMA_FROMDEVICE);
  740. }
  741. static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
  742. {
  743. struct sk_buff *skb = re->skb;
  744. int i;
  745. pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
  746. PCI_DMA_FROMDEVICE);
  747. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
  748. pci_unmap_page(pdev, re->frag_addr[i],
  749. skb_shinfo(skb)->frags[i].size,
  750. PCI_DMA_FROMDEVICE);
  751. }
  752. /* Tell chip where to start receive checksum.
  753. * Actually has two checksums, but set both same to avoid possible byte
  754. * order problems.
  755. */
  756. static void rx_set_checksum(struct sky2_port *sky2)
  757. {
  758. struct sky2_rx_le *le;
  759. le = sky2_next_rx(sky2);
  760. le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
  761. le->ctrl = 0;
  762. le->opcode = OP_TCPSTART | HW_OWNER;
  763. sky2_write32(sky2->hw,
  764. Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  765. sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  766. }
  767. /*
  768. * The RX Stop command will not work for Yukon-2 if the BMU does not
  769. * reach the end of packet and since we can't make sure that we have
  770. * incoming data, we must reset the BMU while it is not doing a DMA
  771. * transfer. Since it is possible that the RX path is still active,
  772. * the RX RAM buffer will be stopped first, so any possible incoming
  773. * data will not trigger a DMA. After the RAM buffer is stopped, the
  774. * BMU is polled until any DMA in progress is ended and only then it
  775. * will be reset.
  776. */
  777. static void sky2_rx_stop(struct sky2_port *sky2)
  778. {
  779. struct sky2_hw *hw = sky2->hw;
  780. unsigned rxq = rxqaddr[sky2->port];
  781. int i;
  782. /* disable the RAM Buffer receive queue */
  783. sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
  784. for (i = 0; i < 0xffff; i++)
  785. if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
  786. == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
  787. goto stopped;
  788. printk(KERN_WARNING PFX "%s: receiver stop failed\n",
  789. sky2->netdev->name);
  790. stopped:
  791. sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
  792. /* reset the Rx prefetch unit */
  793. sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  794. }
  795. /* Clean out receive buffer area, assumes receiver hardware stopped */
  796. static void sky2_rx_clean(struct sky2_port *sky2)
  797. {
  798. unsigned i;
  799. memset(sky2->rx_le, 0, RX_LE_BYTES);
  800. for (i = 0; i < sky2->rx_pending; i++) {
  801. struct rx_ring_info *re = sky2->rx_ring + i;
  802. if (re->skb) {
  803. sky2_rx_unmap_skb(sky2->hw->pdev, re);
  804. kfree_skb(re->skb);
  805. re->skb = NULL;
  806. }
  807. }
  808. }
  809. /* Basic MII support */
  810. static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  811. {
  812. struct mii_ioctl_data *data = if_mii(ifr);
  813. struct sky2_port *sky2 = netdev_priv(dev);
  814. struct sky2_hw *hw = sky2->hw;
  815. int err = -EOPNOTSUPP;
  816. if (!netif_running(dev))
  817. return -ENODEV; /* Phy still in reset */
  818. switch (cmd) {
  819. case SIOCGMIIPHY:
  820. data->phy_id = PHY_ADDR_MARV;
  821. /* fallthru */
  822. case SIOCGMIIREG: {
  823. u16 val = 0;
  824. spin_lock_bh(&sky2->phy_lock);
  825. err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
  826. spin_unlock_bh(&sky2->phy_lock);
  827. data->val_out = val;
  828. break;
  829. }
  830. case SIOCSMIIREG:
  831. if (!capable(CAP_NET_ADMIN))
  832. return -EPERM;
  833. spin_lock_bh(&sky2->phy_lock);
  834. err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
  835. data->val_in);
  836. spin_unlock_bh(&sky2->phy_lock);
  837. break;
  838. }
  839. return err;
  840. }
  841. #ifdef SKY2_VLAN_TAG_USED
  842. static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  843. {
  844. struct sky2_port *sky2 = netdev_priv(dev);
  845. struct sky2_hw *hw = sky2->hw;
  846. u16 port = sky2->port;
  847. netif_tx_lock_bh(dev);
  848. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
  849. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
  850. sky2->vlgrp = grp;
  851. netif_tx_unlock_bh(dev);
  852. }
  853. static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  854. {
  855. struct sky2_port *sky2 = netdev_priv(dev);
  856. struct sky2_hw *hw = sky2->hw;
  857. u16 port = sky2->port;
  858. netif_tx_lock_bh(dev);
  859. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
  860. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
  861. vlan_group_set_device(sky2->vlgrp, vid, NULL);
  862. netif_tx_unlock_bh(dev);
  863. }
  864. #endif
  865. /*
  866. * Allocate an skb for receiving. If the MTU is large enough
  867. * make the skb non-linear with a fragment list of pages.
  868. *
  869. * It appears the hardware has a bug in the FIFO logic that
  870. * cause it to hang if the FIFO gets overrun and the receive buffer
  871. * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
  872. * aligned except if slab debugging is enabled.
  873. */
  874. static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
  875. {
  876. struct sk_buff *skb;
  877. unsigned long p;
  878. int i;
  879. skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
  880. if (!skb)
  881. goto nomem;
  882. p = (unsigned long) skb->data;
  883. skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
  884. for (i = 0; i < sky2->rx_nfrags; i++) {
  885. struct page *page = alloc_page(GFP_ATOMIC);
  886. if (!page)
  887. goto free_partial;
  888. skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
  889. }
  890. return skb;
  891. free_partial:
  892. kfree_skb(skb);
  893. nomem:
  894. return NULL;
  895. }
  896. /*
  897. * Allocate and setup receiver buffer pool.
  898. * Normal case this ends up creating one list element for skb
  899. * in the receive ring. Worst case if using large MTU and each
  900. * allocation falls on a different 64 bit region, that results
  901. * in 6 list elements per ring entry.
  902. * One element is used for checksum enable/disable, and one
  903. * extra to avoid wrap.
  904. */
  905. static int sky2_rx_start(struct sky2_port *sky2)
  906. {
  907. struct sky2_hw *hw = sky2->hw;
  908. struct rx_ring_info *re;
  909. unsigned rxq = rxqaddr[sky2->port];
  910. unsigned i, size, space, thresh;
  911. sky2->rx_put = sky2->rx_next = 0;
  912. sky2_qset(hw, rxq);
  913. /* On PCI express lowering the watermark gives better performance */
  914. if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
  915. sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
  916. /* These chips have no ram buffer?
  917. * MAC Rx RAM Read is controlled by hardware */
  918. if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
  919. (hw->chip_rev == CHIP_REV_YU_EC_U_A1
  920. || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
  921. sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
  922. sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
  923. rx_set_checksum(sky2);
  924. /* Space needed for frame data + headers rounded up */
  925. size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
  926. + 8;
  927. /* Stopping point for hardware truncation */
  928. thresh = (size - 8) / sizeof(u32);
  929. /* Account for overhead of skb - to avoid order > 0 allocation */
  930. space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
  931. + sizeof(struct skb_shared_info);
  932. sky2->rx_nfrags = space >> PAGE_SHIFT;
  933. BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
  934. if (sky2->rx_nfrags != 0) {
  935. /* Compute residue after pages */
  936. space = sky2->rx_nfrags << PAGE_SHIFT;
  937. if (space < size)
  938. size -= space;
  939. else
  940. size = 0;
  941. /* Optimize to handle small packets and headers */
  942. if (size < copybreak)
  943. size = copybreak;
  944. if (size < ETH_HLEN)
  945. size = ETH_HLEN;
  946. }
  947. sky2->rx_data_size = size;
  948. /* Fill Rx ring */
  949. for (i = 0; i < sky2->rx_pending; i++) {
  950. re = sky2->rx_ring + i;
  951. re->skb = sky2_rx_alloc(sky2);
  952. if (!re->skb)
  953. goto nomem;
  954. sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
  955. sky2_rx_submit(sky2, re);
  956. }
  957. /*
  958. * The receiver hangs if it receives frames larger than the
  959. * packet buffer. As a workaround, truncate oversize frames, but
  960. * the register is limited to 9 bits, so if you do frames > 2052
  961. * you better get the MTU right!
  962. */
  963. if (thresh > 0x1ff)
  964. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
  965. else {
  966. sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
  967. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
  968. }
  969. /* Tell chip about available buffers */
  970. sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
  971. return 0;
  972. nomem:
  973. sky2_rx_clean(sky2);
  974. return -ENOMEM;
  975. }
  976. /* Bring up network interface. */
  977. static int sky2_up(struct net_device *dev)
  978. {
  979. struct sky2_port *sky2 = netdev_priv(dev);
  980. struct sky2_hw *hw = sky2->hw;
  981. unsigned port = sky2->port;
  982. u32 ramsize, imask;
  983. int cap, err = -ENOMEM;
  984. struct net_device *otherdev = hw->dev[sky2->port^1];
  985. /*
  986. * On dual port PCI-X card, there is an problem where status
  987. * can be received out of order due to split transactions
  988. */
  989. if (otherdev && netif_running(otherdev) &&
  990. (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
  991. struct sky2_port *osky2 = netdev_priv(otherdev);
  992. u16 cmd;
  993. cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
  994. cmd &= ~PCI_X_CMD_MAX_SPLIT;
  995. sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
  996. sky2->rx_csum = 0;
  997. osky2->rx_csum = 0;
  998. }
  999. if (netif_msg_ifup(sky2))
  1000. printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
  1001. /* must be power of 2 */
  1002. sky2->tx_le = pci_alloc_consistent(hw->pdev,
  1003. TX_RING_SIZE *
  1004. sizeof(struct sky2_tx_le),
  1005. &sky2->tx_le_map);
  1006. if (!sky2->tx_le)
  1007. goto err_out;
  1008. sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
  1009. GFP_KERNEL);
  1010. if (!sky2->tx_ring)
  1011. goto err_out;
  1012. sky2->tx_prod = sky2->tx_cons = 0;
  1013. sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
  1014. &sky2->rx_le_map);
  1015. if (!sky2->rx_le)
  1016. goto err_out;
  1017. memset(sky2->rx_le, 0, RX_LE_BYTES);
  1018. sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
  1019. GFP_KERNEL);
  1020. if (!sky2->rx_ring)
  1021. goto err_out;
  1022. sky2_phy_power(hw, port, 1);
  1023. sky2_mac_init(hw, port);
  1024. /* Register is number of 4K blocks on internal RAM buffer. */
  1025. ramsize = sky2_read8(hw, B2_E_0) * 4;
  1026. printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
  1027. if (ramsize > 0) {
  1028. u32 rxspace;
  1029. if (ramsize < 16)
  1030. rxspace = ramsize / 2;
  1031. else
  1032. rxspace = 8 + (2*(ramsize - 16))/3;
  1033. sky2_ramset(hw, rxqaddr[port], 0, rxspace);
  1034. sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
  1035. /* Make sure SyncQ is disabled */
  1036. sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
  1037. RB_RST_SET);
  1038. }
  1039. sky2_qset(hw, txqaddr[port]);
  1040. /* Set almost empty threshold */
  1041. if (hw->chip_id == CHIP_ID_YUKON_EC_U
  1042. && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
  1043. sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
  1044. sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
  1045. TX_RING_SIZE - 1);
  1046. err = sky2_rx_start(sky2);
  1047. if (err)
  1048. goto err_out;
  1049. /* Enable interrupts from phy/mac for port */
  1050. imask = sky2_read32(hw, B0_IMSK);
  1051. imask |= portirq_msk[port];
  1052. sky2_write32(hw, B0_IMSK, imask);
  1053. return 0;
  1054. err_out:
  1055. if (sky2->rx_le) {
  1056. pci_free_consistent(hw->pdev, RX_LE_BYTES,
  1057. sky2->rx_le, sky2->rx_le_map);
  1058. sky2->rx_le = NULL;
  1059. }
  1060. if (sky2->tx_le) {
  1061. pci_free_consistent(hw->pdev,
  1062. TX_RING_SIZE * sizeof(struct sky2_tx_le),
  1063. sky2->tx_le, sky2->tx_le_map);
  1064. sky2->tx_le = NULL;
  1065. }
  1066. kfree(sky2->tx_ring);
  1067. kfree(sky2->rx_ring);
  1068. sky2->tx_ring = NULL;
  1069. sky2->rx_ring = NULL;
  1070. return err;
  1071. }
  1072. /* Modular subtraction in ring */
  1073. static inline int tx_dist(unsigned tail, unsigned head)
  1074. {
  1075. return (head - tail) & (TX_RING_SIZE - 1);
  1076. }
  1077. /* Number of list elements available for next tx */
  1078. static inline int tx_avail(const struct sky2_port *sky2)
  1079. {
  1080. return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
  1081. }
  1082. /* Estimate of number of transmit list elements required */
  1083. static unsigned tx_le_req(const struct sk_buff *skb)
  1084. {
  1085. unsigned count;
  1086. count = sizeof(dma_addr_t) / sizeof(u32);
  1087. count += skb_shinfo(skb)->nr_frags * count;
  1088. if (skb_is_gso(skb))
  1089. ++count;
  1090. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1091. ++count;
  1092. return count;
  1093. }
  1094. /*
  1095. * Put one packet in ring for transmit.
  1096. * A single packet can generate multiple list elements, and
  1097. * the number of ring elements will probably be less than the number
  1098. * of list elements used.
  1099. */
  1100. static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
  1101. {
  1102. struct sky2_port *sky2 = netdev_priv(dev);
  1103. struct sky2_hw *hw = sky2->hw;
  1104. struct sky2_tx_le *le = NULL;
  1105. struct tx_ring_info *re;
  1106. unsigned i, len;
  1107. dma_addr_t mapping;
  1108. u32 addr64;
  1109. u16 mss;
  1110. u8 ctrl;
  1111. if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
  1112. return NETDEV_TX_BUSY;
  1113. if (unlikely(netif_msg_tx_queued(sky2)))
  1114. printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
  1115. dev->name, sky2->tx_prod, skb->len);
  1116. len = skb_headlen(skb);
  1117. mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
  1118. addr64 = high32(mapping);
  1119. /* Send high bits if changed or crosses boundary */
  1120. if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
  1121. le = get_tx_le(sky2);
  1122. le->addr = cpu_to_le32(addr64);
  1123. le->opcode = OP_ADDR64 | HW_OWNER;
  1124. sky2->tx_addr64 = high32(mapping + len);
  1125. }
  1126. /* Check for TCP Segmentation Offload */
  1127. mss = skb_shinfo(skb)->gso_size;
  1128. if (mss != 0) {
  1129. mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
  1130. mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
  1131. mss += ETH_HLEN;
  1132. if (mss != sky2->tx_last_mss) {
  1133. le = get_tx_le(sky2);
  1134. le->addr = cpu_to_le32(mss);
  1135. le->opcode = OP_LRGLEN | HW_OWNER;
  1136. sky2->tx_last_mss = mss;
  1137. }
  1138. }
  1139. ctrl = 0;
  1140. #ifdef SKY2_VLAN_TAG_USED
  1141. /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
  1142. if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
  1143. if (!le) {
  1144. le = get_tx_le(sky2);
  1145. le->addr = 0;
  1146. le->opcode = OP_VLAN|HW_OWNER;
  1147. } else
  1148. le->opcode |= OP_VLAN;
  1149. le->length = cpu_to_be16(vlan_tx_tag_get(skb));
  1150. ctrl |= INS_VLAN;
  1151. }
  1152. #endif
  1153. /* Handle TCP checksum offload */
  1154. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1155. unsigned offset = skb->h.raw - skb->data;
  1156. u32 tcpsum;
  1157. tcpsum = offset << 16; /* sum start */
  1158. tcpsum |= offset + skb->csum_offset; /* sum write */
  1159. ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
  1160. if (skb->nh.iph->protocol == IPPROTO_UDP)
  1161. ctrl |= UDPTCP;
  1162. if (tcpsum != sky2->tx_tcpsum) {
  1163. sky2->tx_tcpsum = tcpsum;
  1164. le = get_tx_le(sky2);
  1165. le->addr = cpu_to_le32(tcpsum);
  1166. le->length = 0; /* initial checksum value */
  1167. le->ctrl = 1; /* one packet */
  1168. le->opcode = OP_TCPLISW | HW_OWNER;
  1169. }
  1170. }
  1171. le = get_tx_le(sky2);
  1172. le->addr = cpu_to_le32((u32) mapping);
  1173. le->length = cpu_to_le16(len);
  1174. le->ctrl = ctrl;
  1175. le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
  1176. re = tx_le_re(sky2, le);
  1177. re->skb = skb;
  1178. pci_unmap_addr_set(re, mapaddr, mapping);
  1179. pci_unmap_len_set(re, maplen, len);
  1180. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1181. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1182. mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
  1183. frag->size, PCI_DMA_TODEVICE);
  1184. addr64 = high32(mapping);
  1185. if (addr64 != sky2->tx_addr64) {
  1186. le = get_tx_le(sky2);
  1187. le->addr = cpu_to_le32(addr64);
  1188. le->ctrl = 0;
  1189. le->opcode = OP_ADDR64 | HW_OWNER;
  1190. sky2->tx_addr64 = addr64;
  1191. }
  1192. le = get_tx_le(sky2);
  1193. le->addr = cpu_to_le32((u32) mapping);
  1194. le->length = cpu_to_le16(frag->size);
  1195. le->ctrl = ctrl;
  1196. le->opcode = OP_BUFFER | HW_OWNER;
  1197. re = tx_le_re(sky2, le);
  1198. re->skb = skb;
  1199. pci_unmap_addr_set(re, mapaddr, mapping);
  1200. pci_unmap_len_set(re, maplen, frag->size);
  1201. }
  1202. le->ctrl |= EOP;
  1203. if (tx_avail(sky2) <= MAX_SKB_TX_LE)
  1204. netif_stop_queue(dev);
  1205. sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
  1206. dev->trans_start = jiffies;
  1207. return NETDEV_TX_OK;
  1208. }
  1209. /*
  1210. * Free ring elements from starting at tx_cons until "done"
  1211. *
  1212. * NB: the hardware will tell us about partial completion of multi-part
  1213. * buffers so make sure not to free skb to early.
  1214. */
  1215. static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
  1216. {
  1217. struct net_device *dev = sky2->netdev;
  1218. struct pci_dev *pdev = sky2->hw->pdev;
  1219. unsigned idx;
  1220. BUG_ON(done >= TX_RING_SIZE);
  1221. for (idx = sky2->tx_cons; idx != done;
  1222. idx = RING_NEXT(idx, TX_RING_SIZE)) {
  1223. struct sky2_tx_le *le = sky2->tx_le + idx;
  1224. struct tx_ring_info *re = sky2->tx_ring + idx;
  1225. switch(le->opcode & ~HW_OWNER) {
  1226. case OP_LARGESEND:
  1227. case OP_PACKET:
  1228. pci_unmap_single(pdev,
  1229. pci_unmap_addr(re, mapaddr),
  1230. pci_unmap_len(re, maplen),
  1231. PCI_DMA_TODEVICE);
  1232. break;
  1233. case OP_BUFFER:
  1234. pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
  1235. pci_unmap_len(re, maplen),
  1236. PCI_DMA_TODEVICE);
  1237. break;
  1238. }
  1239. if (le->ctrl & EOP) {
  1240. if (unlikely(netif_msg_tx_done(sky2)))
  1241. printk(KERN_DEBUG "%s: tx done %u\n",
  1242. dev->name, idx);
  1243. sky2->net_stats.tx_packets++;
  1244. sky2->net_stats.tx_bytes += re->skb->len;
  1245. dev_kfree_skb_any(re->skb);
  1246. }
  1247. le->opcode = 0; /* paranoia */
  1248. }
  1249. sky2->tx_cons = idx;
  1250. if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
  1251. netif_wake_queue(dev);
  1252. }
  1253. /* Cleanup all untransmitted buffers, assume transmitter not running */
  1254. static void sky2_tx_clean(struct net_device *dev)
  1255. {
  1256. struct sky2_port *sky2 = netdev_priv(dev);
  1257. netif_tx_lock_bh(dev);
  1258. sky2_tx_complete(sky2, sky2->tx_prod);
  1259. netif_tx_unlock_bh(dev);
  1260. }
  1261. /* Network shutdown */
  1262. static int sky2_down(struct net_device *dev)
  1263. {
  1264. struct sky2_port *sky2 = netdev_priv(dev);
  1265. struct sky2_hw *hw = sky2->hw;
  1266. unsigned port = sky2->port;
  1267. u16 ctrl;
  1268. u32 imask;
  1269. /* Never really got started! */
  1270. if (!sky2->tx_le)
  1271. return 0;
  1272. if (netif_msg_ifdown(sky2))
  1273. printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
  1274. /* Stop more packets from being queued */
  1275. netif_stop_queue(dev);
  1276. netif_carrier_off(dev);
  1277. /* Disable port IRQ */
  1278. imask = sky2_read32(hw, B0_IMSK);
  1279. imask &= ~portirq_msk[port];
  1280. sky2_write32(hw, B0_IMSK, imask);
  1281. /*
  1282. * Both ports share the NAPI poll on port 0, so if necessary undo the
  1283. * the disable that is done in dev_close.
  1284. */
  1285. if (sky2->port == 0 && hw->ports > 1)
  1286. netif_poll_enable(dev);
  1287. sky2_gmac_reset(hw, port);
  1288. /* Stop transmitter */
  1289. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
  1290. sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
  1291. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  1292. RB_RST_SET | RB_DIS_OP_MD);
  1293. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1294. ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
  1295. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1296. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1297. /* Workaround shared GMAC reset */
  1298. if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
  1299. && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
  1300. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1301. /* Disable Force Sync bit and Enable Alloc bit */
  1302. sky2_write8(hw, SK_REG(port, TXA_CTRL),
  1303. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  1304. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  1305. sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  1306. sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  1307. /* Reset the PCI FIFO of the async Tx queue */
  1308. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
  1309. BMU_RST_SET | BMU_FIFO_RST);
  1310. /* Reset the Tx prefetch units */
  1311. sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
  1312. PREF_UNIT_RST_SET);
  1313. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  1314. sky2_rx_stop(sky2);
  1315. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  1316. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  1317. sky2_phy_power(hw, port, 0);
  1318. /* turn off LED's */
  1319. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  1320. synchronize_irq(hw->pdev->irq);
  1321. sky2_tx_clean(dev);
  1322. sky2_rx_clean(sky2);
  1323. pci_free_consistent(hw->pdev, RX_LE_BYTES,
  1324. sky2->rx_le, sky2->rx_le_map);
  1325. kfree(sky2->rx_ring);
  1326. pci_free_consistent(hw->pdev,
  1327. TX_RING_SIZE * sizeof(struct sky2_tx_le),
  1328. sky2->tx_le, sky2->tx_le_map);
  1329. kfree(sky2->tx_ring);
  1330. sky2->tx_le = NULL;
  1331. sky2->rx_le = NULL;
  1332. sky2->rx_ring = NULL;
  1333. sky2->tx_ring = NULL;
  1334. return 0;
  1335. }
  1336. static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
  1337. {
  1338. if (!sky2_is_copper(hw))
  1339. return SPEED_1000;
  1340. if (hw->chip_id == CHIP_ID_YUKON_FE)
  1341. return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
  1342. switch (aux & PHY_M_PS_SPEED_MSK) {
  1343. case PHY_M_PS_SPEED_1000:
  1344. return SPEED_1000;
  1345. case PHY_M_PS_SPEED_100:
  1346. return SPEED_100;
  1347. default:
  1348. return SPEED_10;
  1349. }
  1350. }
  1351. static void sky2_link_up(struct sky2_port *sky2)
  1352. {
  1353. struct sky2_hw *hw = sky2->hw;
  1354. unsigned port = sky2->port;
  1355. u16 reg;
  1356. static const char *fc_name[] = {
  1357. [FC_NONE] = "none",
  1358. [FC_TX] = "tx",
  1359. [FC_RX] = "rx",
  1360. [FC_BOTH] = "both",
  1361. };
  1362. /* enable Rx/Tx */
  1363. reg = gma_read16(hw, port, GM_GP_CTRL);
  1364. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1365. gma_write16(hw, port, GM_GP_CTRL, reg);
  1366. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  1367. netif_carrier_on(sky2->netdev);
  1368. netif_wake_queue(sky2->netdev);
  1369. /* Turn on link LED */
  1370. sky2_write8(hw, SK_REG(port, LNK_LED_REG),
  1371. LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
  1372. if (hw->chip_id == CHIP_ID_YUKON_XL
  1373. || hw->chip_id == CHIP_ID_YUKON_EC_U
  1374. || hw->chip_id == CHIP_ID_YUKON_EX) {
  1375. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  1376. u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
  1377. switch(sky2->speed) {
  1378. case SPEED_10:
  1379. led |= PHY_M_LEDC_INIT_CTRL(7);
  1380. break;
  1381. case SPEED_100:
  1382. led |= PHY_M_LEDC_STA1_CTRL(7);
  1383. break;
  1384. case SPEED_1000:
  1385. led |= PHY_M_LEDC_STA0_CTRL(7);
  1386. break;
  1387. }
  1388. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  1389. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
  1390. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  1391. }
  1392. if (netif_msg_link(sky2))
  1393. printk(KERN_INFO PFX
  1394. "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
  1395. sky2->netdev->name, sky2->speed,
  1396. sky2->duplex == DUPLEX_FULL ? "full" : "half",
  1397. fc_name[sky2->flow_status]);
  1398. }
  1399. static void sky2_link_down(struct sky2_port *sky2)
  1400. {
  1401. struct sky2_hw *hw = sky2->hw;
  1402. unsigned port = sky2->port;
  1403. u16 reg;
  1404. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  1405. reg = gma_read16(hw, port, GM_GP_CTRL);
  1406. reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1407. gma_write16(hw, port, GM_GP_CTRL, reg);
  1408. netif_carrier_off(sky2->netdev);
  1409. netif_stop_queue(sky2->netdev);
  1410. /* Turn on link LED */
  1411. sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  1412. if (netif_msg_link(sky2))
  1413. printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
  1414. sky2_phy_init(hw, port);
  1415. }
  1416. static enum flow_control sky2_flow(int rx, int tx)
  1417. {
  1418. if (rx)
  1419. return tx ? FC_BOTH : FC_RX;
  1420. else
  1421. return tx ? FC_TX : FC_NONE;
  1422. }
  1423. static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
  1424. {
  1425. struct sky2_hw *hw = sky2->hw;
  1426. unsigned port = sky2->port;
  1427. u16 advert, lpa;
  1428. advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
  1429. lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
  1430. if (lpa & PHY_M_AN_RF) {
  1431. printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
  1432. return -1;
  1433. }
  1434. if (!(aux & PHY_M_PS_SPDUP_RES)) {
  1435. printk(KERN_ERR PFX "%s: speed/duplex mismatch",
  1436. sky2->netdev->name);
  1437. return -1;
  1438. }
  1439. sky2->speed = sky2_phy_speed(hw, aux);
  1440. sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1441. /* Since the pause result bits seem to in different positions on
  1442. * different chips. look at registers.
  1443. */
  1444. if (!sky2_is_copper(hw)) {
  1445. /* Shift for bits in fiber PHY */
  1446. advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
  1447. lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
  1448. if (advert & ADVERTISE_1000XPAUSE)
  1449. advert |= ADVERTISE_PAUSE_CAP;
  1450. if (advert & ADVERTISE_1000XPSE_ASYM)
  1451. advert |= ADVERTISE_PAUSE_ASYM;
  1452. if (lpa & LPA_1000XPAUSE)
  1453. lpa |= LPA_PAUSE_CAP;
  1454. if (lpa & LPA_1000XPAUSE_ASYM)
  1455. lpa |= LPA_PAUSE_ASYM;
  1456. }
  1457. sky2->flow_status = FC_NONE;
  1458. if (advert & ADVERTISE_PAUSE_CAP) {
  1459. if (lpa & LPA_PAUSE_CAP)
  1460. sky2->flow_status = FC_BOTH;
  1461. else if (advert & ADVERTISE_PAUSE_ASYM)
  1462. sky2->flow_status = FC_RX;
  1463. } else if (advert & ADVERTISE_PAUSE_ASYM) {
  1464. if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
  1465. sky2->flow_status = FC_TX;
  1466. }
  1467. if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
  1468. && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
  1469. sky2->flow_status = FC_NONE;
  1470. if (sky2->flow_status & FC_TX)
  1471. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1472. else
  1473. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1474. return 0;
  1475. }
  1476. /* Interrupt from PHY */
  1477. static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
  1478. {
  1479. struct net_device *dev = hw->dev[port];
  1480. struct sky2_port *sky2 = netdev_priv(dev);
  1481. u16 istatus, phystat;
  1482. if (!netif_running(dev))
  1483. return;
  1484. spin_lock(&sky2->phy_lock);
  1485. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1486. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1487. if (netif_msg_intr(sky2))
  1488. printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1489. sky2->netdev->name, istatus, phystat);
  1490. if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
  1491. if (sky2_autoneg_done(sky2, phystat) == 0)
  1492. sky2_link_up(sky2);
  1493. goto out;
  1494. }
  1495. if (istatus & PHY_M_IS_LSP_CHANGE)
  1496. sky2->speed = sky2_phy_speed(hw, phystat);
  1497. if (istatus & PHY_M_IS_DUP_CHANGE)
  1498. sky2->duplex =
  1499. (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1500. if (istatus & PHY_M_IS_LST_CHANGE) {
  1501. if (phystat & PHY_M_PS_LINK_UP)
  1502. sky2_link_up(sky2);
  1503. else
  1504. sky2_link_down(sky2);
  1505. }
  1506. out:
  1507. spin_unlock(&sky2->phy_lock);
  1508. }
  1509. /* Transmit timeout is only called if we are running, carrier is up
  1510. * and tx queue is full (stopped).
  1511. */
  1512. static void sky2_tx_timeout(struct net_device *dev)
  1513. {
  1514. struct sky2_port *sky2 = netdev_priv(dev);
  1515. struct sky2_hw *hw = sky2->hw;
  1516. if (netif_msg_timer(sky2))
  1517. printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
  1518. printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
  1519. dev->name, sky2->tx_cons, sky2->tx_prod,
  1520. sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
  1521. sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
  1522. /* can't restart safely under softirq */
  1523. schedule_work(&hw->restart_work);
  1524. }
  1525. static int sky2_change_mtu(struct net_device *dev, int new_mtu)
  1526. {
  1527. struct sky2_port *sky2 = netdev_priv(dev);
  1528. struct sky2_hw *hw = sky2->hw;
  1529. unsigned port = sky2->port;
  1530. int err;
  1531. u16 ctl, mode;
  1532. u32 imask;
  1533. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  1534. return -EINVAL;
  1535. if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
  1536. return -EINVAL;
  1537. if (!netif_running(dev)) {
  1538. dev->mtu = new_mtu;
  1539. return 0;
  1540. }
  1541. imask = sky2_read32(hw, B0_IMSK);
  1542. sky2_write32(hw, B0_IMSK, 0);
  1543. dev->trans_start = jiffies; /* prevent tx timeout */
  1544. netif_stop_queue(dev);
  1545. netif_poll_disable(hw->dev[0]);
  1546. synchronize_irq(hw->pdev->irq);
  1547. if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
  1548. if (new_mtu > ETH_DATA_LEN) {
  1549. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  1550. TX_JUMBO_ENA | TX_STFW_DIS);
  1551. dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
  1552. } else
  1553. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  1554. TX_JUMBO_DIS | TX_STFW_ENA);
  1555. }
  1556. ctl = gma_read16(hw, port, GM_GP_CTRL);
  1557. gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
  1558. sky2_rx_stop(sky2);
  1559. sky2_rx_clean(sky2);
  1560. dev->mtu = new_mtu;
  1561. mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  1562. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  1563. if (dev->mtu > ETH_DATA_LEN)
  1564. mode |= GM_SMOD_JUMBO_ENA;
  1565. gma_write16(hw, port, GM_SERIAL_MODE, mode);
  1566. sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
  1567. err = sky2_rx_start(sky2);
  1568. sky2_write32(hw, B0_IMSK, imask);
  1569. if (err)
  1570. dev_close(dev);
  1571. else {
  1572. gma_write16(hw, port, GM_GP_CTRL, ctl);
  1573. netif_poll_enable(hw->dev[0]);
  1574. netif_wake_queue(dev);
  1575. }
  1576. return err;
  1577. }
  1578. /* For small just reuse existing skb for next receive */
  1579. static struct sk_buff *receive_copy(struct sky2_port *sky2,
  1580. const struct rx_ring_info *re,
  1581. unsigned length)
  1582. {
  1583. struct sk_buff *skb;
  1584. skb = netdev_alloc_skb(sky2->netdev, length + 2);
  1585. if (likely(skb)) {
  1586. skb_reserve(skb, 2);
  1587. pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
  1588. length, PCI_DMA_FROMDEVICE);
  1589. memcpy(skb->data, re->skb->data, length);
  1590. skb->ip_summed = re->skb->ip_summed;
  1591. skb->csum = re->skb->csum;
  1592. pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
  1593. length, PCI_DMA_FROMDEVICE);
  1594. re->skb->ip_summed = CHECKSUM_NONE;
  1595. skb_put(skb, length);
  1596. }
  1597. return skb;
  1598. }
  1599. /* Adjust length of skb with fragments to match received data */
  1600. static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
  1601. unsigned int length)
  1602. {
  1603. int i, num_frags;
  1604. unsigned int size;
  1605. /* put header into skb */
  1606. size = min(length, hdr_space);
  1607. skb->tail += size;
  1608. skb->len += size;
  1609. length -= size;
  1610. num_frags = skb_shinfo(skb)->nr_frags;
  1611. for (i = 0; i < num_frags; i++) {
  1612. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1613. if (length == 0) {
  1614. /* don't need this page */
  1615. __free_page(frag->page);
  1616. --skb_shinfo(skb)->nr_frags;
  1617. } else {
  1618. size = min(length, (unsigned) PAGE_SIZE);
  1619. frag->size = size;
  1620. skb->data_len += size;
  1621. skb->truesize += size;
  1622. skb->len += size;
  1623. length -= size;
  1624. }
  1625. }
  1626. }
  1627. /* Normal packet - take skb from ring element and put in a new one */
  1628. static struct sk_buff *receive_new(struct sky2_port *sky2,
  1629. struct rx_ring_info *re,
  1630. unsigned int length)
  1631. {
  1632. struct sk_buff *skb, *nskb;
  1633. unsigned hdr_space = sky2->rx_data_size;
  1634. pr_debug(PFX "receive new length=%d\n", length);
  1635. /* Don't be tricky about reusing pages (yet) */
  1636. nskb = sky2_rx_alloc(sky2);
  1637. if (unlikely(!nskb))
  1638. return NULL;
  1639. skb = re->skb;
  1640. sky2_rx_unmap_skb(sky2->hw->pdev, re);
  1641. prefetch(skb->data);
  1642. re->skb = nskb;
  1643. sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
  1644. if (skb_shinfo(skb)->nr_frags)
  1645. skb_put_frags(skb, hdr_space, length);
  1646. else
  1647. skb_put(skb, length);
  1648. return skb;
  1649. }
  1650. /*
  1651. * Receive one packet.
  1652. * For larger packets, get new buffer.
  1653. */
  1654. static struct sk_buff *sky2_receive(struct net_device *dev,
  1655. u16 length, u32 status)
  1656. {
  1657. struct sky2_port *sky2 = netdev_priv(dev);
  1658. struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
  1659. struct sk_buff *skb = NULL;
  1660. if (unlikely(netif_msg_rx_status(sky2)))
  1661. printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
  1662. dev->name, sky2->rx_next, status, length);
  1663. sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
  1664. prefetch(sky2->rx_ring + sky2->rx_next);
  1665. if (status & GMR_FS_ANY_ERR)
  1666. goto error;
  1667. if (!(status & GMR_FS_RX_OK))
  1668. goto resubmit;
  1669. if (length < copybreak)
  1670. skb = receive_copy(sky2, re, length);
  1671. else
  1672. skb = receive_new(sky2, re, length);
  1673. resubmit:
  1674. sky2_rx_submit(sky2, re);
  1675. return skb;
  1676. error:
  1677. ++sky2->net_stats.rx_errors;
  1678. if (status & GMR_FS_RX_FF_OV) {
  1679. sky2->net_stats.rx_over_errors++;
  1680. goto resubmit;
  1681. }
  1682. if (netif_msg_rx_err(sky2) && net_ratelimit())
  1683. printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
  1684. dev->name, status, length);
  1685. if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
  1686. sky2->net_stats.rx_length_errors++;
  1687. if (status & GMR_FS_FRAGMENT)
  1688. sky2->net_stats.rx_frame_errors++;
  1689. if (status & GMR_FS_CRC_ERR)
  1690. sky2->net_stats.rx_crc_errors++;
  1691. goto resubmit;
  1692. }
  1693. /* Transmit complete */
  1694. static inline void sky2_tx_done(struct net_device *dev, u16 last)
  1695. {
  1696. struct sky2_port *sky2 = netdev_priv(dev);
  1697. if (netif_running(dev)) {
  1698. netif_tx_lock(dev);
  1699. sky2_tx_complete(sky2, last);
  1700. netif_tx_unlock(dev);
  1701. }
  1702. }
  1703. /* Process status response ring */
  1704. static int sky2_status_intr(struct sky2_hw *hw, int to_do)
  1705. {
  1706. struct sky2_port *sky2;
  1707. int work_done = 0;
  1708. unsigned buf_write[2] = { 0, 0 };
  1709. u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
  1710. rmb();
  1711. while (hw->st_idx != hwidx) {
  1712. struct sky2_status_le *le = hw->st_le + hw->st_idx;
  1713. struct net_device *dev;
  1714. struct sk_buff *skb;
  1715. u32 status;
  1716. u16 length;
  1717. hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
  1718. BUG_ON(le->link >= 2);
  1719. dev = hw->dev[le->link];
  1720. sky2 = netdev_priv(dev);
  1721. length = le16_to_cpu(le->length);
  1722. status = le32_to_cpu(le->status);
  1723. switch (le->opcode & ~HW_OWNER) {
  1724. case OP_RXSTAT:
  1725. skb = sky2_receive(dev, length, status);
  1726. if (!skb)
  1727. goto force_update;
  1728. skb->protocol = eth_type_trans(skb, dev);
  1729. sky2->net_stats.rx_packets++;
  1730. sky2->net_stats.rx_bytes += skb->len;
  1731. dev->last_rx = jiffies;
  1732. #ifdef SKY2_VLAN_TAG_USED
  1733. if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
  1734. vlan_hwaccel_receive_skb(skb,
  1735. sky2->vlgrp,
  1736. be16_to_cpu(sky2->rx_tag));
  1737. } else
  1738. #endif
  1739. netif_receive_skb(skb);
  1740. /* Update receiver after 16 frames */
  1741. if (++buf_write[le->link] == RX_BUF_WRITE) {
  1742. force_update:
  1743. sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
  1744. buf_write[le->link] = 0;
  1745. }
  1746. /* Stop after net poll weight */
  1747. if (++work_done >= to_do)
  1748. goto exit_loop;
  1749. break;
  1750. #ifdef SKY2_VLAN_TAG_USED
  1751. case OP_RXVLAN:
  1752. sky2->rx_tag = length;
  1753. break;
  1754. case OP_RXCHKSVLAN:
  1755. sky2->rx_tag = length;
  1756. /* fall through */
  1757. #endif
  1758. case OP_RXCHKS:
  1759. if (!sky2->rx_csum)
  1760. break;
  1761. /* Both checksum counters are programmed to start at
  1762. * the same offset, so unless there is a problem they
  1763. * should match. This failure is an early indication that
  1764. * hardware receive checksumming won't work.
  1765. */
  1766. if (likely(status >> 16 == (status & 0xffff))) {
  1767. skb = sky2->rx_ring[sky2->rx_next].skb;
  1768. skb->ip_summed = CHECKSUM_COMPLETE;
  1769. skb->csum = status & 0xffff;
  1770. } else {
  1771. printk(KERN_NOTICE PFX "%s: hardware receive "
  1772. "checksum problem (status = %#x)\n",
  1773. dev->name, status);
  1774. sky2->rx_csum = 0;
  1775. sky2_write32(sky2->hw,
  1776. Q_ADDR(rxqaddr[le->link], Q_CSR),
  1777. BMU_DIS_RX_CHKSUM);
  1778. }
  1779. break;
  1780. case OP_TXINDEXLE:
  1781. /* TX index reports status for both ports */
  1782. BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
  1783. sky2_tx_done(hw->dev[0], status & 0xfff);
  1784. if (hw->dev[1])
  1785. sky2_tx_done(hw->dev[1],
  1786. ((status >> 24) & 0xff)
  1787. | (u16)(length & 0xf) << 8);
  1788. break;
  1789. default:
  1790. if (net_ratelimit())
  1791. printk(KERN_WARNING PFX
  1792. "unknown status opcode 0x%x\n", le->opcode);
  1793. goto exit_loop;
  1794. }
  1795. }
  1796. /* Fully processed status ring so clear irq */
  1797. sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
  1798. exit_loop:
  1799. if (buf_write[0]) {
  1800. sky2 = netdev_priv(hw->dev[0]);
  1801. sky2_put_idx(hw, Q_R1, sky2->rx_put);
  1802. }
  1803. if (buf_write[1]) {
  1804. sky2 = netdev_priv(hw->dev[1]);
  1805. sky2_put_idx(hw, Q_R2, sky2->rx_put);
  1806. }
  1807. return work_done;
  1808. }
  1809. static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
  1810. {
  1811. struct net_device *dev = hw->dev[port];
  1812. if (net_ratelimit())
  1813. printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
  1814. dev->name, status);
  1815. if (status & Y2_IS_PAR_RD1) {
  1816. if (net_ratelimit())
  1817. printk(KERN_ERR PFX "%s: ram data read parity error\n",
  1818. dev->name);
  1819. /* Clear IRQ */
  1820. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
  1821. }
  1822. if (status & Y2_IS_PAR_WR1) {
  1823. if (net_ratelimit())
  1824. printk(KERN_ERR PFX "%s: ram data write parity error\n",
  1825. dev->name);
  1826. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
  1827. }
  1828. if (status & Y2_IS_PAR_MAC1) {
  1829. if (net_ratelimit())
  1830. printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
  1831. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
  1832. }
  1833. if (status & Y2_IS_PAR_RX1) {
  1834. if (net_ratelimit())
  1835. printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
  1836. sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
  1837. }
  1838. if (status & Y2_IS_TCP_TXA1) {
  1839. if (net_ratelimit())
  1840. printk(KERN_ERR PFX "%s: TCP segmentation error\n",
  1841. dev->name);
  1842. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
  1843. }
  1844. }
  1845. static void sky2_hw_intr(struct sky2_hw *hw)
  1846. {
  1847. u32 status = sky2_read32(hw, B0_HWE_ISRC);
  1848. if (status & Y2_IS_TIST_OV)
  1849. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  1850. if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
  1851. u16 pci_err;
  1852. pci_err = sky2_pci_read16(hw, PCI_STATUS);
  1853. if (net_ratelimit())
  1854. dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
  1855. pci_err);
  1856. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1857. sky2_pci_write16(hw, PCI_STATUS,
  1858. pci_err | PCI_STATUS_ERROR_BITS);
  1859. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1860. }
  1861. if (status & Y2_IS_PCI_EXP) {
  1862. /* PCI-Express uncorrectable Error occurred */
  1863. u32 pex_err;
  1864. pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
  1865. if (net_ratelimit())
  1866. dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
  1867. pex_err);
  1868. /* clear the interrupt */
  1869. sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1870. sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
  1871. 0xffffffffUL);
  1872. sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1873. if (pex_err & PEX_FATAL_ERRORS) {
  1874. u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
  1875. hwmsk &= ~Y2_IS_PCI_EXP;
  1876. sky2_write32(hw, B0_HWE_IMSK, hwmsk);
  1877. }
  1878. }
  1879. if (status & Y2_HWE_L1_MASK)
  1880. sky2_hw_error(hw, 0, status);
  1881. status >>= 8;
  1882. if (status & Y2_HWE_L1_MASK)
  1883. sky2_hw_error(hw, 1, status);
  1884. }
  1885. static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
  1886. {
  1887. struct net_device *dev = hw->dev[port];
  1888. struct sky2_port *sky2 = netdev_priv(dev);
  1889. u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  1890. if (netif_msg_intr(sky2))
  1891. printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
  1892. dev->name, status);
  1893. if (status & GM_IS_RX_FF_OR) {
  1894. ++sky2->net_stats.rx_fifo_errors;
  1895. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  1896. }
  1897. if (status & GM_IS_TX_FF_UR) {
  1898. ++sky2->net_stats.tx_fifo_errors;
  1899. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  1900. }
  1901. }
  1902. /* This should never happen it is a bug. */
  1903. static void sky2_le_error(struct sky2_hw *hw, unsigned port,
  1904. u16 q, unsigned ring_size)
  1905. {
  1906. struct net_device *dev = hw->dev[port];
  1907. struct sky2_port *sky2 = netdev_priv(dev);
  1908. unsigned idx;
  1909. const u64 *le = (q == Q_R1 || q == Q_R2)
  1910. ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
  1911. idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
  1912. printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
  1913. dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
  1914. (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
  1915. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
  1916. }
  1917. /* If idle then force a fake soft NAPI poll once a second
  1918. * to work around cases where sharing an edge triggered interrupt.
  1919. */
  1920. static inline void sky2_idle_start(struct sky2_hw *hw)
  1921. {
  1922. if (idle_timeout > 0)
  1923. mod_timer(&hw->idle_timer,
  1924. jiffies + msecs_to_jiffies(idle_timeout));
  1925. }
  1926. static void sky2_idle(unsigned long arg)
  1927. {
  1928. struct sky2_hw *hw = (struct sky2_hw *) arg;
  1929. struct net_device *dev = hw->dev[0];
  1930. if (__netif_rx_schedule_prep(dev))
  1931. __netif_rx_schedule(dev);
  1932. mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
  1933. }
  1934. /* Hardware/software error handling */
  1935. static void sky2_err_intr(struct sky2_hw *hw, u32 status)
  1936. {
  1937. if (net_ratelimit())
  1938. dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
  1939. if (status & Y2_IS_HW_ERR)
  1940. sky2_hw_intr(hw);
  1941. if (status & Y2_IS_IRQ_MAC1)
  1942. sky2_mac_intr(hw, 0);
  1943. if (status & Y2_IS_IRQ_MAC2)
  1944. sky2_mac_intr(hw, 1);
  1945. if (status & Y2_IS_CHK_RX1)
  1946. sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
  1947. if (status & Y2_IS_CHK_RX2)
  1948. sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
  1949. if (status & Y2_IS_CHK_TXA1)
  1950. sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
  1951. if (status & Y2_IS_CHK_TXA2)
  1952. sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
  1953. }
  1954. static int sky2_poll(struct net_device *dev0, int *budget)
  1955. {
  1956. struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
  1957. int work_limit = min(dev0->quota, *budget);
  1958. int work_done = 0;
  1959. u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
  1960. if (unlikely(status & Y2_IS_ERROR))
  1961. sky2_err_intr(hw, status);
  1962. if (status & Y2_IS_IRQ_PHY1)
  1963. sky2_phy_intr(hw, 0);
  1964. if (status & Y2_IS_IRQ_PHY2)
  1965. sky2_phy_intr(hw, 1);
  1966. work_done = sky2_status_intr(hw, work_limit);
  1967. if (work_done < work_limit) {
  1968. netif_rx_complete(dev0);
  1969. sky2_read32(hw, B0_Y2_SP_LISR);
  1970. return 0;
  1971. } else {
  1972. *budget -= work_done;
  1973. dev0->quota -= work_done;
  1974. return 1;
  1975. }
  1976. }
  1977. static irqreturn_t sky2_intr(int irq, void *dev_id)
  1978. {
  1979. struct sky2_hw *hw = dev_id;
  1980. struct net_device *dev0 = hw->dev[0];
  1981. u32 status;
  1982. /* Reading this mask interrupts as side effect */
  1983. status = sky2_read32(hw, B0_Y2_SP_ISRC2);
  1984. if (status == 0 || status == ~0)
  1985. return IRQ_NONE;
  1986. prefetch(&hw->st_le[hw->st_idx]);
  1987. if (likely(__netif_rx_schedule_prep(dev0)))
  1988. __netif_rx_schedule(dev0);
  1989. return IRQ_HANDLED;
  1990. }
  1991. #ifdef CONFIG_NET_POLL_CONTROLLER
  1992. static void sky2_netpoll(struct net_device *dev)
  1993. {
  1994. struct sky2_port *sky2 = netdev_priv(dev);
  1995. struct net_device *dev0 = sky2->hw->dev[0];
  1996. if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
  1997. __netif_rx_schedule(dev0);
  1998. }
  1999. #endif
  2000. /* Chip internal frequency for clock calculations */
  2001. static inline u32 sky2_mhz(const struct sky2_hw *hw)
  2002. {
  2003. switch (hw->chip_id) {
  2004. case CHIP_ID_YUKON_EC:
  2005. case CHIP_ID_YUKON_EC_U:
  2006. case CHIP_ID_YUKON_EX:
  2007. return 125; /* 125 Mhz */
  2008. case CHIP_ID_YUKON_FE:
  2009. return 100; /* 100 Mhz */
  2010. default: /* YUKON_XL */
  2011. return 156; /* 156 Mhz */
  2012. }
  2013. }
  2014. static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
  2015. {
  2016. return sky2_mhz(hw) * us;
  2017. }
  2018. static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
  2019. {
  2020. return clk / sky2_mhz(hw);
  2021. }
  2022. static int __devinit sky2_init(struct sky2_hw *hw)
  2023. {
  2024. u8 t8;
  2025. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  2026. hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
  2027. if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
  2028. dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
  2029. hw->chip_id);
  2030. return -EOPNOTSUPP;
  2031. }
  2032. if (hw->chip_id == CHIP_ID_YUKON_EX)
  2033. dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
  2034. "Please report success or failure to <netdev@vger.kernel.org>\n");
  2035. /* Make sure and enable all clocks */
  2036. if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
  2037. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  2038. hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
  2039. /* This rev is really old, and requires untested workarounds */
  2040. if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
  2041. dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
  2042. yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
  2043. hw->chip_id, hw->chip_rev);
  2044. return -EOPNOTSUPP;
  2045. }
  2046. hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
  2047. hw->ports = 1;
  2048. t8 = sky2_read8(hw, B2_Y2_HW_RES);
  2049. if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
  2050. if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
  2051. ++hw->ports;
  2052. }
  2053. return 0;
  2054. }
  2055. static void sky2_reset(struct sky2_hw *hw)
  2056. {
  2057. u16 status;
  2058. int i;
  2059. /* disable ASF */
  2060. if (hw->chip_id == CHIP_ID_YUKON_EX) {
  2061. status = sky2_read16(hw, HCU_CCSR);
  2062. status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
  2063. HCU_CCSR_UC_STATE_MSK);
  2064. sky2_write16(hw, HCU_CCSR, status);
  2065. } else
  2066. sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
  2067. sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
  2068. /* do a SW reset */
  2069. sky2_write8(hw, B0_CTST, CS_RST_SET);
  2070. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  2071. /* clear PCI errors, if any */
  2072. status = sky2_pci_read16(hw, PCI_STATUS);
  2073. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2074. sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
  2075. sky2_write8(hw, B0_CTST, CS_MRST_CLR);
  2076. /* clear any PEX errors */
  2077. if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
  2078. sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
  2079. sky2_power_on(hw);
  2080. for (i = 0; i < hw->ports; i++) {
  2081. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  2082. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  2083. }
  2084. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2085. /* Clear I2C IRQ noise */
  2086. sky2_write32(hw, B2_I2C_IRQ, 1);
  2087. /* turn off hardware timer (unused) */
  2088. sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
  2089. sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  2090. sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
  2091. /* Turn off descriptor polling */
  2092. sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
  2093. /* Turn off receive timestamp */
  2094. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  2095. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  2096. /* enable the Tx Arbiters */
  2097. for (i = 0; i < hw->ports; i++)
  2098. sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  2099. /* Initialize ram interface */
  2100. for (i = 0; i < hw->ports; i++) {
  2101. sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  2102. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
  2103. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
  2104. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
  2105. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
  2106. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
  2107. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
  2108. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
  2109. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
  2110. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
  2111. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
  2112. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
  2113. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
  2114. }
  2115. sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
  2116. for (i = 0; i < hw->ports; i++)
  2117. sky2_gmac_reset(hw, i);
  2118. memset(hw->st_le, 0, STATUS_LE_BYTES);
  2119. hw->st_idx = 0;
  2120. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
  2121. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
  2122. sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
  2123. sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
  2124. /* Set the list last index */
  2125. sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
  2126. sky2_write16(hw, STAT_TX_IDX_TH, 10);
  2127. sky2_write8(hw, STAT_FIFO_WM, 16);
  2128. /* set Status-FIFO ISR watermark */
  2129. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
  2130. sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
  2131. else
  2132. sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
  2133. sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
  2134. sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
  2135. sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
  2136. /* enable status unit */
  2137. sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
  2138. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  2139. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  2140. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  2141. }
  2142. static void sky2_restart(struct work_struct *work)
  2143. {
  2144. struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
  2145. struct net_device *dev;
  2146. int i, err;
  2147. dev_dbg(&hw->pdev->dev, "restarting\n");
  2148. del_timer_sync(&hw->idle_timer);
  2149. rtnl_lock();
  2150. sky2_write32(hw, B0_IMSK, 0);
  2151. sky2_read32(hw, B0_IMSK);
  2152. netif_poll_disable(hw->dev[0]);
  2153. for (i = 0; i < hw->ports; i++) {
  2154. dev = hw->dev[i];
  2155. if (netif_running(dev))
  2156. sky2_down(dev);
  2157. }
  2158. sky2_reset(hw);
  2159. sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
  2160. netif_poll_enable(hw->dev[0]);
  2161. for (i = 0; i < hw->ports; i++) {
  2162. dev = hw->dev[i];
  2163. if (netif_running(dev)) {
  2164. err = sky2_up(dev);
  2165. if (err) {
  2166. printk(KERN_INFO PFX "%s: could not restart %d\n",
  2167. dev->name, err);
  2168. dev_close(dev);
  2169. }
  2170. }
  2171. }
  2172. sky2_idle_start(hw);
  2173. rtnl_unlock();
  2174. }
  2175. static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
  2176. {
  2177. return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
  2178. }
  2179. static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2180. {
  2181. const struct sky2_port *sky2 = netdev_priv(dev);
  2182. wol->supported = sky2_wol_supported(sky2->hw);
  2183. wol->wolopts = sky2->wol;
  2184. }
  2185. static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2186. {
  2187. struct sky2_port *sky2 = netdev_priv(dev);
  2188. struct sky2_hw *hw = sky2->hw;
  2189. if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
  2190. return -EOPNOTSUPP;
  2191. sky2->wol = wol->wolopts;
  2192. if (hw->chip_id == CHIP_ID_YUKON_EC_U)
  2193. sky2_write32(hw, B0_CTST, sky2->wol
  2194. ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
  2195. if (!netif_running(dev))
  2196. sky2_wol_init(sky2);
  2197. return 0;
  2198. }
  2199. static u32 sky2_supported_modes(const struct sky2_hw *hw)
  2200. {
  2201. if (sky2_is_copper(hw)) {
  2202. u32 modes = SUPPORTED_10baseT_Half
  2203. | SUPPORTED_10baseT_Full
  2204. | SUPPORTED_100baseT_Half
  2205. | SUPPORTED_100baseT_Full
  2206. | SUPPORTED_Autoneg | SUPPORTED_TP;
  2207. if (hw->chip_id != CHIP_ID_YUKON_FE)
  2208. modes |= SUPPORTED_1000baseT_Half
  2209. | SUPPORTED_1000baseT_Full;
  2210. return modes;
  2211. } else
  2212. return SUPPORTED_1000baseT_Half
  2213. | SUPPORTED_1000baseT_Full
  2214. | SUPPORTED_Autoneg
  2215. | SUPPORTED_FIBRE;
  2216. }
  2217. static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2218. {
  2219. struct sky2_port *sky2 = netdev_priv(dev);
  2220. struct sky2_hw *hw = sky2->hw;
  2221. ecmd->transceiver = XCVR_INTERNAL;
  2222. ecmd->supported = sky2_supported_modes(hw);
  2223. ecmd->phy_address = PHY_ADDR_MARV;
  2224. if (sky2_is_copper(hw)) {
  2225. ecmd->supported = SUPPORTED_10baseT_Half
  2226. | SUPPORTED_10baseT_Full
  2227. | SUPPORTED_100baseT_Half
  2228. | SUPPORTED_100baseT_Full
  2229. | SUPPORTED_1000baseT_Half
  2230. | SUPPORTED_1000baseT_Full
  2231. | SUPPORTED_Autoneg | SUPPORTED_TP;
  2232. ecmd->port = PORT_TP;
  2233. ecmd->speed = sky2->speed;
  2234. } else {
  2235. ecmd->speed = SPEED_1000;
  2236. ecmd->port = PORT_FIBRE;
  2237. }
  2238. ecmd->advertising = sky2->advertising;
  2239. ecmd->autoneg = sky2->autoneg;
  2240. ecmd->duplex = sky2->duplex;
  2241. return 0;
  2242. }
  2243. static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2244. {
  2245. struct sky2_port *sky2 = netdev_priv(dev);
  2246. const struct sky2_hw *hw = sky2->hw;
  2247. u32 supported = sky2_supported_modes(hw);
  2248. if (ecmd->autoneg == AUTONEG_ENABLE) {
  2249. ecmd->advertising = supported;
  2250. sky2->duplex = -1;
  2251. sky2->speed = -1;
  2252. } else {
  2253. u32 setting;
  2254. switch (ecmd->speed) {
  2255. case SPEED_1000:
  2256. if (ecmd->duplex == DUPLEX_FULL)
  2257. setting = SUPPORTED_1000baseT_Full;
  2258. else if (ecmd->duplex == DUPLEX_HALF)
  2259. setting = SUPPORTED_1000baseT_Half;
  2260. else
  2261. return -EINVAL;
  2262. break;
  2263. case SPEED_100:
  2264. if (ecmd->duplex == DUPLEX_FULL)
  2265. setting = SUPPORTED_100baseT_Full;
  2266. else if (ecmd->duplex == DUPLEX_HALF)
  2267. setting = SUPPORTED_100baseT_Half;
  2268. else
  2269. return -EINVAL;
  2270. break;
  2271. case SPEED_10:
  2272. if (ecmd->duplex == DUPLEX_FULL)
  2273. setting = SUPPORTED_10baseT_Full;
  2274. else if (ecmd->duplex == DUPLEX_HALF)
  2275. setting = SUPPORTED_10baseT_Half;
  2276. else
  2277. return -EINVAL;
  2278. break;
  2279. default:
  2280. return -EINVAL;
  2281. }
  2282. if ((setting & supported) == 0)
  2283. return -EINVAL;
  2284. sky2->speed = ecmd->speed;
  2285. sky2->duplex = ecmd->duplex;
  2286. }
  2287. sky2->autoneg = ecmd->autoneg;
  2288. sky2->advertising = ecmd->advertising;
  2289. if (netif_running(dev))
  2290. sky2_phy_reinit(sky2);
  2291. return 0;
  2292. }
  2293. static void sky2_get_drvinfo(struct net_device *dev,
  2294. struct ethtool_drvinfo *info)
  2295. {
  2296. struct sky2_port *sky2 = netdev_priv(dev);
  2297. strcpy(info->driver, DRV_NAME);
  2298. strcpy(info->version, DRV_VERSION);
  2299. strcpy(info->fw_version, "N/A");
  2300. strcpy(info->bus_info, pci_name(sky2->hw->pdev));
  2301. }
  2302. static const struct sky2_stat {
  2303. char name[ETH_GSTRING_LEN];
  2304. u16 offset;
  2305. } sky2_stats[] = {
  2306. { "tx_bytes", GM_TXO_OK_HI },
  2307. { "rx_bytes", GM_RXO_OK_HI },
  2308. { "tx_broadcast", GM_TXF_BC_OK },
  2309. { "rx_broadcast", GM_RXF_BC_OK },
  2310. { "tx_multicast", GM_TXF_MC_OK },
  2311. { "rx_multicast", GM_RXF_MC_OK },
  2312. { "tx_unicast", GM_TXF_UC_OK },
  2313. { "rx_unicast", GM_RXF_UC_OK },
  2314. { "tx_mac_pause", GM_TXF_MPAUSE },
  2315. { "rx_mac_pause", GM_RXF_MPAUSE },
  2316. { "collisions", GM_TXF_COL },
  2317. { "late_collision",GM_TXF_LAT_COL },
  2318. { "aborted", GM_TXF_ABO_COL },
  2319. { "single_collisions", GM_TXF_SNG_COL },
  2320. { "multi_collisions", GM_TXF_MUL_COL },
  2321. { "rx_short", GM_RXF_SHT },
  2322. { "rx_runt", GM_RXE_FRAG },
  2323. { "rx_64_byte_packets", GM_RXF_64B },
  2324. { "rx_65_to_127_byte_packets", GM_RXF_127B },
  2325. { "rx_128_to_255_byte_packets", GM_RXF_255B },
  2326. { "rx_256_to_511_byte_packets", GM_RXF_511B },
  2327. { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
  2328. { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
  2329. { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
  2330. { "rx_too_long", GM_RXF_LNG_ERR },
  2331. { "rx_fifo_overflow", GM_RXE_FIFO_OV },
  2332. { "rx_jabber", GM_RXF_JAB_PKT },
  2333. { "rx_fcs_error", GM_RXF_FCS_ERR },
  2334. { "tx_64_byte_packets", GM_TXF_64B },
  2335. { "tx_65_to_127_byte_packets", GM_TXF_127B },
  2336. { "tx_128_to_255_byte_packets", GM_TXF_255B },
  2337. { "tx_256_to_511_byte_packets", GM_TXF_511B },
  2338. { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
  2339. { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
  2340. { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
  2341. { "tx_fifo_underrun", GM_TXE_FIFO_UR },
  2342. };
  2343. static u32 sky2_get_rx_csum(struct net_device *dev)
  2344. {
  2345. struct sky2_port *sky2 = netdev_priv(dev);
  2346. return sky2->rx_csum;
  2347. }
  2348. static int sky2_set_rx_csum(struct net_device *dev, u32 data)
  2349. {
  2350. struct sky2_port *sky2 = netdev_priv(dev);
  2351. sky2->rx_csum = data;
  2352. sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  2353. data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  2354. return 0;
  2355. }
  2356. static u32 sky2_get_msglevel(struct net_device *netdev)
  2357. {
  2358. struct sky2_port *sky2 = netdev_priv(netdev);
  2359. return sky2->msg_enable;
  2360. }
  2361. static int sky2_nway_reset(struct net_device *dev)
  2362. {
  2363. struct sky2_port *sky2 = netdev_priv(dev);
  2364. if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
  2365. return -EINVAL;
  2366. sky2_phy_reinit(sky2);
  2367. return 0;
  2368. }
  2369. static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
  2370. {
  2371. struct sky2_hw *hw = sky2->hw;
  2372. unsigned port = sky2->port;
  2373. int i;
  2374. data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
  2375. | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
  2376. data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
  2377. | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
  2378. for (i = 2; i < count; i++)
  2379. data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
  2380. }
  2381. static void sky2_set_msglevel(struct net_device *netdev, u32 value)
  2382. {
  2383. struct sky2_port *sky2 = netdev_priv(netdev);
  2384. sky2->msg_enable = value;
  2385. }
  2386. static int sky2_get_stats_count(struct net_device *dev)
  2387. {
  2388. return ARRAY_SIZE(sky2_stats);
  2389. }
  2390. static void sky2_get_ethtool_stats(struct net_device *dev,
  2391. struct ethtool_stats *stats, u64 * data)
  2392. {
  2393. struct sky2_port *sky2 = netdev_priv(dev);
  2394. sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
  2395. }
  2396. static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
  2397. {
  2398. int i;
  2399. switch (stringset) {
  2400. case ETH_SS_STATS:
  2401. for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
  2402. memcpy(data + i * ETH_GSTRING_LEN,
  2403. sky2_stats[i].name, ETH_GSTRING_LEN);
  2404. break;
  2405. }
  2406. }
  2407. static struct net_device_stats *sky2_get_stats(struct net_device *dev)
  2408. {
  2409. struct sky2_port *sky2 = netdev_priv(dev);
  2410. return &sky2->net_stats;
  2411. }
  2412. static int sky2_set_mac_address(struct net_device *dev, void *p)
  2413. {
  2414. struct sky2_port *sky2 = netdev_priv(dev);
  2415. struct sky2_hw *hw = sky2->hw;
  2416. unsigned port = sky2->port;
  2417. const struct sockaddr *addr = p;
  2418. if (!is_valid_ether_addr(addr->sa_data))
  2419. return -EADDRNOTAVAIL;
  2420. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  2421. memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
  2422. dev->dev_addr, ETH_ALEN);
  2423. memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
  2424. dev->dev_addr, ETH_ALEN);
  2425. /* virtual address for data */
  2426. gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
  2427. /* physical address: used for pause frames */
  2428. gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
  2429. return 0;
  2430. }
  2431. static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
  2432. {
  2433. u32 bit;
  2434. bit = ether_crc(ETH_ALEN, addr) & 63;
  2435. filter[bit >> 3] |= 1 << (bit & 7);
  2436. }
  2437. static void sky2_set_multicast(struct net_device *dev)
  2438. {
  2439. struct sky2_port *sky2 = netdev_priv(dev);
  2440. struct sky2_hw *hw = sky2->hw;
  2441. unsigned port = sky2->port;
  2442. struct dev_mc_list *list = dev->mc_list;
  2443. u16 reg;
  2444. u8 filter[8];
  2445. int rx_pause;
  2446. static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
  2447. rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
  2448. memset(filter, 0, sizeof(filter));
  2449. reg = gma_read16(hw, port, GM_RX_CTRL);
  2450. reg |= GM_RXCR_UCF_ENA;
  2451. if (dev->flags & IFF_PROMISC) /* promiscuous */
  2452. reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  2453. else if (dev->flags & IFF_ALLMULTI)
  2454. memset(filter, 0xff, sizeof(filter));
  2455. else if (dev->mc_count == 0 && !rx_pause)
  2456. reg &= ~GM_RXCR_MCF_ENA;
  2457. else {
  2458. int i;
  2459. reg |= GM_RXCR_MCF_ENA;
  2460. if (rx_pause)
  2461. sky2_add_filter(filter, pause_mc_addr);
  2462. for (i = 0; list && i < dev->mc_count; i++, list = list->next)
  2463. sky2_add_filter(filter, list->dmi_addr);
  2464. }
  2465. gma_write16(hw, port, GM_MC_ADDR_H1,
  2466. (u16) filter[0] | ((u16) filter[1] << 8));
  2467. gma_write16(hw, port, GM_MC_ADDR_H2,
  2468. (u16) filter[2] | ((u16) filter[3] << 8));
  2469. gma_write16(hw, port, GM_MC_ADDR_H3,
  2470. (u16) filter[4] | ((u16) filter[5] << 8));
  2471. gma_write16(hw, port, GM_MC_ADDR_H4,
  2472. (u16) filter[6] | ((u16) filter[7] << 8));
  2473. gma_write16(hw, port, GM_RX_CTRL, reg);
  2474. }
  2475. /* Can have one global because blinking is controlled by
  2476. * ethtool and that is always under RTNL mutex
  2477. */
  2478. static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
  2479. {
  2480. u16 pg;
  2481. switch (hw->chip_id) {
  2482. case CHIP_ID_YUKON_XL:
  2483. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2484. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2485. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  2486. on ? (PHY_M_LEDC_LOS_CTRL(1) |
  2487. PHY_M_LEDC_INIT_CTRL(7) |
  2488. PHY_M_LEDC_STA1_CTRL(7) |
  2489. PHY_M_LEDC_STA0_CTRL(7))
  2490. : 0);
  2491. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2492. break;
  2493. default:
  2494. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  2495. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  2496. on ? PHY_M_LED_ALL : 0);
  2497. }
  2498. }
  2499. /* blink LED's for finding board */
  2500. static int sky2_phys_id(struct net_device *dev, u32 data)
  2501. {
  2502. struct sky2_port *sky2 = netdev_priv(dev);
  2503. struct sky2_hw *hw = sky2->hw;
  2504. unsigned port = sky2->port;
  2505. u16 ledctrl, ledover = 0;
  2506. long ms;
  2507. int interrupted;
  2508. int onoff = 1;
  2509. if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
  2510. ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
  2511. else
  2512. ms = data * 1000;
  2513. /* save initial values */
  2514. spin_lock_bh(&sky2->phy_lock);
  2515. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  2516. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2517. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2518. ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  2519. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2520. } else {
  2521. ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
  2522. ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
  2523. }
  2524. interrupted = 0;
  2525. while (!interrupted && ms > 0) {
  2526. sky2_led(hw, port, onoff);
  2527. onoff = !onoff;
  2528. spin_unlock_bh(&sky2->phy_lock);
  2529. interrupted = msleep_interruptible(250);
  2530. spin_lock_bh(&sky2->phy_lock);
  2531. ms -= 250;
  2532. }
  2533. /* resume regularly scheduled programming */
  2534. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  2535. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2536. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2537. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
  2538. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2539. } else {
  2540. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  2541. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  2542. }
  2543. spin_unlock_bh(&sky2->phy_lock);
  2544. return 0;
  2545. }
  2546. static void sky2_get_pauseparam(struct net_device *dev,
  2547. struct ethtool_pauseparam *ecmd)
  2548. {
  2549. struct sky2_port *sky2 = netdev_priv(dev);
  2550. switch (sky2->flow_mode) {
  2551. case FC_NONE:
  2552. ecmd->tx_pause = ecmd->rx_pause = 0;
  2553. break;
  2554. case FC_TX:
  2555. ecmd->tx_pause = 1, ecmd->rx_pause = 0;
  2556. break;
  2557. case FC_RX:
  2558. ecmd->tx_pause = 0, ecmd->rx_pause = 1;
  2559. break;
  2560. case FC_BOTH:
  2561. ecmd->tx_pause = ecmd->rx_pause = 1;
  2562. }
  2563. ecmd->autoneg = sky2->autoneg;
  2564. }
  2565. static int sky2_set_pauseparam(struct net_device *dev,
  2566. struct ethtool_pauseparam *ecmd)
  2567. {
  2568. struct sky2_port *sky2 = netdev_priv(dev);
  2569. sky2->autoneg = ecmd->autoneg;
  2570. sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
  2571. if (netif_running(dev))
  2572. sky2_phy_reinit(sky2);
  2573. return 0;
  2574. }
  2575. static int sky2_get_coalesce(struct net_device *dev,
  2576. struct ethtool_coalesce *ecmd)
  2577. {
  2578. struct sky2_port *sky2 = netdev_priv(dev);
  2579. struct sky2_hw *hw = sky2->hw;
  2580. if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
  2581. ecmd->tx_coalesce_usecs = 0;
  2582. else {
  2583. u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
  2584. ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
  2585. }
  2586. ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
  2587. if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
  2588. ecmd->rx_coalesce_usecs = 0;
  2589. else {
  2590. u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
  2591. ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
  2592. }
  2593. ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
  2594. if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
  2595. ecmd->rx_coalesce_usecs_irq = 0;
  2596. else {
  2597. u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
  2598. ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
  2599. }
  2600. ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
  2601. return 0;
  2602. }
  2603. /* Note: this affect both ports */
  2604. static int sky2_set_coalesce(struct net_device *dev,
  2605. struct ethtool_coalesce *ecmd)
  2606. {
  2607. struct sky2_port *sky2 = netdev_priv(dev);
  2608. struct sky2_hw *hw = sky2->hw;
  2609. const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
  2610. if (ecmd->tx_coalesce_usecs > tmax ||
  2611. ecmd->rx_coalesce_usecs > tmax ||
  2612. ecmd->rx_coalesce_usecs_irq > tmax)
  2613. return -EINVAL;
  2614. if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
  2615. return -EINVAL;
  2616. if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
  2617. return -EINVAL;
  2618. if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
  2619. return -EINVAL;
  2620. if (ecmd->tx_coalesce_usecs == 0)
  2621. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
  2622. else {
  2623. sky2_write32(hw, STAT_TX_TIMER_INI,
  2624. sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
  2625. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  2626. }
  2627. sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
  2628. if (ecmd->rx_coalesce_usecs == 0)
  2629. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
  2630. else {
  2631. sky2_write32(hw, STAT_LEV_TIMER_INI,
  2632. sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
  2633. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  2634. }
  2635. sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
  2636. if (ecmd->rx_coalesce_usecs_irq == 0)
  2637. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
  2638. else {
  2639. sky2_write32(hw, STAT_ISR_TIMER_INI,
  2640. sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
  2641. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  2642. }
  2643. sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
  2644. return 0;
  2645. }
  2646. static void sky2_get_ringparam(struct net_device *dev,
  2647. struct ethtool_ringparam *ering)
  2648. {
  2649. struct sky2_port *sky2 = netdev_priv(dev);
  2650. ering->rx_max_pending = RX_MAX_PENDING;
  2651. ering->rx_mini_max_pending = 0;
  2652. ering->rx_jumbo_max_pending = 0;
  2653. ering->tx_max_pending = TX_RING_SIZE - 1;
  2654. ering->rx_pending = sky2->rx_pending;
  2655. ering->rx_mini_pending = 0;
  2656. ering->rx_jumbo_pending = 0;
  2657. ering->tx_pending = sky2->tx_pending;
  2658. }
  2659. static int sky2_set_ringparam(struct net_device *dev,
  2660. struct ethtool_ringparam *ering)
  2661. {
  2662. struct sky2_port *sky2 = netdev_priv(dev);
  2663. int err = 0;
  2664. if (ering->rx_pending > RX_MAX_PENDING ||
  2665. ering->rx_pending < 8 ||
  2666. ering->tx_pending < MAX_SKB_TX_LE ||
  2667. ering->tx_pending > TX_RING_SIZE - 1)
  2668. return -EINVAL;
  2669. if (netif_running(dev))
  2670. sky2_down(dev);
  2671. sky2->rx_pending = ering->rx_pending;
  2672. sky2->tx_pending = ering->tx_pending;
  2673. if (netif_running(dev)) {
  2674. err = sky2_up(dev);
  2675. if (err)
  2676. dev_close(dev);
  2677. else
  2678. sky2_set_multicast(dev);
  2679. }
  2680. return err;
  2681. }
  2682. static int sky2_get_regs_len(struct net_device *dev)
  2683. {
  2684. return 0x4000;
  2685. }
  2686. /*
  2687. * Returns copy of control register region
  2688. * Note: access to the RAM address register set will cause timeouts.
  2689. */
  2690. static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  2691. void *p)
  2692. {
  2693. const struct sky2_port *sky2 = netdev_priv(dev);
  2694. const void __iomem *io = sky2->hw->regs;
  2695. BUG_ON(regs->len < B3_RI_WTO_R1);
  2696. regs->version = 1;
  2697. memset(p, 0, regs->len);
  2698. memcpy_fromio(p, io, B3_RAM_ADDR);
  2699. memcpy_fromio(p + B3_RI_WTO_R1,
  2700. io + B3_RI_WTO_R1,
  2701. regs->len - B3_RI_WTO_R1);
  2702. }
  2703. /* In order to do Jumbo packets on these chips, need to turn off the
  2704. * transmit store/forward. Therefore checksum offload won't work.
  2705. */
  2706. static int no_tx_offload(struct net_device *dev)
  2707. {
  2708. const struct sky2_port *sky2 = netdev_priv(dev);
  2709. const struct sky2_hw *hw = sky2->hw;
  2710. return dev->mtu > ETH_DATA_LEN &&
  2711. (hw->chip_id == CHIP_ID_YUKON_EX
  2712. || hw->chip_id == CHIP_ID_YUKON_EC_U);
  2713. }
  2714. static int sky2_set_tx_csum(struct net_device *dev, u32 data)
  2715. {
  2716. if (data && no_tx_offload(dev))
  2717. return -EINVAL;
  2718. return ethtool_op_set_tx_csum(dev, data);
  2719. }
  2720. static int sky2_set_tso(struct net_device *dev, u32 data)
  2721. {
  2722. if (data && no_tx_offload(dev))
  2723. return -EINVAL;
  2724. return ethtool_op_set_tso(dev, data);
  2725. }
  2726. static const struct ethtool_ops sky2_ethtool_ops = {
  2727. .get_settings = sky2_get_settings,
  2728. .set_settings = sky2_set_settings,
  2729. .get_drvinfo = sky2_get_drvinfo,
  2730. .get_wol = sky2_get_wol,
  2731. .set_wol = sky2_set_wol,
  2732. .get_msglevel = sky2_get_msglevel,
  2733. .set_msglevel = sky2_set_msglevel,
  2734. .nway_reset = sky2_nway_reset,
  2735. .get_regs_len = sky2_get_regs_len,
  2736. .get_regs = sky2_get_regs,
  2737. .get_link = ethtool_op_get_link,
  2738. .get_sg = ethtool_op_get_sg,
  2739. .set_sg = ethtool_op_set_sg,
  2740. .get_tx_csum = ethtool_op_get_tx_csum,
  2741. .set_tx_csum = sky2_set_tx_csum,
  2742. .get_tso = ethtool_op_get_tso,
  2743. .set_tso = sky2_set_tso,
  2744. .get_rx_csum = sky2_get_rx_csum,
  2745. .set_rx_csum = sky2_set_rx_csum,
  2746. .get_strings = sky2_get_strings,
  2747. .get_coalesce = sky2_get_coalesce,
  2748. .set_coalesce = sky2_set_coalesce,
  2749. .get_ringparam = sky2_get_ringparam,
  2750. .set_ringparam = sky2_set_ringparam,
  2751. .get_pauseparam = sky2_get_pauseparam,
  2752. .set_pauseparam = sky2_set_pauseparam,
  2753. .phys_id = sky2_phys_id,
  2754. .get_stats_count = sky2_get_stats_count,
  2755. .get_ethtool_stats = sky2_get_ethtool_stats,
  2756. .get_perm_addr = ethtool_op_get_perm_addr,
  2757. };
  2758. /* Initialize network device */
  2759. static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
  2760. unsigned port,
  2761. int highmem, int wol)
  2762. {
  2763. struct sky2_port *sky2;
  2764. struct net_device *dev = alloc_etherdev(sizeof(*sky2));
  2765. if (!dev) {
  2766. dev_err(&hw->pdev->dev, "etherdev alloc failed");
  2767. return NULL;
  2768. }
  2769. SET_MODULE_OWNER(dev);
  2770. SET_NETDEV_DEV(dev, &hw->pdev->dev);
  2771. dev->irq = hw->pdev->irq;
  2772. dev->open = sky2_up;
  2773. dev->stop = sky2_down;
  2774. dev->do_ioctl = sky2_ioctl;
  2775. dev->hard_start_xmit = sky2_xmit_frame;
  2776. dev->get_stats = sky2_get_stats;
  2777. dev->set_multicast_list = sky2_set_multicast;
  2778. dev->set_mac_address = sky2_set_mac_address;
  2779. dev->change_mtu = sky2_change_mtu;
  2780. SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
  2781. dev->tx_timeout = sky2_tx_timeout;
  2782. dev->watchdog_timeo = TX_WATCHDOG;
  2783. if (port == 0)
  2784. dev->poll = sky2_poll;
  2785. dev->weight = NAPI_WEIGHT;
  2786. #ifdef CONFIG_NET_POLL_CONTROLLER
  2787. /* Network console (only works on port 0)
  2788. * because netpoll makes assumptions about NAPI
  2789. */
  2790. if (port == 0)
  2791. dev->poll_controller = sky2_netpoll;
  2792. #endif
  2793. sky2 = netdev_priv(dev);
  2794. sky2->netdev = dev;
  2795. sky2->hw = hw;
  2796. sky2->msg_enable = netif_msg_init(debug, default_msg);
  2797. /* Auto speed and flow control */
  2798. sky2->autoneg = AUTONEG_ENABLE;
  2799. sky2->flow_mode = FC_BOTH;
  2800. sky2->duplex = -1;
  2801. sky2->speed = -1;
  2802. sky2->advertising = sky2_supported_modes(hw);
  2803. sky2->rx_csum = 1;
  2804. sky2->wol = wol;
  2805. spin_lock_init(&sky2->phy_lock);
  2806. sky2->tx_pending = TX_DEF_PENDING;
  2807. sky2->rx_pending = RX_DEF_PENDING;
  2808. hw->dev[port] = dev;
  2809. sky2->port = port;
  2810. dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
  2811. if (highmem)
  2812. dev->features |= NETIF_F_HIGHDMA;
  2813. #ifdef SKY2_VLAN_TAG_USED
  2814. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  2815. dev->vlan_rx_register = sky2_vlan_rx_register;
  2816. dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
  2817. #endif
  2818. /* read the mac address */
  2819. memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
  2820. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  2821. /* device is off until link detection */
  2822. netif_carrier_off(dev);
  2823. netif_stop_queue(dev);
  2824. return dev;
  2825. }
  2826. static void __devinit sky2_show_addr(struct net_device *dev)
  2827. {
  2828. const struct sky2_port *sky2 = netdev_priv(dev);
  2829. if (netif_msg_probe(sky2))
  2830. printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  2831. dev->name,
  2832. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  2833. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  2834. }
  2835. /* Handle software interrupt used during MSI test */
  2836. static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
  2837. {
  2838. struct sky2_hw *hw = dev_id;
  2839. u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
  2840. if (status == 0)
  2841. return IRQ_NONE;
  2842. if (status & Y2_IS_IRQ_SW) {
  2843. hw->msi = 1;
  2844. wake_up(&hw->msi_wait);
  2845. sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
  2846. }
  2847. sky2_write32(hw, B0_Y2_SP_ICR, 2);
  2848. return IRQ_HANDLED;
  2849. }
  2850. /* Test interrupt path by forcing a a software IRQ */
  2851. static int __devinit sky2_test_msi(struct sky2_hw *hw)
  2852. {
  2853. struct pci_dev *pdev = hw->pdev;
  2854. int err;
  2855. init_waitqueue_head (&hw->msi_wait);
  2856. sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
  2857. err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
  2858. if (err) {
  2859. dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
  2860. return err;
  2861. }
  2862. sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
  2863. sky2_read8(hw, B0_CTST);
  2864. wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
  2865. if (!hw->msi) {
  2866. /* MSI test failed, go back to INTx mode */
  2867. dev_info(&pdev->dev, "No interrupt generated using MSI, "
  2868. "switching to INTx mode.\n");
  2869. err = -EOPNOTSUPP;
  2870. sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
  2871. }
  2872. sky2_write32(hw, B0_IMSK, 0);
  2873. sky2_read32(hw, B0_IMSK);
  2874. free_irq(pdev->irq, hw);
  2875. return err;
  2876. }
  2877. static int __devinit pci_wake_enabled(struct pci_dev *dev)
  2878. {
  2879. int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  2880. u16 value;
  2881. if (!pm)
  2882. return 0;
  2883. if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
  2884. return 0;
  2885. return value & PCI_PM_CTRL_PME_ENABLE;
  2886. }
  2887. static int __devinit sky2_probe(struct pci_dev *pdev,
  2888. const struct pci_device_id *ent)
  2889. {
  2890. struct net_device *dev;
  2891. struct sky2_hw *hw;
  2892. int err, using_dac = 0, wol_default;
  2893. err = pci_enable_device(pdev);
  2894. if (err) {
  2895. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2896. goto err_out;
  2897. }
  2898. err = pci_request_regions(pdev, DRV_NAME);
  2899. if (err) {
  2900. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2901. goto err_out;
  2902. }
  2903. pci_set_master(pdev);
  2904. if (sizeof(dma_addr_t) > sizeof(u32) &&
  2905. !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
  2906. using_dac = 1;
  2907. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  2908. if (err < 0) {
  2909. dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
  2910. "for consistent allocations\n");
  2911. goto err_out_free_regions;
  2912. }
  2913. } else {
  2914. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2915. if (err) {
  2916. dev_err(&pdev->dev, "no usable DMA configuration\n");
  2917. goto err_out_free_regions;
  2918. }
  2919. }
  2920. wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
  2921. err = -ENOMEM;
  2922. hw = kzalloc(sizeof(*hw), GFP_KERNEL);
  2923. if (!hw) {
  2924. dev_err(&pdev->dev, "cannot allocate hardware struct\n");
  2925. goto err_out_free_regions;
  2926. }
  2927. hw->pdev = pdev;
  2928. hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
  2929. if (!hw->regs) {
  2930. dev_err(&pdev->dev, "cannot map device registers\n");
  2931. goto err_out_free_hw;
  2932. }
  2933. #ifdef __BIG_ENDIAN
  2934. /* The sk98lin vendor driver uses hardware byte swapping but
  2935. * this driver uses software swapping.
  2936. */
  2937. {
  2938. u32 reg;
  2939. reg = sky2_pci_read32(hw, PCI_DEV_REG2);
  2940. reg &= ~PCI_REV_DESC;
  2941. sky2_pci_write32(hw, PCI_DEV_REG2, reg);
  2942. }
  2943. #endif
  2944. /* ring for status responses */
  2945. hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
  2946. &hw->st_dma);
  2947. if (!hw->st_le)
  2948. goto err_out_iounmap;
  2949. err = sky2_init(hw);
  2950. if (err)
  2951. goto err_out_iounmap;
  2952. dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
  2953. DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
  2954. pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
  2955. hw->chip_id, hw->chip_rev);
  2956. sky2_reset(hw);
  2957. dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
  2958. if (!dev) {
  2959. err = -ENOMEM;
  2960. goto err_out_free_pci;
  2961. }
  2962. if (!disable_msi && pci_enable_msi(pdev) == 0) {
  2963. err = sky2_test_msi(hw);
  2964. if (err == -EOPNOTSUPP)
  2965. pci_disable_msi(pdev);
  2966. else if (err)
  2967. goto err_out_free_netdev;
  2968. }
  2969. err = register_netdev(dev);
  2970. if (err) {
  2971. dev_err(&pdev->dev, "cannot register net device\n");
  2972. goto err_out_free_netdev;
  2973. }
  2974. err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
  2975. dev->name, hw);
  2976. if (err) {
  2977. dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
  2978. goto err_out_unregister;
  2979. }
  2980. sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
  2981. sky2_show_addr(dev);
  2982. if (hw->ports > 1) {
  2983. struct net_device *dev1;
  2984. dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
  2985. if (!dev1)
  2986. dev_warn(&pdev->dev, "allocation for second device failed\n");
  2987. else if ((err = register_netdev(dev1))) {
  2988. dev_warn(&pdev->dev,
  2989. "register of second port failed (%d)\n", err);
  2990. hw->dev[1] = NULL;
  2991. free_netdev(dev1);
  2992. } else
  2993. sky2_show_addr(dev1);
  2994. }
  2995. setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
  2996. INIT_WORK(&hw->restart_work, sky2_restart);
  2997. sky2_idle_start(hw);
  2998. pci_set_drvdata(pdev, hw);
  2999. return 0;
  3000. err_out_unregister:
  3001. if (hw->msi)
  3002. pci_disable_msi(pdev);
  3003. unregister_netdev(dev);
  3004. err_out_free_netdev:
  3005. free_netdev(dev);
  3006. err_out_free_pci:
  3007. sky2_write8(hw, B0_CTST, CS_RST_SET);
  3008. pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
  3009. err_out_iounmap:
  3010. iounmap(hw->regs);
  3011. err_out_free_hw:
  3012. kfree(hw);
  3013. err_out_free_regions:
  3014. pci_release_regions(pdev);
  3015. pci_disable_device(pdev);
  3016. err_out:
  3017. pci_set_drvdata(pdev, NULL);
  3018. return err;
  3019. }
  3020. static void __devexit sky2_remove(struct pci_dev *pdev)
  3021. {
  3022. struct sky2_hw *hw = pci_get_drvdata(pdev);
  3023. struct net_device *dev0, *dev1;
  3024. if (!hw)
  3025. return;
  3026. del_timer_sync(&hw->idle_timer);
  3027. flush_scheduled_work();
  3028. sky2_write32(hw, B0_IMSK, 0);
  3029. synchronize_irq(hw->pdev->irq);
  3030. dev0 = hw->dev[0];
  3031. dev1 = hw->dev[1];
  3032. if (dev1)
  3033. unregister_netdev(dev1);
  3034. unregister_netdev(dev0);
  3035. sky2_power_aux(hw);
  3036. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  3037. sky2_write8(hw, B0_CTST, CS_RST_SET);
  3038. sky2_read8(hw, B0_CTST);
  3039. free_irq(pdev->irq, hw);
  3040. if (hw->msi)
  3041. pci_disable_msi(pdev);
  3042. pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
  3043. pci_release_regions(pdev);
  3044. pci_disable_device(pdev);
  3045. if (dev1)
  3046. free_netdev(dev1);
  3047. free_netdev(dev0);
  3048. iounmap(hw->regs);
  3049. kfree(hw);
  3050. pci_set_drvdata(pdev, NULL);
  3051. }
  3052. #ifdef CONFIG_PM
  3053. static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
  3054. {
  3055. struct sky2_hw *hw = pci_get_drvdata(pdev);
  3056. int i, wol = 0;
  3057. if (!hw)
  3058. return 0;
  3059. del_timer_sync(&hw->idle_timer);
  3060. netif_poll_disable(hw->dev[0]);
  3061. for (i = 0; i < hw->ports; i++) {
  3062. struct net_device *dev = hw->dev[i];
  3063. struct sky2_port *sky2 = netdev_priv(dev);
  3064. if (netif_running(dev))
  3065. sky2_down(dev);
  3066. if (sky2->wol)
  3067. sky2_wol_init(sky2);
  3068. wol |= sky2->wol;
  3069. }
  3070. sky2_write32(hw, B0_IMSK, 0);
  3071. sky2_power_aux(hw);
  3072. pci_save_state(pdev);
  3073. pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
  3074. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  3075. return 0;
  3076. }
  3077. static int sky2_resume(struct pci_dev *pdev)
  3078. {
  3079. struct sky2_hw *hw = pci_get_drvdata(pdev);
  3080. int i, err;
  3081. if (!hw)
  3082. return 0;
  3083. err = pci_set_power_state(pdev, PCI_D0);
  3084. if (err)
  3085. goto out;
  3086. err = pci_restore_state(pdev);
  3087. if (err)
  3088. goto out;
  3089. pci_enable_wake(pdev, PCI_D0, 0);
  3090. /* Re-enable all clocks */
  3091. if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
  3092. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  3093. sky2_reset(hw);
  3094. sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
  3095. for (i = 0; i < hw->ports; i++) {
  3096. struct net_device *dev = hw->dev[i];
  3097. if (netif_running(dev)) {
  3098. err = sky2_up(dev);
  3099. if (err) {
  3100. printk(KERN_ERR PFX "%s: could not up: %d\n",
  3101. dev->name, err);
  3102. dev_close(dev);
  3103. goto out;
  3104. }
  3105. }
  3106. }
  3107. netif_poll_enable(hw->dev[0]);
  3108. sky2_idle_start(hw);
  3109. return 0;
  3110. out:
  3111. dev_err(&pdev->dev, "resume failed (%d)\n", err);
  3112. pci_disable_device(pdev);
  3113. return err;
  3114. }
  3115. #endif
  3116. static void sky2_shutdown(struct pci_dev *pdev)
  3117. {
  3118. struct sky2_hw *hw = pci_get_drvdata(pdev);
  3119. int i, wol = 0;
  3120. if (!hw)
  3121. return;
  3122. del_timer_sync(&hw->idle_timer);
  3123. netif_poll_disable(hw->dev[0]);
  3124. for (i = 0; i < hw->ports; i++) {
  3125. struct net_device *dev = hw->dev[i];
  3126. struct sky2_port *sky2 = netdev_priv(dev);
  3127. if (sky2->wol) {
  3128. wol = 1;
  3129. sky2_wol_init(sky2);
  3130. }
  3131. }
  3132. if (wol)
  3133. sky2_power_aux(hw);
  3134. pci_enable_wake(pdev, PCI_D3hot, wol);
  3135. pci_enable_wake(pdev, PCI_D3cold, wol);
  3136. pci_disable_device(pdev);
  3137. pci_set_power_state(pdev, PCI_D3hot);
  3138. }
  3139. static struct pci_driver sky2_driver = {
  3140. .name = DRV_NAME,
  3141. .id_table = sky2_id_table,
  3142. .probe = sky2_probe,
  3143. .remove = __devexit_p(sky2_remove),
  3144. #ifdef CONFIG_PM
  3145. .suspend = sky2_suspend,
  3146. .resume = sky2_resume,
  3147. #endif
  3148. .shutdown = sky2_shutdown,
  3149. };
  3150. static int __init sky2_init_module(void)
  3151. {
  3152. return pci_register_driver(&sky2_driver);
  3153. }
  3154. static void __exit sky2_cleanup_module(void)
  3155. {
  3156. pci_unregister_driver(&sky2_driver);
  3157. }
  3158. module_init(sky2_init_module);
  3159. module_exit(sky2_cleanup_module);
  3160. MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
  3161. MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
  3162. MODULE_LICENSE("GPL");
  3163. MODULE_VERSION(DRV_VERSION);