skge.c 100 KB

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  1. /*
  2. * New driver for Marvell Yukon chipset and SysKonnect Gigabit
  3. * Ethernet adapters. Based on earlier sk98lin, e100 and
  4. * FreeBSD if_sk drivers.
  5. *
  6. * This driver intentionally does not support all the features
  7. * of the original driver such as link fail-over and link management because
  8. * those should be done at higher levels.
  9. *
  10. * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #include <linux/in.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/moduleparam.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/pci.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/ip.h>
  35. #include <linux/delay.h>
  36. #include <linux/crc32.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/mii.h>
  39. #include <asm/irq.h>
  40. #include "skge.h"
  41. #define DRV_NAME "skge"
  42. #define DRV_VERSION "1.10"
  43. #define PFX DRV_NAME " "
  44. #define DEFAULT_TX_RING_SIZE 128
  45. #define DEFAULT_RX_RING_SIZE 512
  46. #define MAX_TX_RING_SIZE 1024
  47. #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
  48. #define MAX_RX_RING_SIZE 4096
  49. #define RX_COPY_THRESHOLD 128
  50. #define RX_BUF_SIZE 1536
  51. #define PHY_RETRIES 1000
  52. #define ETH_JUMBO_MTU 9000
  53. #define TX_WATCHDOG (5 * HZ)
  54. #define NAPI_WEIGHT 64
  55. #define BLINK_MS 250
  56. #define LINK_HZ (HZ/2)
  57. MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
  58. MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
  59. MODULE_LICENSE("GPL");
  60. MODULE_VERSION(DRV_VERSION);
  61. static const u32 default_msg
  62. = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
  63. | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
  64. static int debug = -1; /* defaults above */
  65. module_param(debug, int, 0);
  66. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  67. static const struct pci_device_id skge_id_table[] = {
  68. { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
  71. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
  74. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
  76. { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
  77. { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
  78. { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
  79. { 0 }
  80. };
  81. MODULE_DEVICE_TABLE(pci, skge_id_table);
  82. static int skge_up(struct net_device *dev);
  83. static int skge_down(struct net_device *dev);
  84. static void skge_phy_reset(struct skge_port *skge);
  85. static void skge_tx_clean(struct net_device *dev);
  86. static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  87. static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  88. static void genesis_get_stats(struct skge_port *skge, u64 *data);
  89. static void yukon_get_stats(struct skge_port *skge, u64 *data);
  90. static void yukon_init(struct skge_hw *hw, int port);
  91. static void genesis_mac_init(struct skge_hw *hw, int port);
  92. static void genesis_link_up(struct skge_port *skge);
  93. /* Avoid conditionals by using array */
  94. static const int txqaddr[] = { Q_XA1, Q_XA2 };
  95. static const int rxqaddr[] = { Q_R1, Q_R2 };
  96. static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
  97. static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
  98. static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
  99. static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
  100. static int skge_get_regs_len(struct net_device *dev)
  101. {
  102. return 0x4000;
  103. }
  104. /*
  105. * Returns copy of whole control register region
  106. * Note: skip RAM address register because accessing it will
  107. * cause bus hangs!
  108. */
  109. static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  110. void *p)
  111. {
  112. const struct skge_port *skge = netdev_priv(dev);
  113. const void __iomem *io = skge->hw->regs;
  114. regs->version = 1;
  115. memset(p, 0, regs->len);
  116. memcpy_fromio(p, io, B3_RAM_ADDR);
  117. memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
  118. regs->len - B3_RI_WTO_R1);
  119. }
  120. /* Wake on Lan only supported on Yukon chips with rev 1 or above */
  121. static u32 wol_supported(const struct skge_hw *hw)
  122. {
  123. if (hw->chip_id == CHIP_ID_GENESIS)
  124. return 0;
  125. if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
  126. return 0;
  127. return WAKE_MAGIC | WAKE_PHY;
  128. }
  129. static u32 pci_wake_enabled(struct pci_dev *dev)
  130. {
  131. int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  132. u16 value;
  133. /* If device doesn't support PM Capabilities, but request is to disable
  134. * wake events, it's a nop; otherwise fail */
  135. if (!pm)
  136. return 0;
  137. pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
  138. value &= PCI_PM_CAP_PME_MASK;
  139. value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
  140. return value != 0;
  141. }
  142. static void skge_wol_init(struct skge_port *skge)
  143. {
  144. struct skge_hw *hw = skge->hw;
  145. int port = skge->port;
  146. u16 ctrl;
  147. skge_write16(hw, B0_CTST, CS_RST_CLR);
  148. skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
  149. /* Turn on Vaux */
  150. skge_write8(hw, B0_POWER_CTRL,
  151. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
  152. /* WA code for COMA mode -- clear PHY reset */
  153. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  154. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  155. u32 reg = skge_read32(hw, B2_GP_IO);
  156. reg |= GP_DIR_9;
  157. reg &= ~GP_IO_9;
  158. skge_write32(hw, B2_GP_IO, reg);
  159. }
  160. skge_write32(hw, SK_REG(port, GPHY_CTRL),
  161. GPC_DIS_SLEEP |
  162. GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
  163. GPC_ANEG_1 | GPC_RST_SET);
  164. skge_write32(hw, SK_REG(port, GPHY_CTRL),
  165. GPC_DIS_SLEEP |
  166. GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
  167. GPC_ANEG_1 | GPC_RST_CLR);
  168. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  169. /* Force to 10/100 skge_reset will re-enable on resume */
  170. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
  171. PHY_AN_100FULL | PHY_AN_100HALF |
  172. PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
  173. /* no 1000 HD/FD */
  174. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
  175. gm_phy_write(hw, port, PHY_MARV_CTRL,
  176. PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
  177. PHY_CT_RE_CFG | PHY_CT_DUP_MD);
  178. /* Set GMAC to no flow control and auto update for speed/duplex */
  179. gma_write16(hw, port, GM_GP_CTRL,
  180. GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
  181. GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
  182. /* Set WOL address */
  183. memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
  184. skge->netdev->dev_addr, ETH_ALEN);
  185. /* Turn on appropriate WOL control bits */
  186. skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
  187. ctrl = 0;
  188. if (skge->wol & WAKE_PHY)
  189. ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
  190. else
  191. ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
  192. if (skge->wol & WAKE_MAGIC)
  193. ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
  194. else
  195. ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
  196. ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
  197. skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
  198. /* block receiver */
  199. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  200. }
  201. static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  202. {
  203. struct skge_port *skge = netdev_priv(dev);
  204. wol->supported = wol_supported(skge->hw);
  205. wol->wolopts = skge->wol;
  206. }
  207. static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  208. {
  209. struct skge_port *skge = netdev_priv(dev);
  210. struct skge_hw *hw = skge->hw;
  211. if (wol->wolopts & ~wol_supported(hw))
  212. return -EOPNOTSUPP;
  213. skge->wol = wol->wolopts;
  214. return 0;
  215. }
  216. /* Determine supported/advertised modes based on hardware.
  217. * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
  218. */
  219. static u32 skge_supported_modes(const struct skge_hw *hw)
  220. {
  221. u32 supported;
  222. if (hw->copper) {
  223. supported = SUPPORTED_10baseT_Half
  224. | SUPPORTED_10baseT_Full
  225. | SUPPORTED_100baseT_Half
  226. | SUPPORTED_100baseT_Full
  227. | SUPPORTED_1000baseT_Half
  228. | SUPPORTED_1000baseT_Full
  229. | SUPPORTED_Autoneg| SUPPORTED_TP;
  230. if (hw->chip_id == CHIP_ID_GENESIS)
  231. supported &= ~(SUPPORTED_10baseT_Half
  232. | SUPPORTED_10baseT_Full
  233. | SUPPORTED_100baseT_Half
  234. | SUPPORTED_100baseT_Full);
  235. else if (hw->chip_id == CHIP_ID_YUKON)
  236. supported &= ~SUPPORTED_1000baseT_Half;
  237. } else
  238. supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
  239. | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
  240. return supported;
  241. }
  242. static int skge_get_settings(struct net_device *dev,
  243. struct ethtool_cmd *ecmd)
  244. {
  245. struct skge_port *skge = netdev_priv(dev);
  246. struct skge_hw *hw = skge->hw;
  247. ecmd->transceiver = XCVR_INTERNAL;
  248. ecmd->supported = skge_supported_modes(hw);
  249. if (hw->copper) {
  250. ecmd->port = PORT_TP;
  251. ecmd->phy_address = hw->phy_addr;
  252. } else
  253. ecmd->port = PORT_FIBRE;
  254. ecmd->advertising = skge->advertising;
  255. ecmd->autoneg = skge->autoneg;
  256. ecmd->speed = skge->speed;
  257. ecmd->duplex = skge->duplex;
  258. return 0;
  259. }
  260. static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  261. {
  262. struct skge_port *skge = netdev_priv(dev);
  263. const struct skge_hw *hw = skge->hw;
  264. u32 supported = skge_supported_modes(hw);
  265. if (ecmd->autoneg == AUTONEG_ENABLE) {
  266. ecmd->advertising = supported;
  267. skge->duplex = -1;
  268. skge->speed = -1;
  269. } else {
  270. u32 setting;
  271. switch (ecmd->speed) {
  272. case SPEED_1000:
  273. if (ecmd->duplex == DUPLEX_FULL)
  274. setting = SUPPORTED_1000baseT_Full;
  275. else if (ecmd->duplex == DUPLEX_HALF)
  276. setting = SUPPORTED_1000baseT_Half;
  277. else
  278. return -EINVAL;
  279. break;
  280. case SPEED_100:
  281. if (ecmd->duplex == DUPLEX_FULL)
  282. setting = SUPPORTED_100baseT_Full;
  283. else if (ecmd->duplex == DUPLEX_HALF)
  284. setting = SUPPORTED_100baseT_Half;
  285. else
  286. return -EINVAL;
  287. break;
  288. case SPEED_10:
  289. if (ecmd->duplex == DUPLEX_FULL)
  290. setting = SUPPORTED_10baseT_Full;
  291. else if (ecmd->duplex == DUPLEX_HALF)
  292. setting = SUPPORTED_10baseT_Half;
  293. else
  294. return -EINVAL;
  295. break;
  296. default:
  297. return -EINVAL;
  298. }
  299. if ((setting & supported) == 0)
  300. return -EINVAL;
  301. skge->speed = ecmd->speed;
  302. skge->duplex = ecmd->duplex;
  303. }
  304. skge->autoneg = ecmd->autoneg;
  305. skge->advertising = ecmd->advertising;
  306. if (netif_running(dev))
  307. skge_phy_reset(skge);
  308. return (0);
  309. }
  310. static void skge_get_drvinfo(struct net_device *dev,
  311. struct ethtool_drvinfo *info)
  312. {
  313. struct skge_port *skge = netdev_priv(dev);
  314. strcpy(info->driver, DRV_NAME);
  315. strcpy(info->version, DRV_VERSION);
  316. strcpy(info->fw_version, "N/A");
  317. strcpy(info->bus_info, pci_name(skge->hw->pdev));
  318. }
  319. static const struct skge_stat {
  320. char name[ETH_GSTRING_LEN];
  321. u16 xmac_offset;
  322. u16 gma_offset;
  323. } skge_stats[] = {
  324. { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
  325. { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
  326. { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
  327. { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
  328. { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
  329. { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
  330. { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
  331. { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
  332. { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
  333. { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
  334. { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
  335. { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
  336. { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
  337. { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
  338. { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
  339. { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
  340. { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
  341. { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
  342. { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
  343. { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
  344. { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
  345. };
  346. static int skge_get_stats_count(struct net_device *dev)
  347. {
  348. return ARRAY_SIZE(skge_stats);
  349. }
  350. static void skge_get_ethtool_stats(struct net_device *dev,
  351. struct ethtool_stats *stats, u64 *data)
  352. {
  353. struct skge_port *skge = netdev_priv(dev);
  354. if (skge->hw->chip_id == CHIP_ID_GENESIS)
  355. genesis_get_stats(skge, data);
  356. else
  357. yukon_get_stats(skge, data);
  358. }
  359. /* Use hardware MIB variables for critical path statistics and
  360. * transmit feedback not reported at interrupt.
  361. * Other errors are accounted for in interrupt handler.
  362. */
  363. static struct net_device_stats *skge_get_stats(struct net_device *dev)
  364. {
  365. struct skge_port *skge = netdev_priv(dev);
  366. u64 data[ARRAY_SIZE(skge_stats)];
  367. if (skge->hw->chip_id == CHIP_ID_GENESIS)
  368. genesis_get_stats(skge, data);
  369. else
  370. yukon_get_stats(skge, data);
  371. skge->net_stats.tx_bytes = data[0];
  372. skge->net_stats.rx_bytes = data[1];
  373. skge->net_stats.tx_packets = data[2] + data[4] + data[6];
  374. skge->net_stats.rx_packets = data[3] + data[5] + data[7];
  375. skge->net_stats.multicast = data[3] + data[5];
  376. skge->net_stats.collisions = data[10];
  377. skge->net_stats.tx_aborted_errors = data[12];
  378. return &skge->net_stats;
  379. }
  380. static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  381. {
  382. int i;
  383. switch (stringset) {
  384. case ETH_SS_STATS:
  385. for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
  386. memcpy(data + i * ETH_GSTRING_LEN,
  387. skge_stats[i].name, ETH_GSTRING_LEN);
  388. break;
  389. }
  390. }
  391. static void skge_get_ring_param(struct net_device *dev,
  392. struct ethtool_ringparam *p)
  393. {
  394. struct skge_port *skge = netdev_priv(dev);
  395. p->rx_max_pending = MAX_RX_RING_SIZE;
  396. p->tx_max_pending = MAX_TX_RING_SIZE;
  397. p->rx_mini_max_pending = 0;
  398. p->rx_jumbo_max_pending = 0;
  399. p->rx_pending = skge->rx_ring.count;
  400. p->tx_pending = skge->tx_ring.count;
  401. p->rx_mini_pending = 0;
  402. p->rx_jumbo_pending = 0;
  403. }
  404. static int skge_set_ring_param(struct net_device *dev,
  405. struct ethtool_ringparam *p)
  406. {
  407. struct skge_port *skge = netdev_priv(dev);
  408. int err;
  409. if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
  410. p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
  411. return -EINVAL;
  412. skge->rx_ring.count = p->rx_pending;
  413. skge->tx_ring.count = p->tx_pending;
  414. if (netif_running(dev)) {
  415. skge_down(dev);
  416. err = skge_up(dev);
  417. if (err)
  418. dev_close(dev);
  419. }
  420. return 0;
  421. }
  422. static u32 skge_get_msglevel(struct net_device *netdev)
  423. {
  424. struct skge_port *skge = netdev_priv(netdev);
  425. return skge->msg_enable;
  426. }
  427. static void skge_set_msglevel(struct net_device *netdev, u32 value)
  428. {
  429. struct skge_port *skge = netdev_priv(netdev);
  430. skge->msg_enable = value;
  431. }
  432. static int skge_nway_reset(struct net_device *dev)
  433. {
  434. struct skge_port *skge = netdev_priv(dev);
  435. if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
  436. return -EINVAL;
  437. skge_phy_reset(skge);
  438. return 0;
  439. }
  440. static int skge_set_sg(struct net_device *dev, u32 data)
  441. {
  442. struct skge_port *skge = netdev_priv(dev);
  443. struct skge_hw *hw = skge->hw;
  444. if (hw->chip_id == CHIP_ID_GENESIS && data)
  445. return -EOPNOTSUPP;
  446. return ethtool_op_set_sg(dev, data);
  447. }
  448. static int skge_set_tx_csum(struct net_device *dev, u32 data)
  449. {
  450. struct skge_port *skge = netdev_priv(dev);
  451. struct skge_hw *hw = skge->hw;
  452. if (hw->chip_id == CHIP_ID_GENESIS && data)
  453. return -EOPNOTSUPP;
  454. return ethtool_op_set_tx_csum(dev, data);
  455. }
  456. static u32 skge_get_rx_csum(struct net_device *dev)
  457. {
  458. struct skge_port *skge = netdev_priv(dev);
  459. return skge->rx_csum;
  460. }
  461. /* Only Yukon supports checksum offload. */
  462. static int skge_set_rx_csum(struct net_device *dev, u32 data)
  463. {
  464. struct skge_port *skge = netdev_priv(dev);
  465. if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
  466. return -EOPNOTSUPP;
  467. skge->rx_csum = data;
  468. return 0;
  469. }
  470. static void skge_get_pauseparam(struct net_device *dev,
  471. struct ethtool_pauseparam *ecmd)
  472. {
  473. struct skge_port *skge = netdev_priv(dev);
  474. ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
  475. || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
  476. ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
  477. ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
  478. }
  479. static int skge_set_pauseparam(struct net_device *dev,
  480. struct ethtool_pauseparam *ecmd)
  481. {
  482. struct skge_port *skge = netdev_priv(dev);
  483. struct ethtool_pauseparam old;
  484. skge_get_pauseparam(dev, &old);
  485. if (ecmd->autoneg != old.autoneg)
  486. skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
  487. else {
  488. if (ecmd->rx_pause && ecmd->tx_pause)
  489. skge->flow_control = FLOW_MODE_SYMMETRIC;
  490. else if (ecmd->rx_pause && !ecmd->tx_pause)
  491. skge->flow_control = FLOW_MODE_SYM_OR_REM;
  492. else if (!ecmd->rx_pause && ecmd->tx_pause)
  493. skge->flow_control = FLOW_MODE_LOC_SEND;
  494. else
  495. skge->flow_control = FLOW_MODE_NONE;
  496. }
  497. if (netif_running(dev))
  498. skge_phy_reset(skge);
  499. return 0;
  500. }
  501. /* Chip internal frequency for clock calculations */
  502. static inline u32 hwkhz(const struct skge_hw *hw)
  503. {
  504. return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
  505. }
  506. /* Chip HZ to microseconds */
  507. static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
  508. {
  509. return (ticks * 1000) / hwkhz(hw);
  510. }
  511. /* Microseconds to chip HZ */
  512. static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
  513. {
  514. return hwkhz(hw) * usec / 1000;
  515. }
  516. static int skge_get_coalesce(struct net_device *dev,
  517. struct ethtool_coalesce *ecmd)
  518. {
  519. struct skge_port *skge = netdev_priv(dev);
  520. struct skge_hw *hw = skge->hw;
  521. int port = skge->port;
  522. ecmd->rx_coalesce_usecs = 0;
  523. ecmd->tx_coalesce_usecs = 0;
  524. if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
  525. u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
  526. u32 msk = skge_read32(hw, B2_IRQM_MSK);
  527. if (msk & rxirqmask[port])
  528. ecmd->rx_coalesce_usecs = delay;
  529. if (msk & txirqmask[port])
  530. ecmd->tx_coalesce_usecs = delay;
  531. }
  532. return 0;
  533. }
  534. /* Note: interrupt timer is per board, but can turn on/off per port */
  535. static int skge_set_coalesce(struct net_device *dev,
  536. struct ethtool_coalesce *ecmd)
  537. {
  538. struct skge_port *skge = netdev_priv(dev);
  539. struct skge_hw *hw = skge->hw;
  540. int port = skge->port;
  541. u32 msk = skge_read32(hw, B2_IRQM_MSK);
  542. u32 delay = 25;
  543. if (ecmd->rx_coalesce_usecs == 0)
  544. msk &= ~rxirqmask[port];
  545. else if (ecmd->rx_coalesce_usecs < 25 ||
  546. ecmd->rx_coalesce_usecs > 33333)
  547. return -EINVAL;
  548. else {
  549. msk |= rxirqmask[port];
  550. delay = ecmd->rx_coalesce_usecs;
  551. }
  552. if (ecmd->tx_coalesce_usecs == 0)
  553. msk &= ~txirqmask[port];
  554. else if (ecmd->tx_coalesce_usecs < 25 ||
  555. ecmd->tx_coalesce_usecs > 33333)
  556. return -EINVAL;
  557. else {
  558. msk |= txirqmask[port];
  559. delay = min(delay, ecmd->rx_coalesce_usecs);
  560. }
  561. skge_write32(hw, B2_IRQM_MSK, msk);
  562. if (msk == 0)
  563. skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
  564. else {
  565. skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
  566. skge_write32(hw, B2_IRQM_CTRL, TIM_START);
  567. }
  568. return 0;
  569. }
  570. enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
  571. static void skge_led(struct skge_port *skge, enum led_mode mode)
  572. {
  573. struct skge_hw *hw = skge->hw;
  574. int port = skge->port;
  575. spin_lock_bh(&hw->phy_lock);
  576. if (hw->chip_id == CHIP_ID_GENESIS) {
  577. switch (mode) {
  578. case LED_MODE_OFF:
  579. if (hw->phy_type == SK_PHY_BCOM)
  580. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
  581. else {
  582. skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
  583. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
  584. }
  585. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  586. skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
  587. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
  588. break;
  589. case LED_MODE_ON:
  590. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
  591. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
  592. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  593. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
  594. break;
  595. case LED_MODE_TST:
  596. skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
  597. skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
  598. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  599. if (hw->phy_type == SK_PHY_BCOM)
  600. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
  601. else {
  602. skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
  603. skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
  604. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
  605. }
  606. }
  607. } else {
  608. switch (mode) {
  609. case LED_MODE_OFF:
  610. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  611. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  612. PHY_M_LED_MO_DUP(MO_LED_OFF) |
  613. PHY_M_LED_MO_10(MO_LED_OFF) |
  614. PHY_M_LED_MO_100(MO_LED_OFF) |
  615. PHY_M_LED_MO_1000(MO_LED_OFF) |
  616. PHY_M_LED_MO_RX(MO_LED_OFF));
  617. break;
  618. case LED_MODE_ON:
  619. gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
  620. PHY_M_LED_PULS_DUR(PULS_170MS) |
  621. PHY_M_LED_BLINK_RT(BLINK_84MS) |
  622. PHY_M_LEDC_TX_CTRL |
  623. PHY_M_LEDC_DP_CTRL);
  624. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  625. PHY_M_LED_MO_RX(MO_LED_OFF) |
  626. (skge->speed == SPEED_100 ?
  627. PHY_M_LED_MO_100(MO_LED_ON) : 0));
  628. break;
  629. case LED_MODE_TST:
  630. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  631. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  632. PHY_M_LED_MO_DUP(MO_LED_ON) |
  633. PHY_M_LED_MO_10(MO_LED_ON) |
  634. PHY_M_LED_MO_100(MO_LED_ON) |
  635. PHY_M_LED_MO_1000(MO_LED_ON) |
  636. PHY_M_LED_MO_RX(MO_LED_ON));
  637. }
  638. }
  639. spin_unlock_bh(&hw->phy_lock);
  640. }
  641. /* blink LED's for finding board */
  642. static int skge_phys_id(struct net_device *dev, u32 data)
  643. {
  644. struct skge_port *skge = netdev_priv(dev);
  645. unsigned long ms;
  646. enum led_mode mode = LED_MODE_TST;
  647. if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
  648. ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
  649. else
  650. ms = data * 1000;
  651. while (ms > 0) {
  652. skge_led(skge, mode);
  653. mode ^= LED_MODE_TST;
  654. if (msleep_interruptible(BLINK_MS))
  655. break;
  656. ms -= BLINK_MS;
  657. }
  658. /* back to regular LED state */
  659. skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
  660. return 0;
  661. }
  662. static const struct ethtool_ops skge_ethtool_ops = {
  663. .get_settings = skge_get_settings,
  664. .set_settings = skge_set_settings,
  665. .get_drvinfo = skge_get_drvinfo,
  666. .get_regs_len = skge_get_regs_len,
  667. .get_regs = skge_get_regs,
  668. .get_wol = skge_get_wol,
  669. .set_wol = skge_set_wol,
  670. .get_msglevel = skge_get_msglevel,
  671. .set_msglevel = skge_set_msglevel,
  672. .nway_reset = skge_nway_reset,
  673. .get_link = ethtool_op_get_link,
  674. .get_ringparam = skge_get_ring_param,
  675. .set_ringparam = skge_set_ring_param,
  676. .get_pauseparam = skge_get_pauseparam,
  677. .set_pauseparam = skge_set_pauseparam,
  678. .get_coalesce = skge_get_coalesce,
  679. .set_coalesce = skge_set_coalesce,
  680. .get_sg = ethtool_op_get_sg,
  681. .set_sg = skge_set_sg,
  682. .get_tx_csum = ethtool_op_get_tx_csum,
  683. .set_tx_csum = skge_set_tx_csum,
  684. .get_rx_csum = skge_get_rx_csum,
  685. .set_rx_csum = skge_set_rx_csum,
  686. .get_strings = skge_get_strings,
  687. .phys_id = skge_phys_id,
  688. .get_stats_count = skge_get_stats_count,
  689. .get_ethtool_stats = skge_get_ethtool_stats,
  690. .get_perm_addr = ethtool_op_get_perm_addr,
  691. };
  692. /*
  693. * Allocate ring elements and chain them together
  694. * One-to-one association of board descriptors with ring elements
  695. */
  696. static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
  697. {
  698. struct skge_tx_desc *d;
  699. struct skge_element *e;
  700. int i;
  701. ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
  702. if (!ring->start)
  703. return -ENOMEM;
  704. for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
  705. e->desc = d;
  706. if (i == ring->count - 1) {
  707. e->next = ring->start;
  708. d->next_offset = base;
  709. } else {
  710. e->next = e + 1;
  711. d->next_offset = base + (i+1) * sizeof(*d);
  712. }
  713. }
  714. ring->to_use = ring->to_clean = ring->start;
  715. return 0;
  716. }
  717. /* Allocate and setup a new buffer for receiving */
  718. static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
  719. struct sk_buff *skb, unsigned int bufsize)
  720. {
  721. struct skge_rx_desc *rd = e->desc;
  722. u64 map;
  723. map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
  724. PCI_DMA_FROMDEVICE);
  725. rd->dma_lo = map;
  726. rd->dma_hi = map >> 32;
  727. e->skb = skb;
  728. rd->csum1_start = ETH_HLEN;
  729. rd->csum2_start = ETH_HLEN;
  730. rd->csum1 = 0;
  731. rd->csum2 = 0;
  732. wmb();
  733. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
  734. pci_unmap_addr_set(e, mapaddr, map);
  735. pci_unmap_len_set(e, maplen, bufsize);
  736. }
  737. /* Resume receiving using existing skb,
  738. * Note: DMA address is not changed by chip.
  739. * MTU not changed while receiver active.
  740. */
  741. static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
  742. {
  743. struct skge_rx_desc *rd = e->desc;
  744. rd->csum2 = 0;
  745. rd->csum2_start = ETH_HLEN;
  746. wmb();
  747. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
  748. }
  749. /* Free all buffers in receive ring, assumes receiver stopped */
  750. static void skge_rx_clean(struct skge_port *skge)
  751. {
  752. struct skge_hw *hw = skge->hw;
  753. struct skge_ring *ring = &skge->rx_ring;
  754. struct skge_element *e;
  755. e = ring->start;
  756. do {
  757. struct skge_rx_desc *rd = e->desc;
  758. rd->control = 0;
  759. if (e->skb) {
  760. pci_unmap_single(hw->pdev,
  761. pci_unmap_addr(e, mapaddr),
  762. pci_unmap_len(e, maplen),
  763. PCI_DMA_FROMDEVICE);
  764. dev_kfree_skb(e->skb);
  765. e->skb = NULL;
  766. }
  767. } while ((e = e->next) != ring->start);
  768. }
  769. /* Allocate buffers for receive ring
  770. * For receive: to_clean is next received frame.
  771. */
  772. static int skge_rx_fill(struct net_device *dev)
  773. {
  774. struct skge_port *skge = netdev_priv(dev);
  775. struct skge_ring *ring = &skge->rx_ring;
  776. struct skge_element *e;
  777. e = ring->start;
  778. do {
  779. struct sk_buff *skb;
  780. skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
  781. GFP_KERNEL);
  782. if (!skb)
  783. return -ENOMEM;
  784. skb_reserve(skb, NET_IP_ALIGN);
  785. skge_rx_setup(skge, e, skb, skge->rx_buf_size);
  786. } while ( (e = e->next) != ring->start);
  787. ring->to_clean = ring->start;
  788. return 0;
  789. }
  790. static const char *skge_pause(enum pause_status status)
  791. {
  792. switch(status) {
  793. case FLOW_STAT_NONE:
  794. return "none";
  795. case FLOW_STAT_REM_SEND:
  796. return "rx only";
  797. case FLOW_STAT_LOC_SEND:
  798. return "tx_only";
  799. case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
  800. return "both";
  801. default:
  802. return "indeterminated";
  803. }
  804. }
  805. static void skge_link_up(struct skge_port *skge)
  806. {
  807. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
  808. LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
  809. netif_carrier_on(skge->netdev);
  810. netif_wake_queue(skge->netdev);
  811. if (netif_msg_link(skge)) {
  812. printk(KERN_INFO PFX
  813. "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
  814. skge->netdev->name, skge->speed,
  815. skge->duplex == DUPLEX_FULL ? "full" : "half",
  816. skge_pause(skge->flow_status));
  817. }
  818. }
  819. static void skge_link_down(struct skge_port *skge)
  820. {
  821. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
  822. netif_carrier_off(skge->netdev);
  823. netif_stop_queue(skge->netdev);
  824. if (netif_msg_link(skge))
  825. printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
  826. }
  827. static void xm_link_down(struct skge_hw *hw, int port)
  828. {
  829. struct net_device *dev = hw->dev[port];
  830. struct skge_port *skge = netdev_priv(dev);
  831. u16 cmd, msk;
  832. if (hw->phy_type == SK_PHY_XMAC) {
  833. msk = xm_read16(hw, port, XM_IMSK);
  834. msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
  835. xm_write16(hw, port, XM_IMSK, msk);
  836. }
  837. cmd = xm_read16(hw, port, XM_MMU_CMD);
  838. cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  839. xm_write16(hw, port, XM_MMU_CMD, cmd);
  840. /* dummy read to ensure writing */
  841. (void) xm_read16(hw, port, XM_MMU_CMD);
  842. if (netif_carrier_ok(dev))
  843. skge_link_down(skge);
  844. }
  845. static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
  846. {
  847. int i;
  848. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  849. *val = xm_read16(hw, port, XM_PHY_DATA);
  850. if (hw->phy_type == SK_PHY_XMAC)
  851. goto ready;
  852. for (i = 0; i < PHY_RETRIES; i++) {
  853. if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
  854. goto ready;
  855. udelay(1);
  856. }
  857. return -ETIMEDOUT;
  858. ready:
  859. *val = xm_read16(hw, port, XM_PHY_DATA);
  860. return 0;
  861. }
  862. static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
  863. {
  864. u16 v = 0;
  865. if (__xm_phy_read(hw, port, reg, &v))
  866. printk(KERN_WARNING PFX "%s: phy read timed out\n",
  867. hw->dev[port]->name);
  868. return v;
  869. }
  870. static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  871. {
  872. int i;
  873. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  874. for (i = 0; i < PHY_RETRIES; i++) {
  875. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  876. goto ready;
  877. udelay(1);
  878. }
  879. return -EIO;
  880. ready:
  881. xm_write16(hw, port, XM_PHY_DATA, val);
  882. for (i = 0; i < PHY_RETRIES; i++) {
  883. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  884. return 0;
  885. udelay(1);
  886. }
  887. return -ETIMEDOUT;
  888. }
  889. static void genesis_init(struct skge_hw *hw)
  890. {
  891. /* set blink source counter */
  892. skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
  893. skge_write8(hw, B2_BSC_CTRL, BSC_START);
  894. /* configure mac arbiter */
  895. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  896. /* configure mac arbiter timeout values */
  897. skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
  898. skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
  899. skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
  900. skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
  901. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  902. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  903. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  904. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  905. /* configure packet arbiter timeout */
  906. skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
  907. skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
  908. skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
  909. skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
  910. skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
  911. }
  912. static void genesis_reset(struct skge_hw *hw, int port)
  913. {
  914. const u8 zero[8] = { 0 };
  915. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  916. /* reset the statistics module */
  917. xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
  918. xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
  919. xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
  920. xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
  921. xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
  922. /* disable Broadcom PHY IRQ */
  923. if (hw->phy_type == SK_PHY_BCOM)
  924. xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
  925. xm_outhash(hw, port, XM_HSM, zero);
  926. }
  927. /* Convert mode to MII values */
  928. static const u16 phy_pause_map[] = {
  929. [FLOW_MODE_NONE] = 0,
  930. [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
  931. [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
  932. [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
  933. };
  934. /* special defines for FIBER (88E1011S only) */
  935. static const u16 fiber_pause_map[] = {
  936. [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
  937. [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
  938. [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
  939. [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
  940. };
  941. /* Check status of Broadcom phy link */
  942. static void bcom_check_link(struct skge_hw *hw, int port)
  943. {
  944. struct net_device *dev = hw->dev[port];
  945. struct skge_port *skge = netdev_priv(dev);
  946. u16 status;
  947. /* read twice because of latch */
  948. (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
  949. status = xm_phy_read(hw, port, PHY_BCOM_STAT);
  950. if ((status & PHY_ST_LSYNC) == 0) {
  951. xm_link_down(hw, port);
  952. return;
  953. }
  954. if (skge->autoneg == AUTONEG_ENABLE) {
  955. u16 lpa, aux;
  956. if (!(status & PHY_ST_AN_OVER))
  957. return;
  958. lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
  959. if (lpa & PHY_B_AN_RF) {
  960. printk(KERN_NOTICE PFX "%s: remote fault\n",
  961. dev->name);
  962. return;
  963. }
  964. aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
  965. /* Check Duplex mismatch */
  966. switch (aux & PHY_B_AS_AN_RES_MSK) {
  967. case PHY_B_RES_1000FD:
  968. skge->duplex = DUPLEX_FULL;
  969. break;
  970. case PHY_B_RES_1000HD:
  971. skge->duplex = DUPLEX_HALF;
  972. break;
  973. default:
  974. printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
  975. dev->name);
  976. return;
  977. }
  978. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  979. switch (aux & PHY_B_AS_PAUSE_MSK) {
  980. case PHY_B_AS_PAUSE_MSK:
  981. skge->flow_status = FLOW_STAT_SYMMETRIC;
  982. break;
  983. case PHY_B_AS_PRR:
  984. skge->flow_status = FLOW_STAT_REM_SEND;
  985. break;
  986. case PHY_B_AS_PRT:
  987. skge->flow_status = FLOW_STAT_LOC_SEND;
  988. break;
  989. default:
  990. skge->flow_status = FLOW_STAT_NONE;
  991. }
  992. skge->speed = SPEED_1000;
  993. }
  994. if (!netif_carrier_ok(dev))
  995. genesis_link_up(skge);
  996. }
  997. /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
  998. * Phy on for 100 or 10Mbit operation
  999. */
  1000. static void bcom_phy_init(struct skge_port *skge)
  1001. {
  1002. struct skge_hw *hw = skge->hw;
  1003. int port = skge->port;
  1004. int i;
  1005. u16 id1, r, ext, ctl;
  1006. /* magic workaround patterns for Broadcom */
  1007. static const struct {
  1008. u16 reg;
  1009. u16 val;
  1010. } A1hack[] = {
  1011. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
  1012. { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
  1013. { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
  1014. { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
  1015. }, C0hack[] = {
  1016. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
  1017. { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
  1018. };
  1019. /* read Id from external PHY (all have the same address) */
  1020. id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
  1021. /* Optimize MDIO transfer by suppressing preamble. */
  1022. r = xm_read16(hw, port, XM_MMU_CMD);
  1023. r |= XM_MMU_NO_PRE;
  1024. xm_write16(hw, port, XM_MMU_CMD,r);
  1025. switch (id1) {
  1026. case PHY_BCOM_ID1_C0:
  1027. /*
  1028. * Workaround BCOM Errata for the C0 type.
  1029. * Write magic patterns to reserved registers.
  1030. */
  1031. for (i = 0; i < ARRAY_SIZE(C0hack); i++)
  1032. xm_phy_write(hw, port,
  1033. C0hack[i].reg, C0hack[i].val);
  1034. break;
  1035. case PHY_BCOM_ID1_A1:
  1036. /*
  1037. * Workaround BCOM Errata for the A1 type.
  1038. * Write magic patterns to reserved registers.
  1039. */
  1040. for (i = 0; i < ARRAY_SIZE(A1hack); i++)
  1041. xm_phy_write(hw, port,
  1042. A1hack[i].reg, A1hack[i].val);
  1043. break;
  1044. }
  1045. /*
  1046. * Workaround BCOM Errata (#10523) for all BCom PHYs.
  1047. * Disable Power Management after reset.
  1048. */
  1049. r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
  1050. r |= PHY_B_AC_DIS_PM;
  1051. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
  1052. /* Dummy read */
  1053. xm_read16(hw, port, XM_ISRC);
  1054. ext = PHY_B_PEC_EN_LTR; /* enable tx led */
  1055. ctl = PHY_CT_SP1000; /* always 1000mbit */
  1056. if (skge->autoneg == AUTONEG_ENABLE) {
  1057. /*
  1058. * Workaround BCOM Errata #1 for the C5 type.
  1059. * 1000Base-T Link Acquisition Failure in Slave Mode
  1060. * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
  1061. */
  1062. u16 adv = PHY_B_1000C_RD;
  1063. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1064. adv |= PHY_B_1000C_AHD;
  1065. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1066. adv |= PHY_B_1000C_AFD;
  1067. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
  1068. ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  1069. } else {
  1070. if (skge->duplex == DUPLEX_FULL)
  1071. ctl |= PHY_CT_DUP_MD;
  1072. /* Force to slave */
  1073. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
  1074. }
  1075. /* Set autonegotiation pause parameters */
  1076. xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
  1077. phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
  1078. /* Handle Jumbo frames */
  1079. if (hw->dev[port]->mtu > ETH_DATA_LEN) {
  1080. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
  1081. PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
  1082. ext |= PHY_B_PEC_HIGH_LA;
  1083. }
  1084. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
  1085. xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
  1086. /* Use link status change interrupt */
  1087. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  1088. }
  1089. static void xm_phy_init(struct skge_port *skge)
  1090. {
  1091. struct skge_hw *hw = skge->hw;
  1092. int port = skge->port;
  1093. u16 ctrl = 0;
  1094. if (skge->autoneg == AUTONEG_ENABLE) {
  1095. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1096. ctrl |= PHY_X_AN_HD;
  1097. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1098. ctrl |= PHY_X_AN_FD;
  1099. ctrl |= fiber_pause_map[skge->flow_control];
  1100. xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
  1101. /* Restart Auto-negotiation */
  1102. ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
  1103. } else {
  1104. /* Set DuplexMode in Config register */
  1105. if (skge->duplex == DUPLEX_FULL)
  1106. ctrl |= PHY_CT_DUP_MD;
  1107. /*
  1108. * Do NOT enable Auto-negotiation here. This would hold
  1109. * the link down because no IDLEs are transmitted
  1110. */
  1111. }
  1112. xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
  1113. /* Poll PHY for status changes */
  1114. mod_timer(&skge->link_timer, jiffies + LINK_HZ);
  1115. }
  1116. static void xm_check_link(struct net_device *dev)
  1117. {
  1118. struct skge_port *skge = netdev_priv(dev);
  1119. struct skge_hw *hw = skge->hw;
  1120. int port = skge->port;
  1121. u16 status;
  1122. /* read twice because of latch */
  1123. (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
  1124. status = xm_phy_read(hw, port, PHY_XMAC_STAT);
  1125. if ((status & PHY_ST_LSYNC) == 0) {
  1126. xm_link_down(hw, port);
  1127. return;
  1128. }
  1129. if (skge->autoneg == AUTONEG_ENABLE) {
  1130. u16 lpa, res;
  1131. if (!(status & PHY_ST_AN_OVER))
  1132. return;
  1133. lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
  1134. if (lpa & PHY_B_AN_RF) {
  1135. printk(KERN_NOTICE PFX "%s: remote fault\n",
  1136. dev->name);
  1137. return;
  1138. }
  1139. res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
  1140. /* Check Duplex mismatch */
  1141. switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
  1142. case PHY_X_RS_FD:
  1143. skge->duplex = DUPLEX_FULL;
  1144. break;
  1145. case PHY_X_RS_HD:
  1146. skge->duplex = DUPLEX_HALF;
  1147. break;
  1148. default:
  1149. printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
  1150. dev->name);
  1151. return;
  1152. }
  1153. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  1154. if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
  1155. skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
  1156. (lpa & PHY_X_P_SYM_MD))
  1157. skge->flow_status = FLOW_STAT_SYMMETRIC;
  1158. else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
  1159. (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
  1160. /* Enable PAUSE receive, disable PAUSE transmit */
  1161. skge->flow_status = FLOW_STAT_REM_SEND;
  1162. else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
  1163. (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
  1164. /* Disable PAUSE receive, enable PAUSE transmit */
  1165. skge->flow_status = FLOW_STAT_LOC_SEND;
  1166. else
  1167. skge->flow_status = FLOW_STAT_NONE;
  1168. skge->speed = SPEED_1000;
  1169. }
  1170. if (!netif_carrier_ok(dev))
  1171. genesis_link_up(skge);
  1172. }
  1173. /* Poll to check for link coming up.
  1174. * Since internal PHY is wired to a level triggered pin, can't
  1175. * get an interrupt when carrier is detected.
  1176. */
  1177. static void xm_link_timer(unsigned long arg)
  1178. {
  1179. struct skge_port *skge = (struct skge_port *) arg;
  1180. struct net_device *dev = skge->netdev;
  1181. struct skge_hw *hw = skge->hw;
  1182. int port = skge->port;
  1183. if (!netif_running(dev))
  1184. return;
  1185. if (netif_carrier_ok(dev)) {
  1186. xm_read16(hw, port, XM_ISRC);
  1187. if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
  1188. goto nochange;
  1189. } else {
  1190. if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
  1191. goto nochange;
  1192. xm_read16(hw, port, XM_ISRC);
  1193. if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
  1194. goto nochange;
  1195. }
  1196. spin_lock(&hw->phy_lock);
  1197. xm_check_link(dev);
  1198. spin_unlock(&hw->phy_lock);
  1199. nochange:
  1200. if (netif_running(dev))
  1201. mod_timer(&skge->link_timer, jiffies + LINK_HZ);
  1202. }
  1203. static void genesis_mac_init(struct skge_hw *hw, int port)
  1204. {
  1205. struct net_device *dev = hw->dev[port];
  1206. struct skge_port *skge = netdev_priv(dev);
  1207. int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
  1208. int i;
  1209. u32 r;
  1210. const u8 zero[6] = { 0 };
  1211. for (i = 0; i < 10; i++) {
  1212. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
  1213. MFF_SET_MAC_RST);
  1214. if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
  1215. goto reset_ok;
  1216. udelay(1);
  1217. }
  1218. printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
  1219. reset_ok:
  1220. /* Unreset the XMAC. */
  1221. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  1222. /*
  1223. * Perform additional initialization for external PHYs,
  1224. * namely for the 1000baseTX cards that use the XMAC's
  1225. * GMII mode.
  1226. */
  1227. if (hw->phy_type != SK_PHY_XMAC) {
  1228. /* Take external Phy out of reset */
  1229. r = skge_read32(hw, B2_GP_IO);
  1230. if (port == 0)
  1231. r |= GP_DIR_0|GP_IO_0;
  1232. else
  1233. r |= GP_DIR_2|GP_IO_2;
  1234. skge_write32(hw, B2_GP_IO, r);
  1235. /* Enable GMII interface */
  1236. xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
  1237. }
  1238. switch(hw->phy_type) {
  1239. case SK_PHY_XMAC:
  1240. xm_phy_init(skge);
  1241. break;
  1242. case SK_PHY_BCOM:
  1243. bcom_phy_init(skge);
  1244. bcom_check_link(hw, port);
  1245. }
  1246. /* Set Station Address */
  1247. xm_outaddr(hw, port, XM_SA, dev->dev_addr);
  1248. /* We don't use match addresses so clear */
  1249. for (i = 1; i < 16; i++)
  1250. xm_outaddr(hw, port, XM_EXM(i), zero);
  1251. /* Clear MIB counters */
  1252. xm_write16(hw, port, XM_STAT_CMD,
  1253. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  1254. /* Clear two times according to Errata #3 */
  1255. xm_write16(hw, port, XM_STAT_CMD,
  1256. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  1257. /* configure Rx High Water Mark (XM_RX_HI_WM) */
  1258. xm_write16(hw, port, XM_RX_HI_WM, 1450);
  1259. /* We don't need the FCS appended to the packet. */
  1260. r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
  1261. if (jumbo)
  1262. r |= XM_RX_BIG_PK_OK;
  1263. if (skge->duplex == DUPLEX_HALF) {
  1264. /*
  1265. * If in manual half duplex mode the other side might be in
  1266. * full duplex mode, so ignore if a carrier extension is not seen
  1267. * on frames received
  1268. */
  1269. r |= XM_RX_DIS_CEXT;
  1270. }
  1271. xm_write16(hw, port, XM_RX_CMD, r);
  1272. /* We want short frames padded to 60 bytes. */
  1273. xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
  1274. /*
  1275. * Bump up the transmit threshold. This helps hold off transmit
  1276. * underruns when we're blasting traffic from both ports at once.
  1277. */
  1278. xm_write16(hw, port, XM_TX_THR, 512);
  1279. /*
  1280. * Enable the reception of all error frames. This is is
  1281. * a necessary evil due to the design of the XMAC. The
  1282. * XMAC's receive FIFO is only 8K in size, however jumbo
  1283. * frames can be up to 9000 bytes in length. When bad
  1284. * frame filtering is enabled, the XMAC's RX FIFO operates
  1285. * in 'store and forward' mode. For this to work, the
  1286. * entire frame has to fit into the FIFO, but that means
  1287. * that jumbo frames larger than 8192 bytes will be
  1288. * truncated. Disabling all bad frame filtering causes
  1289. * the RX FIFO to operate in streaming mode, in which
  1290. * case the XMAC will start transferring frames out of the
  1291. * RX FIFO as soon as the FIFO threshold is reached.
  1292. */
  1293. xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
  1294. /*
  1295. * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
  1296. * - Enable all bits excepting 'Octets Rx OK Low CntOv'
  1297. * and 'Octets Rx OK Hi Cnt Ov'.
  1298. */
  1299. xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
  1300. /*
  1301. * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
  1302. * - Enable all bits excepting 'Octets Tx OK Low CntOv'
  1303. * and 'Octets Tx OK Hi Cnt Ov'.
  1304. */
  1305. xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
  1306. /* Configure MAC arbiter */
  1307. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  1308. /* configure timeout values */
  1309. skge_write8(hw, B3_MA_TOINI_RX1, 72);
  1310. skge_write8(hw, B3_MA_TOINI_RX2, 72);
  1311. skge_write8(hw, B3_MA_TOINI_TX1, 72);
  1312. skge_write8(hw, B3_MA_TOINI_TX2, 72);
  1313. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  1314. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  1315. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  1316. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  1317. /* Configure Rx MAC FIFO */
  1318. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
  1319. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
  1320. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
  1321. /* Configure Tx MAC FIFO */
  1322. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
  1323. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
  1324. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
  1325. if (jumbo) {
  1326. /* Enable frame flushing if jumbo frames used */
  1327. skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
  1328. } else {
  1329. /* enable timeout timers if normal frames */
  1330. skge_write16(hw, B3_PA_CTRL,
  1331. (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
  1332. }
  1333. }
  1334. static void genesis_stop(struct skge_port *skge)
  1335. {
  1336. struct skge_hw *hw = skge->hw;
  1337. int port = skge->port;
  1338. u32 reg;
  1339. genesis_reset(hw, port);
  1340. /* Clear Tx packet arbiter timeout IRQ */
  1341. skge_write16(hw, B3_PA_CTRL,
  1342. port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
  1343. /*
  1344. * If the transfer sticks at the MAC the STOP command will not
  1345. * terminate if we don't flush the XMAC's transmit FIFO !
  1346. */
  1347. xm_write32(hw, port, XM_MODE,
  1348. xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
  1349. /* Reset the MAC */
  1350. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
  1351. /* For external PHYs there must be special handling */
  1352. if (hw->phy_type != SK_PHY_XMAC) {
  1353. reg = skge_read32(hw, B2_GP_IO);
  1354. if (port == 0) {
  1355. reg |= GP_DIR_0;
  1356. reg &= ~GP_IO_0;
  1357. } else {
  1358. reg |= GP_DIR_2;
  1359. reg &= ~GP_IO_2;
  1360. }
  1361. skge_write32(hw, B2_GP_IO, reg);
  1362. skge_read32(hw, B2_GP_IO);
  1363. }
  1364. xm_write16(hw, port, XM_MMU_CMD,
  1365. xm_read16(hw, port, XM_MMU_CMD)
  1366. & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
  1367. xm_read16(hw, port, XM_MMU_CMD);
  1368. }
  1369. static void genesis_get_stats(struct skge_port *skge, u64 *data)
  1370. {
  1371. struct skge_hw *hw = skge->hw;
  1372. int port = skge->port;
  1373. int i;
  1374. unsigned long timeout = jiffies + HZ;
  1375. xm_write16(hw, port,
  1376. XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
  1377. /* wait for update to complete */
  1378. while (xm_read16(hw, port, XM_STAT_CMD)
  1379. & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
  1380. if (time_after(jiffies, timeout))
  1381. break;
  1382. udelay(10);
  1383. }
  1384. /* special case for 64 bit octet counter */
  1385. data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
  1386. | xm_read32(hw, port, XM_TXO_OK_LO);
  1387. data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
  1388. | xm_read32(hw, port, XM_RXO_OK_LO);
  1389. for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
  1390. data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
  1391. }
  1392. static void genesis_mac_intr(struct skge_hw *hw, int port)
  1393. {
  1394. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1395. u16 status = xm_read16(hw, port, XM_ISRC);
  1396. if (netif_msg_intr(skge))
  1397. printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
  1398. skge->netdev->name, status);
  1399. if (hw->phy_type == SK_PHY_XMAC &&
  1400. (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
  1401. xm_link_down(hw, port);
  1402. if (status & XM_IS_TXF_UR) {
  1403. xm_write32(hw, port, XM_MODE, XM_MD_FTF);
  1404. ++skge->net_stats.tx_fifo_errors;
  1405. }
  1406. if (status & XM_IS_RXF_OV) {
  1407. xm_write32(hw, port, XM_MODE, XM_MD_FRF);
  1408. ++skge->net_stats.rx_fifo_errors;
  1409. }
  1410. }
  1411. static void genesis_link_up(struct skge_port *skge)
  1412. {
  1413. struct skge_hw *hw = skge->hw;
  1414. int port = skge->port;
  1415. u16 cmd, msk;
  1416. u32 mode;
  1417. cmd = xm_read16(hw, port, XM_MMU_CMD);
  1418. /*
  1419. * enabling pause frame reception is required for 1000BT
  1420. * because the XMAC is not reset if the link is going down
  1421. */
  1422. if (skge->flow_status == FLOW_STAT_NONE ||
  1423. skge->flow_status == FLOW_STAT_LOC_SEND)
  1424. /* Disable Pause Frame Reception */
  1425. cmd |= XM_MMU_IGN_PF;
  1426. else
  1427. /* Enable Pause Frame Reception */
  1428. cmd &= ~XM_MMU_IGN_PF;
  1429. xm_write16(hw, port, XM_MMU_CMD, cmd);
  1430. mode = xm_read32(hw, port, XM_MODE);
  1431. if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
  1432. skge->flow_status == FLOW_STAT_LOC_SEND) {
  1433. /*
  1434. * Configure Pause Frame Generation
  1435. * Use internal and external Pause Frame Generation.
  1436. * Sending pause frames is edge triggered.
  1437. * Send a Pause frame with the maximum pause time if
  1438. * internal oder external FIFO full condition occurs.
  1439. * Send a zero pause time frame to re-start transmission.
  1440. */
  1441. /* XM_PAUSE_DA = '010000C28001' (default) */
  1442. /* XM_MAC_PTIME = 0xffff (maximum) */
  1443. /* remember this value is defined in big endian (!) */
  1444. xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
  1445. mode |= XM_PAUSE_MODE;
  1446. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
  1447. } else {
  1448. /*
  1449. * disable pause frame generation is required for 1000BT
  1450. * because the XMAC is not reset if the link is going down
  1451. */
  1452. /* Disable Pause Mode in Mode Register */
  1453. mode &= ~XM_PAUSE_MODE;
  1454. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
  1455. }
  1456. xm_write32(hw, port, XM_MODE, mode);
  1457. msk = XM_DEF_MSK;
  1458. if (hw->phy_type != SK_PHY_XMAC)
  1459. msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
  1460. xm_write16(hw, port, XM_IMSK, msk);
  1461. xm_read16(hw, port, XM_ISRC);
  1462. /* get MMU Command Reg. */
  1463. cmd = xm_read16(hw, port, XM_MMU_CMD);
  1464. if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
  1465. cmd |= XM_MMU_GMII_FD;
  1466. /*
  1467. * Workaround BCOM Errata (#10523) for all BCom Phys
  1468. * Enable Power Management after link up
  1469. */
  1470. if (hw->phy_type == SK_PHY_BCOM) {
  1471. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
  1472. xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
  1473. & ~PHY_B_AC_DIS_PM);
  1474. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  1475. }
  1476. /* enable Rx/Tx */
  1477. xm_write16(hw, port, XM_MMU_CMD,
  1478. cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  1479. skge_link_up(skge);
  1480. }
  1481. static inline void bcom_phy_intr(struct skge_port *skge)
  1482. {
  1483. struct skge_hw *hw = skge->hw;
  1484. int port = skge->port;
  1485. u16 isrc;
  1486. isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
  1487. if (netif_msg_intr(skge))
  1488. printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
  1489. skge->netdev->name, isrc);
  1490. if (isrc & PHY_B_IS_PSE)
  1491. printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
  1492. hw->dev[port]->name);
  1493. /* Workaround BCom Errata:
  1494. * enable and disable loopback mode if "NO HCD" occurs.
  1495. */
  1496. if (isrc & PHY_B_IS_NO_HDCL) {
  1497. u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
  1498. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  1499. ctrl | PHY_CT_LOOP);
  1500. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  1501. ctrl & ~PHY_CT_LOOP);
  1502. }
  1503. if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
  1504. bcom_check_link(hw, port);
  1505. }
  1506. static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  1507. {
  1508. int i;
  1509. gma_write16(hw, port, GM_SMI_DATA, val);
  1510. gma_write16(hw, port, GM_SMI_CTRL,
  1511. GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
  1512. for (i = 0; i < PHY_RETRIES; i++) {
  1513. udelay(1);
  1514. if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
  1515. return 0;
  1516. }
  1517. printk(KERN_WARNING PFX "%s: phy write timeout\n",
  1518. hw->dev[port]->name);
  1519. return -EIO;
  1520. }
  1521. static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
  1522. {
  1523. int i;
  1524. gma_write16(hw, port, GM_SMI_CTRL,
  1525. GM_SMI_CT_PHY_AD(hw->phy_addr)
  1526. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  1527. for (i = 0; i < PHY_RETRIES; i++) {
  1528. udelay(1);
  1529. if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
  1530. goto ready;
  1531. }
  1532. return -ETIMEDOUT;
  1533. ready:
  1534. *val = gma_read16(hw, port, GM_SMI_DATA);
  1535. return 0;
  1536. }
  1537. static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
  1538. {
  1539. u16 v = 0;
  1540. if (__gm_phy_read(hw, port, reg, &v))
  1541. printk(KERN_WARNING PFX "%s: phy read timeout\n",
  1542. hw->dev[port]->name);
  1543. return v;
  1544. }
  1545. /* Marvell Phy Initialization */
  1546. static void yukon_init(struct skge_hw *hw, int port)
  1547. {
  1548. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1549. u16 ctrl, ct1000, adv;
  1550. if (skge->autoneg == AUTONEG_ENABLE) {
  1551. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  1552. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  1553. PHY_M_EC_MAC_S_MSK);
  1554. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  1555. ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
  1556. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  1557. }
  1558. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1559. if (skge->autoneg == AUTONEG_DISABLE)
  1560. ctrl &= ~PHY_CT_ANE;
  1561. ctrl |= PHY_CT_RESET;
  1562. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1563. ctrl = 0;
  1564. ct1000 = 0;
  1565. adv = PHY_AN_CSMA;
  1566. if (skge->autoneg == AUTONEG_ENABLE) {
  1567. if (hw->copper) {
  1568. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1569. ct1000 |= PHY_M_1000C_AFD;
  1570. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1571. ct1000 |= PHY_M_1000C_AHD;
  1572. if (skge->advertising & ADVERTISED_100baseT_Full)
  1573. adv |= PHY_M_AN_100_FD;
  1574. if (skge->advertising & ADVERTISED_100baseT_Half)
  1575. adv |= PHY_M_AN_100_HD;
  1576. if (skge->advertising & ADVERTISED_10baseT_Full)
  1577. adv |= PHY_M_AN_10_FD;
  1578. if (skge->advertising & ADVERTISED_10baseT_Half)
  1579. adv |= PHY_M_AN_10_HD;
  1580. /* Set Flow-control capabilities */
  1581. adv |= phy_pause_map[skge->flow_control];
  1582. } else {
  1583. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1584. adv |= PHY_M_AN_1000X_AFD;
  1585. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1586. adv |= PHY_M_AN_1000X_AHD;
  1587. adv |= fiber_pause_map[skge->flow_control];
  1588. }
  1589. /* Restart Auto-negotiation */
  1590. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  1591. } else {
  1592. /* forced speed/duplex settings */
  1593. ct1000 = PHY_M_1000C_MSE;
  1594. if (skge->duplex == DUPLEX_FULL)
  1595. ctrl |= PHY_CT_DUP_MD;
  1596. switch (skge->speed) {
  1597. case SPEED_1000:
  1598. ctrl |= PHY_CT_SP1000;
  1599. break;
  1600. case SPEED_100:
  1601. ctrl |= PHY_CT_SP100;
  1602. break;
  1603. }
  1604. ctrl |= PHY_CT_RESET;
  1605. }
  1606. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  1607. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  1608. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1609. /* Enable phy interrupt on autonegotiation complete (or link up) */
  1610. if (skge->autoneg == AUTONEG_ENABLE)
  1611. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
  1612. else
  1613. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1614. }
  1615. static void yukon_reset(struct skge_hw *hw, int port)
  1616. {
  1617. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
  1618. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  1619. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  1620. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  1621. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  1622. gma_write16(hw, port, GM_RX_CTRL,
  1623. gma_read16(hw, port, GM_RX_CTRL)
  1624. | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  1625. }
  1626. /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
  1627. static int is_yukon_lite_a0(struct skge_hw *hw)
  1628. {
  1629. u32 reg;
  1630. int ret;
  1631. if (hw->chip_id != CHIP_ID_YUKON)
  1632. return 0;
  1633. reg = skge_read32(hw, B2_FAR);
  1634. skge_write8(hw, B2_FAR + 3, 0xff);
  1635. ret = (skge_read8(hw, B2_FAR + 3) != 0);
  1636. skge_write32(hw, B2_FAR, reg);
  1637. return ret;
  1638. }
  1639. static void yukon_mac_init(struct skge_hw *hw, int port)
  1640. {
  1641. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1642. int i;
  1643. u32 reg;
  1644. const u8 *addr = hw->dev[port]->dev_addr;
  1645. /* WA code for COMA mode -- set PHY reset */
  1646. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1647. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  1648. reg = skge_read32(hw, B2_GP_IO);
  1649. reg |= GP_DIR_9 | GP_IO_9;
  1650. skge_write32(hw, B2_GP_IO, reg);
  1651. }
  1652. /* hard reset */
  1653. skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1654. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1655. /* WA code for COMA mode -- clear PHY reset */
  1656. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1657. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  1658. reg = skge_read32(hw, B2_GP_IO);
  1659. reg |= GP_DIR_9;
  1660. reg &= ~GP_IO_9;
  1661. skge_write32(hw, B2_GP_IO, reg);
  1662. }
  1663. /* Set hardware config mode */
  1664. reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
  1665. GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
  1666. reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
  1667. /* Clear GMC reset */
  1668. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
  1669. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
  1670. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
  1671. if (skge->autoneg == AUTONEG_DISABLE) {
  1672. reg = GM_GPCR_AU_ALL_DIS;
  1673. gma_write16(hw, port, GM_GP_CTRL,
  1674. gma_read16(hw, port, GM_GP_CTRL) | reg);
  1675. switch (skge->speed) {
  1676. case SPEED_1000:
  1677. reg &= ~GM_GPCR_SPEED_100;
  1678. reg |= GM_GPCR_SPEED_1000;
  1679. break;
  1680. case SPEED_100:
  1681. reg &= ~GM_GPCR_SPEED_1000;
  1682. reg |= GM_GPCR_SPEED_100;
  1683. break;
  1684. case SPEED_10:
  1685. reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
  1686. break;
  1687. }
  1688. if (skge->duplex == DUPLEX_FULL)
  1689. reg |= GM_GPCR_DUP_FULL;
  1690. } else
  1691. reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
  1692. switch (skge->flow_control) {
  1693. case FLOW_MODE_NONE:
  1694. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1695. reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1696. break;
  1697. case FLOW_MODE_LOC_SEND:
  1698. /* disable Rx flow-control */
  1699. reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1700. break;
  1701. case FLOW_MODE_SYMMETRIC:
  1702. case FLOW_MODE_SYM_OR_REM:
  1703. /* enable Tx & Rx flow-control */
  1704. break;
  1705. }
  1706. gma_write16(hw, port, GM_GP_CTRL, reg);
  1707. skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  1708. yukon_init(hw, port);
  1709. /* MIB clear */
  1710. reg = gma_read16(hw, port, GM_PHY_ADDR);
  1711. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  1712. for (i = 0; i < GM_MIB_CNT_SIZE; i++)
  1713. gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
  1714. gma_write16(hw, port, GM_PHY_ADDR, reg);
  1715. /* transmit control */
  1716. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  1717. /* receive control reg: unicast + multicast + no FCS */
  1718. gma_write16(hw, port, GM_RX_CTRL,
  1719. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  1720. /* transmit flow control */
  1721. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  1722. /* transmit parameter */
  1723. gma_write16(hw, port, GM_TX_PARAM,
  1724. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  1725. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  1726. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
  1727. /* serial mode register */
  1728. reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  1729. if (hw->dev[port]->mtu > 1500)
  1730. reg |= GM_SMOD_JUMBO_ENA;
  1731. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  1732. /* physical address: used for pause frames */
  1733. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  1734. /* virtual address for data */
  1735. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  1736. /* enable interrupt mask for counter overflows */
  1737. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  1738. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  1739. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  1740. /* Initialize Mac Fifo */
  1741. /* Configure Rx MAC FIFO */
  1742. skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
  1743. reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
  1744. /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
  1745. if (is_yukon_lite_a0(hw))
  1746. reg &= ~GMF_RX_F_FL_ON;
  1747. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  1748. skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
  1749. /*
  1750. * because Pause Packet Truncation in GMAC is not working
  1751. * we have to increase the Flush Threshold to 64 bytes
  1752. * in order to flush pause packets in Rx FIFO on Yukon-1
  1753. */
  1754. skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
  1755. /* Configure Tx MAC FIFO */
  1756. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  1757. skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  1758. }
  1759. /* Go into power down mode */
  1760. static void yukon_suspend(struct skge_hw *hw, int port)
  1761. {
  1762. u16 ctrl;
  1763. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  1764. ctrl |= PHY_M_PC_POL_R_DIS;
  1765. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  1766. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1767. ctrl |= PHY_CT_RESET;
  1768. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1769. /* switch IEEE compatible power down mode on */
  1770. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1771. ctrl |= PHY_CT_PDOWN;
  1772. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1773. }
  1774. static void yukon_stop(struct skge_port *skge)
  1775. {
  1776. struct skge_hw *hw = skge->hw;
  1777. int port = skge->port;
  1778. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  1779. yukon_reset(hw, port);
  1780. gma_write16(hw, port, GM_GP_CTRL,
  1781. gma_read16(hw, port, GM_GP_CTRL)
  1782. & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
  1783. gma_read16(hw, port, GM_GP_CTRL);
  1784. yukon_suspend(hw, port);
  1785. /* set GPHY Control reset */
  1786. skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1787. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1788. }
  1789. static void yukon_get_stats(struct skge_port *skge, u64 *data)
  1790. {
  1791. struct skge_hw *hw = skge->hw;
  1792. int port = skge->port;
  1793. int i;
  1794. data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
  1795. | gma_read32(hw, port, GM_TXO_OK_LO);
  1796. data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
  1797. | gma_read32(hw, port, GM_RXO_OK_LO);
  1798. for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
  1799. data[i] = gma_read32(hw, port,
  1800. skge_stats[i].gma_offset);
  1801. }
  1802. static void yukon_mac_intr(struct skge_hw *hw, int port)
  1803. {
  1804. struct net_device *dev = hw->dev[port];
  1805. struct skge_port *skge = netdev_priv(dev);
  1806. u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  1807. if (netif_msg_intr(skge))
  1808. printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
  1809. dev->name, status);
  1810. if (status & GM_IS_RX_FF_OR) {
  1811. ++skge->net_stats.rx_fifo_errors;
  1812. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  1813. }
  1814. if (status & GM_IS_TX_FF_UR) {
  1815. ++skge->net_stats.tx_fifo_errors;
  1816. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  1817. }
  1818. }
  1819. static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
  1820. {
  1821. switch (aux & PHY_M_PS_SPEED_MSK) {
  1822. case PHY_M_PS_SPEED_1000:
  1823. return SPEED_1000;
  1824. case PHY_M_PS_SPEED_100:
  1825. return SPEED_100;
  1826. default:
  1827. return SPEED_10;
  1828. }
  1829. }
  1830. static void yukon_link_up(struct skge_port *skge)
  1831. {
  1832. struct skge_hw *hw = skge->hw;
  1833. int port = skge->port;
  1834. u16 reg;
  1835. /* Enable Transmit FIFO Underrun */
  1836. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  1837. reg = gma_read16(hw, port, GM_GP_CTRL);
  1838. if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
  1839. reg |= GM_GPCR_DUP_FULL;
  1840. /* enable Rx/Tx */
  1841. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1842. gma_write16(hw, port, GM_GP_CTRL, reg);
  1843. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1844. skge_link_up(skge);
  1845. }
  1846. static void yukon_link_down(struct skge_port *skge)
  1847. {
  1848. struct skge_hw *hw = skge->hw;
  1849. int port = skge->port;
  1850. u16 ctrl;
  1851. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1852. ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1853. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1854. if (skge->flow_status == FLOW_STAT_REM_SEND) {
  1855. ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
  1856. ctrl |= PHY_M_AN_ASP;
  1857. /* restore Asymmetric Pause bit */
  1858. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
  1859. }
  1860. skge_link_down(skge);
  1861. yukon_init(hw, port);
  1862. }
  1863. static void yukon_phy_intr(struct skge_port *skge)
  1864. {
  1865. struct skge_hw *hw = skge->hw;
  1866. int port = skge->port;
  1867. const char *reason = NULL;
  1868. u16 istatus, phystat;
  1869. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1870. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1871. if (netif_msg_intr(skge))
  1872. printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1873. skge->netdev->name, istatus, phystat);
  1874. if (istatus & PHY_M_IS_AN_COMPL) {
  1875. if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
  1876. & PHY_M_AN_RF) {
  1877. reason = "remote fault";
  1878. goto failed;
  1879. }
  1880. if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
  1881. reason = "master/slave fault";
  1882. goto failed;
  1883. }
  1884. if (!(phystat & PHY_M_PS_SPDUP_RES)) {
  1885. reason = "speed/duplex";
  1886. goto failed;
  1887. }
  1888. skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
  1889. ? DUPLEX_FULL : DUPLEX_HALF;
  1890. skge->speed = yukon_speed(hw, phystat);
  1891. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  1892. switch (phystat & PHY_M_PS_PAUSE_MSK) {
  1893. case PHY_M_PS_PAUSE_MSK:
  1894. skge->flow_status = FLOW_STAT_SYMMETRIC;
  1895. break;
  1896. case PHY_M_PS_RX_P_EN:
  1897. skge->flow_status = FLOW_STAT_REM_SEND;
  1898. break;
  1899. case PHY_M_PS_TX_P_EN:
  1900. skge->flow_status = FLOW_STAT_LOC_SEND;
  1901. break;
  1902. default:
  1903. skge->flow_status = FLOW_STAT_NONE;
  1904. }
  1905. if (skge->flow_status == FLOW_STAT_NONE ||
  1906. (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
  1907. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1908. else
  1909. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1910. yukon_link_up(skge);
  1911. return;
  1912. }
  1913. if (istatus & PHY_M_IS_LSP_CHANGE)
  1914. skge->speed = yukon_speed(hw, phystat);
  1915. if (istatus & PHY_M_IS_DUP_CHANGE)
  1916. skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1917. if (istatus & PHY_M_IS_LST_CHANGE) {
  1918. if (phystat & PHY_M_PS_LINK_UP)
  1919. yukon_link_up(skge);
  1920. else
  1921. yukon_link_down(skge);
  1922. }
  1923. return;
  1924. failed:
  1925. printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
  1926. skge->netdev->name, reason);
  1927. /* XXX restart autonegotiation? */
  1928. }
  1929. static void skge_phy_reset(struct skge_port *skge)
  1930. {
  1931. struct skge_hw *hw = skge->hw;
  1932. int port = skge->port;
  1933. struct net_device *dev = hw->dev[port];
  1934. netif_stop_queue(skge->netdev);
  1935. netif_carrier_off(skge->netdev);
  1936. spin_lock_bh(&hw->phy_lock);
  1937. if (hw->chip_id == CHIP_ID_GENESIS) {
  1938. genesis_reset(hw, port);
  1939. genesis_mac_init(hw, port);
  1940. } else {
  1941. yukon_reset(hw, port);
  1942. yukon_init(hw, port);
  1943. }
  1944. spin_unlock_bh(&hw->phy_lock);
  1945. dev->set_multicast_list(dev);
  1946. }
  1947. /* Basic MII support */
  1948. static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1949. {
  1950. struct mii_ioctl_data *data = if_mii(ifr);
  1951. struct skge_port *skge = netdev_priv(dev);
  1952. struct skge_hw *hw = skge->hw;
  1953. int err = -EOPNOTSUPP;
  1954. if (!netif_running(dev))
  1955. return -ENODEV; /* Phy still in reset */
  1956. switch(cmd) {
  1957. case SIOCGMIIPHY:
  1958. data->phy_id = hw->phy_addr;
  1959. /* fallthru */
  1960. case SIOCGMIIREG: {
  1961. u16 val = 0;
  1962. spin_lock_bh(&hw->phy_lock);
  1963. if (hw->chip_id == CHIP_ID_GENESIS)
  1964. err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
  1965. else
  1966. err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
  1967. spin_unlock_bh(&hw->phy_lock);
  1968. data->val_out = val;
  1969. break;
  1970. }
  1971. case SIOCSMIIREG:
  1972. if (!capable(CAP_NET_ADMIN))
  1973. return -EPERM;
  1974. spin_lock_bh(&hw->phy_lock);
  1975. if (hw->chip_id == CHIP_ID_GENESIS)
  1976. err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
  1977. data->val_in);
  1978. else
  1979. err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
  1980. data->val_in);
  1981. spin_unlock_bh(&hw->phy_lock);
  1982. break;
  1983. }
  1984. return err;
  1985. }
  1986. static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
  1987. {
  1988. u32 end;
  1989. start /= 8;
  1990. len /= 8;
  1991. end = start + len - 1;
  1992. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  1993. skge_write32(hw, RB_ADDR(q, RB_START), start);
  1994. skge_write32(hw, RB_ADDR(q, RB_WP), start);
  1995. skge_write32(hw, RB_ADDR(q, RB_RP), start);
  1996. skge_write32(hw, RB_ADDR(q, RB_END), end);
  1997. if (q == Q_R1 || q == Q_R2) {
  1998. /* Set thresholds on receive queue's */
  1999. skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
  2000. start + (2*len)/3);
  2001. skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
  2002. start + (len/3));
  2003. } else {
  2004. /* Enable store & forward on Tx queue's because
  2005. * Tx FIFO is only 4K on Genesis and 1K on Yukon
  2006. */
  2007. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  2008. }
  2009. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  2010. }
  2011. /* Setup Bus Memory Interface */
  2012. static void skge_qset(struct skge_port *skge, u16 q,
  2013. const struct skge_element *e)
  2014. {
  2015. struct skge_hw *hw = skge->hw;
  2016. u32 watermark = 0x600;
  2017. u64 base = skge->dma + (e->desc - skge->mem);
  2018. /* optimization to reduce window on 32bit/33mhz */
  2019. if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
  2020. watermark /= 2;
  2021. skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
  2022. skge_write32(hw, Q_ADDR(q, Q_F), watermark);
  2023. skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
  2024. skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
  2025. }
  2026. static int skge_up(struct net_device *dev)
  2027. {
  2028. struct skge_port *skge = netdev_priv(dev);
  2029. struct skge_hw *hw = skge->hw;
  2030. int port = skge->port;
  2031. u32 chunk, ram_addr;
  2032. size_t rx_size, tx_size;
  2033. int err;
  2034. if (!is_valid_ether_addr(dev->dev_addr))
  2035. return -EINVAL;
  2036. if (netif_msg_ifup(skge))
  2037. printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
  2038. if (dev->mtu > RX_BUF_SIZE)
  2039. skge->rx_buf_size = dev->mtu + ETH_HLEN;
  2040. else
  2041. skge->rx_buf_size = RX_BUF_SIZE;
  2042. rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
  2043. tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
  2044. skge->mem_size = tx_size + rx_size;
  2045. skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
  2046. if (!skge->mem)
  2047. return -ENOMEM;
  2048. BUG_ON(skge->dma & 7);
  2049. if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
  2050. dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
  2051. err = -EINVAL;
  2052. goto free_pci_mem;
  2053. }
  2054. memset(skge->mem, 0, skge->mem_size);
  2055. err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
  2056. if (err)
  2057. goto free_pci_mem;
  2058. err = skge_rx_fill(dev);
  2059. if (err)
  2060. goto free_rx_ring;
  2061. err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
  2062. skge->dma + rx_size);
  2063. if (err)
  2064. goto free_rx_ring;
  2065. /* Initialize MAC */
  2066. spin_lock_bh(&hw->phy_lock);
  2067. if (hw->chip_id == CHIP_ID_GENESIS)
  2068. genesis_mac_init(hw, port);
  2069. else
  2070. yukon_mac_init(hw, port);
  2071. spin_unlock_bh(&hw->phy_lock);
  2072. /* Configure RAMbuffers */
  2073. chunk = hw->ram_size / ((hw->ports + 1)*2);
  2074. ram_addr = hw->ram_offset + 2 * chunk * port;
  2075. skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
  2076. skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
  2077. BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
  2078. skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
  2079. skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
  2080. /* Start receiver BMU */
  2081. wmb();
  2082. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
  2083. skge_led(skge, LED_MODE_ON);
  2084. spin_lock_irq(&hw->hw_lock);
  2085. hw->intr_mask |= portmask[port];
  2086. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2087. spin_unlock_irq(&hw->hw_lock);
  2088. netif_poll_enable(dev);
  2089. return 0;
  2090. free_rx_ring:
  2091. skge_rx_clean(skge);
  2092. kfree(skge->rx_ring.start);
  2093. free_pci_mem:
  2094. pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
  2095. skge->mem = NULL;
  2096. return err;
  2097. }
  2098. static int skge_down(struct net_device *dev)
  2099. {
  2100. struct skge_port *skge = netdev_priv(dev);
  2101. struct skge_hw *hw = skge->hw;
  2102. int port = skge->port;
  2103. if (skge->mem == NULL)
  2104. return 0;
  2105. if (netif_msg_ifdown(skge))
  2106. printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
  2107. netif_stop_queue(dev);
  2108. if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
  2109. del_timer_sync(&skge->link_timer);
  2110. netif_poll_disable(dev);
  2111. netif_carrier_off(dev);
  2112. spin_lock_irq(&hw->hw_lock);
  2113. hw->intr_mask &= ~portmask[port];
  2114. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2115. spin_unlock_irq(&hw->hw_lock);
  2116. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
  2117. if (hw->chip_id == CHIP_ID_GENESIS)
  2118. genesis_stop(skge);
  2119. else
  2120. yukon_stop(skge);
  2121. /* Stop transmitter */
  2122. skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
  2123. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  2124. RB_RST_SET|RB_DIS_OP_MD);
  2125. /* Disable Force Sync bit and Enable Alloc bit */
  2126. skge_write8(hw, SK_REG(port, TXA_CTRL),
  2127. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  2128. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  2129. skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  2130. skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  2131. /* Reset PCI FIFO */
  2132. skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
  2133. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  2134. /* Reset the RAM Buffer async Tx queue */
  2135. skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
  2136. /* stop receiver */
  2137. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
  2138. skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
  2139. RB_RST_SET|RB_DIS_OP_MD);
  2140. skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
  2141. if (hw->chip_id == CHIP_ID_GENESIS) {
  2142. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
  2143. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
  2144. } else {
  2145. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  2146. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  2147. }
  2148. skge_led(skge, LED_MODE_OFF);
  2149. netif_tx_lock_bh(dev);
  2150. skge_tx_clean(dev);
  2151. netif_tx_unlock_bh(dev);
  2152. skge_rx_clean(skge);
  2153. kfree(skge->rx_ring.start);
  2154. kfree(skge->tx_ring.start);
  2155. pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
  2156. skge->mem = NULL;
  2157. return 0;
  2158. }
  2159. static inline int skge_avail(const struct skge_ring *ring)
  2160. {
  2161. return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
  2162. + (ring->to_clean - ring->to_use) - 1;
  2163. }
  2164. static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
  2165. {
  2166. struct skge_port *skge = netdev_priv(dev);
  2167. struct skge_hw *hw = skge->hw;
  2168. struct skge_element *e;
  2169. struct skge_tx_desc *td;
  2170. int i;
  2171. u32 control, len;
  2172. u64 map;
  2173. if (skb_padto(skb, ETH_ZLEN))
  2174. return NETDEV_TX_OK;
  2175. if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
  2176. return NETDEV_TX_BUSY;
  2177. e = skge->tx_ring.to_use;
  2178. td = e->desc;
  2179. BUG_ON(td->control & BMU_OWN);
  2180. e->skb = skb;
  2181. len = skb_headlen(skb);
  2182. map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
  2183. pci_unmap_addr_set(e, mapaddr, map);
  2184. pci_unmap_len_set(e, maplen, len);
  2185. td->dma_lo = map;
  2186. td->dma_hi = map >> 32;
  2187. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  2188. int offset = skb->h.raw - skb->data;
  2189. /* This seems backwards, but it is what the sk98lin
  2190. * does. Looks like hardware is wrong?
  2191. */
  2192. if (skb->h.ipiph->protocol == IPPROTO_UDP
  2193. && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
  2194. control = BMU_TCP_CHECK;
  2195. else
  2196. control = BMU_UDP_CHECK;
  2197. td->csum_offs = 0;
  2198. td->csum_start = offset;
  2199. td->csum_write = offset + skb->csum_offset;
  2200. } else
  2201. control = BMU_CHECK;
  2202. if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
  2203. control |= BMU_EOF| BMU_IRQ_EOF;
  2204. else {
  2205. struct skge_tx_desc *tf = td;
  2206. control |= BMU_STFWD;
  2207. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2208. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2209. map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
  2210. frag->size, PCI_DMA_TODEVICE);
  2211. e = e->next;
  2212. e->skb = skb;
  2213. tf = e->desc;
  2214. BUG_ON(tf->control & BMU_OWN);
  2215. tf->dma_lo = map;
  2216. tf->dma_hi = (u64) map >> 32;
  2217. pci_unmap_addr_set(e, mapaddr, map);
  2218. pci_unmap_len_set(e, maplen, frag->size);
  2219. tf->control = BMU_OWN | BMU_SW | control | frag->size;
  2220. }
  2221. tf->control |= BMU_EOF | BMU_IRQ_EOF;
  2222. }
  2223. /* Make sure all the descriptors written */
  2224. wmb();
  2225. td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
  2226. wmb();
  2227. skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
  2228. if (unlikely(netif_msg_tx_queued(skge)))
  2229. printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
  2230. dev->name, e - skge->tx_ring.start, skb->len);
  2231. skge->tx_ring.to_use = e->next;
  2232. if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
  2233. pr_debug("%s: transmit queue full\n", dev->name);
  2234. netif_stop_queue(dev);
  2235. }
  2236. dev->trans_start = jiffies;
  2237. return NETDEV_TX_OK;
  2238. }
  2239. /* Free resources associated with this reing element */
  2240. static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
  2241. u32 control)
  2242. {
  2243. struct pci_dev *pdev = skge->hw->pdev;
  2244. BUG_ON(!e->skb);
  2245. /* skb header vs. fragment */
  2246. if (control & BMU_STF)
  2247. pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
  2248. pci_unmap_len(e, maplen),
  2249. PCI_DMA_TODEVICE);
  2250. else
  2251. pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
  2252. pci_unmap_len(e, maplen),
  2253. PCI_DMA_TODEVICE);
  2254. if (control & BMU_EOF) {
  2255. if (unlikely(netif_msg_tx_done(skge)))
  2256. printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
  2257. skge->netdev->name, e - skge->tx_ring.start);
  2258. dev_kfree_skb(e->skb);
  2259. }
  2260. e->skb = NULL;
  2261. }
  2262. /* Free all buffers in transmit ring */
  2263. static void skge_tx_clean(struct net_device *dev)
  2264. {
  2265. struct skge_port *skge = netdev_priv(dev);
  2266. struct skge_element *e;
  2267. for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
  2268. struct skge_tx_desc *td = e->desc;
  2269. skge_tx_free(skge, e, td->control);
  2270. td->control = 0;
  2271. }
  2272. skge->tx_ring.to_clean = e;
  2273. netif_wake_queue(dev);
  2274. }
  2275. static void skge_tx_timeout(struct net_device *dev)
  2276. {
  2277. struct skge_port *skge = netdev_priv(dev);
  2278. if (netif_msg_timer(skge))
  2279. printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
  2280. skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
  2281. skge_tx_clean(dev);
  2282. }
  2283. static int skge_change_mtu(struct net_device *dev, int new_mtu)
  2284. {
  2285. int err;
  2286. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  2287. return -EINVAL;
  2288. if (!netif_running(dev)) {
  2289. dev->mtu = new_mtu;
  2290. return 0;
  2291. }
  2292. skge_down(dev);
  2293. dev->mtu = new_mtu;
  2294. err = skge_up(dev);
  2295. if (err)
  2296. dev_close(dev);
  2297. return err;
  2298. }
  2299. static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
  2300. static void genesis_add_filter(u8 filter[8], const u8 *addr)
  2301. {
  2302. u32 crc, bit;
  2303. crc = ether_crc_le(ETH_ALEN, addr);
  2304. bit = ~crc & 0x3f;
  2305. filter[bit/8] |= 1 << (bit%8);
  2306. }
  2307. static void genesis_set_multicast(struct net_device *dev)
  2308. {
  2309. struct skge_port *skge = netdev_priv(dev);
  2310. struct skge_hw *hw = skge->hw;
  2311. int port = skge->port;
  2312. int i, count = dev->mc_count;
  2313. struct dev_mc_list *list = dev->mc_list;
  2314. u32 mode;
  2315. u8 filter[8];
  2316. mode = xm_read32(hw, port, XM_MODE);
  2317. mode |= XM_MD_ENA_HASH;
  2318. if (dev->flags & IFF_PROMISC)
  2319. mode |= XM_MD_ENA_PROM;
  2320. else
  2321. mode &= ~XM_MD_ENA_PROM;
  2322. if (dev->flags & IFF_ALLMULTI)
  2323. memset(filter, 0xff, sizeof(filter));
  2324. else {
  2325. memset(filter, 0, sizeof(filter));
  2326. if (skge->flow_status == FLOW_STAT_REM_SEND
  2327. || skge->flow_status == FLOW_STAT_SYMMETRIC)
  2328. genesis_add_filter(filter, pause_mc_addr);
  2329. for (i = 0; list && i < count; i++, list = list->next)
  2330. genesis_add_filter(filter, list->dmi_addr);
  2331. }
  2332. xm_write32(hw, port, XM_MODE, mode);
  2333. xm_outhash(hw, port, XM_HSM, filter);
  2334. }
  2335. static void yukon_add_filter(u8 filter[8], const u8 *addr)
  2336. {
  2337. u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
  2338. filter[bit/8] |= 1 << (bit%8);
  2339. }
  2340. static void yukon_set_multicast(struct net_device *dev)
  2341. {
  2342. struct skge_port *skge = netdev_priv(dev);
  2343. struct skge_hw *hw = skge->hw;
  2344. int port = skge->port;
  2345. struct dev_mc_list *list = dev->mc_list;
  2346. int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
  2347. || skge->flow_status == FLOW_STAT_SYMMETRIC);
  2348. u16 reg;
  2349. u8 filter[8];
  2350. memset(filter, 0, sizeof(filter));
  2351. reg = gma_read16(hw, port, GM_RX_CTRL);
  2352. reg |= GM_RXCR_UCF_ENA;
  2353. if (dev->flags & IFF_PROMISC) /* promiscuous */
  2354. reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  2355. else if (dev->flags & IFF_ALLMULTI) /* all multicast */
  2356. memset(filter, 0xff, sizeof(filter));
  2357. else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
  2358. reg &= ~GM_RXCR_MCF_ENA;
  2359. else {
  2360. int i;
  2361. reg |= GM_RXCR_MCF_ENA;
  2362. if (rx_pause)
  2363. yukon_add_filter(filter, pause_mc_addr);
  2364. for (i = 0; list && i < dev->mc_count; i++, list = list->next)
  2365. yukon_add_filter(filter, list->dmi_addr);
  2366. }
  2367. gma_write16(hw, port, GM_MC_ADDR_H1,
  2368. (u16)filter[0] | ((u16)filter[1] << 8));
  2369. gma_write16(hw, port, GM_MC_ADDR_H2,
  2370. (u16)filter[2] | ((u16)filter[3] << 8));
  2371. gma_write16(hw, port, GM_MC_ADDR_H3,
  2372. (u16)filter[4] | ((u16)filter[5] << 8));
  2373. gma_write16(hw, port, GM_MC_ADDR_H4,
  2374. (u16)filter[6] | ((u16)filter[7] << 8));
  2375. gma_write16(hw, port, GM_RX_CTRL, reg);
  2376. }
  2377. static inline u16 phy_length(const struct skge_hw *hw, u32 status)
  2378. {
  2379. if (hw->chip_id == CHIP_ID_GENESIS)
  2380. return status >> XMR_FS_LEN_SHIFT;
  2381. else
  2382. return status >> GMR_FS_LEN_SHIFT;
  2383. }
  2384. static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
  2385. {
  2386. if (hw->chip_id == CHIP_ID_GENESIS)
  2387. return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
  2388. else
  2389. return (status & GMR_FS_ANY_ERR) ||
  2390. (status & GMR_FS_RX_OK) == 0;
  2391. }
  2392. /* Get receive buffer from descriptor.
  2393. * Handles copy of small buffers and reallocation failures
  2394. */
  2395. static struct sk_buff *skge_rx_get(struct net_device *dev,
  2396. struct skge_element *e,
  2397. u32 control, u32 status, u16 csum)
  2398. {
  2399. struct skge_port *skge = netdev_priv(dev);
  2400. struct sk_buff *skb;
  2401. u16 len = control & BMU_BBC;
  2402. if (unlikely(netif_msg_rx_status(skge)))
  2403. printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
  2404. dev->name, e - skge->rx_ring.start,
  2405. status, len);
  2406. if (len > skge->rx_buf_size)
  2407. goto error;
  2408. if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
  2409. goto error;
  2410. if (bad_phy_status(skge->hw, status))
  2411. goto error;
  2412. if (phy_length(skge->hw, status) != len)
  2413. goto error;
  2414. if (len < RX_COPY_THRESHOLD) {
  2415. skb = netdev_alloc_skb(dev, len + 2);
  2416. if (!skb)
  2417. goto resubmit;
  2418. skb_reserve(skb, 2);
  2419. pci_dma_sync_single_for_cpu(skge->hw->pdev,
  2420. pci_unmap_addr(e, mapaddr),
  2421. len, PCI_DMA_FROMDEVICE);
  2422. memcpy(skb->data, e->skb->data, len);
  2423. pci_dma_sync_single_for_device(skge->hw->pdev,
  2424. pci_unmap_addr(e, mapaddr),
  2425. len, PCI_DMA_FROMDEVICE);
  2426. skge_rx_reuse(e, skge->rx_buf_size);
  2427. } else {
  2428. struct sk_buff *nskb;
  2429. nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
  2430. if (!nskb)
  2431. goto resubmit;
  2432. skb_reserve(nskb, NET_IP_ALIGN);
  2433. pci_unmap_single(skge->hw->pdev,
  2434. pci_unmap_addr(e, mapaddr),
  2435. pci_unmap_len(e, maplen),
  2436. PCI_DMA_FROMDEVICE);
  2437. skb = e->skb;
  2438. prefetch(skb->data);
  2439. skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
  2440. }
  2441. skb_put(skb, len);
  2442. if (skge->rx_csum) {
  2443. skb->csum = csum;
  2444. skb->ip_summed = CHECKSUM_COMPLETE;
  2445. }
  2446. skb->protocol = eth_type_trans(skb, dev);
  2447. return skb;
  2448. error:
  2449. if (netif_msg_rx_err(skge))
  2450. printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
  2451. dev->name, e - skge->rx_ring.start,
  2452. control, status);
  2453. if (skge->hw->chip_id == CHIP_ID_GENESIS) {
  2454. if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
  2455. skge->net_stats.rx_length_errors++;
  2456. if (status & XMR_FS_FRA_ERR)
  2457. skge->net_stats.rx_frame_errors++;
  2458. if (status & XMR_FS_FCS_ERR)
  2459. skge->net_stats.rx_crc_errors++;
  2460. } else {
  2461. if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
  2462. skge->net_stats.rx_length_errors++;
  2463. if (status & GMR_FS_FRAGMENT)
  2464. skge->net_stats.rx_frame_errors++;
  2465. if (status & GMR_FS_CRC_ERR)
  2466. skge->net_stats.rx_crc_errors++;
  2467. }
  2468. resubmit:
  2469. skge_rx_reuse(e, skge->rx_buf_size);
  2470. return NULL;
  2471. }
  2472. /* Free all buffers in Tx ring which are no longer owned by device */
  2473. static void skge_tx_done(struct net_device *dev)
  2474. {
  2475. struct skge_port *skge = netdev_priv(dev);
  2476. struct skge_ring *ring = &skge->tx_ring;
  2477. struct skge_element *e;
  2478. skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
  2479. netif_tx_lock(dev);
  2480. for (e = ring->to_clean; e != ring->to_use; e = e->next) {
  2481. struct skge_tx_desc *td = e->desc;
  2482. if (td->control & BMU_OWN)
  2483. break;
  2484. skge_tx_free(skge, e, td->control);
  2485. }
  2486. skge->tx_ring.to_clean = e;
  2487. if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
  2488. netif_wake_queue(dev);
  2489. netif_tx_unlock(dev);
  2490. }
  2491. static int skge_poll(struct net_device *dev, int *budget)
  2492. {
  2493. struct skge_port *skge = netdev_priv(dev);
  2494. struct skge_hw *hw = skge->hw;
  2495. struct skge_ring *ring = &skge->rx_ring;
  2496. struct skge_element *e;
  2497. unsigned long flags;
  2498. int to_do = min(dev->quota, *budget);
  2499. int work_done = 0;
  2500. skge_tx_done(dev);
  2501. skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
  2502. for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
  2503. struct skge_rx_desc *rd = e->desc;
  2504. struct sk_buff *skb;
  2505. u32 control;
  2506. rmb();
  2507. control = rd->control;
  2508. if (control & BMU_OWN)
  2509. break;
  2510. skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
  2511. if (likely(skb)) {
  2512. dev->last_rx = jiffies;
  2513. netif_receive_skb(skb);
  2514. ++work_done;
  2515. }
  2516. }
  2517. ring->to_clean = e;
  2518. /* restart receiver */
  2519. wmb();
  2520. skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
  2521. *budget -= work_done;
  2522. dev->quota -= work_done;
  2523. if (work_done >= to_do)
  2524. return 1; /* not done */
  2525. spin_lock_irqsave(&hw->hw_lock, flags);
  2526. __netif_rx_complete(dev);
  2527. hw->intr_mask |= napimask[skge->port];
  2528. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2529. skge_read32(hw, B0_IMSK);
  2530. spin_unlock_irqrestore(&hw->hw_lock, flags);
  2531. return 0;
  2532. }
  2533. /* Parity errors seem to happen when Genesis is connected to a switch
  2534. * with no other ports present. Heartbeat error??
  2535. */
  2536. static void skge_mac_parity(struct skge_hw *hw, int port)
  2537. {
  2538. struct net_device *dev = hw->dev[port];
  2539. if (dev) {
  2540. struct skge_port *skge = netdev_priv(dev);
  2541. ++skge->net_stats.tx_heartbeat_errors;
  2542. }
  2543. if (hw->chip_id == CHIP_ID_GENESIS)
  2544. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
  2545. MFF_CLR_PERR);
  2546. else
  2547. /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
  2548. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
  2549. (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
  2550. ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
  2551. }
  2552. static void skge_mac_intr(struct skge_hw *hw, int port)
  2553. {
  2554. if (hw->chip_id == CHIP_ID_GENESIS)
  2555. genesis_mac_intr(hw, port);
  2556. else
  2557. yukon_mac_intr(hw, port);
  2558. }
  2559. /* Handle device specific framing and timeout interrupts */
  2560. static void skge_error_irq(struct skge_hw *hw)
  2561. {
  2562. struct pci_dev *pdev = hw->pdev;
  2563. u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
  2564. if (hw->chip_id == CHIP_ID_GENESIS) {
  2565. /* clear xmac errors */
  2566. if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
  2567. skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
  2568. if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
  2569. skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
  2570. } else {
  2571. /* Timestamp (unused) overflow */
  2572. if (hwstatus & IS_IRQ_TIST_OV)
  2573. skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  2574. }
  2575. if (hwstatus & IS_RAM_RD_PAR) {
  2576. dev_err(&pdev->dev, "Ram read data parity error\n");
  2577. skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
  2578. }
  2579. if (hwstatus & IS_RAM_WR_PAR) {
  2580. dev_err(&pdev->dev, "Ram write data parity error\n");
  2581. skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
  2582. }
  2583. if (hwstatus & IS_M1_PAR_ERR)
  2584. skge_mac_parity(hw, 0);
  2585. if (hwstatus & IS_M2_PAR_ERR)
  2586. skge_mac_parity(hw, 1);
  2587. if (hwstatus & IS_R1_PAR_ERR) {
  2588. dev_err(&pdev->dev, "%s: receive queue parity error\n",
  2589. hw->dev[0]->name);
  2590. skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
  2591. }
  2592. if (hwstatus & IS_R2_PAR_ERR) {
  2593. dev_err(&pdev->dev, "%s: receive queue parity error\n",
  2594. hw->dev[1]->name);
  2595. skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
  2596. }
  2597. if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
  2598. u16 pci_status, pci_cmd;
  2599. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  2600. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  2601. dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
  2602. pci_cmd, pci_status);
  2603. /* Write the error bits back to clear them. */
  2604. pci_status &= PCI_STATUS_ERROR_BITS;
  2605. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2606. pci_write_config_word(pdev, PCI_COMMAND,
  2607. pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  2608. pci_write_config_word(pdev, PCI_STATUS, pci_status);
  2609. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2610. /* if error still set then just ignore it */
  2611. hwstatus = skge_read32(hw, B0_HWE_ISRC);
  2612. if (hwstatus & IS_IRQ_STAT) {
  2613. dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
  2614. hw->intr_mask &= ~IS_HW_ERR;
  2615. }
  2616. }
  2617. }
  2618. /*
  2619. * Interrupt from PHY are handled in tasklet (softirq)
  2620. * because accessing phy registers requires spin wait which might
  2621. * cause excess interrupt latency.
  2622. */
  2623. static void skge_extirq(unsigned long arg)
  2624. {
  2625. struct skge_hw *hw = (struct skge_hw *) arg;
  2626. int port;
  2627. for (port = 0; port < hw->ports; port++) {
  2628. struct net_device *dev = hw->dev[port];
  2629. if (netif_running(dev)) {
  2630. struct skge_port *skge = netdev_priv(dev);
  2631. spin_lock(&hw->phy_lock);
  2632. if (hw->chip_id != CHIP_ID_GENESIS)
  2633. yukon_phy_intr(skge);
  2634. else if (hw->phy_type == SK_PHY_BCOM)
  2635. bcom_phy_intr(skge);
  2636. spin_unlock(&hw->phy_lock);
  2637. }
  2638. }
  2639. spin_lock_irq(&hw->hw_lock);
  2640. hw->intr_mask |= IS_EXT_REG;
  2641. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2642. skge_read32(hw, B0_IMSK);
  2643. spin_unlock_irq(&hw->hw_lock);
  2644. }
  2645. static irqreturn_t skge_intr(int irq, void *dev_id)
  2646. {
  2647. struct skge_hw *hw = dev_id;
  2648. u32 status;
  2649. int handled = 0;
  2650. spin_lock(&hw->hw_lock);
  2651. /* Reading this register masks IRQ */
  2652. status = skge_read32(hw, B0_SP_ISRC);
  2653. if (status == 0 || status == ~0)
  2654. goto out;
  2655. handled = 1;
  2656. status &= hw->intr_mask;
  2657. if (status & IS_EXT_REG) {
  2658. hw->intr_mask &= ~IS_EXT_REG;
  2659. tasklet_schedule(&hw->phy_task);
  2660. }
  2661. if (status & (IS_XA1_F|IS_R1_F)) {
  2662. hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
  2663. netif_rx_schedule(hw->dev[0]);
  2664. }
  2665. if (status & IS_PA_TO_TX1)
  2666. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
  2667. if (status & IS_PA_TO_RX1) {
  2668. struct skge_port *skge = netdev_priv(hw->dev[0]);
  2669. ++skge->net_stats.rx_over_errors;
  2670. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
  2671. }
  2672. if (status & IS_MAC1)
  2673. skge_mac_intr(hw, 0);
  2674. if (hw->dev[1]) {
  2675. if (status & (IS_XA2_F|IS_R2_F)) {
  2676. hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
  2677. netif_rx_schedule(hw->dev[1]);
  2678. }
  2679. if (status & IS_PA_TO_RX2) {
  2680. struct skge_port *skge = netdev_priv(hw->dev[1]);
  2681. ++skge->net_stats.rx_over_errors;
  2682. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
  2683. }
  2684. if (status & IS_PA_TO_TX2)
  2685. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
  2686. if (status & IS_MAC2)
  2687. skge_mac_intr(hw, 1);
  2688. }
  2689. if (status & IS_HW_ERR)
  2690. skge_error_irq(hw);
  2691. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2692. skge_read32(hw, B0_IMSK);
  2693. out:
  2694. spin_unlock(&hw->hw_lock);
  2695. return IRQ_RETVAL(handled);
  2696. }
  2697. #ifdef CONFIG_NET_POLL_CONTROLLER
  2698. static void skge_netpoll(struct net_device *dev)
  2699. {
  2700. struct skge_port *skge = netdev_priv(dev);
  2701. disable_irq(dev->irq);
  2702. skge_intr(dev->irq, skge->hw);
  2703. enable_irq(dev->irq);
  2704. }
  2705. #endif
  2706. static int skge_set_mac_address(struct net_device *dev, void *p)
  2707. {
  2708. struct skge_port *skge = netdev_priv(dev);
  2709. struct skge_hw *hw = skge->hw;
  2710. unsigned port = skge->port;
  2711. const struct sockaddr *addr = p;
  2712. u16 ctrl;
  2713. if (!is_valid_ether_addr(addr->sa_data))
  2714. return -EADDRNOTAVAIL;
  2715. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  2716. if (!netif_running(dev)) {
  2717. memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
  2718. memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
  2719. } else {
  2720. /* disable Rx */
  2721. spin_lock_bh(&hw->phy_lock);
  2722. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  2723. gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
  2724. memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
  2725. memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
  2726. if (hw->chip_id == CHIP_ID_GENESIS)
  2727. xm_outaddr(hw, port, XM_SA, dev->dev_addr);
  2728. else {
  2729. gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
  2730. gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
  2731. }
  2732. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  2733. spin_unlock_bh(&hw->phy_lock);
  2734. }
  2735. return 0;
  2736. }
  2737. static const struct {
  2738. u8 id;
  2739. const char *name;
  2740. } skge_chips[] = {
  2741. { CHIP_ID_GENESIS, "Genesis" },
  2742. { CHIP_ID_YUKON, "Yukon" },
  2743. { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
  2744. { CHIP_ID_YUKON_LP, "Yukon-LP"},
  2745. };
  2746. static const char *skge_board_name(const struct skge_hw *hw)
  2747. {
  2748. int i;
  2749. static char buf[16];
  2750. for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
  2751. if (skge_chips[i].id == hw->chip_id)
  2752. return skge_chips[i].name;
  2753. snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
  2754. return buf;
  2755. }
  2756. /*
  2757. * Setup the board data structure, but don't bring up
  2758. * the port(s)
  2759. */
  2760. static int skge_reset(struct skge_hw *hw)
  2761. {
  2762. u32 reg;
  2763. u16 ctst, pci_status;
  2764. u8 t8, mac_cfg, pmd_type;
  2765. int i;
  2766. ctst = skge_read16(hw, B0_CTST);
  2767. /* do a SW reset */
  2768. skge_write8(hw, B0_CTST, CS_RST_SET);
  2769. skge_write8(hw, B0_CTST, CS_RST_CLR);
  2770. /* clear PCI errors, if any */
  2771. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2772. skge_write8(hw, B2_TST_CTRL2, 0);
  2773. pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
  2774. pci_write_config_word(hw->pdev, PCI_STATUS,
  2775. pci_status | PCI_STATUS_ERROR_BITS);
  2776. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2777. skge_write8(hw, B0_CTST, CS_MRST_CLR);
  2778. /* restore CLK_RUN bits (for Yukon-Lite) */
  2779. skge_write16(hw, B0_CTST,
  2780. ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
  2781. hw->chip_id = skge_read8(hw, B2_CHIP_ID);
  2782. hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
  2783. pmd_type = skge_read8(hw, B2_PMD_TYP);
  2784. hw->copper = (pmd_type == 'T' || pmd_type == '1');
  2785. switch (hw->chip_id) {
  2786. case CHIP_ID_GENESIS:
  2787. switch (hw->phy_type) {
  2788. case SK_PHY_XMAC:
  2789. hw->phy_addr = PHY_ADDR_XMAC;
  2790. break;
  2791. case SK_PHY_BCOM:
  2792. hw->phy_addr = PHY_ADDR_BCOM;
  2793. break;
  2794. default:
  2795. dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
  2796. hw->phy_type);
  2797. return -EOPNOTSUPP;
  2798. }
  2799. break;
  2800. case CHIP_ID_YUKON:
  2801. case CHIP_ID_YUKON_LITE:
  2802. case CHIP_ID_YUKON_LP:
  2803. if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
  2804. hw->copper = 1;
  2805. hw->phy_addr = PHY_ADDR_MARV;
  2806. break;
  2807. default:
  2808. dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
  2809. hw->chip_id);
  2810. return -EOPNOTSUPP;
  2811. }
  2812. mac_cfg = skge_read8(hw, B2_MAC_CFG);
  2813. hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
  2814. hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
  2815. /* read the adapters RAM size */
  2816. t8 = skge_read8(hw, B2_E_0);
  2817. if (hw->chip_id == CHIP_ID_GENESIS) {
  2818. if (t8 == 3) {
  2819. /* special case: 4 x 64k x 36, offset = 0x80000 */
  2820. hw->ram_size = 0x100000;
  2821. hw->ram_offset = 0x80000;
  2822. } else
  2823. hw->ram_size = t8 * 512;
  2824. }
  2825. else if (t8 == 0)
  2826. hw->ram_size = 0x20000;
  2827. else
  2828. hw->ram_size = t8 * 4096;
  2829. hw->intr_mask = IS_HW_ERR;
  2830. /* Use PHY IRQ for all but fiber based Genesis board */
  2831. if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
  2832. hw->intr_mask |= IS_EXT_REG;
  2833. if (hw->chip_id == CHIP_ID_GENESIS)
  2834. genesis_init(hw);
  2835. else {
  2836. /* switch power to VCC (WA for VAUX problem) */
  2837. skge_write8(hw, B0_POWER_CTRL,
  2838. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  2839. /* avoid boards with stuck Hardware error bits */
  2840. if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
  2841. (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
  2842. dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
  2843. hw->intr_mask &= ~IS_HW_ERR;
  2844. }
  2845. /* Clear PHY COMA */
  2846. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2847. pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
  2848. reg &= ~PCI_PHY_COMA;
  2849. pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
  2850. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2851. for (i = 0; i < hw->ports; i++) {
  2852. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  2853. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  2854. }
  2855. }
  2856. /* turn off hardware timer (unused) */
  2857. skge_write8(hw, B2_TI_CTRL, TIM_STOP);
  2858. skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  2859. skge_write8(hw, B0_LED, LED_STAT_ON);
  2860. /* enable the Tx Arbiters */
  2861. for (i = 0; i < hw->ports; i++)
  2862. skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  2863. /* Initialize ram interface */
  2864. skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
  2865. skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
  2866. skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
  2867. skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
  2868. skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
  2869. skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
  2870. skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
  2871. skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
  2872. skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
  2873. skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
  2874. skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
  2875. skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
  2876. skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
  2877. skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
  2878. /* Set interrupt moderation for Transmit only
  2879. * Receive interrupts avoided by NAPI
  2880. */
  2881. skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
  2882. skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
  2883. skge_write32(hw, B2_IRQM_CTRL, TIM_START);
  2884. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2885. for (i = 0; i < hw->ports; i++) {
  2886. if (hw->chip_id == CHIP_ID_GENESIS)
  2887. genesis_reset(hw, i);
  2888. else
  2889. yukon_reset(hw, i);
  2890. }
  2891. return 0;
  2892. }
  2893. /* Initialize network device */
  2894. static struct net_device *skge_devinit(struct skge_hw *hw, int port,
  2895. int highmem)
  2896. {
  2897. struct skge_port *skge;
  2898. struct net_device *dev = alloc_etherdev(sizeof(*skge));
  2899. if (!dev) {
  2900. dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
  2901. return NULL;
  2902. }
  2903. SET_MODULE_OWNER(dev);
  2904. SET_NETDEV_DEV(dev, &hw->pdev->dev);
  2905. dev->open = skge_up;
  2906. dev->stop = skge_down;
  2907. dev->do_ioctl = skge_ioctl;
  2908. dev->hard_start_xmit = skge_xmit_frame;
  2909. dev->get_stats = skge_get_stats;
  2910. if (hw->chip_id == CHIP_ID_GENESIS)
  2911. dev->set_multicast_list = genesis_set_multicast;
  2912. else
  2913. dev->set_multicast_list = yukon_set_multicast;
  2914. dev->set_mac_address = skge_set_mac_address;
  2915. dev->change_mtu = skge_change_mtu;
  2916. SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
  2917. dev->tx_timeout = skge_tx_timeout;
  2918. dev->watchdog_timeo = TX_WATCHDOG;
  2919. dev->poll = skge_poll;
  2920. dev->weight = NAPI_WEIGHT;
  2921. #ifdef CONFIG_NET_POLL_CONTROLLER
  2922. dev->poll_controller = skge_netpoll;
  2923. #endif
  2924. dev->irq = hw->pdev->irq;
  2925. if (highmem)
  2926. dev->features |= NETIF_F_HIGHDMA;
  2927. skge = netdev_priv(dev);
  2928. skge->netdev = dev;
  2929. skge->hw = hw;
  2930. skge->msg_enable = netif_msg_init(debug, default_msg);
  2931. skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
  2932. skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
  2933. /* Auto speed and flow control */
  2934. skge->autoneg = AUTONEG_ENABLE;
  2935. skge->flow_control = FLOW_MODE_SYM_OR_REM;
  2936. skge->duplex = -1;
  2937. skge->speed = -1;
  2938. skge->advertising = skge_supported_modes(hw);
  2939. if (pci_wake_enabled(hw->pdev))
  2940. skge->wol = wol_supported(hw) & WAKE_MAGIC;
  2941. hw->dev[port] = dev;
  2942. skge->port = port;
  2943. /* Only used for Genesis XMAC */
  2944. setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
  2945. if (hw->chip_id != CHIP_ID_GENESIS) {
  2946. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  2947. skge->rx_csum = 1;
  2948. }
  2949. /* read the mac address */
  2950. memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
  2951. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  2952. /* device is off until link detection */
  2953. netif_carrier_off(dev);
  2954. netif_stop_queue(dev);
  2955. return dev;
  2956. }
  2957. static void __devinit skge_show_addr(struct net_device *dev)
  2958. {
  2959. const struct skge_port *skge = netdev_priv(dev);
  2960. if (netif_msg_probe(skge))
  2961. printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  2962. dev->name,
  2963. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  2964. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  2965. }
  2966. static int __devinit skge_probe(struct pci_dev *pdev,
  2967. const struct pci_device_id *ent)
  2968. {
  2969. struct net_device *dev, *dev1;
  2970. struct skge_hw *hw;
  2971. int err, using_dac = 0;
  2972. err = pci_enable_device(pdev);
  2973. if (err) {
  2974. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2975. goto err_out;
  2976. }
  2977. err = pci_request_regions(pdev, DRV_NAME);
  2978. if (err) {
  2979. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2980. goto err_out_disable_pdev;
  2981. }
  2982. pci_set_master(pdev);
  2983. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  2984. using_dac = 1;
  2985. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  2986. } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
  2987. using_dac = 0;
  2988. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  2989. }
  2990. if (err) {
  2991. dev_err(&pdev->dev, "no usable DMA configuration\n");
  2992. goto err_out_free_regions;
  2993. }
  2994. #ifdef __BIG_ENDIAN
  2995. /* byte swap descriptors in hardware */
  2996. {
  2997. u32 reg;
  2998. pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
  2999. reg |= PCI_REV_DESC;
  3000. pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
  3001. }
  3002. #endif
  3003. err = -ENOMEM;
  3004. hw = kzalloc(sizeof(*hw), GFP_KERNEL);
  3005. if (!hw) {
  3006. dev_err(&pdev->dev, "cannot allocate hardware struct\n");
  3007. goto err_out_free_regions;
  3008. }
  3009. hw->pdev = pdev;
  3010. spin_lock_init(&hw->hw_lock);
  3011. spin_lock_init(&hw->phy_lock);
  3012. tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
  3013. hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
  3014. if (!hw->regs) {
  3015. dev_err(&pdev->dev, "cannot map device registers\n");
  3016. goto err_out_free_hw;
  3017. }
  3018. err = skge_reset(hw);
  3019. if (err)
  3020. goto err_out_iounmap;
  3021. printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
  3022. (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
  3023. skge_board_name(hw), hw->chip_rev);
  3024. dev = skge_devinit(hw, 0, using_dac);
  3025. if (!dev)
  3026. goto err_out_led_off;
  3027. /* Some motherboards are broken and has zero in ROM. */
  3028. if (!is_valid_ether_addr(dev->dev_addr))
  3029. dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
  3030. err = register_netdev(dev);
  3031. if (err) {
  3032. dev_err(&pdev->dev, "cannot register net device\n");
  3033. goto err_out_free_netdev;
  3034. }
  3035. err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
  3036. if (err) {
  3037. dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
  3038. dev->name, pdev->irq);
  3039. goto err_out_unregister;
  3040. }
  3041. skge_show_addr(dev);
  3042. if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
  3043. if (register_netdev(dev1) == 0)
  3044. skge_show_addr(dev1);
  3045. else {
  3046. /* Failure to register second port need not be fatal */
  3047. dev_warn(&pdev->dev, "register of second port failed\n");
  3048. hw->dev[1] = NULL;
  3049. free_netdev(dev1);
  3050. }
  3051. }
  3052. pci_set_drvdata(pdev, hw);
  3053. return 0;
  3054. err_out_unregister:
  3055. unregister_netdev(dev);
  3056. err_out_free_netdev:
  3057. free_netdev(dev);
  3058. err_out_led_off:
  3059. skge_write16(hw, B0_LED, LED_STAT_OFF);
  3060. err_out_iounmap:
  3061. iounmap(hw->regs);
  3062. err_out_free_hw:
  3063. kfree(hw);
  3064. err_out_free_regions:
  3065. pci_release_regions(pdev);
  3066. err_out_disable_pdev:
  3067. pci_disable_device(pdev);
  3068. pci_set_drvdata(pdev, NULL);
  3069. err_out:
  3070. return err;
  3071. }
  3072. static void __devexit skge_remove(struct pci_dev *pdev)
  3073. {
  3074. struct skge_hw *hw = pci_get_drvdata(pdev);
  3075. struct net_device *dev0, *dev1;
  3076. if (!hw)
  3077. return;
  3078. flush_scheduled_work();
  3079. if ((dev1 = hw->dev[1]))
  3080. unregister_netdev(dev1);
  3081. dev0 = hw->dev[0];
  3082. unregister_netdev(dev0);
  3083. tasklet_disable(&hw->phy_task);
  3084. spin_lock_irq(&hw->hw_lock);
  3085. hw->intr_mask = 0;
  3086. skge_write32(hw, B0_IMSK, 0);
  3087. skge_read32(hw, B0_IMSK);
  3088. spin_unlock_irq(&hw->hw_lock);
  3089. skge_write16(hw, B0_LED, LED_STAT_OFF);
  3090. skge_write8(hw, B0_CTST, CS_RST_SET);
  3091. free_irq(pdev->irq, hw);
  3092. pci_release_regions(pdev);
  3093. pci_disable_device(pdev);
  3094. if (dev1)
  3095. free_netdev(dev1);
  3096. free_netdev(dev0);
  3097. iounmap(hw->regs);
  3098. kfree(hw);
  3099. pci_set_drvdata(pdev, NULL);
  3100. }
  3101. #ifdef CONFIG_PM
  3102. static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
  3103. {
  3104. struct skge_hw *hw = pci_get_drvdata(pdev);
  3105. int i, err, wol = 0;
  3106. if (!hw)
  3107. return 0;
  3108. err = pci_save_state(pdev);
  3109. if (err)
  3110. return err;
  3111. for (i = 0; i < hw->ports; i++) {
  3112. struct net_device *dev = hw->dev[i];
  3113. struct skge_port *skge = netdev_priv(dev);
  3114. if (netif_running(dev))
  3115. skge_down(dev);
  3116. if (skge->wol)
  3117. skge_wol_init(skge);
  3118. wol |= skge->wol;
  3119. }
  3120. skge_write32(hw, B0_IMSK, 0);
  3121. pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
  3122. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  3123. return 0;
  3124. }
  3125. static int skge_resume(struct pci_dev *pdev)
  3126. {
  3127. struct skge_hw *hw = pci_get_drvdata(pdev);
  3128. int i, err;
  3129. if (!hw)
  3130. return 0;
  3131. err = pci_set_power_state(pdev, PCI_D0);
  3132. if (err)
  3133. goto out;
  3134. err = pci_restore_state(pdev);
  3135. if (err)
  3136. goto out;
  3137. pci_enable_wake(pdev, PCI_D0, 0);
  3138. err = skge_reset(hw);
  3139. if (err)
  3140. goto out;
  3141. for (i = 0; i < hw->ports; i++) {
  3142. struct net_device *dev = hw->dev[i];
  3143. if (netif_running(dev)) {
  3144. err = skge_up(dev);
  3145. if (err) {
  3146. printk(KERN_ERR PFX "%s: could not up: %d\n",
  3147. dev->name, err);
  3148. dev_close(dev);
  3149. goto out;
  3150. }
  3151. }
  3152. }
  3153. out:
  3154. return err;
  3155. }
  3156. #endif
  3157. static void skge_shutdown(struct pci_dev *pdev)
  3158. {
  3159. struct skge_hw *hw = pci_get_drvdata(pdev);
  3160. int i, wol = 0;
  3161. if (!hw)
  3162. return;
  3163. for (i = 0; i < hw->ports; i++) {
  3164. struct net_device *dev = hw->dev[i];
  3165. struct skge_port *skge = netdev_priv(dev);
  3166. if (skge->wol)
  3167. skge_wol_init(skge);
  3168. wol |= skge->wol;
  3169. }
  3170. pci_enable_wake(pdev, PCI_D3hot, wol);
  3171. pci_enable_wake(pdev, PCI_D3cold, wol);
  3172. pci_disable_device(pdev);
  3173. pci_set_power_state(pdev, PCI_D3hot);
  3174. }
  3175. static struct pci_driver skge_driver = {
  3176. .name = DRV_NAME,
  3177. .id_table = skge_id_table,
  3178. .probe = skge_probe,
  3179. .remove = __devexit_p(skge_remove),
  3180. #ifdef CONFIG_PM
  3181. .suspend = skge_suspend,
  3182. .resume = skge_resume,
  3183. #endif
  3184. .shutdown = skge_shutdown,
  3185. };
  3186. static int __init skge_init_module(void)
  3187. {
  3188. return pci_register_driver(&skge_driver);
  3189. }
  3190. static void __exit skge_cleanup_module(void)
  3191. {
  3192. pci_unregister_driver(&skge_driver);
  3193. }
  3194. module_init(skge_init_module);
  3195. module_exit(skge_cleanup_module);