sis900.h 11 KB

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  1. /* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
  2. * Copyright 1999 Silicon Integrated System Corporation
  3. * References:
  4. * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
  5. * preliminary Rev. 1.0 Jan. 14, 1998
  6. * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
  7. * preliminary Rev. 1.0 Nov. 10, 1998
  8. * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
  9. * preliminary Rev. 1.0 Jan. 18, 1998
  10. * http://www.sis.com.tw/support/databook.htm
  11. */
  12. /*
  13. * SiS 7016 and SiS 900 ethernet controller registers
  14. */
  15. /* The I/O extent, SiS 900 needs 256 bytes of io address */
  16. #define SIS900_TOTAL_SIZE 0x100
  17. /* Symbolic offsets to registers. */
  18. enum sis900_registers {
  19. cr=0x0, //Command Register
  20. cfg=0x4, //Configuration Register
  21. mear=0x8, //EEPROM Access Register
  22. ptscr=0xc, //PCI Test Control Register
  23. isr=0x10, //Interrupt Status Register
  24. imr=0x14, //Interrupt Mask Register
  25. ier=0x18, //Interrupt Enable Register
  26. epar=0x18, //Enhanced PHY Access Register
  27. txdp=0x20, //Transmit Descriptor Pointer Register
  28. txcfg=0x24, //Transmit Configuration Register
  29. rxdp=0x30, //Receive Descriptor Pointer Register
  30. rxcfg=0x34, //Receive Configuration Register
  31. flctrl=0x38, //Flow Control Register
  32. rxlen=0x3c, //Receive Packet Length Register
  33. rfcr=0x48, //Receive Filter Control Register
  34. rfdr=0x4C, //Receive Filter Data Register
  35. pmctrl=0xB0, //Power Management Control Register
  36. pmer=0xB4 //Power Management Wake-up Event Register
  37. };
  38. /* Symbolic names for bits in various registers */
  39. enum sis900_command_register_bits {
  40. RELOAD = 0x00000400, ACCESSMODE = 0x00000200,/* ET */
  41. RESET = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020,
  42. TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004,
  43. TxDIS = 0x00000002, TxENA = 0x00000001
  44. };
  45. enum sis900_configuration_register_bits {
  46. DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
  47. SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
  48. PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
  49. /* 635 & 900B Specific */
  50. RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
  51. EDB_MASTER_EN = 0x00002000
  52. };
  53. enum sis900_eeprom_access_reigster_bits {
  54. MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
  55. EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
  56. EEDI = 0x00000001
  57. };
  58. enum sis900_interrupt_register_bits {
  59. WKEVT = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000,
  60. TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000,
  61. SSERR = 0x00400000, RMABT = 0x00200000, RTABT = 0x00100000,
  62. RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000,
  63. MIBINT = 0x00000800, TxURN = 0x00000400, TxIDLE = 0x00000200,
  64. TxERR = 0x00000100, TxDESC = 0x00000080, TxOK = 0x00000040,
  65. RxORN = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008,
  66. RxERR = 0x00000004, RxDESC = 0x00000002, RxOK = 0x00000001
  67. };
  68. enum sis900_interrupt_enable_reigster_bits {
  69. IE = 0x00000001
  70. };
  71. /* maximum dma burst for transmission and receive */
  72. #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */
  73. #define TxMXDMA_shift 20
  74. #define RxMXDMA_shift 20
  75. enum sis900_tx_rx_dma{
  76. DMA_BURST_512 = 0, DMA_BURST_64 = 5
  77. };
  78. /* transmit FIFO thresholds */
  79. #define TX_FILL_THRESH 16 /* 1/4 FIFO size */
  80. #define TxFILLT_shift 8
  81. #define TxDRNT_shift 0
  82. #define TxDRNT_100 48 /* 3/4 FIFO size */
  83. #define TxDRNT_10 16 /* 1/2 FIFO size */
  84. enum sis900_transmit_config_register_bits {
  85. TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000,
  86. TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00,
  87. TxDRNT = 0x0000003F
  88. };
  89. /* recevie FIFO thresholds */
  90. #define RxDRNT_shift 1
  91. #define RxDRNT_100 16 /* 1/2 FIFO size */
  92. #define RxDRNT_10 24 /* 3/4 FIFO size */
  93. enum sis900_reveive_config_register_bits {
  94. RxAEP = 0x80000000, RxARP = 0x40000000, RxATX = 0x10000000,
  95. RxAJAB = 0x08000000, RxDRNT = 0x0000007F
  96. };
  97. #define RFAA_shift 28
  98. #define RFADDR_shift 16
  99. enum sis900_receive_filter_control_register_bits {
  100. RFEN = 0x80000000, RFAAB = 0x40000000, RFAAM = 0x20000000,
  101. RFAAP = 0x10000000, RFPromiscuous = (RFAAB|RFAAM|RFAAP)
  102. };
  103. enum sis900_reveive_filter_data_mask {
  104. RFDAT = 0x0000FFFF
  105. };
  106. /* EEPROM Addresses */
  107. enum sis900_eeprom_address {
  108. EEPROMSignature = 0x00, EEPROMVendorID = 0x02, EEPROMDeviceID = 0x03,
  109. EEPROMMACAddr = 0x08, EEPROMChecksum = 0x0b
  110. };
  111. /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
  112. enum sis900_eeprom_command {
  113. EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
  114. EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
  115. EEeraseAll = 0x0120, EEwriteAll = 0x0110,
  116. EEaddrMask = 0x013F, EEcmdShift = 16
  117. };
  118. /* For SiS962 or SiS963, request the eeprom software access */
  119. enum sis96x_eeprom_command {
  120. EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
  121. };
  122. /* PCI Registers */
  123. enum sis900_pci_registers {
  124. CFGPMC = 0x40,
  125. CFGPMCSR = 0x44
  126. };
  127. /* Power management capabilities bits */
  128. enum sis900_cfgpmc_register_bits {
  129. PMVER = 0x00070000,
  130. DSI = 0x00100000,
  131. PMESP = 0xf8000000
  132. };
  133. enum sis900_pmesp_bits {
  134. PME_D0 = 0x1,
  135. PME_D1 = 0x2,
  136. PME_D2 = 0x4,
  137. PME_D3H = 0x8,
  138. PME_D3C = 0x10
  139. };
  140. /* Power management control/status bits */
  141. enum sis900_cfgpmcsr_register_bits {
  142. PMESTS = 0x00004000,
  143. PME_EN = 0x00000100, // Power management enable
  144. PWR_STA = 0x00000003 // Current power state
  145. };
  146. /* Wake-on-LAN support. */
  147. enum sis900_power_management_control_register_bits {
  148. LINKLOSS = 0x00000001,
  149. LINKON = 0x00000002,
  150. MAGICPKT = 0x00000400,
  151. ALGORITHM = 0x00000800,
  152. FRM1EN = 0x00100000,
  153. FRM2EN = 0x00200000,
  154. FRM3EN = 0x00400000,
  155. FRM1ACS = 0x01000000,
  156. FRM2ACS = 0x02000000,
  157. FRM3ACS = 0x04000000,
  158. WAKEALL = 0x40000000,
  159. GATECLK = 0x80000000
  160. };
  161. /* Management Data I/O (mdio) frame */
  162. #define MIIread 0x6000
  163. #define MIIwrite 0x5002
  164. #define MIIpmdShift 7
  165. #define MIIregShift 2
  166. #define MIIcmdLen 16
  167. #define MIIcmdShift 16
  168. /* Buffer Descriptor Status*/
  169. enum sis900_buffer_status {
  170. OWN = 0x80000000, MORE = 0x40000000, INTR = 0x20000000,
  171. SUPCRC = 0x10000000, INCCRC = 0x10000000,
  172. OK = 0x08000000, DSIZE = 0x00000FFF
  173. };
  174. /* Status for TX Buffers */
  175. enum sis900_tx_buffer_status {
  176. ABORT = 0x04000000, UNDERRUN = 0x02000000, NOCARRIER = 0x01000000,
  177. DEFERD = 0x00800000, EXCDEFER = 0x00400000, OWCOLL = 0x00200000,
  178. EXCCOLL = 0x00100000, COLCNT = 0x000F0000
  179. };
  180. enum sis900_rx_bufer_status {
  181. OVERRUN = 0x02000000, DEST = 0x00800000, BCAST = 0x01800000,
  182. MCAST = 0x01000000, UNIMATCH = 0x00800000, TOOLONG = 0x00400000,
  183. RUNT = 0x00200000, RXISERR = 0x00100000, CRCERR = 0x00080000,
  184. FAERR = 0x00040000, LOOPBK = 0x00020000, RXCOL = 0x00010000
  185. };
  186. /* MII register offsets */
  187. enum mii_registers {
  188. MII_CONTROL = 0x0000, MII_STATUS = 0x0001, MII_PHY_ID0 = 0x0002,
  189. MII_PHY_ID1 = 0x0003, MII_ANADV = 0x0004, MII_ANLPAR = 0x0005,
  190. MII_ANEXT = 0x0006
  191. };
  192. /* mii registers specific to SiS 900 */
  193. enum sis_mii_registers {
  194. MII_CONFIG1 = 0x0010, MII_CONFIG2 = 0x0011, MII_STSOUT = 0x0012,
  195. MII_MASK = 0x0013, MII_RESV = 0x0014
  196. };
  197. /* mii registers specific to ICS 1893 */
  198. enum ics_mii_registers {
  199. MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
  200. MII_EXTCTRL2 = 0x0013
  201. };
  202. /* mii registers specific to AMD 79C901 */
  203. enum amd_mii_registers {
  204. MII_STATUS_SUMMARY = 0x0018
  205. };
  206. /* MII Control register bit definitions. */
  207. enum mii_control_register_bits {
  208. MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
  209. MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800,
  210. MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000,
  211. MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000
  212. };
  213. /* MII Status register bit */
  214. enum mii_status_register_bits {
  215. MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
  216. MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
  217. MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020,
  218. MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000,
  219. MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,
  220. MII_STAT_CAN_T4 = 0x8000
  221. };
  222. #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
  223. #define MII_ID1_MODEL 0x03F0 /* model number */
  224. #define MII_ID1_REV 0x000F /* model number */
  225. /* MII NWAY Register Bits ...
  226. valid for the ANAR (Auto-Negotiation Advertisement) and
  227. ANLPAR (Auto-Negotiation Link Partner) registers */
  228. enum mii_nway_register_bits {
  229. MII_NWAY_NODE_SEL = 0x001f, MII_NWAY_CSMA_CD = 0x0001,
  230. MII_NWAY_T = 0x0020, MII_NWAY_T_FDX = 0x0040,
  231. MII_NWAY_TX = 0x0080, MII_NWAY_TX_FDX = 0x0100,
  232. MII_NWAY_T4 = 0x0200, MII_NWAY_PAUSE = 0x0400,
  233. MII_NWAY_RF = 0x2000, MII_NWAY_ACK = 0x4000,
  234. MII_NWAY_NP = 0x8000
  235. };
  236. enum mii_stsout_register_bits {
  237. MII_STSOUT_LINK_FAIL = 0x4000,
  238. MII_STSOUT_SPD = 0x0080, MII_STSOUT_DPLX = 0x0040
  239. };
  240. enum mii_stsics_register_bits {
  241. MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000,
  242. MII_STSICS_LINKSTS = 0x0001
  243. };
  244. enum mii_stssum_register_bits {
  245. MII_STSSUM_LINK = 0x0008, MII_STSSUM_DPLX = 0x0004,
  246. MII_STSSUM_AUTO = 0x0002, MII_STSSUM_SPD = 0x0001
  247. };
  248. enum sis900_revision_id {
  249. SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81,
  250. SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83,
  251. SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90,
  252. SIS96x_900_REV = 0X91, SIS900B_900_REV = 0x03
  253. };
  254. enum sis630_revision_id {
  255. SIS630A0 = 0x00, SIS630A1 = 0x01,
  256. SIS630B0 = 0x10, SIS630B1 = 0x11
  257. };
  258. #define FDX_CAPABLE_DUPLEX_UNKNOWN 0
  259. #define FDX_CAPABLE_HALF_SELECTED 1
  260. #define FDX_CAPABLE_FULL_SELECTED 2
  261. #define HW_SPEED_UNCONFIG 0
  262. #define HW_SPEED_HOME 1
  263. #define HW_SPEED_10_MBPS 10
  264. #define HW_SPEED_100_MBPS 100
  265. #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
  266. #define CRC_SIZE 4
  267. #define MAC_HEADER_SIZE 14
  268. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  269. #define MAX_FRAME_SIZE (1518 + 4)
  270. #else
  271. #define MAX_FRAME_SIZE 1518
  272. #endif /* CONFIG_VLAN_802_1Q */
  273. #define TX_BUF_SIZE (MAX_FRAME_SIZE+18)
  274. #define RX_BUF_SIZE (MAX_FRAME_SIZE+18)
  275. #define NUM_TX_DESC 16 /* Number of Tx descriptor registers. */
  276. #define NUM_RX_DESC 16 /* Number of Rx descriptor registers. */
  277. #define TX_TOTAL_SIZE NUM_TX_DESC*sizeof(BufferDesc)
  278. #define RX_TOTAL_SIZE NUM_RX_DESC*sizeof(BufferDesc)
  279. /* PCI stuff, should be move to pci.h */
  280. #define SIS630_VENDOR_ID 0x1039
  281. #define SIS630_DEVICE_ID 0x0630