seeq8005.h 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156
  1. /*
  2. * defines, etc for the seeq8005
  3. */
  4. /*
  5. * This file is distributed under GPL.
  6. *
  7. * This style and layout of this file is also copied
  8. * from many of the other linux network device drivers.
  9. */
  10. /* The number of low I/O ports used by the ethercard. */
  11. #define SEEQ8005_IO_EXTENT 16
  12. #define SEEQ_B (ioaddr)
  13. #define SEEQ_CMD (SEEQ_B) /* Write only */
  14. #define SEEQ_STATUS (SEEQ_B) /* Read only */
  15. #define SEEQ_CFG1 (SEEQ_B + 2)
  16. #define SEEQ_CFG2 (SEEQ_B + 4)
  17. #define SEEQ_REA (SEEQ_B + 6) /* Receive End Area Register */
  18. #define SEEQ_RPR (SEEQ_B + 10) /* Receive Pointer Register */
  19. #define SEEQ_TPR (SEEQ_B + 12) /* Transmit Pointer Register */
  20. #define SEEQ_DMAAR (SEEQ_B + 14) /* DMA Address Register */
  21. #define SEEQ_BUFFER (SEEQ_B + 8) /* Buffer Window Register */
  22. #define DEFAULT_TEA (0x3f)
  23. #define SEEQCMD_DMA_INT_EN (0x0001) /* DMA Interrupt Enable */
  24. #define SEEQCMD_RX_INT_EN (0x0002) /* Receive Interrupt Enable */
  25. #define SEEQCMD_TX_INT_EN (0x0004) /* Transmit Interrupt Enable */
  26. #define SEEQCMD_WINDOW_INT_EN (0x0008) /* What the hell is this for?? */
  27. #define SEEQCMD_INT_MASK (0x000f)
  28. #define SEEQCMD_DMA_INT_ACK (0x0010) /* DMA ack */
  29. #define SEEQCMD_RX_INT_ACK (0x0020)
  30. #define SEEQCMD_TX_INT_ACK (0x0040)
  31. #define SEEQCMD_WINDOW_INT_ACK (0x0080)
  32. #define SEEQCMD_ACK_ALL (0x00f0)
  33. #define SEEQCMD_SET_DMA_ON (0x0100) /* Enables DMA Request logic */
  34. #define SEEQCMD_SET_RX_ON (0x0200) /* Enables Packet RX */
  35. #define SEEQCMD_SET_TX_ON (0x0400) /* Starts TX run */
  36. #define SEEQCMD_SET_DMA_OFF (0x0800)
  37. #define SEEQCMD_SET_RX_OFF (0x1000)
  38. #define SEEQCMD_SET_TX_OFF (0x2000)
  39. #define SEEQCMD_SET_ALL_OFF (0x3800) /* set all logic off */
  40. #define SEEQCMD_FIFO_READ (0x4000) /* Set FIFO to read mode (read from Buffer) */
  41. #define SEEQCMD_FIFO_WRITE (0x8000) /* Set FIFO to write mode */
  42. #define SEEQSTAT_DMA_INT_EN (0x0001) /* Status of interrupt enable */
  43. #define SEEQSTAT_RX_INT_EN (0x0002)
  44. #define SEEQSTAT_TX_INT_EN (0x0004)
  45. #define SEEQSTAT_WINDOW_INT_EN (0x0008)
  46. #define SEEQSTAT_DMA_INT (0x0010) /* Interrupt flagged */
  47. #define SEEQSTAT_RX_INT (0x0020)
  48. #define SEEQSTAT_TX_INT (0x0040)
  49. #define SEEQSTAT_WINDOW_INT (0x0080)
  50. #define SEEQSTAT_ANY_INT (0x00f0)
  51. #define SEEQSTAT_DMA_ON (0x0100) /* DMA logic on */
  52. #define SEEQSTAT_RX_ON (0x0200) /* Packet RX on */
  53. #define SEEQSTAT_TX_ON (0x0400) /* TX running */
  54. #define SEEQSTAT_FIFO_FULL (0x2000)
  55. #define SEEQSTAT_FIFO_EMPTY (0x4000)
  56. #define SEEQSTAT_FIFO_DIR (0x8000) /* 1=read, 0=write */
  57. #define SEEQCFG1_BUFFER_MASK (0x000f) /* define what maps into the BUFFER register */
  58. #define SEEQCFG1_BUFFER_MAC0 (0x0000) /* MAC station addresses 0-5 */
  59. #define SEEQCFG1_BUFFER_MAC1 (0x0001)
  60. #define SEEQCFG1_BUFFER_MAC2 (0x0002)
  61. #define SEEQCFG1_BUFFER_MAC3 (0x0003)
  62. #define SEEQCFG1_BUFFER_MAC4 (0x0004)
  63. #define SEEQCFG1_BUFFER_MAC5 (0x0005)
  64. #define SEEQCFG1_BUFFER_PROM (0x0006) /* The Address/CFG PROM */
  65. #define SEEQCFG1_BUFFER_TEA (0x0007) /* Transmit end area */
  66. #define SEEQCFG1_BUFFER_BUFFER (0x0008) /* Packet buffer memory */
  67. #define SEEQCFG1_BUFFER_INT_VEC (0x0009) /* Interrupt Vector */
  68. #define SEEQCFG1_DMA_INTVL_MASK (0x0030)
  69. #define SEEQCFG1_DMA_CONT (0x0000)
  70. #define SEEQCFG1_DMA_800ns (0x0010)
  71. #define SEEQCFG1_DMA_1600ns (0x0020)
  72. #define SEEQCFG1_DMA_3200ns (0x0030)
  73. #define SEEQCFG1_DMA_LEN_MASK (0x00c0)
  74. #define SEEQCFG1_DMA_LEN1 (0x0000)
  75. #define SEEQCFG1_DMA_LEN2 (0x0040)
  76. #define SEEQCFG1_DMA_LEN4 (0x0080)
  77. #define SEEQCFG1_DMA_LEN8 (0x00c0)
  78. #define SEEQCFG1_MAC_MASK (0x3f00) /* Dis/enable bits for MAC addresses */
  79. #define SEEQCFG1_MAC0_EN (0x0100)
  80. #define SEEQCFG1_MAC1_EN (0x0200)
  81. #define SEEQCFG1_MAC2_EN (0x0400)
  82. #define SEEQCFG1_MAC3_EN (0x0800)
  83. #define SEEQCFG1_MAC4_EN (0x1000)
  84. #define SEEQCFG1_MAC5_EN (0x2000)
  85. #define SEEQCFG1_MATCH_MASK (0xc000) /* Packet matching logic cfg bits */
  86. #define SEEQCFG1_MATCH_SPECIFIC (0x0000) /* only matching MAC addresses */
  87. #define SEEQCFG1_MATCH_BROAD (0x4000) /* matching and broadcast addresses */
  88. #define SEEQCFG1_MATCH_MULTI (0x8000) /* matching, broadcast and multicast */
  89. #define SEEQCFG1_MATCH_ALL (0xc000) /* Promiscuous mode */
  90. #define SEEQCFG1_DEFAULT (SEEQCFG1_BUFFER_BUFFER | SEEQCFG1_MAC0_EN | SEEQCFG1_MATCH_BROAD)
  91. #define SEEQCFG2_BYTE_SWAP (0x0001) /* 0=Intel byte-order */
  92. #define SEEQCFG2_AUTO_REA (0x0002) /* if set, Receive End Area will be updated when reading from Buffer */
  93. #define SEEQCFG2_CRC_ERR_EN (0x0008) /* enables receiving of packets with CRC errors */
  94. #define SEEQCFG2_DRIBBLE_EN (0x0010) /* enables receiving of non-aligned packets */
  95. #define SEEQCFG2_SHORT_EN (0x0020) /* enables receiving of short packets */
  96. #define SEEQCFG2_SLOTSEL (0x0040) /* 0= standard IEEE802.3, 1= smaller,faster, non-standard */
  97. #define SEEQCFG2_NO_PREAM (0x0080) /* 1= user supplies Xmit preamble bytes */
  98. #define SEEQCFG2_ADDR_LEN (0x0100) /* 1= 2byte addresses */
  99. #define SEEQCFG2_REC_CRC (0x0200) /* 0= received packets will have CRC stripped from them */
  100. #define SEEQCFG2_XMIT_NO_CRC (0x0400) /* don't xmit CRC with each packet (user supplies it) */
  101. #define SEEQCFG2_LOOPBACK (0x0800)
  102. #define SEEQCFG2_CTRLO (0x1000)
  103. #define SEEQCFG2_RESET (0x8000) /* software Hard-reset bit */
  104. struct seeq_pkt_hdr {
  105. unsigned short next; /* address of next packet header */
  106. unsigned char babble_int:1, /* enable int on >1514 byte packet */
  107. coll_int:1, /* enable int on collision */
  108. coll_16_int:1, /* enable int on >15 collision */
  109. xmit_int:1, /* enable int on success (or xmit with <15 collision) */
  110. unused:1,
  111. data_follows:1, /* if not set, process this as a header and pointer only */
  112. chain_cont:1, /* if set, more headers in chain only cmd bit valid in recv header */
  113. xmit_recv:1; /* if set, a xmit packet, else a receive packet.*/
  114. unsigned char status;
  115. };
  116. #define SEEQPKTH_BAB_INT_EN (0x01) /* xmit only */
  117. #define SEEQPKTH_COL_INT_EN (0x02) /* xmit only */
  118. #define SEEQPKTH_COL16_INT_EN (0x04) /* xmit only */
  119. #define SEEQPKTH_XMIT_INT_EN (0x08) /* xmit only */
  120. #define SEEQPKTH_DATA_FOLLOWS (0x20) /* supposedly in xmit only */
  121. #define SEEQPKTH_CHAIN (0x40) /* more headers follow */
  122. #define SEEQPKTH_XMIT (0x80)
  123. #define SEEQPKTS_BABBLE (0x0100) /* xmit only */
  124. #define SEEQPKTS_OVERSIZE (0x0100) /* recv only */
  125. #define SEEQPKTS_COLLISION (0x0200) /* xmit only */
  126. #define SEEQPKTS_CRC_ERR (0x0200) /* recv only */
  127. #define SEEQPKTS_COLL16 (0x0400) /* xmit only */
  128. #define SEEQPKTS_DRIB (0x0400) /* recv only */
  129. #define SEEQPKTS_SHORT (0x0800) /* recv only */
  130. #define SEEQPKTS_DONE (0x8000)
  131. #define SEEQPKTS_ANY_ERROR (0x0f00)