sc92031.c 40 KB

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  1. /* Silan SC92031 PCI Fast Ethernet Adapter driver
  2. *
  3. * Based on vendor drivers:
  4. * Silan Fast Ethernet Netcard Driver:
  5. * MODULE_AUTHOR ("gaoyonghong");
  6. * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
  7. * MODULE_LICENSE("GPL");
  8. * 8139D Fast Ethernet driver:
  9. * (C) 2002 by gaoyonghong
  10. * MODULE_AUTHOR ("gaoyonghong");
  11. * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
  12. * MODULE_LICENSE("GPL");
  13. * Both are almost identical and seem to be based on pci-skeleton.c
  14. *
  15. * Rewritten for 2.6 by Cesar Eduardo Barros
  16. */
  17. /* Note about set_mac_address: I don't know how to change the hardware
  18. * matching, so you need to enable IFF_PROMISC when using it.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/delay.h>
  23. #include <linux/pci.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/crc32.h>
  29. #include <asm/irq.h>
  30. #define PCI_VENDOR_ID_SILAN 0x1904
  31. #define PCI_DEVICE_ID_SILAN_SC92031 0x2031
  32. #define PCI_DEVICE_ID_SILAN_8139D 0x8139
  33. #define SC92031_NAME "sc92031"
  34. #define SC92031_DESCRIPTION "Silan SC92031 PCI Fast Ethernet Adapter driver"
  35. #define SC92031_VERSION "2.0c"
  36. /* BAR 0 is MMIO, BAR 1 is PIO */
  37. #ifndef SC92031_USE_BAR
  38. #define SC92031_USE_BAR 0
  39. #endif
  40. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
  41. static int multicast_filter_limit = 64;
  42. module_param(multicast_filter_limit, int, 0);
  43. MODULE_PARM_DESC(multicast_filter_limit,
  44. "Maximum number of filtered multicast addresses");
  45. static int media;
  46. module_param(media, int, 0);
  47. MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
  48. " 0x01 = 10M half, 0x02 = 10M full,"
  49. " 0x04 = 100M half, 0x08 = 100M full)");
  50. /* Size of the in-memory receive ring. */
  51. #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
  52. #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
  53. /* Number of Tx descriptor registers. */
  54. #define NUM_TX_DESC 4
  55. /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
  56. #define MAX_ETH_FRAME_SIZE 1536
  57. /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
  58. #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
  59. #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
  60. /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
  61. #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
  62. /* Time in jiffies before concluding the transmitter is hung. */
  63. #define TX_TIMEOUT (4*HZ)
  64. #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
  65. /* media options */
  66. #define AUTOSELECT 0x00
  67. #define M10_HALF 0x01
  68. #define M10_FULL 0x02
  69. #define M100_HALF 0x04
  70. #define M100_FULL 0x08
  71. /* Symbolic offsets to registers. */
  72. enum silan_registers {
  73. Config0 = 0x00, // Config0
  74. Config1 = 0x04, // Config1
  75. RxBufWPtr = 0x08, // Rx buffer writer poiter
  76. IntrStatus = 0x0C, // Interrupt status
  77. IntrMask = 0x10, // Interrupt mask
  78. RxbufAddr = 0x14, // Rx buffer start address
  79. RxBufRPtr = 0x18, // Rx buffer read pointer
  80. Txstatusall = 0x1C, // Transmit status of all descriptors
  81. TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
  82. TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
  83. RxConfig = 0x40, // Rx configuration
  84. MAC0 = 0x44, // Ethernet hardware address.
  85. MAR0 = 0x4C, // Multicast filter.
  86. RxStatus0 = 0x54, // Rx status
  87. TxConfig = 0x5C, // Tx configuration
  88. PhyCtrl = 0x60, // physical control
  89. FlowCtrlConfig = 0x64, // flow control
  90. Miicmd0 = 0x68, // Mii command0 register
  91. Miicmd1 = 0x6C, // Mii command1 register
  92. Miistatus = 0x70, // Mii status register
  93. Timercnt = 0x74, // Timer counter register
  94. TimerIntr = 0x78, // Timer interrupt register
  95. PMConfig = 0x7C, // Power Manager configuration
  96. CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
  97. Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
  98. LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
  99. TestD0 = 0xD0,
  100. TestD4 = 0xD4,
  101. TestD8 = 0xD8,
  102. };
  103. #define MII_BMCR 0 // Basic mode control register
  104. #define MII_BMSR 1 // Basic mode status register
  105. #define MII_JAB 16
  106. #define MII_OutputStatus 24
  107. #define BMCR_FULLDPLX 0x0100 // Full duplex
  108. #define BMCR_ANRESTART 0x0200 // Auto negotiation restart
  109. #define BMCR_ANENABLE 0x1000 // Enable auto negotiation
  110. #define BMCR_SPEED100 0x2000 // Select 100Mbps
  111. #define BMSR_LSTATUS 0x0004 // Link status
  112. #define PHY_16_JAB_ENB 0x1000
  113. #define PHY_16_PORT_ENB 0x1
  114. enum IntrStatusBits {
  115. LinkFail = 0x80000000,
  116. LinkOK = 0x40000000,
  117. TimeOut = 0x20000000,
  118. RxOverflow = 0x0040,
  119. RxOK = 0x0020,
  120. TxOK = 0x0001,
  121. IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
  122. };
  123. enum TxStatusBits {
  124. TxCarrierLost = 0x20000000,
  125. TxAborted = 0x10000000,
  126. TxOutOfWindow = 0x08000000,
  127. TxNccShift = 22,
  128. EarlyTxThresShift = 16,
  129. TxStatOK = 0x8000,
  130. TxUnderrun = 0x4000,
  131. TxOwn = 0x2000,
  132. };
  133. enum RxStatusBits {
  134. RxStatesOK = 0x80000,
  135. RxBadAlign = 0x40000,
  136. RxHugeFrame = 0x20000,
  137. RxSmallFrame = 0x10000,
  138. RxCRCOK = 0x8000,
  139. RxCrlFrame = 0x4000,
  140. Rx_Broadcast = 0x2000,
  141. Rx_Multicast = 0x1000,
  142. RxAddrMatch = 0x0800,
  143. MiiErr = 0x0400,
  144. };
  145. enum RxConfigBits {
  146. RxFullDx = 0x80000000,
  147. RxEnb = 0x40000000,
  148. RxSmall = 0x20000000,
  149. RxHuge = 0x10000000,
  150. RxErr = 0x08000000,
  151. RxAllphys = 0x04000000,
  152. RxMulticast = 0x02000000,
  153. RxBroadcast = 0x01000000,
  154. RxLoopBack = (1 << 23) | (1 << 22),
  155. LowThresholdShift = 12,
  156. HighThresholdShift = 2,
  157. };
  158. enum TxConfigBits {
  159. TxFullDx = 0x80000000,
  160. TxEnb = 0x40000000,
  161. TxEnbPad = 0x20000000,
  162. TxEnbHuge = 0x10000000,
  163. TxEnbFCS = 0x08000000,
  164. TxNoBackOff = 0x04000000,
  165. TxEnbPrem = 0x02000000,
  166. TxCareLostCrs = 0x1000000,
  167. TxExdCollNum = 0xf00000,
  168. TxDataRate = 0x80000,
  169. };
  170. enum PhyCtrlconfigbits {
  171. PhyCtrlAne = 0x80000000,
  172. PhyCtrlSpd100 = 0x40000000,
  173. PhyCtrlSpd10 = 0x20000000,
  174. PhyCtrlPhyBaseAddr = 0x1f000000,
  175. PhyCtrlDux = 0x800000,
  176. PhyCtrlReset = 0x400000,
  177. };
  178. enum FlowCtrlConfigBits {
  179. FlowCtrlFullDX = 0x80000000,
  180. FlowCtrlEnb = 0x40000000,
  181. };
  182. enum Config0Bits {
  183. Cfg0_Reset = 0x80000000,
  184. Cfg0_Anaoff = 0x40000000,
  185. Cfg0_LDPS = 0x20000000,
  186. };
  187. enum Config1Bits {
  188. Cfg1_EarlyRx = 1 << 31,
  189. Cfg1_EarlyTx = 1 << 30,
  190. //rx buffer size
  191. Cfg1_Rcv8K = 0x0,
  192. Cfg1_Rcv16K = 0x1,
  193. Cfg1_Rcv32K = 0x3,
  194. Cfg1_Rcv64K = 0x7,
  195. Cfg1_Rcv128K = 0xf,
  196. };
  197. enum MiiCmd0Bits {
  198. Mii_Divider = 0x20000000,
  199. Mii_WRITE = 0x400000,
  200. Mii_READ = 0x200000,
  201. Mii_SCAN = 0x100000,
  202. Mii_Tamod = 0x80000,
  203. Mii_Drvmod = 0x40000,
  204. Mii_mdc = 0x20000,
  205. Mii_mdoen = 0x10000,
  206. Mii_mdo = 0x8000,
  207. Mii_mdi = 0x4000,
  208. };
  209. enum MiiStatusBits {
  210. Mii_StatusBusy = 0x80000000,
  211. };
  212. enum PMConfigBits {
  213. PM_Enable = 1 << 31,
  214. PM_LongWF = 1 << 30,
  215. PM_Magic = 1 << 29,
  216. PM_LANWake = 1 << 28,
  217. PM_LWPTN = (1 << 27 | 1<< 26),
  218. PM_LinkUp = 1 << 25,
  219. PM_WakeUp = 1 << 24,
  220. };
  221. /* Locking rules:
  222. * priv->lock protects most of the fields of priv and most of the
  223. * hardware registers. It does not have to protect against softirqs
  224. * between sc92031_disable_interrupts and sc92031_enable_interrupts;
  225. * it also does not need to be used in ->open and ->stop while the
  226. * device interrupts are off.
  227. * Not having to protect against softirqs is very useful due to heavy
  228. * use of mdelay() at _sc92031_reset.
  229. * Functions prefixed with _sc92031_ must be called with the lock held;
  230. * functions prefixed with sc92031_ must be called without the lock held.
  231. * Use mmiowb() before unlocking if the hardware was written to.
  232. */
  233. /* Locking rules for the interrupt:
  234. * - the interrupt and the tasklet never run at the same time
  235. * - neither run between sc92031_disable_interrupts and
  236. * sc92031_enable_interrupt
  237. */
  238. struct sc92031_priv {
  239. spinlock_t lock;
  240. /* iomap.h cookie */
  241. void __iomem *port_base;
  242. /* pci device structure */
  243. struct pci_dev *pdev;
  244. /* tasklet */
  245. struct tasklet_struct tasklet;
  246. /* CPU address of rx ring */
  247. void *rx_ring;
  248. /* PCI address of rx ring */
  249. dma_addr_t rx_ring_dma_addr;
  250. /* PCI address of rx ring read pointer */
  251. dma_addr_t rx_ring_tail;
  252. /* tx ring write index */
  253. unsigned tx_head;
  254. /* tx ring read index */
  255. unsigned tx_tail;
  256. /* CPU address of tx bounce buffer */
  257. void *tx_bufs;
  258. /* PCI address of tx bounce buffer */
  259. dma_addr_t tx_bufs_dma_addr;
  260. /* copies of some hardware registers */
  261. u32 intr_status;
  262. atomic_t intr_mask;
  263. u32 rx_config;
  264. u32 tx_config;
  265. u32 pm_config;
  266. /* copy of some flags from dev->flags */
  267. unsigned int mc_flags;
  268. /* for ETHTOOL_GSTATS */
  269. u64 tx_timeouts;
  270. u64 rx_loss;
  271. /* for dev->get_stats */
  272. long rx_value;
  273. struct net_device_stats stats;
  274. };
  275. /* I don't know which registers can be safely read; however, I can guess
  276. * MAC0 is one of them. */
  277. static inline void _sc92031_dummy_read(void __iomem *port_base)
  278. {
  279. ioread32(port_base + MAC0);
  280. }
  281. static u32 _sc92031_mii_wait(void __iomem *port_base)
  282. {
  283. u32 mii_status;
  284. do {
  285. udelay(10);
  286. mii_status = ioread32(port_base + Miistatus);
  287. } while (mii_status & Mii_StatusBusy);
  288. return mii_status;
  289. }
  290. static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
  291. {
  292. iowrite32(Mii_Divider, port_base + Miicmd0);
  293. _sc92031_mii_wait(port_base);
  294. iowrite32(cmd1, port_base + Miicmd1);
  295. iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
  296. return _sc92031_mii_wait(port_base);
  297. }
  298. static void _sc92031_mii_scan(void __iomem *port_base)
  299. {
  300. _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
  301. }
  302. static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
  303. {
  304. return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
  305. }
  306. static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
  307. {
  308. _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
  309. }
  310. static void sc92031_disable_interrupts(struct net_device *dev)
  311. {
  312. struct sc92031_priv *priv = netdev_priv(dev);
  313. void __iomem *port_base = priv->port_base;
  314. /* tell the tasklet/interrupt not to enable interrupts */
  315. atomic_set(&priv->intr_mask, 0);
  316. wmb();
  317. /* stop interrupts */
  318. iowrite32(0, port_base + IntrMask);
  319. _sc92031_dummy_read(port_base);
  320. mmiowb();
  321. /* wait for any concurrent interrupt/tasklet to finish */
  322. synchronize_irq(dev->irq);
  323. tasklet_disable(&priv->tasklet);
  324. }
  325. static void sc92031_enable_interrupts(struct net_device *dev)
  326. {
  327. struct sc92031_priv *priv = netdev_priv(dev);
  328. void __iomem *port_base = priv->port_base;
  329. tasklet_enable(&priv->tasklet);
  330. atomic_set(&priv->intr_mask, IntrBits);
  331. wmb();
  332. iowrite32(IntrBits, port_base + IntrMask);
  333. mmiowb();
  334. }
  335. static void _sc92031_disable_tx_rx(struct net_device *dev)
  336. {
  337. struct sc92031_priv *priv = netdev_priv(dev);
  338. void __iomem *port_base = priv->port_base;
  339. priv->rx_config &= ~RxEnb;
  340. priv->tx_config &= ~TxEnb;
  341. iowrite32(priv->rx_config, port_base + RxConfig);
  342. iowrite32(priv->tx_config, port_base + TxConfig);
  343. }
  344. static void _sc92031_enable_tx_rx(struct net_device *dev)
  345. {
  346. struct sc92031_priv *priv = netdev_priv(dev);
  347. void __iomem *port_base = priv->port_base;
  348. priv->rx_config |= RxEnb;
  349. priv->tx_config |= TxEnb;
  350. iowrite32(priv->rx_config, port_base + RxConfig);
  351. iowrite32(priv->tx_config, port_base + TxConfig);
  352. }
  353. static void _sc92031_tx_clear(struct net_device *dev)
  354. {
  355. struct sc92031_priv *priv = netdev_priv(dev);
  356. while (priv->tx_head - priv->tx_tail > 0) {
  357. priv->tx_tail++;
  358. priv->stats.tx_dropped++;
  359. }
  360. priv->tx_head = priv->tx_tail = 0;
  361. }
  362. static void _sc92031_set_mar(struct net_device *dev)
  363. {
  364. struct sc92031_priv *priv = netdev_priv(dev);
  365. void __iomem *port_base = priv->port_base;
  366. u32 mar0 = 0, mar1 = 0;
  367. if ((dev->flags & IFF_PROMISC)
  368. || dev->mc_count > multicast_filter_limit
  369. || (dev->flags & IFF_ALLMULTI))
  370. mar0 = mar1 = 0xffffffff;
  371. else if (dev->flags & IFF_MULTICAST) {
  372. struct dev_mc_list *mc_list;
  373. for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
  374. u32 crc;
  375. unsigned bit = 0;
  376. crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr);
  377. crc >>= 24;
  378. if (crc & 0x01) bit |= 0x02;
  379. if (crc & 0x02) bit |= 0x01;
  380. if (crc & 0x10) bit |= 0x20;
  381. if (crc & 0x20) bit |= 0x10;
  382. if (crc & 0x40) bit |= 0x08;
  383. if (crc & 0x80) bit |= 0x04;
  384. if (bit > 31)
  385. mar0 |= 0x1 << (bit - 32);
  386. else
  387. mar1 |= 0x1 << bit;
  388. }
  389. }
  390. iowrite32(mar0, port_base + MAR0);
  391. iowrite32(mar1, port_base + MAR0 + 4);
  392. }
  393. static void _sc92031_set_rx_config(struct net_device *dev)
  394. {
  395. struct sc92031_priv *priv = netdev_priv(dev);
  396. void __iomem *port_base = priv->port_base;
  397. unsigned int old_mc_flags;
  398. u32 rx_config_bits = 0;
  399. old_mc_flags = priv->mc_flags;
  400. if (dev->flags & IFF_PROMISC)
  401. rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
  402. | RxMulticast | RxAllphys;
  403. if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
  404. rx_config_bits |= RxMulticast;
  405. if (dev->flags & IFF_BROADCAST)
  406. rx_config_bits |= RxBroadcast;
  407. priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
  408. | RxMulticast | RxAllphys);
  409. priv->rx_config |= rx_config_bits;
  410. priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
  411. | IFF_MULTICAST | IFF_BROADCAST);
  412. if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
  413. iowrite32(priv->rx_config, port_base + RxConfig);
  414. }
  415. static bool _sc92031_check_media(struct net_device *dev)
  416. {
  417. struct sc92031_priv *priv = netdev_priv(dev);
  418. void __iomem *port_base = priv->port_base;
  419. u16 bmsr;
  420. bmsr = _sc92031_mii_read(port_base, MII_BMSR);
  421. rmb();
  422. if (bmsr & BMSR_LSTATUS) {
  423. bool speed_100, duplex_full;
  424. u32 flow_ctrl_config = 0;
  425. u16 output_status = _sc92031_mii_read(port_base,
  426. MII_OutputStatus);
  427. _sc92031_mii_scan(port_base);
  428. speed_100 = output_status & 0x2;
  429. duplex_full = output_status & 0x4;
  430. /* Initial Tx/Rx configuration */
  431. priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
  432. priv->tx_config = 0x48800000;
  433. /* NOTE: vendor driver had dead code here to enable tx padding */
  434. if (!speed_100)
  435. priv->tx_config |= 0x80000;
  436. // configure rx mode
  437. _sc92031_set_rx_config(dev);
  438. if (duplex_full) {
  439. priv->rx_config |= RxFullDx;
  440. priv->tx_config |= TxFullDx;
  441. flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
  442. } else {
  443. priv->rx_config &= ~RxFullDx;
  444. priv->tx_config &= ~TxFullDx;
  445. }
  446. _sc92031_set_mar(dev);
  447. _sc92031_set_rx_config(dev);
  448. _sc92031_enable_tx_rx(dev);
  449. iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
  450. netif_carrier_on(dev);
  451. if (printk_ratelimit())
  452. printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
  453. dev->name,
  454. speed_100 ? "100" : "10",
  455. duplex_full ? "full" : "half");
  456. return true;
  457. } else {
  458. _sc92031_mii_scan(port_base);
  459. netif_carrier_off(dev);
  460. _sc92031_disable_tx_rx(dev);
  461. if (printk_ratelimit())
  462. printk(KERN_INFO "%s: link down\n", dev->name);
  463. return false;
  464. }
  465. }
  466. static void _sc92031_phy_reset(struct net_device *dev)
  467. {
  468. struct sc92031_priv *priv = netdev_priv(dev);
  469. void __iomem *port_base = priv->port_base;
  470. u32 phy_ctrl;
  471. phy_ctrl = ioread32(port_base + PhyCtrl);
  472. phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
  473. phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
  474. switch (media) {
  475. default:
  476. case AUTOSELECT:
  477. phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
  478. break;
  479. case M10_HALF:
  480. phy_ctrl |= PhyCtrlSpd10;
  481. break;
  482. case M10_FULL:
  483. phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
  484. break;
  485. case M100_HALF:
  486. phy_ctrl |= PhyCtrlSpd100;
  487. break;
  488. case M100_FULL:
  489. phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
  490. break;
  491. }
  492. iowrite32(phy_ctrl, port_base + PhyCtrl);
  493. mdelay(10);
  494. phy_ctrl &= ~PhyCtrlReset;
  495. iowrite32(phy_ctrl, port_base + PhyCtrl);
  496. mdelay(1);
  497. _sc92031_mii_write(port_base, MII_JAB,
  498. PHY_16_JAB_ENB | PHY_16_PORT_ENB);
  499. _sc92031_mii_scan(port_base);
  500. netif_carrier_off(dev);
  501. netif_stop_queue(dev);
  502. }
  503. static void _sc92031_reset(struct net_device *dev)
  504. {
  505. struct sc92031_priv *priv = netdev_priv(dev);
  506. void __iomem *port_base = priv->port_base;
  507. /* disable PM */
  508. iowrite32(0, port_base + PMConfig);
  509. /* soft reset the chip */
  510. iowrite32(Cfg0_Reset, port_base + Config0);
  511. mdelay(200);
  512. iowrite32(0, port_base + Config0);
  513. mdelay(10);
  514. /* disable interrupts */
  515. iowrite32(0, port_base + IntrMask);
  516. /* clear multicast address */
  517. iowrite32(0, port_base + MAR0);
  518. iowrite32(0, port_base + MAR0 + 4);
  519. /* init rx ring */
  520. iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
  521. priv->rx_ring_tail = priv->rx_ring_dma_addr;
  522. /* init tx ring */
  523. _sc92031_tx_clear(dev);
  524. /* clear old register values */
  525. priv->intr_status = 0;
  526. atomic_set(&priv->intr_mask, 0);
  527. priv->rx_config = 0;
  528. priv->tx_config = 0;
  529. priv->mc_flags = 0;
  530. /* configure rx buffer size */
  531. /* NOTE: vendor driver had dead code here to enable early tx/rx */
  532. iowrite32(Cfg1_Rcv64K, port_base + Config1);
  533. _sc92031_phy_reset(dev);
  534. _sc92031_check_media(dev);
  535. /* calculate rx fifo overflow */
  536. priv->rx_value = 0;
  537. /* enable PM */
  538. iowrite32(priv->pm_config, port_base + PMConfig);
  539. /* clear intr register */
  540. ioread32(port_base + IntrStatus);
  541. }
  542. static void _sc92031_tx_tasklet(struct net_device *dev)
  543. {
  544. struct sc92031_priv *priv = netdev_priv(dev);
  545. void __iomem *port_base = priv->port_base;
  546. unsigned old_tx_tail;
  547. unsigned entry;
  548. u32 tx_status;
  549. old_tx_tail = priv->tx_tail;
  550. while (priv->tx_head - priv->tx_tail > 0) {
  551. entry = priv->tx_tail % NUM_TX_DESC;
  552. tx_status = ioread32(port_base + TxStatus0 + entry * 4);
  553. if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
  554. break;
  555. priv->tx_tail++;
  556. if (tx_status & TxStatOK) {
  557. priv->stats.tx_bytes += tx_status & 0x1fff;
  558. priv->stats.tx_packets++;
  559. /* Note: TxCarrierLost is always asserted at 100mbps. */
  560. priv->stats.collisions += (tx_status >> 22) & 0xf;
  561. }
  562. if (tx_status & (TxOutOfWindow | TxAborted)) {
  563. priv->stats.tx_errors++;
  564. if (tx_status & TxAborted)
  565. priv->stats.tx_aborted_errors++;
  566. if (tx_status & TxCarrierLost)
  567. priv->stats.tx_carrier_errors++;
  568. if (tx_status & TxOutOfWindow)
  569. priv->stats.tx_window_errors++;
  570. }
  571. if (tx_status & TxUnderrun)
  572. priv->stats.tx_fifo_errors++;
  573. }
  574. if (priv->tx_tail != old_tx_tail)
  575. if (netif_queue_stopped(dev))
  576. netif_wake_queue(dev);
  577. }
  578. static void _sc92031_rx_tasklet_error(u32 rx_status,
  579. struct sc92031_priv *priv, unsigned rx_size)
  580. {
  581. if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
  582. priv->stats.rx_errors++;
  583. priv->stats.rx_length_errors++;
  584. }
  585. if (!(rx_status & RxStatesOK)) {
  586. priv->stats.rx_errors++;
  587. if (rx_status & (RxHugeFrame | RxSmallFrame))
  588. priv->stats.rx_length_errors++;
  589. if (rx_status & RxBadAlign)
  590. priv->stats.rx_frame_errors++;
  591. if (!(rx_status & RxCRCOK))
  592. priv->stats.rx_crc_errors++;
  593. } else
  594. priv->rx_loss++;
  595. }
  596. static void _sc92031_rx_tasklet(struct net_device *dev)
  597. {
  598. struct sc92031_priv *priv = netdev_priv(dev);
  599. void __iomem *port_base = priv->port_base;
  600. dma_addr_t rx_ring_head;
  601. unsigned rx_len;
  602. unsigned rx_ring_offset;
  603. void *rx_ring = priv->rx_ring;
  604. rx_ring_head = ioread32(port_base + RxBufWPtr);
  605. rmb();
  606. /* rx_ring_head is only 17 bits in the RxBufWPtr register.
  607. * we need to change it to 32 bits physical address
  608. */
  609. rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
  610. rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
  611. if (rx_ring_head < priv->rx_ring_dma_addr)
  612. rx_ring_head += RX_BUF_LEN;
  613. if (rx_ring_head >= priv->rx_ring_tail)
  614. rx_len = rx_ring_head - priv->rx_ring_tail;
  615. else
  616. rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
  617. if (!rx_len)
  618. return;
  619. if (unlikely(rx_len > RX_BUF_LEN)) {
  620. if (printk_ratelimit())
  621. printk(KERN_ERR "%s: rx packets length > rx buffer\n",
  622. dev->name);
  623. return;
  624. }
  625. rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
  626. while (rx_len) {
  627. u32 rx_status;
  628. unsigned rx_size, rx_size_align, pkt_size;
  629. struct sk_buff *skb;
  630. rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
  631. rmb();
  632. rx_size = rx_status >> 20;
  633. rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
  634. pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
  635. rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
  636. if (unlikely(rx_status == 0
  637. || rx_size > (MAX_ETH_FRAME_SIZE + 4)
  638. || rx_size < 16
  639. || !(rx_status & RxStatesOK))) {
  640. _sc92031_rx_tasklet_error(rx_status, priv, rx_size);
  641. break;
  642. }
  643. if (unlikely(rx_size_align + 4 > rx_len)) {
  644. if (printk_ratelimit())
  645. printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
  646. break;
  647. }
  648. rx_len -= rx_size_align + 4;
  649. skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
  650. if (unlikely(!skb)) {
  651. if (printk_ratelimit())
  652. printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
  653. dev->name, pkt_size);
  654. goto next;
  655. }
  656. skb_reserve(skb, NET_IP_ALIGN);
  657. if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
  658. memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
  659. rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
  660. memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
  661. rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
  662. } else {
  663. memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
  664. }
  665. skb->dev = dev;
  666. skb->protocol = eth_type_trans(skb, dev);
  667. dev->last_rx = jiffies;
  668. netif_rx(skb);
  669. priv->stats.rx_bytes += pkt_size;
  670. priv->stats.rx_packets++;
  671. if (rx_status & Rx_Multicast)
  672. priv->stats.multicast++;
  673. next:
  674. rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
  675. }
  676. mb();
  677. priv->rx_ring_tail = rx_ring_head;
  678. iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
  679. }
  680. static void _sc92031_link_tasklet(struct net_device *dev)
  681. {
  682. struct sc92031_priv *priv = netdev_priv(dev);
  683. if (_sc92031_check_media(dev))
  684. netif_wake_queue(dev);
  685. else {
  686. netif_stop_queue(dev);
  687. priv->stats.tx_carrier_errors++;
  688. }
  689. }
  690. static void sc92031_tasklet(unsigned long data)
  691. {
  692. struct net_device *dev = (struct net_device *)data;
  693. struct sc92031_priv *priv = netdev_priv(dev);
  694. void __iomem *port_base = priv->port_base;
  695. u32 intr_status, intr_mask;
  696. intr_status = priv->intr_status;
  697. spin_lock(&priv->lock);
  698. if (unlikely(!netif_running(dev)))
  699. goto out;
  700. if (intr_status & TxOK)
  701. _sc92031_tx_tasklet(dev);
  702. if (intr_status & RxOK)
  703. _sc92031_rx_tasklet(dev);
  704. if (intr_status & RxOverflow)
  705. priv->stats.rx_errors++;
  706. if (intr_status & TimeOut) {
  707. priv->stats.rx_errors++;
  708. priv->stats.rx_length_errors++;
  709. }
  710. if (intr_status & (LinkFail | LinkOK))
  711. _sc92031_link_tasklet(dev);
  712. out:
  713. intr_mask = atomic_read(&priv->intr_mask);
  714. rmb();
  715. iowrite32(intr_mask, port_base + IntrMask);
  716. mmiowb();
  717. spin_unlock(&priv->lock);
  718. }
  719. static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
  720. {
  721. struct net_device *dev = dev_id;
  722. struct sc92031_priv *priv = netdev_priv(dev);
  723. void __iomem *port_base = priv->port_base;
  724. u32 intr_status, intr_mask;
  725. /* mask interrupts before clearing IntrStatus */
  726. iowrite32(0, port_base + IntrMask);
  727. _sc92031_dummy_read(port_base);
  728. intr_status = ioread32(port_base + IntrStatus);
  729. if (unlikely(intr_status == 0xffffffff))
  730. return IRQ_NONE; // hardware has gone missing
  731. intr_status &= IntrBits;
  732. if (!intr_status)
  733. goto out_none;
  734. priv->intr_status = intr_status;
  735. tasklet_schedule(&priv->tasklet);
  736. return IRQ_HANDLED;
  737. out_none:
  738. intr_mask = atomic_read(&priv->intr_mask);
  739. rmb();
  740. iowrite32(intr_mask, port_base + IntrMask);
  741. mmiowb();
  742. return IRQ_NONE;
  743. }
  744. static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
  745. {
  746. struct sc92031_priv *priv = netdev_priv(dev);
  747. void __iomem *port_base = priv->port_base;
  748. // FIXME I do not understand what is this trying to do.
  749. if (netif_running(dev)) {
  750. int temp;
  751. spin_lock_bh(&priv->lock);
  752. /* Update the error count. */
  753. temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
  754. if (temp == 0xffff) {
  755. priv->rx_value += temp;
  756. priv->stats.rx_fifo_errors = priv->rx_value;
  757. } else {
  758. priv->stats.rx_fifo_errors = temp + priv->rx_value;
  759. }
  760. spin_unlock_bh(&priv->lock);
  761. }
  762. return &priv->stats;
  763. }
  764. static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
  765. {
  766. int err = 0;
  767. struct sc92031_priv *priv = netdev_priv(dev);
  768. void __iomem *port_base = priv->port_base;
  769. unsigned len;
  770. unsigned entry;
  771. u32 tx_status;
  772. if (unlikely(skb->len > TX_BUF_SIZE)) {
  773. err = -EMSGSIZE;
  774. priv->stats.tx_dropped++;
  775. goto out;
  776. }
  777. spin_lock(&priv->lock);
  778. if (unlikely(!netif_carrier_ok(dev))) {
  779. err = -ENOLINK;
  780. priv->stats.tx_dropped++;
  781. goto out_unlock;
  782. }
  783. BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
  784. entry = priv->tx_head++ % NUM_TX_DESC;
  785. skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
  786. len = skb->len;
  787. if (unlikely(len < ETH_ZLEN)) {
  788. memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
  789. 0, ETH_ZLEN - len);
  790. len = ETH_ZLEN;
  791. }
  792. wmb();
  793. if (len < 100)
  794. tx_status = len;
  795. else if (len < 300)
  796. tx_status = 0x30000 | len;
  797. else
  798. tx_status = 0x50000 | len;
  799. iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
  800. port_base + TxAddr0 + entry * 4);
  801. iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
  802. mmiowb();
  803. dev->trans_start = jiffies;
  804. if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
  805. netif_stop_queue(dev);
  806. out_unlock:
  807. spin_unlock(&priv->lock);
  808. out:
  809. dev_kfree_skb(skb);
  810. return err;
  811. }
  812. static int sc92031_open(struct net_device *dev)
  813. {
  814. int err;
  815. struct sc92031_priv *priv = netdev_priv(dev);
  816. struct pci_dev *pdev = priv->pdev;
  817. priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
  818. &priv->rx_ring_dma_addr);
  819. if (unlikely(!priv->rx_ring)) {
  820. err = -ENOMEM;
  821. goto out_alloc_rx_ring;
  822. }
  823. priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
  824. &priv->tx_bufs_dma_addr);
  825. if (unlikely(!priv->tx_bufs)) {
  826. err = -ENOMEM;
  827. goto out_alloc_tx_bufs;
  828. }
  829. priv->tx_head = priv->tx_tail = 0;
  830. err = request_irq(pdev->irq, sc92031_interrupt,
  831. IRQF_SHARED, dev->name, dev);
  832. if (unlikely(err < 0))
  833. goto out_request_irq;
  834. priv->pm_config = 0;
  835. /* Interrupts already disabled by sc92031_stop or sc92031_probe */
  836. spin_lock_bh(&priv->lock);
  837. _sc92031_reset(dev);
  838. mmiowb();
  839. spin_unlock_bh(&priv->lock);
  840. sc92031_enable_interrupts(dev);
  841. if (netif_carrier_ok(dev))
  842. netif_start_queue(dev);
  843. else
  844. netif_tx_disable(dev);
  845. return 0;
  846. out_request_irq:
  847. pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
  848. priv->tx_bufs_dma_addr);
  849. out_alloc_tx_bufs:
  850. pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
  851. priv->rx_ring_dma_addr);
  852. out_alloc_rx_ring:
  853. return err;
  854. }
  855. static int sc92031_stop(struct net_device *dev)
  856. {
  857. struct sc92031_priv *priv = netdev_priv(dev);
  858. struct pci_dev *pdev = priv->pdev;
  859. netif_tx_disable(dev);
  860. /* Disable interrupts, stop Tx and Rx. */
  861. sc92031_disable_interrupts(dev);
  862. spin_lock_bh(&priv->lock);
  863. _sc92031_disable_tx_rx(dev);
  864. _sc92031_tx_clear(dev);
  865. mmiowb();
  866. spin_unlock_bh(&priv->lock);
  867. free_irq(pdev->irq, dev);
  868. pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
  869. priv->tx_bufs_dma_addr);
  870. pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
  871. priv->rx_ring_dma_addr);
  872. return 0;
  873. }
  874. static void sc92031_set_multicast_list(struct net_device *dev)
  875. {
  876. struct sc92031_priv *priv = netdev_priv(dev);
  877. spin_lock_bh(&priv->lock);
  878. _sc92031_set_mar(dev);
  879. _sc92031_set_rx_config(dev);
  880. mmiowb();
  881. spin_unlock_bh(&priv->lock);
  882. }
  883. static void sc92031_tx_timeout(struct net_device *dev)
  884. {
  885. struct sc92031_priv *priv = netdev_priv(dev);
  886. /* Disable interrupts by clearing the interrupt mask.*/
  887. sc92031_disable_interrupts(dev);
  888. spin_lock(&priv->lock);
  889. priv->tx_timeouts++;
  890. _sc92031_reset(dev);
  891. mmiowb();
  892. spin_unlock(&priv->lock);
  893. /* enable interrupts */
  894. sc92031_enable_interrupts(dev);
  895. if (netif_carrier_ok(dev))
  896. netif_wake_queue(dev);
  897. }
  898. #ifdef CONFIG_NET_POLL_CONTROLLER
  899. static void sc92031_poll_controller(struct net_device *dev)
  900. {
  901. disable_irq(dev->irq);
  902. if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
  903. sc92031_tasklet((unsigned long)dev);
  904. enable_irq(dev->irq);
  905. }
  906. #endif
  907. static int sc92031_ethtool_get_settings(struct net_device *dev,
  908. struct ethtool_cmd *cmd)
  909. {
  910. struct sc92031_priv *priv = netdev_priv(dev);
  911. void __iomem *port_base = priv->port_base;
  912. u8 phy_address;
  913. u32 phy_ctrl;
  914. u16 output_status;
  915. spin_lock_bh(&priv->lock);
  916. phy_address = ioread32(port_base + Miicmd1) >> 27;
  917. phy_ctrl = ioread32(port_base + PhyCtrl);
  918. output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
  919. _sc92031_mii_scan(port_base);
  920. mmiowb();
  921. spin_unlock_bh(&priv->lock);
  922. cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
  923. | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
  924. | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
  925. cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
  926. if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
  927. == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
  928. cmd->advertising |= ADVERTISED_Autoneg;
  929. if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
  930. cmd->advertising |= ADVERTISED_10baseT_Half;
  931. if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
  932. == (PhyCtrlSpd10 | PhyCtrlDux))
  933. cmd->advertising |= ADVERTISED_10baseT_Full;
  934. if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
  935. cmd->advertising |= ADVERTISED_100baseT_Half;
  936. if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
  937. == (PhyCtrlSpd100 | PhyCtrlDux))
  938. cmd->advertising |= ADVERTISED_100baseT_Full;
  939. if (phy_ctrl & PhyCtrlAne)
  940. cmd->advertising |= ADVERTISED_Autoneg;
  941. cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
  942. cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
  943. cmd->port = PORT_MII;
  944. cmd->phy_address = phy_address;
  945. cmd->transceiver = XCVR_INTERNAL;
  946. cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
  947. return 0;
  948. }
  949. static int sc92031_ethtool_set_settings(struct net_device *dev,
  950. struct ethtool_cmd *cmd)
  951. {
  952. struct sc92031_priv *priv = netdev_priv(dev);
  953. void __iomem *port_base = priv->port_base;
  954. u32 phy_ctrl;
  955. u32 old_phy_ctrl;
  956. if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
  957. return -EINVAL;
  958. if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
  959. return -EINVAL;
  960. if (!(cmd->port == PORT_MII))
  961. return -EINVAL;
  962. if (!(cmd->phy_address == 0x1f))
  963. return -EINVAL;
  964. if (!(cmd->transceiver == XCVR_INTERNAL))
  965. return -EINVAL;
  966. if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
  967. return -EINVAL;
  968. if (cmd->autoneg == AUTONEG_ENABLE) {
  969. if (!(cmd->advertising & (ADVERTISED_Autoneg
  970. | ADVERTISED_100baseT_Full
  971. | ADVERTISED_100baseT_Half
  972. | ADVERTISED_10baseT_Full
  973. | ADVERTISED_10baseT_Half)))
  974. return -EINVAL;
  975. phy_ctrl = PhyCtrlAne;
  976. // FIXME: I'm not sure what the original code was trying to do
  977. if (cmd->advertising & ADVERTISED_Autoneg)
  978. phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
  979. if (cmd->advertising & ADVERTISED_100baseT_Full)
  980. phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
  981. if (cmd->advertising & ADVERTISED_100baseT_Half)
  982. phy_ctrl |= PhyCtrlSpd100;
  983. if (cmd->advertising & ADVERTISED_10baseT_Full)
  984. phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
  985. if (cmd->advertising & ADVERTISED_10baseT_Half)
  986. phy_ctrl |= PhyCtrlSpd10;
  987. } else {
  988. // FIXME: Whole branch guessed
  989. phy_ctrl = 0;
  990. if (cmd->speed == SPEED_10)
  991. phy_ctrl |= PhyCtrlSpd10;
  992. else /* cmd->speed == SPEED_100 */
  993. phy_ctrl |= PhyCtrlSpd100;
  994. if (cmd->duplex == DUPLEX_FULL)
  995. phy_ctrl |= PhyCtrlDux;
  996. }
  997. spin_lock_bh(&priv->lock);
  998. old_phy_ctrl = ioread32(port_base + PhyCtrl);
  999. phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
  1000. | PhyCtrlSpd100 | PhyCtrlSpd10);
  1001. if (phy_ctrl != old_phy_ctrl)
  1002. iowrite32(phy_ctrl, port_base + PhyCtrl);
  1003. spin_unlock_bh(&priv->lock);
  1004. return 0;
  1005. }
  1006. static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
  1007. struct ethtool_drvinfo *drvinfo)
  1008. {
  1009. struct sc92031_priv *priv = netdev_priv(dev);
  1010. struct pci_dev *pdev = priv->pdev;
  1011. strcpy(drvinfo->driver, SC92031_NAME);
  1012. strcpy(drvinfo->version, SC92031_VERSION);
  1013. strcpy(drvinfo->bus_info, pci_name(pdev));
  1014. }
  1015. static void sc92031_ethtool_get_wol(struct net_device *dev,
  1016. struct ethtool_wolinfo *wolinfo)
  1017. {
  1018. struct sc92031_priv *priv = netdev_priv(dev);
  1019. void __iomem *port_base = priv->port_base;
  1020. u32 pm_config;
  1021. spin_lock_bh(&priv->lock);
  1022. pm_config = ioread32(port_base + PMConfig);
  1023. spin_unlock_bh(&priv->lock);
  1024. // FIXME: Guessed
  1025. wolinfo->supported = WAKE_PHY | WAKE_MAGIC
  1026. | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
  1027. wolinfo->wolopts = 0;
  1028. if (pm_config & PM_LinkUp)
  1029. wolinfo->wolopts |= WAKE_PHY;
  1030. if (pm_config & PM_Magic)
  1031. wolinfo->wolopts |= WAKE_MAGIC;
  1032. if (pm_config & PM_WakeUp)
  1033. // FIXME: Guessed
  1034. wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
  1035. }
  1036. static int sc92031_ethtool_set_wol(struct net_device *dev,
  1037. struct ethtool_wolinfo *wolinfo)
  1038. {
  1039. struct sc92031_priv *priv = netdev_priv(dev);
  1040. void __iomem *port_base = priv->port_base;
  1041. u32 pm_config;
  1042. spin_lock_bh(&priv->lock);
  1043. pm_config = ioread32(port_base + PMConfig)
  1044. & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
  1045. if (wolinfo->wolopts & WAKE_PHY)
  1046. pm_config |= PM_LinkUp;
  1047. if (wolinfo->wolopts & WAKE_MAGIC)
  1048. pm_config |= PM_Magic;
  1049. // FIXME: Guessed
  1050. if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
  1051. pm_config |= PM_WakeUp;
  1052. priv->pm_config = pm_config;
  1053. iowrite32(pm_config, port_base + PMConfig);
  1054. mmiowb();
  1055. spin_unlock_bh(&priv->lock);
  1056. return 0;
  1057. }
  1058. static int sc92031_ethtool_nway_reset(struct net_device *dev)
  1059. {
  1060. int err = 0;
  1061. struct sc92031_priv *priv = netdev_priv(dev);
  1062. void __iomem *port_base = priv->port_base;
  1063. u16 bmcr;
  1064. spin_lock_bh(&priv->lock);
  1065. bmcr = _sc92031_mii_read(port_base, MII_BMCR);
  1066. if (!(bmcr & BMCR_ANENABLE)) {
  1067. err = -EINVAL;
  1068. goto out;
  1069. }
  1070. _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
  1071. out:
  1072. _sc92031_mii_scan(port_base);
  1073. mmiowb();
  1074. spin_unlock_bh(&priv->lock);
  1075. return err;
  1076. }
  1077. static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
  1078. "tx_timeout",
  1079. "rx_loss",
  1080. };
  1081. static void sc92031_ethtool_get_strings(struct net_device *dev,
  1082. u32 stringset, u8 *data)
  1083. {
  1084. if (stringset == ETH_SS_STATS)
  1085. memcpy(data, sc92031_ethtool_stats_strings,
  1086. SILAN_STATS_NUM * ETH_GSTRING_LEN);
  1087. }
  1088. static int sc92031_ethtool_get_stats_count(struct net_device *dev)
  1089. {
  1090. return SILAN_STATS_NUM;
  1091. }
  1092. static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
  1093. struct ethtool_stats *stats, u64 *data)
  1094. {
  1095. struct sc92031_priv *priv = netdev_priv(dev);
  1096. spin_lock_bh(&priv->lock);
  1097. data[0] = priv->tx_timeouts;
  1098. data[1] = priv->rx_loss;
  1099. spin_unlock_bh(&priv->lock);
  1100. }
  1101. static struct ethtool_ops sc92031_ethtool_ops = {
  1102. .get_settings = sc92031_ethtool_get_settings,
  1103. .set_settings = sc92031_ethtool_set_settings,
  1104. .get_drvinfo = sc92031_ethtool_get_drvinfo,
  1105. .get_wol = sc92031_ethtool_get_wol,
  1106. .set_wol = sc92031_ethtool_set_wol,
  1107. .nway_reset = sc92031_ethtool_nway_reset,
  1108. .get_link = ethtool_op_get_link,
  1109. .get_tx_csum = ethtool_op_get_tx_csum,
  1110. .get_sg = ethtool_op_get_sg,
  1111. .get_tso = ethtool_op_get_tso,
  1112. .get_strings = sc92031_ethtool_get_strings,
  1113. .get_stats_count = sc92031_ethtool_get_stats_count,
  1114. .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
  1115. .get_perm_addr = ethtool_op_get_perm_addr,
  1116. .get_ufo = ethtool_op_get_ufo,
  1117. };
  1118. static int __devinit sc92031_probe(struct pci_dev *pdev,
  1119. const struct pci_device_id *id)
  1120. {
  1121. int err;
  1122. void __iomem* port_base;
  1123. struct net_device *dev;
  1124. struct sc92031_priv *priv;
  1125. u32 mac0, mac1;
  1126. err = pci_enable_device(pdev);
  1127. if (unlikely(err < 0))
  1128. goto out_enable_device;
  1129. pci_set_master(pdev);
  1130. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1131. if (unlikely(err < 0))
  1132. goto out_set_dma_mask;
  1133. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1134. if (unlikely(err < 0))
  1135. goto out_set_dma_mask;
  1136. err = pci_request_regions(pdev, SC92031_NAME);
  1137. if (unlikely(err < 0))
  1138. goto out_request_regions;
  1139. port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
  1140. if (unlikely(!port_base)) {
  1141. err = -EIO;
  1142. goto out_iomap;
  1143. }
  1144. dev = alloc_etherdev(sizeof(struct sc92031_priv));
  1145. if (unlikely(!dev)) {
  1146. err = -ENOMEM;
  1147. goto out_alloc_etherdev;
  1148. }
  1149. pci_set_drvdata(pdev, dev);
  1150. #if SC92031_USE_BAR == 0
  1151. dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
  1152. dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
  1153. #elif SC92031_USE_BAR == 1
  1154. dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
  1155. #endif
  1156. dev->irq = pdev->irq;
  1157. /* faked with skb_copy_and_csum_dev */
  1158. dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
  1159. dev->get_stats = sc92031_get_stats;
  1160. dev->ethtool_ops = &sc92031_ethtool_ops;
  1161. dev->hard_start_xmit = sc92031_start_xmit;
  1162. dev->watchdog_timeo = TX_TIMEOUT;
  1163. dev->open = sc92031_open;
  1164. dev->stop = sc92031_stop;
  1165. dev->set_multicast_list = sc92031_set_multicast_list;
  1166. dev->tx_timeout = sc92031_tx_timeout;
  1167. #ifdef CONFIG_NET_POLL_CONTROLLER
  1168. dev->poll_controller = sc92031_poll_controller;
  1169. #endif
  1170. priv = netdev_priv(dev);
  1171. spin_lock_init(&priv->lock);
  1172. priv->port_base = port_base;
  1173. priv->pdev = pdev;
  1174. tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
  1175. /* Fudge tasklet count so the call to sc92031_enable_interrupts at
  1176. * sc92031_open will work correctly */
  1177. tasklet_disable_nosync(&priv->tasklet);
  1178. /* PCI PM Wakeup */
  1179. iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
  1180. mac0 = ioread32(port_base + MAC0);
  1181. mac1 = ioread32(port_base + MAC0 + 4);
  1182. dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
  1183. dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
  1184. dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
  1185. dev->dev_addr[3] = dev->perm_addr[3] = mac0;
  1186. dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
  1187. dev->dev_addr[5] = dev->perm_addr[5] = mac1;
  1188. err = register_netdev(dev);
  1189. if (err < 0)
  1190. goto out_register_netdev;
  1191. return 0;
  1192. out_register_netdev:
  1193. free_netdev(dev);
  1194. out_alloc_etherdev:
  1195. pci_iounmap(pdev, port_base);
  1196. out_iomap:
  1197. pci_release_regions(pdev);
  1198. out_request_regions:
  1199. out_set_dma_mask:
  1200. pci_disable_device(pdev);
  1201. out_enable_device:
  1202. return err;
  1203. }
  1204. static void __devexit sc92031_remove(struct pci_dev *pdev)
  1205. {
  1206. struct net_device *dev = pci_get_drvdata(pdev);
  1207. struct sc92031_priv *priv = netdev_priv(dev);
  1208. void __iomem* port_base = priv->port_base;
  1209. unregister_netdev(dev);
  1210. free_netdev(dev);
  1211. pci_iounmap(pdev, port_base);
  1212. pci_release_regions(pdev);
  1213. pci_disable_device(pdev);
  1214. }
  1215. static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
  1216. {
  1217. struct net_device *dev = pci_get_drvdata(pdev);
  1218. struct sc92031_priv *priv = netdev_priv(dev);
  1219. pci_save_state(pdev);
  1220. if (!netif_running(dev))
  1221. goto out;
  1222. netif_device_detach(dev);
  1223. /* Disable interrupts, stop Tx and Rx. */
  1224. sc92031_disable_interrupts(dev);
  1225. spin_lock_bh(&priv->lock);
  1226. _sc92031_disable_tx_rx(dev);
  1227. _sc92031_tx_clear(dev);
  1228. mmiowb();
  1229. spin_unlock_bh(&priv->lock);
  1230. out:
  1231. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  1232. return 0;
  1233. }
  1234. static int sc92031_resume(struct pci_dev *pdev)
  1235. {
  1236. struct net_device *dev = pci_get_drvdata(pdev);
  1237. struct sc92031_priv *priv = netdev_priv(dev);
  1238. pci_restore_state(pdev);
  1239. pci_set_power_state(pdev, PCI_D0);
  1240. if (!netif_running(dev))
  1241. goto out;
  1242. /* Interrupts already disabled by sc92031_suspend */
  1243. spin_lock_bh(&priv->lock);
  1244. _sc92031_reset(dev);
  1245. mmiowb();
  1246. spin_unlock_bh(&priv->lock);
  1247. sc92031_enable_interrupts(dev);
  1248. netif_device_attach(dev);
  1249. if (netif_carrier_ok(dev))
  1250. netif_wake_queue(dev);
  1251. else
  1252. netif_tx_disable(dev);
  1253. out:
  1254. return 0;
  1255. }
  1256. static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = {
  1257. { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_SC92031) },
  1258. { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_8139D) },
  1259. { 0, }
  1260. };
  1261. MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
  1262. static struct pci_driver sc92031_pci_driver = {
  1263. .name = SC92031_NAME,
  1264. .id_table = sc92031_pci_device_id_table,
  1265. .probe = sc92031_probe,
  1266. .remove = __devexit_p(sc92031_remove),
  1267. .suspend = sc92031_suspend,
  1268. .resume = sc92031_resume,
  1269. };
  1270. static int __init sc92031_init(void)
  1271. {
  1272. printk(KERN_INFO SC92031_DESCRIPTION " " SC92031_VERSION "\n");
  1273. return pci_register_driver(&sc92031_pci_driver);
  1274. }
  1275. static void __exit sc92031_exit(void)
  1276. {
  1277. pci_unregister_driver(&sc92031_pci_driver);
  1278. }
  1279. module_init(sc92031_init);
  1280. module_exit(sc92031_exit);
  1281. MODULE_LICENSE("GPL");
  1282. MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
  1283. MODULE_DESCRIPTION(SC92031_DESCRIPTION);
  1284. MODULE_VERSION(SC92031_VERSION);